FDS6912A ee FAIRCHILD SEMICONDUCTOR Im FDS6912A June 1998 Dual N-Channel, Logic Level, PowerTrench MOSFET General Description These N-Channel Logic Level MOSFETs are produced using Fairchild Semiconductor's advanced PowerTrench process that has been especially tailored to minimize the on-state resistance and yet maintain superior switching performance. These devices are well suited for low voltage and battery powered applications where low in-line power loss and fast switching are required. in i * Features 6A, 30V. Ragin = 0.028. @ Veg = 10V Rogom = 0-035 Q @ Vag = 4.5 V. = Fast switching speed. a Low gate charge (typical 9 nC). 8 High performance trench technology for extremely low R DS(ON)" High power and current handling capability. Absolute Maximum Ratings T, = 25C unless other wise noted Symbol | Parameter FDS6912A Units Voss Drain-Source Voltage 30 Vows Gate-Source Voltage +20 l, Drain Current - Continuous (Note ta) 6 A - Pulsed 20 P, Power Dissipation for Single Operation _(note ta) 2 Ww (Note 1b) 16 (Note 1c) 0.9 Ti Tet Operating and Storage Temperature Range -55 to 150 c THERMAL CHARACTERISTICS Rasa "| Thermal Resistance, Junction-to-Ambient oe 1a 78 SCAN Pac Thermal Resistance, Junction-to-Case ole 1) 40 C 2-66 FDS6912A Aev.C Electrical Characteristics (T, = 25C unless otherwise noted ) Q be : mize a. 78CMW on a 0.5 in? a 5b, 125CAW on a 0.02 in? pad of 20z copper. x Ne pad of 202 copper. O Scale 1: 1 on letter size paper 2. Pulse Test: Pulse Width < 300us, Duty Cycle < 2.0%, Symbol | Parameter Conditions | Min | Typ Max | Units OFF CHARACTERISTICS BV oss Drain-Source Breakdown Voltage Veg = OV, 1)= 250 WA 30 Vv ABV, ' | i]t 0 _ : a lL pee LL _ 0.4 02 05 1 2 5 10 30 0 3 6 9 12 15 18 Vpg. DRAIN TO SOURCE VOLTAGE (V) Qg . GATE CHARGE (nC) Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics. 100 rye ee 50 =} SINGLE PULSE | <= i ug Raa =135CAV | 10 Exe 7, Ta = 25C | Zz To = i & 70m, 2 5 : & | 3 as = | Zz Ts o iy = ao 2S sy Vgg =10V il jc SINGLE PULSE Toi ~ 905 Rqia= 135C 1 Tt Ty = 25C : an O01 tet o4 05 1 2 5 10 30. 50 Vpg . DRAIN-SOURCE VOLTAGE (V) Figure 9. Maximum Safe Operating Area. 0.01 = 0.005 *- TRANSIENT THERMAL RESISTANCE =F 10 50 100 300 SINGLE PULSE TIME (SEC) Figure 10. Single Pulse Maximum Power Dissipation. Rosa () = ri) * Rasa b 4 Ty-Ty =P Rylan 4 Duty Cycle, D=t, /, - Ww > 22 o2 8 ot Rasa =135 CW Fs t | ~~ r | 0.05 = g r | Zz 00e 0.01 ee tye: _ 3 ey | oc S Z 0.002 - _ ine 1 bie 0.0001 0.001 0.01 1 10 100 300 vel69Sd4 1, TIME (sec) Figure 11. Transient Thermal Response Curve. Therma! characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. 2-69 FOS6912A Rev.C