Rev.3.00, Jul.22.2005, page 1 of 7
HD74LS74A
Dual D-type Positive Edge-triggered Flip-Flops
(with Preset and Clear) REJ03D0415–0300
Rev.3.00
Jul.22.2005
Features
• Ordering Information
Part Name Package Type Package Code
(Previous Code) Package
Abbreviation Taping Abbreviation
(Quantity)
HD74LS74AP DILP-14 pin PRDP0014AB-B
(DP-14AV) P —
HD74LS74AFPEL SOP-14 pin (JEITA) PRSP0014DF-B
(FP-14DAV) FP EL (2,000 pcs/reel)
HD74LS74ARPEL SOP-14 pin (JEDEC) PRSP0014DE-A
(FP-14DNV) RP EL (2,500 pcs/reel)
Note: Please consult the sales office for the above package availability.
Pin Arrangement
(Top view)
V
CC
2CLR
2D
2CK
2Q
2PR
1CLR
GND
1D
1CK
1PR
1Q
1Q
2Q
1
2
3
4
5
6
7
14
8
9
10
11
12
13
PR
CK
D
CLR
Q
Q
D
CK
PR
QQ
CLR
HD74LS74A
Rev.3.00, Jul.22.2005, page 2 of 7
Function Table
Input Output
Preset Clear Clock D Q Q
L H X X H L
H L X X L H
L L X X H* H*
H H ↑ H H L
H H ↑ L L H
H H L X Q0 Q0
H; high level, L; low level, X; irrelevant, ↑; transition from low to high level,
Q0; level of Q before the indicated steady-state input conditions were established.
Q0; complement of Q0 or level of Q before the indicated steady-state input conditions were established.
*;This configuration is nonstable, that is, it will not persist when preset and clear inputs return to their inactive (high) level.
Absolute Maximum Ratings
Item Symbol Ratings Unit
Supply voltage VCC 7 V
Input voltage VIN 7 V
Power dissipation PT 400 mW
Storage temperature Tstg –65 to +150 °C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item Symbol Min Typ Max Unit
Supply voltage VCC 4.75 5.00 5.25 V
IOH — — –400 µA
Output current IOL — — 8 mA
Operating temperature Topr –20 25 75 °C
Clock frequency fclock 0 — 25 MHz
Clock High tw 25 — —
Pulse width Clear Preset tw 25 — — ns
“H” Data tsu 20↑ — —
Setup time “L” Data tsu 20↑ — — ns
Hold time th 5↑ — — ns
Note: ↑; The arrow indicates the rising edge.
HD74LS74A
Rev.3.00, Jul.22.2005, page 3 of 7
Electrical Characteristics
(Ta = –20 to +75 °C)
Item Symbol min. typ.* max. Unit Condition
VIH 2.0 — — V
Input voltage VIL — — 0.8 V
VOH 2.7 — — V
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,
IOH = –400 µA
— — 0.5 IOL = 8 mA
Output voltage VOL — — 0.4 V IOL = 4 mA VCC = 4.75 V, VIL = 0.8 V,
VIH = 2 V
D — — 20
Clear — — 40
Preset — — 40
Clock
IIH
— — 20
µA VCC = 5.25 V, VI = 2.7 V
D — — –0.4
Clear — — –0.8
Preset — — –0.8
Clock
IIL
— — –0.4
mA VCC = 5.25 V, VI = 0.4 V
D — — 0.1
Clear — — 0.2
Preset — — 0.2
Input
current
Clock
II
— — 0.1
mA VCC = 5.25 V, VI = 7 V
Short-circuit output
current IOS –20 — –100 mA VCC = 5.25 V
Supply current ICC** — 4 8 mA VCC = 5.25 V
Input clamp voltag e VIR — — –1.5 V VCC = 4.75 V, IIN = –18 mA
Notes: * VCC = 5 V, Ta = 25°C
** With all output open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the
clock input is grounded.
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item Symbol Inputs Outputs min. typ. max. Unit Condition
Maximum clock frequency fmax 25 33 MHz
tPLH — 13 25 ns
Propagation delay time tPHL Clear, Clock
or Preset Q, Q — 25 40 ns
CL = 15 pF,
RL = 2 kΩ
Timing Definition
Data
Clock 0 V
3 V
0 V
3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V
"H" Data "L" Data
t
w
t
su
t
h
t
su
t
h
HD74LS74A
Rev.3.00, Jul.22.2005, page 4 of 7
Testing Method
Test Circuit
1. ƒmax, tPLH, tPHL (Clock→Q, Q)
PR
4.5V VCC Output Q
Output Q
Input
D
CK Q
Q
CLR
P.G.
Zout = 50Ω
Same as Load Circuit 1.
RLLoad circuit 1
CL
Input
P.G.
Zout = 50Ω
Notes: 1. Test is put into the each flip-flop.
2. CL includes probe and jig capacitance.
3. All diodes are 1S2074(H).
2. tPHL, tPLH (Clear or Preset→ Q, Q)
PR
VCC Output Q
Output Q
Q
Q
CLR Same as Load Circuit 1.
RLLoad circuit 1
CL
D
Input
P.G.
Zout = 50Ω
Input
P.G.
Zout = 50Ω
CK
Notes: 1. Test is put into the each flip-flop.
2. CL includes probe and jig capacitance.
3. All diodes are 1S2074(H).
HD74LS74A
Rev.3.00, Jul.22.2005, page 5 of 7
Waveforms 1
t
w
(H)
tPHL
VOH
VOL
0 V
3 V
0 V
3 V
VOH
VOL
t
w
(L)
tPHL
tPLH
tPLH
10%
90%
1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
10%
90%
Clock
D
Q
Q
tTLH tTHL
Note: Clock input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle = 50% and for fmax,
tTLH = tTHL ≤ 2.5 ns
Waveforms 2
Clear
Preset
Q
Q
V
OH
V
OH
V
OL
V
OL
0V
0V
3V
3V
1.3V 1.3V
1.3V 1.3V
1.3V
1.3V
t
THL
t
TLH
t
w (clear)
≥ 25ns
t
w (preset)
≥ 25ns
t
TLH
t
THL
t
PHL
t
PLH
10%10%
10% 10%
90% 90%
90% 90%
1.3V
1.3V
t
PLH
t
PHL
Note: Crear and presel input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz,
HD74LS74A
Rev.3.00, Jul.22.2005, page 6 of 7
Package Dimensions
( Ni/Pd/Au plating )
7.62
DP-14AV
RENESAS CodeJEITA Package Code Previous Code
MaxNomMin
Dimension in Millimeters
Symbol
Reference
19.2
6.3
5.06
MASS[Typ.]
A
Z
b
D
E
A
b
c
θ
e
L
1
1
p
3
e
0.51
0.56
1.30
0.19 0.25 0.31
2.29 2.54 2.79
0
°
15
°
PRDP0014AB-BP-DIP14-6.3x19.2-2.54
20.32
7.4
0.40 0.48
2.39
2.54
0.97g
814
7
1
p
3
1
1
b
D
E
e
Z
b
LA
A
c
e
θ
1.42
0.15
1.27
7.50 8.00
0.400.34
p
A
1
10.5
FP-14DAV
RENESAS CodeJEITA Package Code Previous Code
MaxNomMin
Dimension in Millimeters
Symbol
Reference
2.20
0.900.700.50
5.50
0.200.100.00
0.46
0.250.200.15
7.80
8
°
0
°
0.12
1.15
10.06
0.23g
MASS[Typ.]
1
E
1
1
2
L
Z
H
y
x
θ
c
b
A
E
D
b
c
e
L
A
P-SOP14-5.5x10.06-1.27 PRSP0014DF-B
Index mark
E
1
*2
*1
7
14 8
F
*3
p
Mx
y
D
E
H
Zb
A
p
Terminal cross section
( Ni/Pd/Au plating )
b
c
Detail F
1
1
L
L
A
θ
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
e
HD74LS74A
Rev.3.00, Jul.22.2005, page 7 of 7
14 8
7
F
*1
*2
*3
p
Mx
y
1
E
Index mark
b
A
Z
H
E
D
Terminal cross section
( Ni/Pd/Au plating )
p
b
c
1
1
Detail F
L
L
A
θ
PRSP0014DE-AP-SOP14-3.95x8.65-1.27
A
L
e
e
c
b
D
E
A
b
c
θ
x
y
H
Z
L
2
1
1
E
1
MASS[Typ.]
0.13g
8.65
1.08
0.25
0
°
8
°
6.10
0.15 0.20 0.25
0.46
0.10 0.14 0.25
3.95
0.40 0.60 1.27
1.75
Reference
Symbol
Dimension in Millimeters
Min Nom Max
Previous CodeJEITA Package Code RENESAS Code
FP-14DNV
9.05
1
A
p
0.34 0.40
6.205.80
1.27
0.15
0.635
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
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