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LMH6624
,
LMH6626
SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
LMH6624 and LMH6626 Single/Dual Ultra Low Noise Wideband Operational Amplifier
1 Features 3 Description
The LMH6624 and LMH6626 devices offer wide
1• VS= ±6 V, TA= 25°C, AV= 20 (Typical Values bandwidth (1.5 GHz for single, 1.3 GHz for dual) with
Unless Specified) very low input noise (0.92 nV/√Hz, 2.3 pA/√Hz) and
• Gain Bandwidth (LMH6624) 1.5 GHz ultra-low dc errors (100 μV VOS, ±0.1 μV/°C drift)
• Input Voltage Noise 0.92 nV/√Hz providing very precise operational amplifiers with
wide dynamic range. This enables the user to
• Input Offset Voltage (limit over temp) 700 µV achieve closed-loop gains of greater than 10, in both
• Slew Rate 350 V/μsinverting and non-inverting configurations.
• Slew Rate (AV= 10) 400 V/μsThe LMH6624 (single) and LMH6626 (dual)
• HD2 at f = 10 MHz, RL= 100 Ω −63 dBc traditional voltage feedback topology provide the
• HD3 at f = 10 MHz, RL= 100 Ω −80 dBc following benefits: balanced inputs, low offset voltage
and offset current, very low offset drift, 81dB open
• Supply Voltage Range (Dual Supply) 2.5 V to 6 V loop gain, 95dB common mode rejection ratio, and
• Supply Voltage Range (Single Supply) 5 V to 12 V 88dB power supply rejection ratio.
• Improved Replacement for the CLC425 The LMH6624 and LMH6626 devices operate from
(LMH6624) ±2.5 V to ±6 V in dual supply mode and from 5 V to
• Stable for Closed Loop |AV|≥10 12 V in single supply configuration.
LMH6624 is offered in SOT-23-5 and SOIC-8
2 Applications packages. The LMH6626 is offered in SOIC-8 and
• Instrumentation Sense Amplifiers VSSOP-8 packages.
• Ultrasound Pre-amps Device Information(1)
• Magnetic Tape & Disk Pre-amps PART NUMBER PACKAGE BODY SIZE (NOM)
• Wide Band Active Filters SOT-23 (5) 2.90 mm × 1.60 mm
• Professional Audio Systems LMH6624 SOIC (8) 4.90 mm × 3.91 mm
• Opto-electronics SOIC (8) 4.90 mm × 3.91 mm
LMH6626
• Medical Diagnostic Systems VSSOP (8) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Voltage Noise vs. Frequency
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6624
,
LMH6626
SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
www.ti.com
Table of Contents
7.3 Device Functional Modes........................................ 22
1 Features.................................................................. 18 Application and Implementation ........................ 23
2 Applications ........................................................... 18.1 Application Information............................................ 23
3 Description............................................................. 18.2 Typical Application.................................................. 23
4 Revision History..................................................... 29 Power Supply Recommendations...................... 26
5 Pin Configuration and Functions......................... 310 Layout................................................................... 26
6 Specifications......................................................... 410.1 Layout Guidelines ................................................. 26
6.1 Absolute Maximum Ratings ...................................... 410.2 Layout Example .................................................... 27
6.2 ESD Ratings.............................................................. 411 Device and Documentation Support................. 28
6.3 Recommended Operating Conditions....................... 411.1 Documentation Support ........................................ 28
6.4 Thermal Information.................................................. 411.2 Related Links ........................................................ 28
6.5 Electrical Characteristics ±2.5 V .............................. 511.3 Trademarks........................................................... 28
6.6 Electrical Characteristics ±6 V ................................. 711.4 Electrostatic Discharge Caution............................ 28
6.7 Typical Characteristics.............................................. 911.5 Glossary................................................................ 28
7 Detailed Description............................................ 17 12 Mechanical, Packaging, and Orderable
7.1 Overview................................................................. 17 Information........................................................... 28
7.2 Feature Description................................................. 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (March 2013) to Revision G Page
• Added, updated, or renamed the following sections: Device Information Table, Pin Configuration and Functions,
Application and Implementation;Power Supply Recommendations;Layout;Device and Documentation Support;
Mechanical, Packaging, and Ordering Information ............................................................................................................... 1
• Added Input Current parameter in Absolute Maximum Ratings ............................................................................................ 4
• Added Operating supply voltage (V+ - V-) parameter in Recommended Operating Conditions............................................ 4
• Revised paragraph beginning with "As seen in ..." in Total Input Noise vs. Source Resistance ........................................ 19
• Changed from 33.5 Ωto 26 Ωin Total Input Noise vs. Source Resistance......................................................................... 19
• Changed from 6.43 kΩto 3.1 kΩin Total Input Noise vs. Source Resistance.................................................................... 19
Changes from Revision E (March 2013) to Revision F Page
• Changed layout of National Data Sheet to TI format ............................................................................................................. 1
• Changed from 464 Ωto 283 Ω............................................................................................................................................. 19
2Submit Documentation Feedback Copyright © 2002–2014, Texas Instruments Incorporated
Product Folder Links: LMH6624 LMH6626
OUT
V-
+IN
V+
-IN
+-
1
2
3
5
4
V+
1
2
3
4 5
6
7
8
N/C
-IN
+IN
V-
N/C
OUT
N/C
-
+
LMH6624
,
LMH6626
www.ti.com
SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
5 Pin Configuration and Functions
8-Pin SOIC Package D and VSSOP
5-Pin SOT-23 (LMH6624) 8-Pin SOIC (LMH6624) (LMH6626)
Package DBV Package D Package D or DGK
Top View Top View Top View
Pin Functions
PIN
NUMBER I/O DESCRIPTION
NAME LMH6624 LMH6626
DBV D DGK or D
-IN 4 2 – I Inverting Input
+IN 3 3 – I Non-inverting Input
IN A- – – 2 I Inverting Input Channel A
IN B- – – 6 I Inverting Input Channel B
IN A+ – – 3 I Non-inverting Input Channel A
IN B+ – – 5 I Non-inverting Input Channel B
N/C – 1, 5, 8 – –– No Connection
OUT 1 6 – O Output
OUT A – – 1 O Output Channel A
OUT B – – 7 O Output Channel B
V- 2 4 4 I Negative Supply
V+ 5 7 8 I Positive Supply
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,
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SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN Differential ±1.2 V
Supply voltage (V+- V−) 13.2 V
V++0.5,
Voltage at Input pins V
V−−0.5
Input Current ±10 mA
Infrared or convection (20 sec.) 235 °C
Soldering information Wave soldering (10 sec.) 260 °C
Junction temperature(2) 150 °C
Storage temperature -65 150 °C
(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
6.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Machine model(2) ±200
(1) Human body model, 1.5 kΩin series with 100 pF. JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a
standard ESD control process. Manufacturing with less than 2000-V HBM is possible with the necessary precautions. Pins listed as
±2000 V may actually have higher performance.
(2) Machine Model, 0 Ωin series with 200 pF. JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard
ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Operating temperature(2) −40 +125 °C
Operating supply voltage (V+ - V-) ±2.25 ±6.3 V
(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
6.4 Thermal Information LMH6624 LMH6626
THERMAL METRIC(1) DBV D DGK D UNIT
5 PINS 8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance(2) 265 166 235 166 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) - TA)/ RθJA . All numbers apply for packages soldered directly onto a PC board.
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SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
6.5 Electrical Characteristics ±2.5 V
Unless otherwise specified, all limits ensured at TA= 25°C, V+= 2.5 V, V−=−2.5 V, VCM = 0 V, AV= +20, RF= 500 Ω,
RL= 100 Ω. See (1).
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
DYNAMIC PERFORMANCE
VO= 400 mVPP (LMH6624) 90
fCL −3dB BW MHz
VO= 400 mVPP (LMH6626) 80
VO= 2 VPP, AV= +20 (LMH6624) 300
VO= 2 VPP, AV= +20 (LMH6626) 290
SR Slew rate(4) V/μs
VO= 2 VPP, AV= +10 (LMH6624) 360
VO= 2 VPP, AV= +10 (LMH6626) 340
trRise time VO= 400 mV Step, 10% to 90% 4.1 ns
tfFall time VO= 400 mV Step, 10% to 90% 4.1 ns
tsSettling time 0.1% VO= 2 VPP (Step) 20 ns
DISTORTION and NOISE RESPONSE
f = 1 MHz (LMH6624) 0.92
enInput referred voltage noise nV/√Hz
f = 1 MHz (LMH6626) 1.0
f = 1 MHz (LMH6624) 2.3
inInput referred current noise pA/√Hz
f = 1 MHz (LMH6626) 1.8
HD2 2nd harmonic distortion fC= 10 MHz, VO= 1 VPP, RL100 Ω −60 dBc
HD3 3rd harmonic distortion fC= 10 MHz, VO= 1 VPP, RL100 Ω −76 dBc
INPUT CHARACTERISTICS
−0.75 −0.25 +0.75
Input offset voltage VCM = 0 V mV
VOS -40°C ≤TJ≤125°C −0.95 +0.95
Average drift(5) VCM = 0 V ±0.25 μV/°C
−1.5 −0.05 +1.5
Input offset current VCM = 0 V μA
IOS -40°C ≤TJ≤125°C −2.0 +2.0
Average drift(5) VCM = 0 V 2 nA/°C
13 +20
Input bias current VCM = 0 V μA
IB-40°C ≤TJ≤125°C +25
Average drift(5) VCM = 0 V 12 nA/°C
Common Mode 6.6 MΩ
RIN Input resistance(6) Differential Mode 4.6 kΩ
Common Mode 0.9
CIN Input capacitance(6) pF
Differential Mode 2.0
Input Referred, VCM =−0.5 to +1.9 V 87 90
Common mode rejection
CMRR dB
Input Referred,
ratio -40°C ≤TJ≤125°C 85
VCM =−0.5 to +1.75 V
(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ> TA. Absolute maximum ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
(2) All limits are specified by testing or statistical analysis.
(3) Typical Values represent the most likely parametric norm.
(4) Slew rate is the slowest of the rising and falling slew rates.
(5) Average drift is determined by dividing the change in parameter at temperature extremes into the total temperature change.
(6) Simulation results.
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Electrical Characteristics ±2.5 V (continued)
Unless otherwise specified, all limits ensured at TA= 25°C, V+= 2.5 V, V−=−2.5 V, VCM = 0 V, AV= +20, RF= 500 Ω,
RL= 100 Ω. See (1).
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
TRANSFER CHARACTERISTICS
75 79
(LMH6624)
RL= 100 Ω, VO=−1 V to +1 V -40°C ≤TJ≤125°C 70
AVOL Large signal voltage gain dB
72 79
(LMH6626)
RL= 100 Ω, VO=−1 V to +1 V -40°C ≤TJ≤125°C 67
XtCrosstalk rejection f = 1 MHz (LMH6626) −75 dB
OUTPUT CHARACTERISTICS
±1.1 ±1.5
RL= 100 Ω-40°C ≤TJ≤125°C ±1.0
VOOutput swing V
±1.4 ±1.7
No Load -40°C ≤TJ≤125°C ±1.25
ROOutput impedance f ≤100 KHz 10 mΩ
(LMH6624) 90 145
Sourcing to Ground -40°C ≤TJ≤125°C 75
ΔVIN = 200 mV (7)(8)
(LMH6624) 90 145
Sinking to Ground -40°C ≤TJ≤125°C 75
ΔVIN =−200 mV (7)(8)
ISC Output short circuit current mA
(LMH6626) 60 120
Sourcing to Ground -40°C ≤TJ≤125°C 50
ΔVIN = 200 mV (7)(8)
(LMH6626) 60 120
Sinking to Ground -40°C ≤TJ≤125°C 50
ΔVIN =−200 mV (7)(8)
(LMH6624)
Sourcing, VO= +0.8 V 100
Sinking, VO=−0.8 V
IOUT Output current mA
(LMH6626)
Sourcing, VO= +0.8 V 75
Sinking, VO=−0.8 V
POWER SUPPLY
82 90
PSRR Power supply rejection ratio VS= ±2.0 V to ±3.0 V dB
-40°C ≤TJ≤125°C 80 11.4 16
ISSupply current (per channel) No Load mA
-40°C ≤TJ≤125°C 18
(7) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
(8) Short circuit test is a momentary test. Output short circuit duration is 1.5 ms.
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SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
6.6 Electrical Characteristics ±6 V
Unless otherwise specified, all limits ensured at TA= 25°C, V+= 6 V, V−=−6 V, VCM = 0 V, AV= +20, RF= 500 Ω,
RL= 100 Ω. See (1).
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
DYNAMIC PERFORMANCE
VO= 400 mVPP (LMH6624) 95
fCL −3dB BW MHz
VO= 400 mVPP (LMH6626) 85
VO= 2 VPP, AV= +20 (LMH6624) 350
VO= 2 VPP, AV= +20 (LMH6626) 320
SR Slew rate(4) V/μs
VO= 2 VPP, AV= +10 (LMH6624) 400
VO= 2 VPP, AV= +10 (LMH6626) 360
trRise time VO= 400 mV Step, 10% to 90% 3.7 ns
tfFall time VO= 400 mV Step, 10% to 90% 3.7 ns
tsSettling time 0.1% VO= 2 VPP (Step) 18 ns
DISTORTION and NOISE RESPONSE
f = 1 MHz (LMH6624) 0.92
enInput referred voltage noise nV/√Hz
f = 1 MHz (LMH6626) 1.0
f = 1 MHz (LMH6624) 2.3
inInput referred current noise pA/√Hz
f = 1 MHz (LMH6626) 1.8
HD2 2nd harmonic distortion fC= 10 MHz, VO= 1 VPP, RL= 100 Ω −63 dBc
HD3 3rd harmonic distortion fC= 10 MHz, VO= 1 VPP, RL= 100 Ω −80 dBc
INPUT CHARACTERISTICS
−0.5 ±0.10 +0.5
Input offset voltage VCM = 0 V mV
VOS -40°C ≤TJ≤125°C −0.7 +0.7
Average drift(5) VCM = 0 V ±0.2 μV/°C
−1.1 0.05 1.1
(LMH6624)
VCM = 0 V -40°C ≤TJ≤125°C −2.5 2.5
Input offset current μA
IOS −2.0 0.1 2.0
(LMH6626)
VCM = 0 V -40°C ≤TJ≤125°C −2.5 2.5
Average drift(5) VCM = 0 V 0.7 nA/°C
13 +20
Input bias current VCM = 0 V μA
IB-40°C ≤TJ≤125°C +25
Average drift(5) VCM = 0 V 12 nA/°C
Common Mode 6.6 MΩ
RIN Input resistance(6) Differential Mode 4.6 kΩ
Common Mode 0.9
CIN Input capacitance(6) pF
Differential Mode 2.0
Input Referred, VCM =−4.5 to +5.25 V 90 95
Common mode rejection
CMRR dB
Input Referred,
ratio -40°C ≤TJ≤125°C 87
VCM =−4.5 to +5.0 V
(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ> TA. Absolute maximum ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
(2) All limits are specified by testing or statistical analysis.
(3) Typical Values represent the most likely parametric norm.
(4) Slew rate is the slowest of the rising and falling slew rates.
(5) Average drift is determined by dividing the change in parameter at temperature extremes into the total temperature change.
(6) Simulation results.
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,
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Electrical Characteristics ±6 V (continued)
Unless otherwise specified, all limits ensured at TA= 25°C, V+= 6 V, V−=−6 V, VCM = 0 V, AV= +20, RF= 500 Ω,
RL= 100 Ω. See (1).
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
TRANSFER CHARACTERISTICS
77 81
(LMH6624)
RL= 100 Ω, VO=−3 V to +3 V -40°C ≤TJ≤125°C 72
AVOL Large signal voltage gain dB
74 80
(LMH6626)
RL= 100 Ω, VO=−3 V to +3 V -40°C ≤TJ≤125°C 70
XtCrosstalk rejection f = 1MHz (LMH6626) −75 dB
OUTPUT CHARACTERISTICS
±4.4 ±4.9
(LMH6624)
RL= 100 Ω-40°C ≤TJ≤125°C ±4.3
±4.8 ±5.2
(LMH6624)
No Load -40°C ≤TJ≤125°C ±4.65
VOOutput swing V
±4.3 ±4.8
(LMH6626)
RL= 100 Ω-40°C ≤TJ≤125°C ±4.2
±4.8 ±5.2
(LMH6626)
No Load -40°C ≤TJ≤125°C ±4.65
ROOutput impedance f ≤100 KHz 10 mΩ
(LMH6624) 100 156
Sourcing to Ground -40°C ≤TJ≤125°C 85
ΔVIN = 200 mV (7)(8)
(LMH6624) 100 156
Sinking to Ground -40°C ≤TJ≤125°C 85
ΔVIN =−200 mV (7)(8)
ISC Output short circuit current mA
(LMH6626) 65 120
Sourcing to Ground -40°C ≤TJ≤125°C 55
ΔVIN = 200 mV (7)(8)
(LMH6626) 65 120
Sinking to Ground -40°C ≤TJ≤125°C 55
ΔVIN =−200 mV(7)(8)
(LMH6624)
Sourcing, VO= +4.3 V 100
Sinking, VO=−4.3 V
IOUT Output current mA
(LMH6626)
Sourcing, VO= +4.3 V 80
Sinking, VO=−4.3 V
POWER SUPPLY
82 88
PSRR Power supply rejection ratio VS= ±5.4 V to ±6.6 V dB
-40°C ≤TJ≤125°C 80 12 16
ISSupply current (per channel) No Load mA
-40°C ≤TJ≤125°C 18
(7) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
(8) Short circuit test is a momentary test. Output short circuit duration is 1.5 ms.
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5
1k 100k 10M 1G
Frequency (Hz)
-5
-3
2
Normalized Gain (dB)
100M
1M
10k
4
3
1
0
-4
-2
-1 AV = +200
AV = +100
AV = +40
AV = +30
AV = +20
AV = +10
5
1k 100k 10M 1G
Frequency (Hz)
-5
-2
2
Normalized Gain (dB)
100M1M
10k
4
3
0
-1
-4
1
-3
AV = +200
AV = +100
AV = +40
AV = +30
AV = +10
AV = +20
5
1k 100k 10M 1G
Frequency (Hz)
-4
-2
2
Normalized Gain (dB)
100M1M
10k
4
3
1
0
-3
-1
-5
AV = -10
AV = -40
AV = -60
AV = -80
AV = -100
AV = -20
5
1k 100k 10M 1G
Frequency (Hz)
-4
-2
2
Normalized Gain (dB)
100M1M
10k
4
3
1
0
-3
-1
-5
AV = -10
AV = -40
AV = -60
AV = -80
AV = -100
AV = -20
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,
LMH6626
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6.7 Typical Characteristics
Figure 1. Voltage Noise vs. Frequency Figure 2. Current Noise vs. Frequency
VS= ±2.5 V VS= ±6V
VIN = 5 mVpp VIN = 5 mVpp
RL= 100 ΩRL= 100 Ω
Figure 3. Inverting Frequency Response Figure 4. Inverting Frequency Response
VS= ±2.5 V VS= ±6 V
RF= 500 ΩRF= 500 Ω
VO= 2 Vpp VO= 2 Vpp
Figure 5. Non-Inverting Frequency Response Figure 6. Non-Inverting Frequency Response
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1M 10M 100M 1G
Frequency (Hz)
-5
-4
-3
-2
-1
0
1
2
3
4
5
Normalized Gain (dB)
33 pF
15 pF
5 pF
10 pF
0 pF
1M 10M 100M 1G
Frequency (Hz)
-5
-4
-3
-2
-1
0
1
2
3
4
5
Normalized Gain (dB)
33 pF
15 pF
5 pF
10 pF
0 pF
1M 10M 100M 1G
Frequency (Hz)
-5
-4
-3
-2
-1
0
1
2
3
4
5
Normalized Gain (dB)
33 pF
15 pF
10 pF
5 pF
0 pF
1M 10M 100M 1G
Frequency (Hz)
-5
-4
-3
-2
-1
0
1
2
3
4
5
Normalized Gain (dB)
33 pF
15 pF
10 pF
5 pF
0 pF
100k 1M 10M 100M 1G
Frequency (Hz)
Gain (dB)
GAIN
PHASE
125°C
-40°C
25°C
125°C
25°C
-40°C
0
10
20
30
40
50
60
70
80
-360
-315
-270
-225
-180
-135
-90
-45
0
Phase (°)
LMH6624
,
LMH6626
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Typical Characteristics (continued)
VS= ±2.5 V VS= ±6V
RL= 100 Ω
Figure 7. Open Loop Frequency Response Figure 8. Open Loop Frequency Response
Over Temperature Over Temperature
VS= ±2.5V RISO = 10 ΩVS= ±6V RISO = 10 Ω
AV= +10 RL= 1 kΩ||CLAV= +10 RL= 1 kΩ||CL
RF= 250 ΩRF= 250 Ω
Figure 9. Frequency Response with Cap. Loading Figure 10. Frequency Response with Cap. Loading
VS= ±2.5 V RISO = 100 ΩVS= ±6 V RISO = 10 Ω
AV= +10 RL= 1 kΩ||CLAV= +10 RL= 1 kΩ||CL
RF= 250 ΩRF= 250 Ω
Figure 11. Frequency Response with Cap. Loading Figure 12. Frequency Response with Cap. Loading
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100k 1M 10M 100M 1G
Frequency (Hz)
-5
-4
-3
-2
-1
0
1
2
3
4
5
Normalized Gain (dB)
VIN = 20 mV
VIN = 200 mV
100k 1M 10M 100M 1G
Frequency (Hz)
-5
-4
-3
-2
-1
0
1
2
3
4
5
Normalized Gain (dB)
VIN = 200 mV
VIN = 20 mV
100k 1M 10M 100M 1G
Frequency (Hz)
-5
-4
-3
-2
-1
0
1
2
3
4
5
Normalized Gain (dB)
VIN = 20 mV
VIN = 200 mV
100k 1M 10M 100M 1G
Frequency (Hz)
-5
-4
-3
-2
-1
0
1
2
3
4
5
Normalized Gain (dB)
VIN = 200 mV
VIN = 20 mV
100k 1M 10M 100M 1G
Frequency (Hz)
-5
-4
-3
-2
-1
0
1
2
3
4
5
Normalized Gain (dB)
VIN = 200 mV
VIN = 20 mV
100k 1M 10M 100M 1G
Frequency (Hz)
-5
-4
-3
-2
-1
0
1
2
3
4
5
Normalized Gain (dB)
VIN = 200 mV
VIN = 20 mV
LMH6624
,
LMH6626
www.ti.com
SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
Typical Characteristics (continued)
VS= ±-2.5 V VS= ±6 V
AV= +10 AV= +10
RF= 500 ΩRF= 500 Ω
Figure 13. Non-Inverting Frequency Response Varying VIN Figure 14. Non-Inverting Frequency Response Varying VIN
VS= ±2.5 V VS= ±2.5 V
AV= +20 AV= +20
RF= 500 ΩRF= 500 Ω
Figure 15. Non-Inverting Frequency Response Varying VIN Figure 16. Non-Inverting Frequency Response Varying VIN
(LMH6624) (LMH6626)
VS= ±6 V VS= ±6 V
AV= +20 AV= +20
RF= 500 ΩRF= 500 Ω
Figure 17. Non-Inverting Frequency Response Varying VIN Figure 18. Non-Inverting Frequency Response Varying VIN
(LMH6624) (LMH6626)
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Product Folder Links: LMH6624 LMH6626
45 6 7 8 9 10 11 12
VSUPPLY (V)
-300
-250
-200
-150
-100
-50
0
50
VOS (PV)
125°C
25°C
-40°C
4567 8 9 10 11 12
VSUPPLY (V)
-250
-200
-150
-100
-50
0
50
100
150
VOS (PV)
25°C
125°C
-40°C
0 1 2 3 4 5
0
20
40
60
80
100
120
140
ISOURCE (mA)
VOUT (V)
-40°C
25°C
125°C
0 1 2 3 4 5
0
20
40
60
80
100
120
140
160
180
ISOURCE (mA)
VOUT (V)
125°C
25°C
-40°C
0 0.5 1 1.5
0
20
40
60
80
100
120
140
ISOURCE (mA)
VOUT (V)
-40°C
125°C 25°C
0 0.5 1 1.5
0
20
40
60
80
100
120
140
160
ISOURCE (mA)
VOUT (V)
125°C 25°C
-40°C
LMH6624
,
LMH6626
SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
www.ti.com
Typical Characteristics (continued)
VS= ±2.5 V VS= ±2.5 V
Figure 19. Sourcing Current vs. VOUT (LMH6624) Figure 20. Sourcing Current vs. VOUT (LMH6626)
VS= ±6 V VS= ±6 V
Figure 21. Sourcing Current vs. VOUT (LMH6624) Figure 22. Sourcing Current vs. VOUT (LMH6626)
Figure 23. VOS vs. VSUPPLY (LMH6624) Figure 24. VOS vs. VSUPPLY (LMH6626)
12 Submit Documentation Feedback Copyright © 2002–2014, Texas Instruments Incorporated
Product Folder Links: LMH6624 LMH6626
45 6 7 8 9 10 11 12
VSUPPLY (V)
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
IOS (PA)
125°C
25°C
-40°C
1k 100k 100M
Frequency (Hz)
-140
-100
-60
0
Crosstalk (dB)
10M
1M
10k
-20
-80
-120
-40
VS = ±6 V
VS = ±2.5 V
CH 1 OUTPUT
CH 2 OUTPUT
0 1 2 3 4 5
0
20
40
60
80
100
120
140
ISINK (mA)
VOUT (V)
-40°C
25°C
125°C
0 1 2 3 4 5
0
20
40
60
80
100
120
140
160
180
ISINK (mA)
VOUT (V)
125°C 25°C
-40°C
0 0.5 1 1.5
0
20
40
60
80
100
120
140
ISINK (mA)
VOUT (V)
-40°C
125°C 25°C
0 0.5 1 1.5
-20
0
20
40
60
80
100
120
140
160
ISINK (mA)
VOUT (V)
125°C 25°C
-40°C
LMH6624
,
LMH6626
www.ti.com
SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
Typical Characteristics (continued)
VS= ±2.5 V VS= ±2.5V
Figure 25. Sinking Current vs. VOUT (LMH6624) Figure 26. Sinking Current vs. VOUT (LMH6626)
VS= ±6 V VS= ±6 V
Figure 27. Sinking Current vs. VOUT (LMH6624) Figure 28. Sinking Current vs. VOUT (LMH6626)
VIN = 60 mVpp
AV= +20
RL= 100 Ω
Figure 30. Crosstalk Rejection vs. Frequency (LMH6626)
Figure 29. IOS vs. VSUPPLY
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Product Folder Links: LMH6624 LMH6626
02 4 6 8 10 12
VOUT (VPP)
-120
-100
-80
-60
-40
-20
0
Distortion (dBc)
fC = 10 MHz
fC = 1 MHz
HD2
HD3
00.5 1 1.5 2 2.5 3 3.5 4
VOUT (V)
-120
-100
-80
-60
-40
-20
0
Distortion (dBc)
HD2
HD3
fC = 10 MHz
fC = 1 MHz
100k 1M 10M 100M
Frequency (Hz)
-140
-120
-100
-80
-60
-40
-20
0
Distortion (dBc)
VS = ±2.5 V,
VO = 1 VPP
VS = ±6 V, VO = 2 VPP
HD2
HD3
0 20 40 60 80 100
-100
-90
-80
-70
-60
-50
Distortion (dBc)
Gain (V/V)
VS = ±6 V
VO = 2 VPP
HD2
HD3
VS = ±2.5 V
VO = 1 VPP
100k 1M 10M 100M
Frequency (Hz)
-140
-120
-100
-80
-60
-40
-20
0
Distortion (dBc)
HD3
HD2
VS = ±6 V, VO = 2 VPP
VS = ±2.5 V, VO = 1 VPP
100k 1M 10M 100M
Frequency (Hz)
-120
-100
-80
-60
-40
-20
0
Distortion (dBc)
VS = ±6 V,
VO = 2 VPP
VS = ±2.5 V,
VO = 1 VPP
HD2
HD3
LMH6624
,
LMH6626
SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
www.ti.com
Typical Characteristics (continued)
AV= +10 AV= +20
RL= 100 ΩRL= 100 Ω
Figure 31. Distortion vs. Frequency Figure 32. Distortion vs. Frequency
AV= +20 VS= ±6 V
RL= 500 ΩVO= 2 Vpp
Figure 33. Distortion vs. Frequency Figure 34. Distortion vs. Gain
AV= +20 AV= +20
AV= ±2.5V VS= ±6 V
RL= 100 ΩRL= 100 Ω
Figure 35. Distortion vs. VOUT Peak to Peak Figure 36. Distortion vs. VOUT Peak to Peak
14 Submit Documentation Feedback Copyright © 2002–2014, Texas Instruments Incorporated
Product Folder Links: LMH6624 LMH6626
0
1k 100k 10M 1G
Frequency (Hz)
-100
-80
-50
PSRR (dB)
100M1M
10k
-10
-20
-60
-70
-90
-40
-30 +PSRR, AV +20
+PSRR, AV +10
-PSRR, AV +20
-PSRR, AV +10
0
1k 100k 10M 1G
Frequency (Hz)
-140
-100
-60
PSRR (dB)
100M
1M
10k
-20
-40
-80
-120
+PSRR, AV = +20
+PSRR, AV = +10
-PSRR, AV = +20
-PSRR, AV = +10
50 mV/DIV
10 ns/DIV
100 mV/DIV
10 ns/DIV
200 mV/DIV
10 ns/DIV
200 mV/DIV
10 ns/DIV
LMH6624
,
LMH6626
www.ti.com
SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
Typical Characteristics (continued)
VS= ±2.5 V RL= 100 ΩVS= ±6 V RL= 100 Ω
VO= 1 Vpp VO= 1 Vpp
AV= +10 AV= +20
Figure 37. Non-Inverting Large Signal Pulse Response Figure 38. Non-Inverting Large Signal Pulse Response
VS= ±2.5 V RL= 100 ΩVS= ±6 V RL= 100 Ω
VO= 200 mv VO= 500 mv
AV= +10 AV= +20
Figure 39. Non-Inverting Small Signal Pulse Response Figure 40. Non-Inverting Small Signal Pulse Response
VS= ±2.5 V VS= ±6 V
Figure 41. PSRR vs. Frequency Figure 42. PSRR vs. Frequency
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Product Folder Links: LMH6624 LMH6626
10M 100M 1G
Frequency (Hz)
-5
-4
-3
-2
-1
0
1
2
3
4
5
Normalized Gain (dB)
RF = 2 k:
RF = 1.5 k:
RF = 1 k:
RF = 511 :
RF = 750 :
10M 100M 1G
Frequency (Hz)
-5
-4
-3
-2
-1
0
1
2
3
4
5
Normalized Gain (dB)
RF = 2 k:
RF = 1.5 k:
RF = 1 k:
RF = 511 :
RF = 750 :
1k 100k 100M
Frequency (Hz)
-90
-70
0
CMRR (dB)
10M
1M
10k
-20
-30
-80
-10
-40
-50
-60
AV = +10
AV = +20
1k 100k 100M
Frequency (Hz)
-90
-70
0
CMRR (dB)
10M
1M
10k
-20
-30
-80
-10
-40
-50
-60 AV = +10
AV = +20
LMH6624
,
LMH6626
SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
www.ti.com
Typical Characteristics (continued)
VS= ±2.5V VS= ±6 V
VIN = 5 mVpp VIN = 5 mVpp
Figure 43. Input Referred CMRR vs. Frequency Figure 44. Input Referred CMRR vs. Frequency
VS= ±2.5 V VS= ±6 V
AV= +10 AV= +10 V
RL= 100 ΩRL= 100 Ω
Figure 45. Amplifier Peaking with Varying RFFigure 46. Amplifier Peaking with Varying RF
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Product Folder Links: LMH6624 LMH6626
LMH6624
,
LMH6626
www.ti.com
SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
7 Detailed Description
7.1 Overview
The LMH6624 and LMH6626 devices are very wide gain bandwidth, ultra low noise voltage feedback operational
amplifiers. Their excellent performances enable applications such as medical diagnostic ultrasound, magnetic
tape & disk storage and fiber-optics to achieve maximum high frequency signal-to-noise ratios. The set of
characteristic plots in Typical Characteristics illustrates many of the performance trade-offs. The following
discussion will demonstrate the proper selection of external components to achieve optimum system
performance.
7.2 Feature Description
7.2.1 Bias Current Cancellation
To cancel the bias current errors of the non-inverting configuration, the parallel combination of the gain setting
(Rg) and feedback (Rf) resistors should equal the equivalent source resistance (Rseq) as defined in Figure 47.
Combining this constraint with the non-inverting gain equation also seen in Figure 47, allows both Rfand Rgto
be determined explicitly from the following equations:
Rf= AVRseq (1)
Rg= Rf/(AV-1) (2)
When driven from a 0-Ωsource, such as the output of an op amp, the non-inverting input of the LMH6624 and
LMH6626 should be isolated with at least a 25-Ωseries resistor.
As seen in Figure 48, bias current cancellation is accomplished for the inverting configuration by placing a
resistor (Rb) on the non-inverting input equal in value to the resistance seen by the inverting input (Rf||(Rg+Rs)).
Rbshould to be no less than 25 Ωfor optimum LMH6624 and LMH6626 performance. A shunt capacitor can
minimize the additional noise of Rb.
Figure 47. Non-Inverting Amplifier Configuration
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,
LMH6626
SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
www.ti.com
Feature Description (continued)
Figure 48. Inverting Amplifier Configuration
7.2.2 Total Input Noise vs. Source Resistance
To determine maximum signal-to-noise ratios from the LMH6624 and LMH6626, an understanding of the
interaction between the amplifier’s intrinsic noise sources and the noise arising from its external resistors is
necessary.
Figure 49 describes the noise model for the non-inverting amplifier configuration showing all noise sources. In
addition to the intrinsic input voltage noise (en) and current noise (in= in+= in−) source, there is also thermal
voltage noise (et=√(4KTR)) associated with each of the external resistors. Equation 3 provides the general form
for total equivalent input voltage noise density (eni). Equation 4 is a simplification of Equation 3 that assumes
Rf||Rg= Rseq for bias current cancellation. Figure 50 illustrates the equivalent noise model using this assumption.
Figure 51 is a plot of eni against equivalent source resistance (Rseq) with all of the contributing voltage noise
sources of Equation 4. This plot gives the expected eni for a given (Rseq) which assumes Rf||Rg= Rseq for bias
current cancellation. The total equivalent output voltage noise (eno) is eni*AV.
Figure 49. Non-Inverting Amplifier Noise Model
(3)
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10 100 1k 10k 100k
RSEQ (:)
0.1
1
10
100
VOLTAGE NOISE DENSITY (nV/ Hz)
eni en
et
in
LMH6624
,
LMH6626
www.ti.com
SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
Feature Description (continued)
Figure 50. Noise Model with Rf||Rg= Rseq
(4)
As seen in Figure 51, eni is dominated by the intrinsic voltage noise (en) of the amplifier for equivalent source
resistances below 26 Ω. Between 26 Ωand 3.1 kΩ, eni is dominated by the thermal noise (et=√(4kT(2Rseq)) of
the equivalent source resistance Rseq. Above 3.1 kΩ, eni is dominated by the amplifier’s current noise (in=√2
inRseq). When Rseq = 283 Ω(that is, Rseq = en/√2 in) the contribution from voltage noise and current noise of
LMH6624 and LMH6626 is equal. For example, configured with a gain of +20V/V giving a −3 dB of 90 MHz and
driven from Rseq = Rf || Rg = 25 Ω(eni = 1.3 nV√Hz from Figure 51), the LMH6624 produces a total output noise
voltage (eni × 20 V/V × √(1.57 × 90 MHz)) of 309 μVrms.
Figure 51. Voltage Noise Density vs. Source Resistance
If bias current cancellation is not a requirement, then Rf|| Rgneed not equal Rseq. In this case, according to
Equation 3, Rf|| Rgshould be as low as possible to minimize noise. Results similar to Equation 3 are obtained
for the inverting configuration of Figure 48 if Rseq is replaced by Rband Rgis replaced by Rg+ Rs. With these
substitutions, Equation 3 will yield an eni referred to the non-inverting input. Referring eni to the inverting input is
easily accomplished by multiplying eni by the ratio of non-inverting to inverting gains.
Copyright © 2002–2014, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LMH6624 LMH6626
RB
RF
CR
RSVO
VIN -
+
50:
50:
RG
RF = RB
RG = RS||R
VO #VIN KO
sRSC;KO = 1 + RF
RG
n
OPT
n
e
R
i
»
NF = 10 LOG
en + in (RSeq + (Rf||Rg) ) + 4KT (RSeq + (Rf||Rg))
2
4KT (RSeq + (Rf||Rg))
222
LMH6624
,
LMH6626
SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
www.ti.com
Feature Description (continued)
7.2.3 Noise Figure
Noise Figure (NF) is a measure of the noise degradation caused by an amplifier.
(5)
The Noise Figure formula is shown in Equation 5. The addition of a terminating resistor RT, reduces the external
thermal noise but increases the resulting NF. The NF is increased because RTreduces the input signal amplitude
thus reducing the input SNR.
(6)
The noise figure is related to the equivalent source resistance (Rseq) and the parallel combination of Rfand Rg.
To minimize "Noise Figure":
• Minimize Rf|| Rg
• Choose the Optimum RS(ROPT)
ROPT is the point at which the NF curve reaches a minimum and is approximated by:
(7)
7.2.4 Low Noise Integrator
The LMH6624 and LMH6626 devices implement a deBoo integrator shown in Figure 52. Positive feedback
maintains integration linearity. The low input offset voltage of the LMH6624 and LMH6626 devices and matched
inputs allow bias current cancellation and provide for very precise integration. Keeping RGand RSlow helps
maintain dynamic stability.
Figure 52. Low Noise Integrator
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Product Folder Links: LMH6624 LMH6626
C1
+
-
R2
R1
C2
RG
RF
LMH6624
,
LMH6626
www.ti.com
SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
Feature Description (continued)
7.2.5 High-gain Sallen-key Active Filters
The LMH6624 and LMH6626 devices are well suited for high gain Sallen-Key type of active filters. Figure 53
shows the 2nd order Sallen-Key low pass filter topology. Using component predistortion methods discussed in
Application Note OA-21, Component Pre-Distortion for Sallen Key Filters (SNOA369) will enable the proper
selection of components for these high-frequency filters.
Figure 53. Sallen-Key Active Filter Topology
7.2.6 Low Noise Magnetic Media Equalizer
The LMH6624 and LMH6626 devices implement a high-performance low noise equalizer for such application as
magnetic tape channels as shown in Figure 54. The circuit combines an integrator with a bandpass filter to
produce the low noise equalization. The circuit’s simulated frequency response is illustrated in Figure 55.
Figure 54. Low Noise Magnetic Media Equalizer
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Product Folder Links: LMH6624 LMH6626
LMH6624
,
LMH6626
SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
www.ti.com
Feature Description (continued)
Figure 55. Equalizer Frequency Response
7.3 Device Functional Modes
7.3.1 Single Supply Operation
The LMH6624 and LMH6626 devices can be operated with single power supply as shown in Figure 56. Both the
input and output are capacitively coupled to set the DC operating point.
Figure 56. Single Supply Operation
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Product Folder Links: LMH6624 LMH6626
RL
500
R2
2 k
RF
1.2 k
R1
3 k
C1
0.1 µF
5 VDC
VOUT = 3 VDC - 1200 × I D
5 VDC
D1
CD= 10 pF
LMH6624
5 VDC
CF
1.1 pF
+
ID
Ω
Ω
–
LMH6624
,
LMH6626
www.ti.com
SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
A Transimpedance amplifier is used to convert the small output current of a photodiode to a voltage, while
maintaining a near constant voltage across the photodiode to minimize non-linearity. Extracting the small signal
requires high gain and a low noise amplifier, and therefore, the LMH6624 and LMH6626 devices are ideal for
such an application in order to maximize SNR. Furthermore, because of the large gain (RFvalue) needed, the
device used must be high speed so that even with high noise gain (due to the interaction of the feedback resistor
and photodiode capacitance), bandwidth is not heavily impacted.
Figure 47 implements a high-speed, single supply, low-noise Transimpedance amplifier commonly used with
photo-diodes. The transimpedance gain is set by RF.
8.2 Typical Application
Figure 57. LMH6624 Application Schematic
Copyright © 2002–2014, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LMH6624 LMH6626
f#
dB3- GBWP
INFCRS2
F
R)GBWP(2S
IN
C
F
C =
NOISE GAIN (NG)
OP AMP OPEN
LOOP GAIN
I-V GAIN (:)
GAIN (dB)
0 dB
FREQUENCY
1 + sRF (CIN + CF)
1 + sRFCF
1 + CIN
CF
GBWP
fz #
1
2SRFCIN fP = 1
2SRFCF
LMH6624
,
LMH6626
SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
www.ti.com
Typical Application (continued)
8.2.1 Design Requirements
Figure 58 shows the Noise Gain (NG) and transfer function (I-V Gain). As with most Transimpedance amplifiers,
it is required to compensate for the additional phase lag (Noise Gain zero at fZ) created by the total input
capacitance: CD(diode capacitance) + CCM (LMH6624 CM input capacitance) + CDIFF (LMH6624 DIFF input
capacitance) looking into RF. This is accomplished by placing CFacross RFto create enough phase lead (Noise
Gain pole at fP) to stabilize the loop.
Figure 58. Transimpedance Amplifier Noise Gain and Transfer Function
8.2.2 Detailed Design Procedure
The optimum value of CFis given by Equation 8 resulting in the I-V -3dB bandwidth shown in Equation 9, or
around 124 MHz in this case, assuming GBWP = 1.5 GHz, CCM (LMH6624 CM input capacitance) = 0.9 pF, and
CDIFF (LMH6624 DIFF input capacitance) = 2 pF. This CFvalue is a “starting point” and CFneeds to be tuned for
the particular application as it is often less than 1 pF and thus is easily affected by board parasitics.
Optimum CFValue:
(8)
Resulting -3dB Bandwidth:
(9)
Equation 10 provides the total input current noise density (ini) equation for the basic Transimpedance
configuration and is plotted against feedback resistance (RF) showing all contributing noise sources in Figure 59.
The plot indicates the expected total equivalent input current noise density (ini) for a given feedback resistance
(RF). This is depicted in the schematic of Figure 60 where total equivalent current noise density (ini) is shown at
the input of a noiseless amplifier and noiseless feedback resistor (RF). The total equivalent output voltage noise
density (eno) is ini*RF. Noise Equation for Transimpedance Amplifier:
(10)
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Product Folder Links: LMH6624 LMH6626
100 1k 10k
0
2
4
6
8
10
12
14
16
FEEDBACK RESISTANCE, RF (:)
CURRENT NOISE DENSITY (pA/ Hz)
in
ini
it
en/RF
RF
(Noiseless)
D1
+5VDC
CD = 10 pF
Noiseless Op Amp
ID
ini
100 1k 10k
Rf (:)
Current Noise Density (pA/ Hz)
16
14
12
10
8
6
4
2
0
it
ini
en/RF
in
LMH6624
,
LMH6626
www.ti.com
SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
Typical Application (continued)
Figure 59. Current Noise Density vs. Feedback Resistance
Figure 60. Transimpedance Amplifier Equivalent Input Source Mode
From Figure 61, it is clear that with the LMH6624 extremely low-noise characteristics, for RF< 3 kΩ, the noise
performance is entirely dominated by RFthermal noise. Only above this RFthreshold, the input noise current (in)
of LMH6624 becomes a factor and at no RFsetting does the LMH6624 input noise voltage play a significant role.
This noise analysis has ignored the possible noise gain increase, due to photo-diode capacitance, at higher
frequencies.
8.2.3 Application Curve
Figure 61. Current Noise Density vs. Feedback Resistance
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,
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SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
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9 Power Supply Recommendations
The LMH6624 and LMH6626 devices can operate off a single supply or with dual supplies as long as the input
CM voltage range (CMIR) has the required headroom to either supply rail. Supplies should be decoupled with
low inductance, often ceramic, capacitors to ground less than 0.5 inches from the device pins. The use of ground
plane is recommended, and as in most high speed devices, it is advisable to remove ground plane close to
device sensitive pins such as the inputs.
10 Layout
10.1 Layout Guidelines
TI suggests the copper patterns on the evaluation boards shown in Figure 62 and Figure 63 as a guide for high
frequency layout. These boards are also useful as an aid in device testing and characterization. As is the case
with all high-speed amplifiers, accepted-practice RF design technique on the PCB layout is mandatory.
Generally, a good high frequency layout exhibits a separation of power supply and ground traces from the
inverting input and output pins as shown in Figure 62. Parasitic capacitances between these nodes and ground
may cause frequency response peaking and possible circuit oscillations. See Application Note OA-15, Frequent
Faux Pas in Applying Wideband Current Feedback Amplifiers (SNOA367) for more information. Use high quality
chip capacitors with values in the range of 1000 pF to 0.1 µF for power supply bypassing as shown in Figure 62.
One terminal of each chip capacitor is connected to the ground plane and the other terminal is connected to a
point that is as close as possible to each supply pin as allowed by the manufacturer’s design rules. In addition,
connect a tantalum capacitor with a value between 4.7 μF and 10 μF in parallel with the chip capacitor. Signal
lines connecting the feedback and gain resistors should be as short as possible to minimize inductance and
microstrip line effect as shown in Figure 63. Place input and output termination resistors as close as possible to
the input/output pins. Traces greater than 1 inch in length should be impedance matched to the corresponding
load termination.
Symmetry between the positive and negative paths in the layout of differential circuitry should be maintained to
minimize the imbalance of amplitude and phase of the differential signal.
Component value selection is another important parameter in working with high speed and high performance
amplifiers. Choosing external resistors that are large in value compared to the value of other critical components
will affect the closed loop behavior of the stage because of the interaction of these resistors with parasitic
capacitances. These parasitic capacitors could either be inherent to the device or be a by-product of the board
layout and component placement. Moreover, a large resistor will also add more thermal noise to the signal path.
Either way, keeping the resistor values low will diminish this interaction. On the other hand, choosing very low
value resistors could load down nodes and will contribute to higher overall power dissipation and high distortion.
DEVICE PACKAGE EVALUATION BOARD PART NUMBER
LMH6624MF SOT-23–5 LMH730216
LMH6624MA SOIC-8 LMH730227
LMH6626MA SOIC-8 LMH730036
LMH6626MM VSSOP-8 LMH730123
26 Submit Documentation Feedback Copyright © 2002–2014, Texas Instruments Incorporated
Product Folder Links: LMH6624 LMH6626
LMH6624
,
LMH6626
www.ti.com
SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
10.2 Layout Example
Figure 62. LMH6624 and LMH6626
EVM Board Layout Example
Figure 63. LMH6624 and LMH6626
EVM Board Layout Example
Copyright © 2002–2014, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: LMH6624 LMH6626
LMH6624
,
LMH6626
SNOSA42G –NOVEMBER 2002–REVISED DECEMBER 2014
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
•Absolute Maximum Ratings for Soldering (SNOA549)
•Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers, Application Note OA-15 (SNOA367)
•Semiconductor and IC Package Thermal Metrics (SPRA953)
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
LMH6624 Click here Click here Click here Click here Click here
LMH6626 Click here Click here Click here Click here Click here
11.3 Trademarks
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28 Submit Documentation Feedback Copyright © 2002–2014, Texas Instruments Incorporated
Product Folder Links: LMH6624 LMH6626
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMH6624MA NRND SOIC D 8 95 TBD Call TI Call TI -40 to 125 LMH66
24MA
LMH6624MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LMH66
24MA
LMH6624MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LMH66
24MA
LMH6624MF NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 125 A94A
LMH6624MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 A94A
LMH6624MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 A94A
LMH6626MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LMH66
26MA
LMH6626MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LMH66
26MA
LMH6626MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 A98A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 2
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMH6624MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMH6624MF SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6624MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6624MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6626MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMH6626MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH6624MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMH6624MF SOT-23 DBV 5 1000 210.0 185.0 35.0
LMH6624MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMH6624MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMH6626MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMH6626MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.9
1.45
0.90
0.15
0.00 TYP
5X 0.5
0.3
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/E 09/2019
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
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