Charge Pump Regulator for Color TFT Panels ADM8839 FUNCTIONAL BLOCK DIAGRAM FEATURES 3 voltages (+5 V, +15 V, -15 V) from a single 3 V supply Power efficiency optimized for use with TFT in mobile phones Low quiescent current Low shutdown current (<5 A) Shutdown function Option to use external LDO C1+ ADM8839 VOLTAGE DOUBLER C1, 2.2F VOUT LDO_IN OSCILLATOR LDO_ON/OFF C1- LDO VOLTAGE REGULATOR CONTROL LOGIC Hand-held instruments TFT LCD panels Cellular phones DOUBLE VOLTAGE TRIPLER TRIPLE TIMING GENERATOR C6, 2.2F +5VOUT +5VIN C2+ C2- C2, 0.22F C3+ C3- C3, 0.22F +15VOUT SHUTDOWN CONTROL DISCHARGE VOLTAGE INVERTER C4- C4, 0.22F -15VOUT GND +15V C8, 0.22F C4+ SHDN +5V C7, 2.2F -15V C9, 0.22F 03075-001 APPLICATIONS C5, 2.2F VCC Figure 1. GENERAL DESCRIPTION The ADM8839 is a charge pump regulator used for color thin film transistor (TFT) liquid crystal displays (LCDs). Using charge pump technology, the device can be used to generate three voltages (+5 V 2%, +15 V, -15 V) from a single 3 V supply. These voltages are then used to provide supplies for the LCD controller (5 V) and the gate drives for the transistors in the panel (+15 V and -15 V). Only a few external capacitors are needed for the charge pumps. An efficient low dropout (LDO) voltage regulator ensures that the power efficiency is high, and provides a low ripple 5 V output. This LDO can be shut down and an external LDO can be used to regulate the 5 V doubler output and drive the input to the charge pump section that generates the +15 V and -15 V outputs, if required by the user. The ADM8839 has a power save shutdown feature. The 5 V output consumes the most power, so power efficiency is also maximized on this output with an oscillator-enabling scheme (Green IdleTM). This effectively senses the load current that is flowing and turns on the charge pump only when charge needs to be delivered to the 5 V pump doubler output. The ADM8839 is fabricated using CMOS technology for minimal power consumption. The part is packaged in a 20-lead LFCSP (lead frame chip scale package). Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. ADM8839 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................4 Applications....................................................................................... 1 Pin Configuration and Function Descriptions..............................5 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................6 General Description ......................................................................... 1 Theory of Operation .........................................................................8 Revision History ............................................................................... 2 Power Sequencing .........................................................................8 Specifications..................................................................................... 3 Transient Response .......................................................................8 Timing Specifications .................................................................. 3 Boosting the Current Drive of the 15 V Supply .....................8 Absolute Maximum Ratings............................................................ 4 Outline Dimensions ....................................................................... 10 Thermal Characteristics .............................................................. 4 Ordering Guide .......................................................................... 10 REVISION HISTORY 7/06--Rev. B to Rev. C Updated Format..................................................................Universal Changes to Table 1............................................................................ 3 Changes to Table 5............................................................................ 5 Changes to Ordering Guide .......................................................... 10 Updated Outline Dimension......................................................... 10 7/05--Rev. A to Rev. B Updated Ordering Guide .................................................................3 2/03--Rev. 0 to Rev. A Changed Specifications.....................................................................2 Updated Outline Dimensions..........................................................8 Rev. C | Page 2 of 12 ADM8839 SPECIFICATIONS VCC = 3 V (+40%/-10%); TA = -40C to +85C; C1, C5, C6, C7 = 2.2 F; C2, C3, C4, C8, C9 = 0.22 F; unless otherwise noted. Table 1. Parameter INPUT VOLTAGE, VCC SUPPLY CURRENT, ICC +5 V OUTPUT Output Voltage Output Current Output Ripple Transient Response +15 V OUTPUT Output Voltage Output Current Output Ripple -15 V OUTPUT Output Voltage Output Current Output Ripple POWER EFFICIENCY CHARGE PUMP FREQUENCY CONTROL PINS, SHDN Input Voltage, V SHDN Test Conditions Min 2.7 Unloaded Shutdown mode, TA = 25C IL = 10 A to 20 mA 250 IL = 1 A to 150 A 5.1 20 V mA mV p-p s 14.0 15.0 1 50 16.0 150 V A mV p-p -16.0 -150 -15.0 -1 50 82 100 -14.0 140 V A mV p-p % kHz 0.3 x VCC V 1 10 V A pF IL = -100 A R5 VOUT load = 5 mA, 15 V load = 150 A, VCC = 3.0 V 60 SHDN low = shutdown mode Low = External LDO High = Internal LDO 0.7 x VCC 0.3 x VCC 0.7 x VCC Digital Input Current Digital Input Capacitance1 1 Unit V A A 5.0 5 10 5 IL = 100 A IL = -1 A to -150 A Max 4.2 500 5 4.9 8 mA load IL stepped from 10 A to 8 mA SHDN high = normal mode Digital Input Current Digital Input Capacitance 1 LDO_ON/OFF Input Voltage Typ 1 10 V V A pF Guaranteed by design. Not 100% production tested. TIMING SPECIFICATIONS VCC = 3 V, TA = 25C; C1, C5, C6, C7 = 2.2 F; C2, C3, C4, C8, C9 = 0.22 F. Table 2. Parameter POWER-UP SEQUENCE +5 V Rise Time, tR5V +15 V Rise Time, tR15V -15 V Fall Time, tFM15V Delay Between -15 V Fall and +15 V, tDELAY POWER-DOWN SEQUENCE +5 V Fall Time, tF5V +15 V Fall Time, tF15V -15 V Rise Time, tRM15V Test Conditions/Comments Min Typ Max Unit 10% to 90%, see Figure 14 10% to 90%, see Figure 14 90% to 10%, see Figure 14 See Figure 14 250 3 3 600 s ms ms s 90% to 10%, see Figure 14 90% to 10%, see Figure 14 10% to 90%, see Figure 14 35 10 20 ms ms ms Rev. C | Page 3 of 12 ADM8839 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 3. Parameter Supply Voltage Input Voltage on Digital Inputs Output Short-Circuit Duration to GND Output Voltage +5 V Output -15 V Output +15 V Output Operating Temperature Range Power Dissipation Storage Temperature Range ESD Rating -0.3 V to +6.0 V -0.3 V to +6.0 V 10 sec 0 V to 7.0 V -17 V to +0.3 V -0.3 V to +17 V -40C to +85C 50 mW -65C to +150C Class I Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type 20-Lead LFCSP_VQ JA 31C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 4 of 12 Unit C/W ADM8839 20 C1+ 19 C1- 18 GND 17 -15VOUT 16 C4+ PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TOP VIEW 15 C4- 14 C2+ 13 C2- 12 C3+ 11 C3- 03075-002 PIN 1 INDICATOR ADM8839 LDO_ON/OFF 6 SHDN 7 VCC 8 GND 9 +15VOUT 10 VCC 1 VOUT 2 LDO_IN 3 +5VOUT 4 +5VIN 5 Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 Mnemonic VCC 2 VOUT 3 4 LDO_IN +5VOUT 5 6 +5VIN LDO_ON/OFF 7 SHDN 8 9 10 11, 12 13, 14 15, 16 17 VCC GND +15VOUT C3-, C3+ C2-, C2+ C4-, C4+ -15VOUT 18 19, 20 GND C1-, C1+ Description Positive Supply Voltage Input. Connect this pin to the 3 V supply with a 2.2 F decoupling capacitor. Must be electrically tied together with Pin 8 by a PCB trace. Voltage Doubler Output. This is derived by doubling the 3 V supply. A 2.2 F capacitor to ground is required on this pin. Voltage Regulator Input. The user can bypass this circuit by using the LDO_ON/OFF pin. 5 V Output. This is derived by doubling and regulating the 3 V supply. A 2.2 F capacitor to ground is required on this pin to stabilize the regulator. 5 V Input. This is the input to the voltage tripler and inverter charge pump circuits. Control Logic Input. 3 V CMOS logic. A logic high selects the internal LDO for regulation of the 5 V voltage doubler output. A logic low isolates the internal LDO from the rest of the charge pump circuits. This allows the use of an external LDO to regulate the 5 V voltage doubler output. The output of this LDO is then fed back into the voltage tripler and inverter circuits of the ADM8839. Digital Input. 3 V CMOS logic. Active low shutdown control. This shuts down the timing generator and enables the discharge circuit to dissipate the charge on the voltage outputs, thus driving them to 0 V. Connect this pin to VCC. Must be electrically tied with Pin 1 by a PCB trace. Connect this pin to GND. Must be electrically tied with Pin 18 by a PCB trace. 15 V Output. This is derived by tripling the 5 V regulated output. A 0.22 F capacitor is required on this pin. External Capacitor C3 is connected between these pins. A 0.22 F capacitor is recommended. External Capacitor C2 is connected between these pins. A 0.22 F capacitor is recommended. External Capacitor C4 is connected between these pins. A 0.22 F capacitor is recommended. -15 V Output. This is derived by tripling and inverting the 5 V regulated output. A 0.22 F capacitor is required on this pin. Device Ground. Must be electrically tied with Pin 9 by a PCB trace. External Capacitor C1 is connected between these pins. A 2.2 F capacitor is recommended. Rev. C | Page 5 of 12 ADM8839 TYPICAL PERFORMANCE CHARACTERISTICS 84 5.10 DEVICE AT +25C DEVICE AT +85C 83 LDO POWER EFFICIENCY (%) 5.00 4.95 DEVICE AT -40C 4.90 4.85 4.80 4.75 81 80 79 78 77 76 3.1 3.3 3 .5 3.7 SUPPLY VOLTAGE (V) 3 .9 4.1 4.2 75 1 2 3 4 5 6 7 8 LOAD CURRENT (mA) Figure 3. LDO O/P Voltage Variation over Temperature and Supply 03075-006 2.9 03075-003 4.70 2.7 Figure 6. LDO Power Efficiency vs. Load Current, VCC = 3 V 5.020 400 5.015 350 SUPPLY CURRENT (A) LDO O/P VOLTAGE (V) 82 5.010 5.005 300 250 200 5.000 4.995 150 1 2 3 4 5 6 7 8 ILOAD (mA) 2 .7 03075-004 0 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.2 SUPPLY VOLTAGE (V) 03075-007 LDO O/P VOLTAGE (V) 5.05 Figure 7. Supply Current vs. Supply Voltage Figure 4. LDO O/P Voltage vs. Load Current 15.1 100 OUTPUT VOLTAGE (V) 14.9 80 70 60 50 14.8 +15V AT 25C 14.7 14.6 -15V AT 25C 14.5 14.4 14.3 40 14.2 10 20 30 40 50 60 70 80 90 ILOAD (A) Figure 5. +15 V/-15 V Power Efficiency vs. Load Current 100 0 50 100 ILOAD (A) 150 200 03075-008 14.1 30 03075-005 +15V/-15V POWER EFFICIENCY (%) 15.0 90 Figure 8. +15 V/-15 V Output Voltage vs. Load Current, Typical Configuration Rev. C | Page 6 of 12 ADM8839 LOAD ENABLE +15V OUTPUT 5V OUTPUT -15V OUTPUT 03075-009 03075-012 5VOUT Figure 12. Output Transient Response for Maximum Load Current Figure 9. +15 V and -15 V Outputs at Power-Up VOUT RIPPLE (DOUBLER OUTPUT RIPPLE) +15V OUTPUT LDO OUTPUT RIPPLE VCC RIPPLE -15V OUTPUT 03075-010 03075-013 5VOUT Figure 10. Output Ripple on LDO (5 V Output) Figure 13. +15 V and -15 V Outputs at Power-Down LOAD DISABLE 03075-011 5V OUTPUT Figure 11. 5 V Output Transient Response, Load Disconnected Rev. C | Page 7 of 12 ADM8839 THEORY OF OPERATION POWER SEQUENCING For the TFT panel to power up correctly, the gate drive supplies must be sequenced such that the -15 V supply is up before the +15 V supply. The ADM8839 controls this sequence. When the device is turned on (a logic high on SHDN), the ADM8839 allows the -15 V output to ramp immediately but holds off the +15 V output. It continues to do this until the negative output has reached -3 V. At this point, the positive output is enabled and allowed to ramp to +15 V. This sequence is highlighted in Figure 14. BOOSTING THE CURRENT DRIVE OF THE 15 V SUPPLY The ADM8839 15 V output can deliver 150 A of current in the typical configuration, as shown in Figure 15. It is also possible to draw 100 A from the +15 V output and 200 A from the -15 V output, or vice versa. It is possible to draw a maximum of only 300 A combined from the +15 V and the -15 V outputs at any time (see Figure 16). In this configuration, +5VOUT (Pin 4) is connected to +5VIN (Pin 5), as shown in the functional block diagram (see Figure 1). C5, 2.2F VCC VCC C1+ ADM8839 VOLTAGE DOUBLER SHDN OSCILLATOR LDO VOLTAGE REGULATOR 90% tF5V CONTROL LOGIC LDO_ON/OFF C6, 2.2F +5VOUT +5VIN +5V C7, 2.2F tR15V 90% DOUBLE tF15V VOLTAGE TRIPLER tDELAY -3V tFM15V C3- C3, 0.22F +15VOUT 03075-014 tRM15V 10% C2, 0.22F C3+ TRIPLE TIMING GENERATOR -15V 90% C2- +15V C8, 0.22F C4+ SHUTDOWN CONTROL SHDN Figure 14. Power Sequence DISCHARGE VOLTAGE INVERTER C4- C4, 0.22F -15VOUT TRANSIENT RESPONSE Figure 15. Typical Configuration 15.1 15.0 14.9 OUTPUT VOLTAGE (V) The ADM8839 features extremely fast transient response, making it very suitable for fast image updates on TFT LCD panels. This means that even under changing load conditions, there is still very effective regulation of the 5 V output. Figure 11 and Figure 12 show how the 5 V output responds when a maximum load is dynamically connected and disconnected. Note that the output settles within 5 s to less than 1% of the output level. -15V C9, 0.22F GND 14.8 +15V AT 25C 14.7 14.6 -15V AT 25C 14.5 14.4 14.3 14.2 14.1 0 50 100 150 ILOAD (A) Figure 16. +15 V/-15 V Output Voltage vs. Load Current, Typical Configuration Rev. C | Page 8 of 12 200 03075-015 10% +15V C2+ 03075-016 10% C1, 2.2F VOUT LDO_IN tR5V +5V C1- ADM8839 It is possible to configure the ADM8839 to supply up to 400 A on the 15 V outputs by changing its configuration slightly, as shown in Figure 17. C5, 2.2F The configuration in Figure 17 can supply up to 400 A of current on both the +15 V and the -15 V outputs. If the load on the 15 V does not draw any current, the voltage on the 15 V outputs can rise up to 16.5 V (see Figure 18). In this configuration, VOUT (Pin 2) is connected to +5VIN (Pin 5). VCC 17.0 C1+ C1- C1, 2.2F OSCILLATOR LDO VOLTAGE REGULATOR CONTROL LOGIC C6, 2.2F +5VOUT +5V +5VIN LDO_ON/OFF C7, 2.2F DOUBLE VOLTAGE TRIPLER TRIPLE TIMING GENERATOR C2+ C2- 16.5 CURRENT BOOST CONFIGURATION CONNECTION VOUT LDO_IN C2, 0.22F C3, 0.22F +15VOUT 14.0 C4- 0 C4, 0.22F -15VOUT GND -15V C9, 0.22F 100 200 300 400 ILOAD (A) 03075-017 SHDN 15.0 +15V C8, 0.22F DISCHARGE -15V AT 25C 15.5 14.5 C4+ SHUTDOWN CONTROL 16.0 C3+ C3- VOLTAGE INVERTER +15V AT 25C Figure 17. Current Boost Configuration Rev. C | Page 9 of 12 Figure 18. +15 V/-15 V Output Voltage vs. Load Current, Current Boost Configuration 500 03075-018 VOLTAGE DOUBLER OUTPUT VOLTAGE (V) ADM8839 ADM8839 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ 0.60 MAX PIN 1 INDICATOR TOP VIEW 1.00 0.85 0.80 SEATING PLANE 2.25 2.10 SQ 1.95 11 10 0.80 MAX 0.65 TYP 0.20 REF 6 5 0.25 MIN 0.30 0.23 0.18 0.05 MAX 0.02 NOM 0.50 BSC 20 1 16 15 3.75 BCS SQ 0.75 0.55 0.35 12 MAX PIN 1 INDICATOR COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 Figure 19. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-20-1) Dimensions shown in millimeters ORDERING GUIDE Model ADM8839ACP ADM8839ACP-REEL ADM8839ACP-REEL7 ADM8839ACPZ 1 ADM8839ACPZ-REEL1 ADM8839ACPZ-REEL71 EVAL-ADM8839EB 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Ordering Quantity 75 5,000 1,500 75 5,000 1,500 Z = Pb-free part. Rev. C | Page 10 of 12 Package Description 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ Evaluation Board Package Option CP-20-1 CP-20-1 CP-20-1 CP-20-1 CP-20-1 CP-20-1 ADM8839 NOTES Rev. C | Page 11 of 12 ADM8839 NOTES (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03075-0-7/06(C) Rev. C | Page 12 of 12