1. General description
The 74HC366-Q100; 74HCT366-Q100 is a hex inverter/line driver with 3-state outputs
controlled by the output enable inputs (OEn). A HIGH on OEn causes the outputs to
assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use
of current limiting resistors to interface inputs to voltages in excess of VCC.
The 74HC366-Q100; 74HCT366-Q100 is functionally identical to:
•74HC365-Q100; 74HCT365-Q100, but has inverted outputs
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Inverting outputs
Input levels:
For 74HC366-Q100: CMOS level
For 74HC366-Q100: TTL level
Complies with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
Rev. 1 — 7 August 2012 Product data sheet
74HC_HCT366_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 2 of 19
NXP Semiconductors 74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temp erature range Name Description Version
74HC366-Q100
74HC366D-Q100 40 Cto+125C SO16 plastic small outline package; 16 leads; body width
3.9 mm SOT109-1
74HC366PW-Q100 40 Cto+125C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
74HCT366-Q100
74HCT366D-Q100 40 Cto+125C SO16 plastic small outline package; 16 leads; body width
3.9 mm SOT109-1
74HCT366PW-Q100 40 Cto+125C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
Fig 1. Functional diagram Fig 2. Logic symbol Fig 3. IEC logic symbol
001aaf583
1A
2
4
6
10
12
13
11
9
7
5
3
14
1
15
1Y
2A 2Y
3A 3Y
4A 4Y
6A
OE1
OE2
6Y
5A 5Y
001aaf581
1A 1Y
2A 2Y
3A 3Y
4A 4Y
6A
OE1
OE2
6Y
5A 5Y
001aaf582
15 &
1EN
2 3
5
7
9
11
13
4
6
10
12
14
74HC_HCT366_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 3 of 19
NXP Semiconductors 74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
5. Pinning information
5.1 Pinning
Fig 4. Logic diagra m
001aaf584
V
CC
GND
1A
OE1
OE2
2A 2Y
1Y
3Y
4Y
5Y
6Y
3A
4A
5A
6A
buffer/line driver 1
buffer/line driver 2
buffer/line driver 3
buffer/line driver 4
buffer/line driver 5
buffer/line driver 6
Fig 5. Pin configuration
+&4
+&74
2( 9&&
$
2(
<
$
$
<
<
$
$
<
<
$
*1' <
DDD







74HC_HCT366_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 4 of 19
NXP Semiconductors 74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
Table 2. Pin description
Symbol Pin Description
OE1 1 output enable input 1 (active LOW)
1A 2 data input 1
1Y 3 data output 1
2A 4 data input 2
2Y 5 data output 2
3A 6 data input 3
3Y 7 data output 3
GND 8 ground (0 V)
4Y 9 data output 4
4A 10 data input 4
5Y 11 data output 5
5A 12 data input 5
6Y 13 data output 6
6A 14 data input 6
OE2 15 output enable input 2 (active LOW)
VCC 16 supply voltage
Table 3. Function table[1]
Control Input Output
OE1 OE2 nA nY
LLLH
LLHL
XHXZ
HXXZ
74HC_HCT366_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 5 of 19
NXP Semiconductors 74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
7. Limiting values
[1] For SO16 packages: Ptot derates linearly with 8 mW/K above 70 C.
[2] For TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC + 0.5 V - 20 mA
IOK output clamping current VO<0.5 V or VO>V
CC +0.5V - 20 mA
IOoutput current VO = 0.5 V to (VCC +0.5V) - 35 mA
ICC supply current - 70 mA
IGND ground current - 70 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation SO16 package [1] -500mW
TSSOP16 package [2] -500mW
Table 5. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC366-Q100 74HCT366-Q100 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0- V
CC V
VOoutput voltage 0 - VCC 0- V
CC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V--83---ns/V
74HC_HCT366_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 6 of 19
NXP Semiconductors 74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
9. Static characteristics
Table 6. Static characteristics 74HC366-Q100
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - V
VCC = 4.5 V 3.15 2.4 - V
VCC = 6.0 V 4.2 3.2 - V
VIL LOW-level input voltage VCC = 2.0 V - 0.8 0.5 V
VCC = 4.5 V - 2.1 1.35 V
VCC = 6.0 V - 2.8 1.8 V
VOH HIGH-level output voltage VI = VIH or VIL ---
IO=20 A; VCC = 2.0 V 1.9 2.0 - V
IO=20 A; VCC = 4.5 V 4.4 4.5 - V
IO=20 A; VCC = 6.0 V 5.9 6.0 - V
IO = 6.0 mA; VCC = 4.5 V 3.98 4.32 - V
IO = 7.8 mA; VCC = 6.0 V 5.48 5.81 - V
VOL LOW-level output voltage VI = VIH or VIL
IO=20A; VCC = 2.0 V - 0 0.1 V
IO=20A; VCC = 4.5 V - 0 0.1 V
IO=20A; VCC = 6.0 V - 0 0.1 V
IO = 6.0 mA; VCC = 4.5 V - 0.15 0.26 V
IO = 7.8 mA; VCC = 6.0 V - 0.16 0.26 V
IIinput leakage current VI=V
CC or GND; VCC = 6.0 V - - 0.1 A
IOZ OFF-state output current VI = VIH or VIL; VO=V
CC or GND; VCC = 6.0 V - - 0.5 A
ICC supply current VI=V
CC or GND; IO = 0 A; VCC =6.0V --8.0A
CIinput capacitance - 3.5 - pF
Tamb =40 Cto+85C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VOH HIGH-level output voltage VI = VIH or VIL
IO=20 A; VCC = 2.0 V 1.9 - - V
IO=20 A; VCC = 4.5 V 4.4 - - V
IO=20 A; VCC = 6.0 V 5.9 - - V
IO = 6.0 mA; VCC = 4.5 V 3.84 - - V
IO = 7.8 mA; VCC = 6.0 V 5.34 - - V
74HC_HCT366_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 7 of 19
NXP Semiconductors 74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
VOL LOW-level output voltage VI = VIH or VIL
IO=20A; VCC = 2.0 V - - 0.1 V
IO=20A; VCC = 4.5 V - - 0.1 V
IO=20A; VCC = 6.0 V - - 0.1 V
IO = 6.0 mA; VCC = 4.5 V - - 0.33 V
IO = 7.8 mA; VCC = 6.0 V - - 0.33 V
IIinput leakage current VI=V
CC or GND; VCC = 6.0 V; - - 1.0 A
IOZ OFF-state output current VI = VIH or VIL; VO=V
CC or GND; VCC = 6.0 V - - 5.0 A
ICC supply current VI=V
CC or GND; IO = 0 A; VCC =6.0V --80A
Tamb =40 C to +125 C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VOH HIGH-level output voltage VI = VIH or VIL
IO=20 A; VCC = 2.0 V 1.9 - - V
IO=20 A; VCC = 4.5 V 4.4 - - V
IO=20 A; VCC = 6.0 V 5.9 - - V
IO = 6.0 mA; VCC = 4.5 V 3.7 - - V
IO = 7.8 mA; VCC = 6.0 V 5.2 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO=20A; VCC = 2.0 V - - 0.1 V
IO=20A; VCC = 4.5 V - - 0.1 V
IO=20A; VCC = 6.0 V - - 0.1 V
IO = 6.0 mA; VCC = 4.5 V - - 0.4 V
IO = 7.8 mA; VCC = 6.0 V - - 0.4 V
IIinput leakage current VI=V
CC or GND; VCC = 6.0 V - - 1.0 A
IOZ OFF-state output current VI = VIH or VIL; VO=V
CC or GND; VCC = 6.0 V - - 10.0 A
ICC supply current VI=V
CC or GND; IO = 0 A; VCC =6.0V --160A
Table 6. Static characteristics 74HC366-Q100 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Table 7. Static characteristics 74HCT366-Q100
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL; VCC =4.5V
IO=20 A4.44.5-V
IO=6.0 mA 3.98 4.32 - V
74HC_HCT366_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 8 of 19
NXP Semiconductors 74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
VOL LOW-level output
voltage VI=V
IH or VIL; VCC =4.5V
IO=20A-00.1V
IO= 6.0 mA - 0.16 0.26 V
IIinput leakage current VI=V
CC or GND; VCC =5.5V - - 0.1 A
IOZ OFF-st ate output current VI = VIH or VIL; VO=V
CC or GND per input pin; other
inputs at GND or VCC; IO=0A; V
CC =5.5V --0.5 A
ICC supply current VI=V
CC or GND; IO=0A; V
CC = 5.5 V - - 8.0 A
ICC additional supply current VI=V
CC 2.1 V; other inputs at VCC or GND; IO=0A
pins nA - 100 360 A
pin OE1 - 100 360 A
pin OE2 -90320A
CIinput capacitance - 3.5 - pF
Tamb =40 C to +85 C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL; VCC =4.5V
IO=20 A4.4--V
IO=6.0 mA 3.84 - - V
VOL LOW-level output
voltage VI=V
IH or VIL; VCC =4.5V
IO=20A--0.1V
IO= 6.0 mA - - 0.33 V
IIinput leakage current VI=V
CC or GND; VCC =5.5V - - 1.0 A
IOZ OFF-st ate output current VI = VIH or VIL; VO=V
CC or GND per input pin; other
inputs at GND or VCC; IO=0A; V
CC =5.5V 5.0 A
ICC supply current VI=V
CC or GND; IO=0A; V
CC =5.5V - - 80 A
ICC additional supply current VI=V
CC 2.1 V; other inputs at VCC or GND; IO=0A
pins nA - - 450 A
pin OE1 --450A
pin OE2 --400A
Tamb =40 C to +125 C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2. 0 - - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL; VCC =4.5V
IO=20 A4.4--V
IO=6.0 mA 3.7 - - V
VOL LOW-level output
voltage VI=V
IH or VIL; VCC =4.5V
IO=20A--0.1V
IO=6.0mA - - 0.4 V
IIinput leakage current VI=V
CC or GND; VCC =5.5V - - 1.0 A
IOZ OFF-st ate output current VI = VIH or VIL; VO=V
CC or GND per input pin; other
inputs at GND or VCC; IO=0A; V
CC =5.5V --10.0 A
Table 7. Static characteristics 74HCT366-Q100 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT366_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 9 of 19
NXP Semiconductors 74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
10. Dynamic characteristics
ICC supply current VI=V
CC or GND; IO=0A; V
CC =5.5V - - 160 A
ICC additional supply current VI=V
CC 2.1 V; other inputs at VCC or GND; IO=0A
pins nA - - 490 A
pin OE1 --490A
pin OE2 --441A
Table 7. Static characteristics 74HCT366-Q100 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Table 8. Dynamic characteristics 74HC366-Q100
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; see test circuit Figure 8.
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25C
tpd propagation delay nA to nY; see Figure 6 [1]
VCC = 2.0 V - 33 100 ns
VCC = 4.5 V - 12 20 ns
VCC = 5 V; CL= 15 pF - 10 - ns
VCC = 6.0 V - 10 17 ns
ten enable time OEn to nY; see Figure 7 [2]
VCC = 2.0 V - 44 150 ns
VCC = 4.5 V - 16 30 ns
VCC = 6.0 V - 13 26 ns
tdis disable time OEn to nY; see Figure 7 [3]
VCC = 2.0 V - 55 150 ns
VCC = 4.5 V - 20 30 ns
VCC = 6.0 V - 16 26 ns
tttransition time see Figure 6 [4]
VCC = 2.0 V - 14 60 ns
VCC =4.5V - 5 12 ns
VCC =6.0V - 4 10 ns
CPD power dissipation
capacitance per bu ffer; VI=GNDtoV
CC [5] -30- pF
Tamb =40 Cto+85C
tpd propagation delay nA to nY; see Figure 6 [1]
VCC = 2.0 V - - 125 ns
VCC =4.5V --25ns
VCC =6.0V --21ns
ten enable time OEn to nY; see Figure 7 [2]
VCC = 2.0 V - - 190 ns
VCC =4.5V --38ns
VCC =6.0V --33ns
74HC_HCT366_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 10 of 19
NXP Semiconductors 74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
[1] tpd is the same as tPHL and tPLH.
[2] ten is the same as tPZH and tPZL.
[3] tdis is the same as tPHZ and tPLZ.
[4] tt is the same as tTHL and tTLH.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fiN + (CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
tdis disable time OEn to nY; see Figure 7 [3]
VCC = 2.0 V - - 190 ns
VCC =4.5V --38ns
VCC =6.0V --33ns
tttransition time see Figure 6 [4]
VCC =2.0V --75ns
VCC =4.5V --15ns
VCC =6.0V --13ns
Tamb =40 C to +125 C
tpd propagation delay nA to nY; see Figure 6 [1]
VCC = 2.0 V - - 150 ns
VCC =4.5V --30ns
VCC =6.0V --26ns
ten enable time OEn to nY; see Figure 7 [2]
VCC = 2.0 V - - 225 ns
VCC =4.5V --45ns
VCC =6.0V --38ns
tdis disable time OEn to nY; see Figure 7 [3]
VCC = 2.0 V - - 225 ns
VCC =4.5V --45ns
VCC =6.0V --38ns
tttransition time see Figure 6 [4]
VCC =2.0V --90ns
VCC =4.5V --18ns
VCC =6.0V --15ns
Table 8. Dynamic characteristics 74HC366-Q100 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; see test circuit Figure 8.
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT366_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 11 of 19
NXP Semiconductors 74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
[1] tpd is the same as tPHL and tPLH.
[2] ten is the same as tPZH and tPZL.
[3] tdis is the same as tPHZ and tPLZ.
[4] tt is the same as tTHL and tTLH.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fiN + (CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
Table 9. Dynamic characteristics 74HCT366-Q100
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; see test circuit Figure 8.
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25C
tpd propagation delay nA to nY; see Figure 6 [1]
VCC = 4.5 V - 13 24 ns
VCC =5 V; C
L= 15 pF - 11 - ns
ten enable time OEn to nY; VCC = 4 .5 V; see Figure 7 [2] - 1635ns
tdis disable time OEn to nY; VCC = 4.5 V; see Figure 7 [3] - 2035ns
tttransition time VCC =4.5V; see Figure 6 [4] - 5 12 ns
CPD power dissipation
capacitance per buffer; VI=GND to(V
CC 1.5 V) [5] -30-pF
Tamb =40 C to +85 C
tpd propagation delay nA to nY; VCC =4.5V; see Figure 6 [1] --30ns
ten enable time OEn to nY; VCC = 4 .5 V; see Figure 7 [2] --44ns
tdis disable time OEn to nY; VCC = 4.5 V; see Figure 7 [3] --44ns
tttransition time VCC =4.5V; see Figure 6 [4] --15ns
Tamb =40 C to +125 C
tpd propagation delay nA to nY; VCC =4.5V; see Figure 6 [1] --36ns
ten enable time OEn to nY; VCC = 4 .5 V; see Figure 7 [2] --53ns
tdis disable time OEn to nY; VCC = 4.5 V; see Figure 7 [3] --53ns
tttransition time VCC =4.5V; see Figure 6 [4] --18ns
74HC_HCT366_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 12 of 19
NXP Semiconductors 74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
11. Waveforms
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. Propagation delay data input (nA) to output (nY) and output transition time
001aaf585
VMVM
tPHL
tTHL tTLH
tPLH
VMVM
nA input
VI
GND
VOH
VOL
nY output
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. 3-state enable and disa ble times
001aaf586
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
VI
GND
VCC
VOL
VOH
GND outputs
enabled
nY output
LOW-to-OFF
OFF-to-LOW
nY output
HIGH-to-OFF
OFF-to-HIGH
OEn input VMVM
tPZL
tPZH
VM
VM
Table 10 . Measurement points
Type Input Output
VMVMVXVY
74HC366-Q100 0.5VCC 0.5VCC 0.1 VCC 0.9 VCC
74HCT366-Q100 1.3 V 1.3 V 0.1 VCC 0.9 VCC
74HC_HCT366_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 13 of 19
NXP Semiconductors 74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
Test data is given in Table 11.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistor
S1 = Test selection switch
Fig 8. Load circuitry for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
VIVO
RT
RLS1
CL
open
G
Table 11. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC366-Q100 VCC 6ns 15pF, 50 pF 1kopen GND VCC
74HCT366-Q100 3 V 6 ns 15 pF, 50 pF 1 kopen GND VCC
74HC_HCT366_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 14 of 19
NXP Semiconductors 74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
12. Package outline
Fig 9. Package outline SOT109-1 (SO16)
74HC_HCT366_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 15 of 19
NXP Semiconductors 74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
Fig 10. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
74HC_HCT366_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 16 of 19
NXP Semiconductors 74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
13. Abbreviations
14. Revision history
Table 12. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
LSTTL Low-power Schottky Transistor-Transistor Logic
MM Machine Model
MIL Military
Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT366_Q10 0 v.1 20120807 Product data sheet - -
74HC_HCT366_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 17 of 19
NXP Semiconductors 74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect , incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconduct ors’ aggregate and cumulati ve liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe propert y or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly object s to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74HC_HCT366_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 18 of 19
NXP Semiconductors 74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 August 2012
Document identi fier: 74HC_HCT366_Q100
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional di agram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional de scription . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16 Contact information. . . . . . . . . . . . . . . . . . . . . 18
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19