1999 Microchip Technology Inc. Preliminary DS30605B-page 1
Devices included in this data sheet:
PIC16CXX Microcontroller Core Features:
High-performance RISC CPU
Only 35 single word instructions to learn
All single cycle instructions except for program
branches which are two cycle
Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
4K x 14 words of Program Memory,
192 x 8 bytes of Data Memory (RAM)
Interrupt capability
Eight-level deep hardware stack
Direct, indirect and relative addressing modes
Power-on Reset (POR)
Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
Pr ogrammable code-protection
Power-saving SLEEP mode
Selectable oscillator options
Low-power, high-speed CMOS EPROM
technology
Wide operating voltage range: 2.5V to 5.5V
High Sink/Source Current 25/25 mA
Commercial, Industrial and Automotive
temperature ranges
Low-power consumption:
- < 5 mA @ 5V, 4 MHz
- 23 µA typical @ 3V, 32 kHz
-< 3 µA typical standby current
PIC16C7X Peripheral Features:
Timer0: 8-bit timer/counter with 8-bit prescaler
Timer1: 16-bit timer/counter with prescaler
can be incremented during sleep via external
crystal/clock
Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
Capture, Compare, PWM modules
- Capture is 16-bit, max. resolution is 200 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
8-bit multichannel Analo g-to -Digi tal converter
Synchronous Seri al Port (SSP) with SPI
and I2C
Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
Parallel Slave Port (PSP), 8-bits wide with
ex ternal RD, WR and CS control s
Brown-out detection circuitry for Brown-out Reset
(BOR)
Pin Di agram:
PIC16C63A PIC16C73B
PIC16C65B PIC16C74B
Devices I/O
Pins A/D
Chan. PSP Interrupts
PIC16C63A 22 - No 10
PIC16C65B 33 - Yes 11
PIC16C73B 22 5 No 11
PIC16C74B 33 8 Yes 12
PDIP, Windowed CERDIP
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC16C65B
PIC16C74B
PIC16C63A/65B/73B/74B
8-Bit CMOS Microcontrollers with A/D Converter
PIC16C63A/65B/73B/74B
DS30605B-page 2 Preliminary 1999 Microchip Technology Inc.
Key Features
PICmicro Mid-Range MCU Family
Reference Manual (DS33023) PIC16C63A PIC16C65B PIC16C73B PIC16C74B
Program Memor y (EP ROM) x 14 4K 4K 4K 4K
Data Memory (Bytes) x 8 192 192 192 192
Pins 28 40 28 40
P arallel Slave Port Yes Yes
Capture/Compare/PWM Modules 2 2 2 2
Timer Modules 3 3 3 3
A/D Channels 5 8
Serial Communication SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART
In-Circuit Serial Programming Yes Yes Yes Ye s
Brown-out Reset Yes Yes Yes Ye s
Interrupt Sources 10 11 11 12
P ackages 28-pin SDIP, SOIC,
SSOP, Windowed
Cerdip
40-pin PDIP;
44-pin PLCC,
MQFP, TQFP,
Windowed Cerdip
28-pin SDIP, SOIC,
SSOP, W indowed
Cerdip
40-pin PDIP;
44-pin PLCC,
MQ FP, TQF P,
Windowed Cerdip
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SDIP, SOIC, SSOP, Windowed CERDIP
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RA4/T0CKI
RA5/SS/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
NC
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1 6
5
4
3
2
1
44
43
42
41
40
28
27
26
25
24
23
22
21
20
19
18
PIC16C65B
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/SS/AN4
RA4/T0CKI
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
NC
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
MCLR/VPP
RB7
RB6
RB5
RB4
NC
NC 44
43
42
41
40
39
38
37
36
35
34
22
21
20
19
18
17
16
15
14
13
12
MQFP
PLCC
PIC16C74B
TQFP
RC1/T1OSI/CCP2
PIC16C65B
PIC16C74B
PIC16C63A
PIC16C73B
1999 Microchip Technology Inc. Preliminary DS30605B-page 3
PIC16C63A/65B/73B/74B
Table of Contents
1.0 General Description ............. ....... .... .. .. .... .. ....... .. .... .. .... .. .. ....... .... .. .... .. .. ....... .... .. .. .... .. ................................................................... 5
2.0 PIC1 6 C6 3 A/65B/73B/74B Device Varieties........................ .................. ................... ................... ................... ................... ............ 7
3.0 Arc hitectural Overview.................................................................................................................................................................. 9
4.0 Memory Organization.................................................................................................................................................................. 15
5.0 I /O Po r ts.................................... .................. ................... ................... ................... ..................... ................... ................... ............ 29
6.0 Timer0 Module. ........................................................................................................................................................................... 39
7.0 Timer1 Module. ........................................................................................................................................................................... 43
8.0 Timer2 Module. ........................................................................................................................................................................... 47
9.0 Capture/Compare/PWM ModuleS .......... .... ....... .... .. .... .... ....... .... .... .. .... ....... .... .... .. .... ......... .. .... .... .............................................. 49
10.0 Synchronous Serial Port (SS P) Mo dule...................................................................................................................................... 55
11.0 Universal Synchronous Asynchronous Receiver Transmitter (USART)................................... ...... ............... ............................. 67
12.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 79
13.0 Special Features of the CPU ...................................................................................................................................................... 85
14.0 Instruction Set Summary............................................................................................................................................................. 99
15.0 Development Support....................................................... . ................................. ...................................................................... 107
16.0 Electrical Characteristics ........................................................................................................................................................... 113
17.0 DC and AC Characteristics Graphs and Tables .............. ......... .... .... .... ....... .... .... .... .. ......... .... .... .... .......................................... 137
18.0 P a ck a g i n g In fo rmation. ................... ................... ................... .......... ................... ........................... ................... ................... ...... 139
Appendix A: Revision History ................ .... .... ........... .... .... .... ........... ...... .... ........... .... .... ........... ...................................................... 151
Appendix B: Device Differences.................................... .... .. ......... .. .... .. .... .. ......... .. .... .. .... ....... .... .................................................... 151
Appendix C: DEVICE MIGRATIONS - PIC16C63/65A/73A/74A PIC16C63A/65B/73B/74B..... ................... ................... .......... 152
Appendix D: Migration from Baseline to Midrange Devices ........................................ .... ....... .... .. .... .. ......... ................................... 154
On-Line Support.................... .... .. .... ......... .. .... .... .. ......... .... .. .... ......... .. .... .... .. ......... .... .. .... ................................................................... 161
Reader Response.......................... .................................................................................................................................................... 162
Product Identific ation System ............................................................................................................................................................ 163
To Our Valued Customers
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the ver sion number. e.g., DS30000A is vers ion A of document DS30000.
New Customer Notification System
Register on our web site (www.microchip.c om/cn) to rece ive the most current information on our products.
Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recomm ended
workarounds. As de vice/documentation issues become known to us , we wil l publish an errata sheet. The errat a will specify the re vi-
sion of silicon and re vision of document to which it applies.
To determine if an errata sheet exists for a particular dev ice, please check with one of the following:
Microchip’s Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
The Microchip Corporate Literature Center; U. S. FAX: (602) 786-7277
When contacting a sales office or the literature center , please specify which device, revision of silicon and data sheet (include liter-
ature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve t he quality of all our products and documentation. We have spent a great deal of time to ensure
that this document is correct. However , we realize t hat we ma y hav e missed a f e w things. If y ou find any inf ormation that is missing
or appears in error, please:
Fill out and mail in the reader response form in the back of this data sheet.
E-mail us at webmaster@micr ochip.com.
We appr eciate your assistance in making this a better document.
PIC16C63A/65B/73B/74B
DS30605B-page 4 Preliminary 1999 Microchip Technology Inc.
NOTES:
PIC16C63A/65B/73B/74B
1999 Microchip Technology Inc. Preliminary DS30605B-page 5
1.0 GENERAL DESCRIPTION
The PIC16C63A/65B/73B/74B devices are low-cost,
high-performance, CMOS, fully-static, 8 bit microcon-
troller s in the PI C16CXX mid- range family.
All PICmicro® microcontrollers employ an advanced
RISC architecture. The PIC16CXX microcontroller f am-
ily has enhanced core features, eight-level deep stack
and multiple internal and external interrupt sources.
The separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two stage instruction
pipeline allows all instructions to execute in a single
cycle, except for program branches, which require two
cycles. A total of 35 instructions (reduced instruction
set) are a vailab le. Additionally, a large register set gives
some of the architectu ral in nov ation s used to achie v e a
very high performance.
The PIC16C63A/73B devices have 22 I/O pins. The
PIC16C65B/74B devices have 33 I/O pins. Each
device has 192 bytes of RAM. In addition, several
peripheral features are available including: three timer/
counters, two Capture/Compare/PWM modules and
two serial ports. The Synchronous Serial Port (SSP)
can be configured as either a 3-wire Serial Peripheral
Interface (SPI) or the two-wire Inter-Integrated Circuit
(I2C) bus. The Universal Synchronous Asynchronous
Receiver Transmitter (USART) is also known as the
Serial Communications Interface or SCI. Also, a 5-
channel high-speed 8-bit A/D is provided on the
PIC16C73B, while the PIC16C74B offers 8 channels.
The 8-bit resolution is ideally suited for applications
requiring low-cost analog interface, e.g., thermostat
control, pressure sensing, etc.
The PIC16C63A/65B/73B/74B devices have special
features to re duc e external comp one nts, thus redu cing
cost, enhancing system reliability and reducing power
consumption. There are four oscillator opt ions, of which
the single pin RC oscillator provides a low-cost solu-
tion, the LP oscillator minimizes power consumption,
XT is a standard crystal, and the HS is for high speed
crystals. The SLEEP (power-down) feature provides a
power-saving mode. The user can wake up the chip
from SLEEP through several external and internal
interrupts and resets.
A highly reliable Watchdog Timer (WDT), with its own
on-chip RC oscillator, provides protection against soft-
wa re lock-up , an d al so pr o v ides one wa y of w aki ng the
device from SLEEP.
A UV erasable CERDIP packaged version is ideal for
code development, while the cost-effective One-Ti me-
Programmable (OTP) version is suitable for production
in any volume.
The PIC16C63A/65B/73B/74B devices fit nicely in many
applications ranging fr om security and remote sensors
to appliance control and automotive . The EPR O M tech-
nology makes customization of application programs
(transmitter codes, motor speeds, receiver frequencies,
etc.) extremely fast and convenient. The small footprint
packages make this microcontroller series perfect f or all
applications with space limitations. Low cost, low power ,
high performance, ease of use and I/O flexibility make
the PIC16C63A/65B/73B/74B devices very versatile,
even in areas where no microcontroller use has been
considered before (e.g. , timer functions, ser ial commu-
nication, capture and compare, PWM functions and
coprocessor applications).
1.1 Family and Upward Compatibility
Users familiar with the PIC16C5X microcontroller fam-
ily will realize that this is an enhanced version of the
PIC16C5X architecture. Please refer to Appendix A for
a detailed list of enhancements. Code written for the
PIC16C5X c an be eas il y p orted to the PIC16 CXX fam-
ily of devices (Appendix B).
1.2 Development Support
PICmicro® devices are suppor ted by the complete line
of Microchip Development tools.
Please refer to Section 15.0 for more details about
Microchip’s development tools.
PIC16C63A/65B/73B/74B
DS30605B-page 6 Preliminary 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. Preliminary DS30605B-page 7
PIC16C63A/65B/73B/74B
2.0 PIC1 6C63A/ 65B/73B/74B
DEVICE VARIETIES
A variety of frequency ranges and packaging options
are a vai lable . Depending on a pplication an d production
requirem ents, the prop er devi ce option ca n be selected
using the infor mation in the PIC16C63A/65B/73B/74B
Product Identification System section at the end of this
data she et. When placi ng or ders , plea se use that pag e
of the data sheet to specify the correct part number.
For the PIC16C7X family, there are two device “types”
as in dicated in the device nu mber:
1. C, as in PIC16C74. These devices have
EPROM type memory and operate over the
standard voltage range.
2. LC, as in PIC16LC74. These devices have
EPROM type memory and operate over an
extended v ol tag e r an ge .
2.1 UV Erasa ble Devices
The UV erasable version, offered in windowed CERDIP
packages, is optimal for prototype development and
pilot programs. This version can be erased and
reprogrammed to any of the oscillator modes.
Microchip's PICSTART Plus and PRO MATEII
programmers both support programming of the
PIC16C63A/65B/73B/74B.
2.2 One-Ti me- Programm able (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications.
The OTP devices, packaged in plastic packages, per-
mit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
2.3 Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for fac-
tory production orders. This service is made available
f or users who choose not to program a medium to high
quantity of units and whose code patter ns have stabi-
lized. The devices are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factor y. Certain code and
prototype verification procedures apply before produc-
tion shipments are available. Please contact your local
Microchip Technology sales office for more details.
2.4 Serialized Quick-Turnar ound
Production (SQTPSM) Devices
Microchip offers a unique programming ser vice where
a few user-defined locations in each device are pro-
grammed with different serial numbers. The serial num-
bers may be random, ps eudo-random or sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry-code,
password or ID number.
PIC16C63A/65B/73B/74B
DS30605B-page 8 Preliminary 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. Preliminary DS30605B-page 9
PIC16C63A/65B/73B/74B
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be
attributed to a number of architectural features com-
monly found in RISC microprocessors. To begin with,
the PIC16CXX uses a Harvard architecture, in which
program and data are accessed from separate memo-
ries using separate buses. This improves bandwidth
ov er tr aditional von Neu mann archi tecture in wh ich pro-
gram and data are fetched from the same memory
using the same bus. Separating program and data
buses further allows instructions to be sized differently
than the 8-bit w ide data word. Instruction opcodes are
14-b its wid e maki ng it p ossible to have all si ngle wor d
instructions. A 14-bit wide program memory access
bus f et ches a 14 -bit ins truction in a si ngle cy cle . A tw o-
stage pipeline overlaps fetch and execution of instruc-
tions (Example 3-1). Consequently, most instructions
e xecute in a sin gle c ycle (20 0 ns @ 20 MHz) excep t f or
program branches.
All devic es covered b y this datasheet contain 4K x 14-bit
program memory and 192 x 8-bit data memory.
The PIC16CXX can directly or indirectly address its
register files or data mem ory. All spec ial function re gi s-
ters, including the program counter, are mapped in the
data mem ory. The PIC16CXX has an orthogonal (sym-
metr ic al) i nstr uc tio n set that makes i t poss ible t o car r y
out an y oper ation on an y register us ing any addressin g
mode. This symmetrical nature and lack of ‘special
optimal situations’ make programming with the
PIC16CXX s imple y et efficie nt. In addition, the learning
curve is r educed significantly.
PIC16CXX devices contain an 8-bit ALU and working
register. The ALU is a general purpose arithmetic unit.
It performs arithmetic and Boolean functions between
the data in the working register and any register file.
The ALU is 8-bits wide and capable of addition, sub-
traction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two's comple-
ment in nature. In two-operand instructions, typically
one operand is the working register (W register). The
other operand is a file register or an immediate con-
stant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable registe r.
Depending on the instruction executed, the ALU may
aff ect the values of th e Carry (C), Di git Carry (DC), and
Zero ( Z) bits in th e STATUS reg ister . The C and D C bits
operate as a borrow bit and a digit borrow out bit,
respect ively, in subtraction. See th e SUBLW and SUBWF
instructions for examples.
PIC16C63A/65B/73B/74B
DS30605B-page 10 Preliminary 1999 Microchip Technology Inc.
FIGURE 3-1: PIC16C63A/65B/7 3B/74 B BLOCK DIAGRAM
EPROM
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Leve l Stack
(13-bit) RAM
File
Registers
Direct Addr 7
RAM Addr (1) 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD, VSS
PORTA
PORTB
PORTC
PORTD(3)
PORTE(3)
RA4/T0CKI
RA5/SS/AN4(2)
RB0/INT
RB7:RB1
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD7/PSP7:RD0/PSP0(3)
RE0/RD/AN5(2, 3)
RE1/WR/AN6(2, 3)
RE2/CS/AN7(2, 3)
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register.
2: A/D is not available on the PIC16C63A/65B.
3: PSP and Ports D and E are not available on PIC16C63A/73B.
USART
CCP1 CCP2 Synchronous
A/D(2)
Timer0 Timer1 Timer2
Serial Port
RA3/AN3/VREF(2)
RA2/AN2(2)
RA1/AN1(2)
RA0/AN0(2)
Parallel Slave Port
8
3
(3)
1999 Microchip Technology Inc. Preliminary DS30605B-page 11
PIC16C63A/65B/73B/74B
TABLE 3-1: PIC16C63A/73B PINOUT DESCRIPTION
Pin Name DIP
Pin# SOIC
Pin# I/O/P
Type Buffer
Type Description
OSC1/CLKIN 9 9 I ST/CMOS(3) Oscillator cr y stal input/external clock source input.
OSC2/CLKOUT 10 10 O Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
MCLR/VPP 1 1 I/P ST Master clear (reset) input or programming voltage input. This
pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0(4)2 2 I/O TTL RA0 can also be analog input 0(4)
RA1/AN1(4)3 3 I/O TTL RA1 can also be analog input 1(4)
RA2/AN2(4)4 4 I/O TTL RA2 can also be analog input 2(4)
RA3/AN3/VREF(4)5 5 I/O TTL RA3 can also be analog input 3 or analog reference
voltage(4)
RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0 module.
Output is open drain type .
RA5/SS/AN4(4)7 7 I/O TTL RA5 can also be analog input 4(4) or the slave select for
the synchronous ser ial port.
PORTB is a bi-directional I /O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT 21 21 I/O TTL/ST(1) RB0 can also be the external interrupt pin.
RB1 22 22 I/O TTL
RB2 23 23 I/O TTL
RB3 24 24 I/O TTL
RB4 25 25 I /O TTL Interrupt on change pin.
RB5 26 26 I /O TTL Interrupt on change pin.
RB6 27 27 I/O TTL/ST(2) Interrupt on change pin. Serial programming clock.
RB7 28 28 I/O TTL/ST(2) Interrupt on change pin. Serial programming data.
PORTC is a bi- directional I/O port.
RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1/T1OSI/CCP2 12 12 I/O ST RC1 can also be the Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output.
RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1
output/PWM1 output.
RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial cloc k input/output
for both SPI and I2C modes.
RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO 16 16 I/O ST RC5 can also be the SP I Data Out (SPI mode).
RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous Transmit
or Synchronous Clock.
RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronous Receive
or Synchronous Data.
VSS 8, 19 8, 19 P Ground reference for logic and I/O pins.
VDD 20 20 P P osit ive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = powe r
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the e xternal interrupt.
2: This buffer is a Schmitt Tr igger input when used in ser ial programming mode.
3: This buffer is a Schmitt Tr igger input when configured in RC oscillator mode and a CMOS input otherwise.
4: A/D module is not av ailable in the PIC16C63A.
PIC16C63A/65B/73B/74B
DS30605B-page 12 Preliminary 1999 Microchip Technology Inc.
TABLE 3-2: PIC16C65B/74B PINOUT DESCRIPTION
Pin Name DIP
Pin# PLCC
Pin#
TQFP
MQFP
Pin#
I/O/P
Type Buffer
Type Description
OSC1/CLKIN 13 14 30 I ST/CMOS(4) Oscillator crystal input/external clock source input.
OSC2/CLKOUT 14 15 31 O Oscillator crystal output. Connects to crystal or resonator in
cr yst al oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
MCLR/VPP 1 2 18 I/P ST Master clear (reset) input or programming voltage input.
This pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0(5)2 3 19 I/O TTL RA0 can also be analog input 0(5)
RA1/AN1(5)3 4 20 I/O TTL RA1 can also be analog input 1(5)
RA2/AN2(5)4 5 21 I/O TTL RA2 can also be analog input 2(5)
RA3/AN3/VREF(5)5 6 22 I/O TTL RA3 can also be analog input 3 or analog reference
voltage(5)
RA4/T0CKI 6 7 23 I/O S T RA4 can also be the clock input to the Timer0 timer/
counter. Output is open drain type.
RA5/SS/AN4(5)7 8 24 I/O TTL RA5 can also be analog input 4(5) or the slave select for
the synchronous serial port.
PORTB is a bi-directional I/O por t . PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT 33 36 8 I/O TTL/ST(1) RB0 can also be the external interrupt pin.
RB1 34 37 9 I/O TTL
RB2 35 38 10 I/O TTL
RB3 36 39 11 I/O TTL
RB4 37 41 14 I/O TTL I nterr upt on change pin.
RB5 38 42 15 I/O TTL I nterr upt on change pin.
RB6 39 43 16 I/O TTL/ST(2) In terr upt on change pin. Serial programming clock.
RB7 40 44 17 I/O TTL/ST(2) Inter r upt on change pin. Serial programming data.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Tr igger input when used in ser ial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the parallel
slav e port mode (f or interfacing to a microprocessor bus).
4: This buffer is a Schmitt Tr igger input when configured in RC oscillator mode and a CMOS input otherwise.
5: A/D is not available on the PIC16C65B.
1999 Microchip Technology Inc. Preliminary DS30605B-page 13
PIC16C63A/65B/73B/74B
PORTC is a bi-direc tional I/O port.
RC0/T1OSO/T1C KI 15 16 32 I/O ST RC0 can also be the Timer 1 oscillator output or a
Timer1 clock input.
RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output.
RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL 18 20 37 I/O ST RC3 can also be the synchronous ser ial clock input/
output for both SPI and I2C modes.
RC4/SDI/SDA 23 25 42 I/O ST RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out
(SPI mode).
RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
PORTD is a bi-directional I/O port or parallel slave port
when interfacing to a microprocessor bus.
RD0/PSP0 19 21 38 I/O ST/TTL(3)
RD1/PSP1 20 22 39 I/O ST/TTL(3)
RD2/PSP2 21 23 40 I/O ST/TTL(3)
RD3/PSP3 22 24 41 I/O ST/TTL(3)
RD4/PSP4 27 30 2 I/O ST/TTL(3)
RD5/PSP5 28 31 3 I/O ST/TTL(3)
RD6/PSP6 29 32 4 I/O ST/TTL(3)
RD7/PSP7 30 33 5 I/O ST/TTL(3)
PORTE is a bi-directional I/O port.
RE0/RD/AN5(5)8925I/OST/TTL
(3) RE0 can also be read control for the parallel sl ave port,
or analog input 5(5).
RE1/WR/AN6(5)91026I/OST/TTL
(3) RE1 can also be write control for the p arallel slave port,
or analog input 6(5).
RE2/CS/AN7(5)10 11 27 I/O ST/TTL(3) RE2 can also be select control for the parallel slave
port, or analog input 7(5).
VSS 12,31 13,34 6,29 P Ground ref erence fo r logic and I/O pins.
VDD 11 ,32 12,35 7,28 P P ositive supply for logic and I/O pins.
NC 1,17,28,
40 12,13,
33,34 These pins are not internally connected. These pins should
be left unconnected.
TABLE 3-2: PIC16C65B/74B PINOUT DESCRIPTION (CONTINUED)
Pin Name DIP
Pin# PLCC
Pin#
TQFP
MQFP
Pin#
I/O/P
Type Buffer
Type Description
Legend: I = input O = output I/O = input/output P = powe r
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the e xternal interrupt.
2: This buffer is a Schmitt Tr igger input when used in ser ial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the parallel
slave port mode (for interfacing to a microproces sor bus).
4: This buffer is a Schmitt Tr igger input when configured in RC oscillator mode and a CMOS input otherwise.
5: A/D is not available on the PIC16C65B.
PIC16C63A/65B/73B/74B
DS30605B-page 14 Preliminary 1999 Microchip Technology Inc.
3.1 Clocking Scheme/Instruction Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely, Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instr uc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 3-2.
3.2 Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then tw o cycles are required t o complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the e x ecu tion cy cle, t he f etche d instructio n is latche d
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 an d Q4 cycl es. Data m emory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
PC PC+1 PC+2
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+1)
Internal
phase
clock
Note: All instructions are single cycle, except for any program branches. These take t wo cycles, since the fetch instr uction is
“flushed” from the pipeline, while the new instruction is being fetched and then execut ed.
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. CALL SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush
5. Instruction @ address SUB_1 Fetc h SUB_1 Execute SUB_1
1999 Microchip Technology Inc. Preliminary DS30605B-page 15
PIC16C63A/65B/73B/74B
4.0 MEMORY ORGANIZATIO N
4.1 Program Memory Organization
The PIC16C63A/65B/73B/74B has a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. All devices covered by this datasheet
have 4K x 14 bits of program memory. The address
range is 0000h - 0FFFh for all devices.
Accessing a location above 0FFFh will cause a wrap-
around.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 4-1: PIC16C63A/6 5B/73B/74 B
PROGRAM MEMORY MAP
AND STACK
4.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP1
and RP0 are the bank select bits.
RP1:RP0 (STATUS<6:5>)
= 00 Bank0
= 01 Bank1
= 10 Bank2
= 11 Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the SFRs.
Above the SFRs are GPRs, implemented as static
RAM.
All impl ement ed ban ks co ntain SF Rs. Some “h igh use”
SFRs from one bank may be mirrored in another bank
for code reduction and quicker access.
4.2.1 GENERAL PURPOSE REGISTER FILE
The regis ter file c an be ac cess ed eithe r direct ly o r indi-
rectly through the File Select Register (FSR)
(Section 4.5).
PC<12:0>
13
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
On-chip Program
Memory (Page 1)
Memory (Page 0)
CALL,RETURN
RETFIE,RETLW
User Memory
Space
Note: Maintain the IRP and RP1 bits clear in
these devices.
PIC16C63A/65B/73B/74B
DS30605B-page 16 Preliminary 1999 Microchip Technology Inc.
FIGURE 4-2: REGIS T ER FILE MA P 4.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
The Special Function Registers can be classified into
two s ets (c ore a nd peripheral). Those re gi ste rs a ss oc i-
ated wi th the “c ore” func tions are d escribed in this sec -
tion, and those related to the operation of the peripheral
features are descr ibed in the section of that peripheral
feature.
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(2)
PORTE(2)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES(3)
ADCON0(3)
INDF(1)
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD(2)
TRISE(2)
PCLATH
INTCON
PIE1
PIE2
PCON
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ADCON1(3)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
General
Purpose
Register
General
Purpose
Register
7Fh FFh
Bank 0 Bank 1
File
Address File
Address
Unimplemented data memory locations, read
as ’0’.
Note 1: Not a ph ysical register.
2: These registers are not implemented on the
PIC16C63A/73B, read as '0'.
3: These registers are not implemented on the
PIC16C63A/65B, read as '0'.
1999 Microchip Technology Inc. Preliminary DS30605B-page 17
PIC16C63A/65B/73B/74B
TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
resets(3)
Bank 0
00h INDF(4) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
01h TMR0 Timer0 module ’s register xxxx xxxx uuuu uuuu
02h PCL(4) Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h STATUS(4) IRP(2) RP1(2) RP0 TO PD ZDCC0001 1xxx 000q quuu
04h FSR(4) Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h PORTD(5) PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu
09h PORTE(5) RE2 RE1 RE0 ---- -xxx ---- -uuu
0Ah PCLATH(1,4) Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh INTCON(4) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(5) ADIF(6) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 CCP2IF ---- ---0 ---- ---0
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 modul e’s register 0 000 0000 0000 0000
12h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register x xxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM R egister1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capt ure/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
1Eh ADRES(6) A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0(6) ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as 0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not direct ly accessible. PCLATH is a holding register for the PC<12:8>.
2: The IRP and RP1 bits are reserved; always maintain these bits clear.
3: Other (non power-up) resets include external reset through MCLR and watchdog timer reset.
4: These registers can be addressed from either bank.
5: PORTD, PORTE and the parallel slave port are not implemented on the PIC16C63A/73B; always maintain these bits and
registers clear.
6: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits and registers clear.
PIC16C63A/65B/73B/74B
DS30605B-page 18 Preliminary 1999 Microchip Technology Inc.
Bank 1
80h INDF(4) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h PCL(4) Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
83h STATUS(4) IRP(2) RP1(2) RP0 TO PD ZDCC0001 1xxx 000q quuu
84h FSR(4) Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h TRISD(5) PORT D Data Direction Register 1111 1111 1111 1111
89h TRISE(5) IBF OBF IBOV PSPMODE PORTE Data Direction Bits 0000 -111 0000 -111
8Ah PCLATH(1,4) Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh INTCON(4) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 PSPIE(5) ADIE(6) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 —CCP2IE---- ---0 ---- ---0
8Eh PCON —PORBOR ---- --qq ---- --uu
8Fh Unimplemented
90h Unimplemented
91h Unimplemented
92h PR2 Timer2 Peri od Regi ster 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
94h SSPSTAT —D/A PSR/WUA BF --00 0000 --00 0000
95h Unimplemented
96h Unimplemented
97h Unimplemented
98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMTTX9D0 000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
9Ah Unimplemented
9Bh Unimplemented
9Ch Unimplemented
9Dh Unimplemented
9Eh Unimplemented
9Fh ADCON1(6) PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
resets(3)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as 0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper by te of the program counter is not directly ac cess ible. PCLATH is a holding register for the PC<12:8>.
2: The IRP and RP1 bits are reserved; always maintain these bits clear.
3: Other (non power-up) resets include external reset through MCLR and watchdog timer reset.
4: These registers can be addressed from either bank.
5: PORTD, PORTE and the parallel slave port are not implemented on the PIC16C63A/73B; always maintain these bits and
registers clear.
6: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits and registers clear.
1999 Microchip Technology Inc. Preliminary DS30605B-page 19
PIC16C63A/65B/73B/74B
4.2.2.1 STATUS REGISTER
The STATUS register, shown in Register 4-1, contains
the arithmeti c status of th e ALU , the RESET statu s and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disab led . The se bi ts ar e set o r clea red a ccordi ng to the
device logi c. Fur t her more, the TO and PD bits are no t
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS wi ll cl ea r th e up p er- th r ee
bits an d set the Z bit. This lea v e s the STATUS register
as 000u u1uu (where u = unchang ed).
It is recommended that only BCF, BSF, SWAPF and
MOVWF instruc t io ns be us ed to al t er the S TAT U S r eg i s-
ter. These in structions do not affect the Z, C or DC bit s
in the STATUS register. For other inst ruct ion s wh ic h d o
not affect status bits, see the "Instruction Set Sum-
mary."
REGISTER 4-1: STATUS REGISTER (ADDRESS 03h, 83h)
Note 1: These devices do not use bits IRP and
RP1 (STATUS<7:6>), maintain these bits
clear to ensure upward compatibility with
future products.
2: The C and DC b its op er ate as borrow and
digit borrow bits, respectively, in subtrac-
tion. See the SUBLW and SUBWF instruc-
tions for examples.
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP(1) RP1(1) RP0 TO PD ZDC C(2) R = Readable bit
W = Writable bi t
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit7 bit0
bit 7: IRP(1): Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5: RP1(1):RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4: TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time -out occurred
bit 3: PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2: Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1: DC: Digit carry/borrow bit (ADDWF,ADDLW,SUBLW,SUBWF in structions ) (for borrow t he pol arity is rever sed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0: C(2): Carry/borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note 1: Maintain the IRP and RP1 bits clear.
2: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF,RLF) instructions, this bit is loaded with either the high or low order bit
of the source register.
PIC16C63A/65B/73B/74B
DS30605B-page 20 Preliminary 1999 Microchip Technology Inc.
4.2.2.2 OPTION REGISTER
The OPTION_REG register is a readable and writable
register , which contains various control bits to configure
the TMR0/WDT prescaler, the external INT Interrupt,
TMR0 and the weak pull-ups on PORTB.
REGISTER 4-2: OPTION_REG REGISTER (ADDRESS 81h, 181h)
Note: To achi eve a 1:1 pres caler as signmen t fo r
the TMR0 register, as sign the prescaler to
the watchdog timer.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit7 bit0
bit 7: RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6: INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5: T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clo ck (CLKOUT)
bit 4: T0SE: TMR0 Source Edge Select bit
1 = Increment on high-t o-low transitio n on RA4/T0CKI pi n
0 = Increment on low-to-high transitio n on RA4/T0CKI pi n
bit 3: PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
1999 Microchip Technology Inc. Preliminary DS30605B-page 21
PIC16C63A/65B/73B/74B
4.2.2.3 INTC ON REGISTER
The INTCON register is a readable and writable regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Por t change and exter nal
RB0/INT pin interrupts.
REGISTER 4-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh)
Note: Interrupt flag b its a re set when an in terrupt
conditi on occ urs, regardle ss of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = R eadable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit7 bit0
bit 7: GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6: PEIE: Pe ripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5: T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 inte rrupt
bit 4: INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3: RBIE: RB Port Change Interr upt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2: T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1: INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occu r
bit 0: RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
PIC16C63A/65B/73B/74B
DS30605B-page 22 Preliminary 1999 Microchip Technology Inc.
4.2.2.4 PIE 1 REGIS TER
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 4-4: PIE1 REGISTER (ADDRESS 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit7 bit0
bit 7: PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6: ADIE(2): A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5: RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4: TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2: CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1: PIC16C63A/73B devices do not have a parallel slave port implemented; always maintain t his bit clear.
2: PIC16C63A/65B devices do not have an A/D implemented; always maintain t his bit clear.
1999 Microchip Technology Inc. Preliminary DS30605B-page 23
PIC16C63A/65B/73B/74B
4.2.2.5 PIR1 REGIS TER
This register contains the individual flag bits for the
peripheral interrupts.
REGISTER 4-5: PIR1 REGISTER PIC16C73/73A/74/74A/76/77 (ADDRESS 0Ch)
Note: Interrupt flag b its a re set when an in terrupt
conditi on occ urs, regardle ss of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit7 bit0
bit 7: PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6: ADIF(2): A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion i s not complete
bit 5: RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full (clear by reading RCREG)
0 = The USART receive buffer is empty
bit 4: TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty (clear by writing to TXREG)
0 = The USART transmit buffer is full
bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2: CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register captu re occurred
Compare Mode
1 = A TMR1 register compare ma tch occurred (must be cleared in software)
0 = No TMR1 register compare match occu rred
PWM Mode
Unused in this mode
bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 m atch occurred (must be cl eared in software)
0 = No TMR2 to PR2 match occurred
bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1: PIC16C63A/73B devices do not have a parallel slave port implemented. This bit location is reserved on these
devices.
2: PIC16C63A/65B devices do not have an A/D implemented. This bit location is reserved on these devices.
PIC16C63A/65B/73B/74B
DS30605B-page 24 Preliminary 1999 Microchip Technology Inc.
4.2.2.6 PIE 2 REGIS TER
This register contains the individual enable bit for the
CCP2 peripheral interrupt.
REGISTER 4-6: PIE2 REGISTER (ADDRESS 8Dh)
4.2.2.7 PIR2 REGIS TER
This register contains the CCP2 interrupt flag bit.
.
REGISTER 4-7: PIR2 REGISTER (ADDRESS 0Dh)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
CCP2IE R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit7 bit0
bit 7-1: Unimplemented: Read as '0'
bit 0: CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Note: Interrupt flag b its a re set when an in terrupt
conditi on occ urs, regardle ss of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
CCP2IF R = Rea dable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit7 bit0
bit 7-1: Unimplemented: Read as '0'
bit 0: CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TM R1 regist er ca ptur e occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused
1999 Microchip Technology Inc. Preliminary DS30605B-page 25
PIC16C63A/65B/73B/74B
4.2.2.8 PCON REGISTER
The P ower Control (PCON) regi ster contains flag bits to
allo w differentiatio n betwe en a Power-on Res et (POR),
a Brown- out Rese t (BOR), a Watch -dog Rese t (WDT)
and an external MCLR Reset.
REGISTER 4-8: PCON REGISTER (ADDRESS 8Eh)
Note: BOR is unknown on POR. It must be set by
the user and checked on subsequent
resets to see if BOR is clear, indicating a
brown-out has occurred. The BOR status
bit is a don’t care and is not predictable if
the br own-out cir cuit is di sabled (by clear -
ing the BODEN bit in the configuration
word).
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q
POR BOR R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit7 bit0
bit 7-2: Unimplemented: Read as '0'
bit 1: POR: Power-on Reset Status bit
1 = No power-on reset occurred
0 = A power-on reset occurred (must be set in software after a power-on reset occurs)
bit 0: BOR: Brown-out Reset Status bit
1 = No brown-out reset occurred
0 = A brown-out reset oc curred (must be set in software after a brown-out reset occurs)
PIC16C63A/65B/73B/74B
DS30605B-page 26 Preliminary 1999 Microchip Technology Inc.
4.3 PCL and PCLATH
The prog ram counter (PC ) is 13-bits wide. The lo w byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register . On any reset, the upper bits of the PC
will be cleared. Figure 4-3 shows the two situations for
the loading of the PC. The upper example in the figure
shows how the PC is loaded on a write to PCL
(PCLATH<4:0> PCH). The lower example in the fig-
ure shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> PCH).
FIGURE 4-3: LOADING OF PC IN
DIFFERENT SITUATIONS
4.3.1 COMPUTED GOTO
A comput ed GOTO i s a cc om pli sh ed by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised i f the tabl e loc ation crosse s a PCL
memory boundary (each 256 by te block). Refer to the
application note
“Implementing a Table Read"
(AN556).
4.3.2 STACK
The PIC 16CXX f amily ha s an 8-le vel d eep x 13-bi t wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readab le or writab le . The PC is PUSHed on to the stac k
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN,RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
The stac k operates as a circular b uffer . This means that
after the stac k has b een PU SHed e ight ti mes , th e nin th
push overwrites th e value that was stored fro m the firs t
push. The tenth push o verwrites the sec ond pus h (an d
so on).
4.4 Program Memory P aging
PIC16CXX de vices are capab le of addres sing a contin-
uous 8K w ord bl ock of pr ogram me mory. The CALL and
GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memor y page.
When doing a CALL or GOTO instruction, the upper 2
bits of the address are provided by PCLATH<4:3>.
When doi ng a CALL or GOTO instruction, the user m us t
ensure that the page select bits are programmed so
that t he desired pro gr am memo ry page is addressed. If
a return from a CALL instruction (or interrupt) is exe-
cuted, the entire 13-bit PC is pushed onto the stack.
Therefore, manipulation of the PCLATH<4:3> bits are
not require d for the retu rn instruction s (which POPs the
address from the stack).
Example 4-1 shows the calling of a subroutine in
page 1 of the pr ogram m emory. This e xample as sumes
that PCL ATH is sav ed and res tored by the interrupt ser-
vice r outine (if interr upts are used).
EXAMPLE 4-1: CALL OF A SUBR OUTINE IN
PAGE 1 FROM PAGE 0
ORG 0x500
BSF PCLATH,3 ;Select page 1 (800h-FFFh)
CALL SUB1_P1 ;Call subroutine in
: ;page 1 (800h-FFFh)
:
ORG 0x900 ;page 1 (800h-FFFh)
SUB1_P1: ;called subroutine
: ;page 1 (800h-FFFh)
:
RETURN ;return to Call subroutine
;in page 0 (000h-7FFh)
PC
12 8 7 0
5PCLATH<4:0>
PCLATH
Instruction with
ALU
GOTO,CALL
Opcode < 10:0 >
8
PC
12 11 10 0
11
PCLATH<4:3>
PCH PCL
87
2
PCLATH
PCH PCL
PCL as
Destination
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions that
occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instruc-
tions, or the vectoring to an interrupt
address.
Note: PCLATH<4> is not used in these PICmicro®
devic es. The use of PCLATH<4> as a gen-
eral purpose read/write bit is not recom-
mended, since this may affect upward
compatibility with future products.
1999 Microchip Technology Inc. Preliminary DS30605B-page 27
PIC16C63A/65B/73B/74B
4.5 Indirect Addressing, INDF and FSR
Registers
The INDF re gister is not a ph ysical register . Add ressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
acces ses the register p ointed to b y the File Sele ct Reg-
ister, FSR. Reading the INDF register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF register
indirec tly resu lts in a no-o pera tio n (althou gh statu s bits
ma y be affected ). An e ff ecti v e 9-b it ad dress is o btaine d
by c on cat ena tin g the 8 - bit FS R re gis ter an d the IRP bit
(STATUS<7>), as shown in Figure 4-4.
A simple program to clear RAM locations 20h-2Fh
using indirect addressi ng is shown in Exam ple 4-2.
EXAMPLE 4-2: INDIRECT ADDRESSING
movlw 0x20 ;initialize pointer
movwf FSR ;to RAM
NEXT clrf INDF ;clear INDF register
incf FSR,F ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;no clear next
CONTINUE : ;yes continue
FIGURE 4-4: DIRECT/INDIRECT ADDRESSING
Note: Maintain the IRP and RP1 bits clear.
Note: For register file map detail see Figure 4-2.
Shaded portions are not implemented; maintain the IRP and RP1 bits clear.
Data
Memory
Indirect AddressingDirect Addressing
bank select location select
RP1:RP0 6 0
from opcode IRP FSR register
70
bank select location select
00 01 10 11
Bank 0 Bank 1 Bank 2 Bank 3
not used
FFh
80h
7Fh
00h
17Fh
100h
1FFh
180h
0
0
PIC16C63A/65B/73B/74B
DS30605B-page 28 Preliminary 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. Preliminary DS30605B-page 29
PIC16C63A/65B/73B/74B
5.0 I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
5.1 PORTA and TRISA Registers
POR TA is a 6-bit latch.
The RA4/T0CKI pin is a Schmitt Trigger input and an
open drain output. All other RA port pins have TTL
input lev els an d full CMOS output drive rs. All pins h a v e
data direction bits (TRIS registers), which can config-
ure these pins as output or input.
Setting a TRISA register bit puts the correspondin g out-
put driv er in a hi- imped ance m ode . Cleari ng a bit in the
TRISA register puts the contents of the output latch on
the selected pin(s).
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Theref ore, a write to a port implies that the port pins are
read, the value is modified, and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin.
On the PIC16C73B/74B, PORTA pins are multiplexed
with analog inputs and analog VREF input. The opera-
tion of each pin is selected by clearing/setting the con-
trol bits in the ADCON1 register (A/D Control
Register1).
The TRISA register controls the direction of the RA
pins, even when they are being used as an alog inputs.
The user m ust ensure the bits in the TRI SA registe r are
maintained set when using them as analog inp uts.
EXAMPLE 5- 1: INITIALIZING PORTA
(PIC16C73B/74B)
BCF STATUS, RP0 ;
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0x06 ; Configure all pins
MOVWF ADCON1 ; as digital inputs
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as ’0’.
FIGURE 5-1: BLOCK DIAGRAM OF RA3:RA0
AND RA5 PINS
FIGURE 5-2: BLOCK DIAGRAM OF
RA4/T0CKI PIN
Note: On all resets, pins with analog functions
are configured as analog an d digital inputs.
Data
Bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR
Port
WR
TRIS
Data Latch
TRIS Latch
RD TRIS
RD PORT
VSS
VDD
I/O pin
Note 1: I/O pins hav e protection diodes to VDD and
VSS.
Analog
input
mode
TTL
Input
Buffer
To A/D Converter
(1)
Data
Bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
Input
Buffer
N
VSS
I/O pi n
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
QD
Q
CK
QD
Q
CK
EN
QD
EN
(1)
PIC16C63A/65B/73B/74B
DS30605B-page 30 Preliminary 1999 Microchip Technology Inc.
TABLE 5-1: PORTA FUNCTIONS
TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit# Buffer Function
RA0/AN0(1) bit0 TTL Digital input/output or analog input
RA1/AN1(1) bit1 TTL Digital input/output or analog input
RA2/AN2(1) bit2 TTL Digital input/output or analog input
RA3/AN3/VREF(1) bit3 TTL Digital inpu t/output or analog input or VREF
RA4/T0CKI bit4 ST Digital input/output or external clock input for Timer0
Output is open drain type
RA5/SS/AN4(1) bit5 TTL Input/output or slave select input for synchronous serial port or analog input
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: The A/D is not implemented on the PIC16C63A/65B. Pins will operate as digital I/O only. ADCON1 is not implemented;
maintain this register clear.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
V alue on all
other resets
05h PORTA RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA PORTA Data Direction Register --11 1111 --11 1111
9Fh ADCON1(1) PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unc hanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note 1: The A/D is not implemented on the PIC16C63A/65B. Pins will operate as digital I/O only. ADCON1 is not implemented;
maintain this register clear.
1999 Microchip Technology Inc. Preliminary DS30605B-page 31
PIC16C63A/65B/73B/74B
5.2 PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional por t. The corre-
sponding data direction register is TRISB. Setting a bit
in the TRISB register puts the corresponding output
driver in a hi-impedance input mode. Clearing a bit in
the TRISB re gister puts the c ontents of th e output latch
on the selected pin(s).
Each o f the POR TB pins has a weak internal p ull -up. A
single control bit can turn on all the pu ll-ups. This is per-
formed by c learing bi t R BPU (OPTION_REG<7 >). The
weak pu ll-up i s automa tically t ur ned off wh en the por t
pin is configured as an output. The pull-ups are dis-
abled on a power-on reset.
FIGURE 5-3: BLOCK DIAGRAM OF
RB3:RB0 PINS
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause t his interrupt to occur (i.e . an y RB7:RB4 pin con-
figured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compared with the value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user , in th e interrupt service routine , can clear the int er-
rupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
This interr upt on mismatch feature, together with soft-
ware configure able pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key-depression. Refer to the Embedded
Control Handbook,
“Implementing Wake-Up on Key
Stroke
(AN552).
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the in terrup t on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
RB0/IN T is an external interru pt input pin and is confi g-
ured using the INTEDG bit (OPTION_REG< 6>).
RB0/INT is discussed in detail in Section 13.5.1.
FIGURE 5-4: BLOCK DIAGRAM OF
RB7:RB4 PINS
Data Latch
RBPU(2) P
VDD
QD
CK
QD
CK
QD
EN
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
weak
pull-up
RD Port
RB0/INT
I/O
pin
TTL
Input
Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
Schmitt Trigger
Buffer
TRIS Latch
(1)
Data Latch
From other
RBPU(2) P
VDD
I/O
QD
CK
QD
CK
QD
EN
QD
EN
Data Bus
WR Port
WR TRIS
Set RBIF
TRIS Latch
RD TRIS
RD Port
RB7:RB4 pi ns
weak
pull-up
RD Port
Latch
TTL
Input
Buffer
pin
Note 1: I/O pins have d iode prote ction to VDD and VSS.
ST
Buffer
RB7:RB6 in serial programming mode Q3
Q1
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
(1)
PIC16C63A/65B/73B/74B
DS30605B-page 32 Preliminary 1999 Microchip Technology Inc.
TABLE 5-3: PORTB FUNCTIONS
TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit# Buffer Function
RB0/INT bit0 TTL/ST(1) Input/output pin or e x ternal interrupt input. Internal software
programmable weak pull-up.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt on change). Inter nal software programmable weak
pull-up.
RB5 bit5 TTL Input/output pin (with interrupt on change). Inter nal software programmable weak
pull-up.
RB6 bit6 TTL/ST(2) Input/output pin ( with interrupt on change). Internal software programmable weak
pull-up. Serial programming clock.
RB7 bit7 TTL/ST(2) Input/output pin ( with interrupt on change). Internal software programmable weak
pull-up. S erial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: Th is buffer is a Schmitt Trigger input when configured as the exter nal interrupt.
2: This buffer is a Sc hmit t Trigger input when used in serial programming mode.
Address Na me Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB 2 RB1 RB0 xxxx xxxx uuuu uuuu
86h, 186h TRISB PORTB Data Direc tion Register 1111 1111 1111 1111
81h, 181h OPTION_REG RB PU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
1999 Microchip Technology Inc. Preliminary DS30605B-page 33
PIC16C63A/65B/73B/74B
5.3 PORTC and TRISC Registers
PORTC is an 8-bit bi-directional por t. Each pin is indi-
vidually configure ab le as an input or outp ut through the
TRISC register. PORTC is multiplexed with several
peripheral functions (Table 5-5). PORTC pins have
Schmitt Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bi t to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instr uctions (BSF, BCF, XORWF) with TRISC as
destina tion sh ould be a v oided. Th e user should ref er to
the corresponding peripheral section for the correct
TRIS bit settings.
FIGURE 5-5: PORTC BLOCK DIAGRAM
TABLE 5-5: PORTC FUNCTIONS
TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
PORT/PERIPHERAL Select(2)
Data Bus
WR
PORT
WR
TRIS
RD
Data Latch
TRIS Latch
RD TRIS Schmitt
Trigger
QD
Q
CK
QD
EN
Peripheral Data Out 0
1
QD
Q
CK
P
N
VDD
VSS
PORT
Peripheral
OE(3)
Peripheral Input
I/O
pin
Note 1: I/O pins have diode protection to VDD and VSS.
2: P ort/P eripheral select signal selects between port
data and peripheral output.
3: Peripheral OE (output enable) is only activat ed if
peripheral select is active.
(1)
Name Bit# Buffer Type Function
RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input.
RC1/T1OSI/CCP2 bit1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/Compare2 out-
put/PWM2 output.
RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes.
RC4/SDI/SDA bit4 ST R C4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode).
RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output.
RC6/TX/CK bit6 ST Input/output port pin or USART Asynchronous Transmit, or USART Synchro-
nous Clock.
RC7/RX/DT bit7 ST Input/output port pin or USART Asynchronous Receive, or USART Synchro-
nous Data.
Legend: ST = Schmitt Tr igger input
Addr e s s Name Bit 7 Bi t 6 B it 5 Bit 4 Bit 3 B i t 2 Bit 1 B it 0 Value on:
POR,
BOR
Value on all
other resets
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unc hanged.
PIC16C63A/65B/73B/74B
DS30605B-page 34 Preliminary 1999 Microchip Technology Inc.
5.4 PORTD and TRISD Registers
PORTD is an 8-bit por t with Schmitt Trigger input buff-
ers. Each pin is individually configured as an input or
output.
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In th is mode, the in put bu ffe rs
are TTL.
FIGURE 5-6: PORTD BLOCK DIAGRAM
TABLE 5-7: PORTD FUNCTIONS
TABLE 5-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Note: The PIC16C63A and PIC16C73B do not
provide PORTD. The PORTD and TRISD
registers are not implemented.
Data
Bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
Input
Buffer
I/O pin
Note 1: I/O pins have protection diodes to VDD and VSS.
QD
CK
QD
CK
EN
QD
EN
(1)
Name Bit# Buffer Type Function
RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or parallel s lave port bit0
RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel s lave port bit1
RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or parallel s lave port bit2
RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or parallel s lave port bit3
RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or parallel s lave port bit4
RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or parallel s lave port bit5
RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or parallel s lave port bit6
RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or parallel s lave port bit7
Legend: ST = Schmitt Trigger input TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in parallel sla ve port mode.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
88h TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h TRISE IBF OBF IBOV PSPMODE PORTE Data Direction Bits 0000 -111 0000 -111
Legend: x = unknown, u = unc hanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.
1999 Microchip Technology Inc. Preliminary DS30605B-page 35
PIC16C63A/65B/73B/74B
5.5 PORTE and TRISE Register
PORTE has three pins RE0/RD/AN5, RE1/WR/AN6
and RE2/C S/AN7, which are individually configured as
inputs or outputs. These pins have Schmitt Trigger
input buffers.
I/O PORTE becomes control inputs for the micropro-
cessor port when bit PSPMODE (TRISE<4>) is set. In
this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs) and th at regi ster AD CON1 i s con figured f or di g-
ital I/O. In this mode the input buffers are TTL.
Register 5-1 shows the TRISE register , which also con-
trols the parallel slave port operation.
PORTE pins may be multiplexed with analog inputs
(PIC16C74B only). The operation of these pins is
selected by control bits in the ADCON1 register. When
select ed as an analo g input, these pins will r ead as ’ 0’s .
TRISE control s the direction of th e RE pins, e v en when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
FIGURE 5-7: PORTE BLOCK DIAGRAM
TABLE 5-9: PORTE FUNCTIONS
Note 1: The PIC16C63A and PIC16C73B do not
provid e PORTE. The PO RTE and TRISE
registers are not implemented.
2: The PIC16C63A/65B does not provide an
A/D mo dule. A/ D func tions are no t imple -
mented.
Note: On a Power-on Reset these pins are con-
figured as analog inputs.
Data
Bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
Input
Buffer
QD
CK
QD
CK
EN
QD
EN
I/O pin (1)
Note 1: I/O pins have protection diodes to VDD and VSS.
Name Bit# Buffer Type Function
RE0/RD/AN5 bit0 ST/TTL(1) Inpu t/output port pin or read control input in parallel slave port mode or analog
input: RD
1 = Not a read operation
0 = Read operation. Reads PORTD register (if chip selected)
RE1/WR/AN6 bit1 ST/TTL(1) Input/output port pin or write control input in parallel slave port mode or analog
input: WR
1 = Not a write operation
0 = Write operation. Writes PORTD register (if chip selected)
RE2/CS/AN7 bit2 ST/TTL(1) Input/output port pin or chip select control input in parallel slave port mode or
analog input:
CS
1 = Device is not selected
0 = Device is s elected
Legend: ST = Schmitt Trigger input TTL = TTL input
Note 1: Input buffer s are Schmitt Triggers when in I/O mode and TTL buffers when in parallel slave port mode.
PIC16C63A/65B/73B/74B
DS30605B-page 36 Preliminary 1999 Microchip Technology Inc.
REGISTER 5-1: TRISE REGISTER (ADDRESS 89h)
TABLE 5-10: SUMMARY OF REGISTER S ASSOCIATED WITH PORTE
R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1
IBF OBF IBOV PSPMODE TRISE2 TRISE1 TRISE0 R = Readable bit
W = W r itable bit
U = Unimplem ented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7 : IBF: Input Buffer Full Status bit
1 = A word has been receiv ed and is waiting to be read by the CPU
0 = No word has been receiv ed
bit 6: OBF: O ut put Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5: IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1 = A write occurred when a prev iously input word has not been read (must be cleared in software)
0 = N o overflow occur red
bit 4: PSPMODE: Parallel Sla ve Port Mode Select bit
1 = Parallel slave port mode
0 = General purpose I/O mode
bit 3: Unimplemented: Read as '0'
PORTE Data Direction Bits
bit 2: TRISE2: Direction Control bit for pin RE2/CS/AN7
1 = Input
0 = Output
bit 1: TRISE1: Direction Control bit for pin RE1/WR/AN6
1 = Input
0 = Output
bit 0: TRISE0: Direction Control bit for pin RE0/RD/AN5
1 = Input
0 = Output
Address Name Bit 7 Bit 6 Bit 5 B it 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
09h PORTE —RE2 RE1 RE0---- -xxx ---- -uuu
89h TRISE IBF OBF IBOV PSPMODE PORTE Data Direction Bits 0000 -111 0000 -111
9Fh ADCON1 PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unc hanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
1999 Microchip Technology Inc. Preliminary DS30605B-page 37
PIC16C63A/65B/73B/74B
5.6 Parallel Slave P ort (PSP)
PORTD operates as an 8-bit wide Parallel Slave Port
(PSP), or microprocessor port when control bit PSP-
MODE (TRISE<4>) is set. In slave mode, it is asyn-
chronou sly readab le and writab le, b y the e xternal world
through RD control input pin RE0/RD/AN5 and WR
control input pin RE1/WR/AN6.
It can directly interf ace to an 8-bit microprocessor data
bus . The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD/AN5 to be the RD input,
RE1/WR/AN6 to be the WR input and RE2/CS/AN7 to
be the CS (chip select) input. For this functionalit y, the
corresponding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (set) and
the A/D port configuration bits PCFG2:PCFG0
(ADCON1<2:0>) must be set, which will configure pins
RE2:RE0 as digital I/O.
There are actually two 8-bit latches, one for data-out
(from the PICmicro®) and one for data input. The user
writes 8-bit data to PORTD data latch and reads data
from the port pin latch (note that they have the same
address). In this mode, the TRISD register is ignored,
since the microprocessor is controlling the direction of
data flo w.
A write to the PSP occurs when both the CS and WR
lines ar e f irs t de t ec ted l ow. W h en eit h er th e C S or WR
lines become high (level triggered), then the Input
Buff er Full (IBF) status flag bit (TRISE<7>) is set on the
Q4 clock cycle, following the next Q2 cycle, to signal the
write is complete (Figure 5-9). The interrupt flag bit
PSPIF (PIR1<7>) is also set on the same Q4 clock
cycle. IBF can only be cleared by reading the PORTD
input latch. The Input Buff er Overflo w (IBOV) status flag
bit (TRISE<5>) is set if a second write to the PSP is
attempted when the previous byte has not been read
out of the buffer.
A read from t he PSP occurs when both the CS and R D
lines are first detected low. The Output Buffer Full
(OBF) status flag bit (TRISE<6>) is cleared immedi-
ately (Figure 5-10) indicating that the PORTD latch is
wa iti ng t o be rea d by the external bus. When either th e
CS or RD pin becomes hi gh (level triggered), the inter-
rupt flag bit PSPIF is set on the Q4 clock cycl e, follow-
ing the next Q2 cycle, indicating that the read is
complete. OBF remains low until data is written to
PORTD by the user firmware.
When not in PSP mode, the IBF and OBF bits are hel d
clear. However, if flag bit IBOV was previously set, it
must be cleared in firmware.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF mus t be cleare d b y the u ser in firmware a nd the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7>).
FIGURE 5-8: PORTD AND PORTE BLOCK
DIAGRAM (P ARALLEL SLAVE
PORT)
Note: The PIC16C63A and PIC16C73B do not
provid e a par allel sl ave por t. T he PORTD,
PORTE, TRISD and TRISE registers are
not implemented.
Data Bus
WR
PORT
RD
RDx
QD
CK
EN
QD
EN
PORT
pin
One bit of PORTD
Set interrupt flag
PSPI F (PIR1<7> )
Read
Chip Select
Write
RD
CS
WR
Note: I/ O pin has protection diodes to VDD and VSS.
TTL
TTL
TTL
TTL
PIC16C63A/65B/73B/74B
DS30605B-page 38 Preliminary 1999 Microchip Technology Inc.
FIGURE 5-9: PARALLEL SLAVE PORT WRITE WAVEFORMS
FIGURE 5-10: PARALLEL SLAVE PORT READ WAVEFORMS
TABLE 5-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value o n:
POR,
BOR
Value on all
other resets
08h PORTD Port data latch when written: Port pins when read xxxx xxxx uuuu uuuu
09h PORTE —RE2RE1 RE0---- -xxx ---- -uuu
89h TRISE IBF OBF IBOV PSPMODE PORTE Data Direction Bits 0000 -111 0000 -111
0Ch PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8ChPIE1PSPIE
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
9Fh ADCON1 —PCFG2PCFG1PCFG0---- -000 ---- -000
Legend: x = unknown, u = unc hanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
RD
IBF
OBF
PSPIF
PORTD<7:0>
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
IBF
PSPIF
RD
OBF
PORTD<7:0>
1999 Microchip Technology Inc. Preliminary DS30605B-page 39
PIC16C63A/65B/73B/74B
6.0 TIMER0 MODULE
The Tim er0 module timer/count er has the f ollo wing f ea-
tures:
8-bit timer/counter
Readable and writable
8-bit software p rogrammable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
Figu re 6-1 is a b l oc k di ag ra m o f th e Ti me r0 m od ule a nd
the p r e s cal e r s ha red with th e W D T.
Additional information on the Timer0 module is availab le
in the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023A).
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In timer mode, the Timer0 mod-
ule wi ll i nc rem ent every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
use r can wo rk around this by writing an adjusted value
to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
dis c ussed in detail in Section 6.2.
The prescaler is mutually exclusively shared between
the Timer0 module and the watchdog timer. The pres-
caler is not re adab le o r writab le . Sec tion 6.3 details the
oper at ion of the presca le r.
6.1 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister over flows from FFh to 00h . This overflow se ts bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in s oftwa re b y th e Tim er0 mo dule interrupt s er-
vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP.
FIGURE 6-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
RA4/T0CKI
T0SE
pin
M
U
X
CLKOUT (=Fosc/4)
SYNC
2
Cycles TMR 0 r e g
8-bit Prescaler
8 - to - 1MUX
M
U
X
M U X
Watchdog
Timer
PSA
01
0
1
WDT
Time-out
PS2:PS0
8
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
PSA
WDT Enable bit
M
U
X
0
10
1
Data Bus
Set flag bit T0IF
on Overflow
8
PSA
T0CS
PRESCALER
PIC16C63A/65B/73B/74B
DS30605B-page 40 Preliminary 1999 Microchip Technology Inc.
6.2 Using Timer0 with an External Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plishe d by sam pling the presca ler output on th e Q2 and
Q4 cycles of the inter nal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
6.3 Prescaler
There is only one prescaler available which is mutually
exclusively shared between the Timer0 module and the
watchdog timer. A prescaler assignment for the Timer0
module means that there is no prescaler for the Watch-
dog Timer , and vice-versa. This prescaler is not readable
or writable (see Figure 6-1).
The PSA and PS2:PS0 bits (OPTION_REG<3:0>) deter-
mine the prescaler assignment and prescale ratio .
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler . When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writabl e.
REGISTER 6-1: OPTION_REG REGISTER
Note: Writing to TMR0, when the prescaler is
assigned to Timer0, will clear the prescaler
count, but will not change the prescaler
assignment.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPUINTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit
W = W r itable bit
U = Unimplem ented bit,
read as ‘0’
- n = Value at POR reset
bit 7 bit 0
bit 7: RBPU
bit 6: INTEDG
bit 5: T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instructio n cycle clock (CLKOUT)
bit 4: T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transi tion on T0CKI pin
0 = Increment on low-to-high transi tion on T0CKI pin
bit 3: PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
Note: To av oid an unint ended de vice RESET, the in struction sequ ence s how n in the PICmicro™ Mid-Ran ge MCU
Family Reference Manual (DS33023A) must be executed when changing the prescaler assignment from
Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
1999 Microchip Technology Inc. Preliminary DS30605B-page 41
PIC16C63A/65B/73B/74B
TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bi t 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
01h,101h TMR0 Ti mer0 mo dule’s register xxxx xxxx uuuu uuuu
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unc hanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer 0.
PIC16C63A/65B/73B/74B
DS30605B-page 42 Preliminary 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. Preliminary DS30605B-page 43
PIC16C63A/65B/73B/74B
7.0 TIMER1 MODULE
The T ime r1 m od ule is a 1 6-bi t ti mer/counter cons is tin g
of two 8-bit registers (TMR1H and TMR1L), which are
readable and writable. The TMR1 Register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls ov er to 0000h. The TMR1 Interrupt, if enabled,
is generated on overflow, which is latched in interrupt
flag bit TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit TMR1IE (PIE1<0>).
Timer1 can operate in one of two modes:
•As a timer
•As a counter
The operating mode is deter mined by the clock select
bit, TMR1CS (T1CON<1>).
In timer mode, Timer1 increments every instruction
cycle. In coun ter mo de, it in creme nts on every ri sing
edge of the external clock input.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR 1 ON (T1C O N<0>).
Timer1 a lso has an in ternal “reset input ”. This reset can
be generated by either of the two CCP modules
(Section 9.0). Register 7-1 shows the Timer1 control
register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC<1:0> value is
ignored.
Additional infor mation on timer modules is available in
the PICmicro™ Mid-range MCU Family Reference
Manual (DS33023A).
REGISTER 7-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-6: Unimplemented: Read as ’0’
bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 P rescale value
10 = 1:4 P rescale value
01 = 1:2 P rescale value
00 = 1:1 P rescale value
bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillat or is enabled
0 = Oscillator is shut off (The oscillator inverter is turned off to eliminate power drain)
bit 2: T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1: TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0: TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
PIC16C63A/65B/73B/74B
DS30605B-page 44 Preliminary 1999 Microchip Technology Inc.
7.1 Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect since the internal clock is
always in sync.
7.2 Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode , the time r increments on e v ery rising edge of
clock input on pin RC1/T1OSI/CCP2, when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when
bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with inter nal phase clocks. The synchro-
nization is done after the prescaler stage. The pres-
caler stage is an asynchronous ripple-counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut off. The pres-
caler however will continue to increment.
FIGURE 7-1: TIMER1 BLOCK DIAG RAM
TMR1H TMR1L
T1OSC T1SYNC
TMR1CS
T1CKPS1:T1CKPS0 SLEEP input
T1OSCEN
Enable
Oscillator(1) FOSC/4
Internal
Clock
TMR1ON
on/off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
clock input
2
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(2)
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
2: For the PIC16C65B/73B/74B, the Schmitt Trigger is not implemented in external clock mode.
Set flag bit
TMR1IF on
Overflow TMR1
(2)
1999 Microchip Technology Inc. Preliminary DS30605B-page 45
PIC16C63A/65B/73B/74B
7.3 Timer1 Operation in Asynchronous
Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow which will wake-up
the processor. However, special precautions in soft-
ware are needed to read/write the timer (Section 7.3.1).
In asynchronous counter mode, Timer1 can not be used
as a time-base for capture or compare operations.
7.3.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will guarantee a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself poses cer tain problems, since
the timer may overflow between the reads.
For writes, it is r eco mm en ded that the u se r sim pl y sto p
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care . Examples
12-2 and 12-3 in the PICmicro™ Mid-Range MCU Fam-
ily Reference Manual (DS33023A) show how to read
and write Timer1 when it is running in asynchronous
mode.
7.4 Timer1 Oscillator
A crystal oscillator circuit is built-in betw een pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control b it T1OSCEN (T1CON<3>). The osc illa-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for use with a 32 kHz crystal. Table 7-1 shows the
capacitor selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 7-1: CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
7.5 Resetting Timer1 using a CCP Trigger
Output
If the CCP1 or CCP2 module is configured in compare
mode to generate a “special event trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1.
Timer1 must be configured for either timer or synchro-
niz ed counter m ode to tak e adv antage of th is f eature . If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
In the e v ent that a write to Timer1 coi ncides with a spe-
cial event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL regis-
ter pair effectively becomes the period register for
Timer1.
7.6 Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H an d TMR 1 L reg isters are not reset to 00h o n a
POR or an y oth er reset e xce pt b y the CCP1 and C CP2
special event triggers.
T1CON regist er is reset t o 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other resets, the register is
unaffected.
7.7 Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
Osc Type Freq C1 C2
LP 32 kHz 33 pF 33 pF
100 k Hz 15 pF 15 pF
200 k Hz 15 pF 15 pF
Thes e values are for design guidance only.
Crystals Tested:
32.768 kHz Epson C -001R32.768K-A ± 20 PPM
100 kHz Epson C-2 100. 00 KC-P ± 20 PPM
200 kHz STD XTL 200.000 kHz ± 20 PPM
Note 1: Higher capacitance increases the stability of
oscillator but also increases the star t -up time.
2: Since each resonator/crystal has its own charac-
teristics, the user should consult the resonator/
cry st al manufacturer for appropriat e values of
ex ternal components.
Note: The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
PIC16C63A/65B/73B/74B
DS30605B-page 46 Preliminary 1999 Microchip Technology Inc.
TABLE 7-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,
18Bh
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Mos t Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
1999 Microchip Technology Inc. Preliminary DS30605B-page 47
PIC16C63A/65B/73B/74B
8.0 TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mo de of the CCP m od ule (s). The T MR2 re g-
ister is readable and writable, and is cleared on any
device res et.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1: 0>).
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readab le and writable register . The PR2 register is ini-
tialized to FFh upon reset.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
Timer2 can be shut off by clearing co ntrol bit TMR2ON
(T2CON<2>) to minimize power consumptio n.
Register 8-1 shows the Timer2 control register.
Additional infor mation on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manu al (DS330 23A).
8.1 Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
a write to the TMR2 register
a write to the T2CON register
any device reset (POR, MCLR reset, WDT reset
or BOR)
TMR2 is not cleared when T2CON is written.
8.2 Output of TMR2
The outpu t of TMR2 (bef ore th e postscaler) i s fed t o the
SSPort module, which optionally uses it to generate
shift clock.
FIGURE 8-1: TIMER2 BLOCK DIAG RAM
Comparator
TMR2
Sets flag
TMR2 reg
output (1)
Reset
Postscaler
Prescaler
PR2 reg
2
FOSC/4
1:1 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
Note 1: TMR2 register output can be software selected
by the SSP module as a baud clock.
to
T2OUTPS3:
T2OUTPS0
T2CKPS1:
T2CKPS0
REGISTER 8-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: Unimplemented: Read as '0'
bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
0010 = 1:3 Postscale
1111 = 1:16 Postscale
bit 2: TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
PIC16C63A/65B/73B/74B
DS30605B-page 48 Preliminary 1999 Microchip Technology Inc.
TABLE 8-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF(2)RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE(2)RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unk nown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserve d on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
1999 Microchip Technology Inc. Preliminary DS30605B-page 49
PIC16C63A/65B/73B/74B
9.0 CAPTURE/COMPARE/PWM
MODULES
Each Capture/Compare/PWM (CCP) module contains
a 16-bit register which can operate as a:
16-bit capture register
16-bit compare register
PWM master/slave Duty Cycle register
Both the CCP1 and CCP2 modules are identical in
oper ation, with th e e xception be ing the oper ation of the
special event trigger. Table 9-1 and Table 9-2 show the
resources and interactions of the CCP module(s). In
the following sections, the operation of a CCP module
is described with respect to CCP1. CCP2 operates the
same as CCP1, except where noted.
CCP1 Module:
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the oper ation of CCP1. Th e special e vent trigger is gen-
erated by a compa re match and wi ll reset Timer1.
CCP2 Module:
Capture/Compare/PWM Register1 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the oper ation of CCP2. The special e vent trigger is gen-
erated by a compare match and will reset Timer1 and
start an A/D conversion (if the A/D module is enabled).
Additional infor mation on CCP modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023) and in “Using the CCP Modules”
(AN594).
TABLE 9-1: CCP MODE - TIMER
RESOURCES REQUIRED
TABLE 9-2: INTERACTION OF TWO CCP MODULES
CCP Mode Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
CCPx Mode CCPy Mode Interaction
Capture Capture Same TMR1 time-base .
Capture Compare The compare shou ld be conf igure d for the special e vent trigger, which clea rs TMR1.
Compare Compare The compare(s) should be con figur ed for the specia l e vent trigger, which cle ars TMR 1.
PWM PWM The PWMs will have the same fr equency and update rate (TMR2 interrupt).
PWM Capture None.
PWM Compare None.
PIC16C63A/65B/73B/74B
DS30605B-page 50 Preliminary 1999 Microchip Technology Inc.
REGISTER 9-1: CCP1CON REGISTER/CCP2CON REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 R = Readable bit
W = Writable bit
U = Unimplemented bit, read as
‘0’
- n = V alu e at POR reset
bit7 bit0
bit 7-6: Unimplemented: Read as ’0’
bit 5-4: CCPxX:CCPxY: PWM Least Significant bits
Capture Mode : Unused
Compare Mode: Unused
PWM Mode: T hes e b its are t he two LSbs of t he PW M d uty cy cl e . T he eight MSbs are found in C CP RxL .
bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/ PWM off (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = C ompare m ode, generate softw are interrup t on match (CCPxIF b it is se t, CCPx p in is u naff ected)
1011 = Compare mode, tr igger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1 resets
TMR1; CCP2 re sets TMR1 and starts an A/D conversion (if A/D module is enabled)
11xx = PWM mode
1999 Microchip Technology Inc. Preliminary DS30605B-page 51
PIC16C63A/65B/73B/74B
9.1 Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit v alue of the TM R1 register when a n ev ent occu rs
on pin RC2/CCP1. An event is defined as:
Every fal lin g edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
An event is sele cted by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. The
interrupt flag must be cleared in software. If another
capture occurs before the value in register CCPR1 is
read, the old captured value will be lost.
9.1.1 CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
FIGURE 9-1: CAPTURE MODE OPERATION
BLOC K DIAGRAM
9.1.2 TIMER1 MODE SELECTION
Timer1 must be running in timer mode or synchronized
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode, the capture
operation may not work.
9.1.3 SOFTWARE INTERRUPT
When the capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
9.1.4 CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in capture mode,
the prescaler counter is cleared. Any reset will clear the
prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 9-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 9-1: CHANGIN G BETWEEN
CAPTURE PRESCALERS
CLRF CCP1CON ;Turn CCP module off
MOVLW NEW_CAPT_PS ;Load the W reg with
; the new precscaler
; move value and CCP ON
MOVWF CCP1CON ;Load CCP1CON with this
; value
Note: If the RC2/CCP1 pin is configured as an
output, a w rite to the port can cause a cap-
ture condition.
CCPR1H CCPR1L
TMR1H TMR1L
Set flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Q’s CCP1CON<3:0>
RC2/CCP1
Prescaler
÷ 1, 4, 16
and
edge detect
Pin
PIC16C63A/65B/73B/74B
DS30605B-page 52 Preliminary 1999 Microchip Technology Inc.
9.2 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. Wh en a match occ urs, the RC2/CC P1 pin is:
•Driven High
•Driven Low
Remains Unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 9-2: COMPARE MODE OPERATION
BLOCK DIAGRAM
9.2.1 CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
9.2.2 T IMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
9.2.3 SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set causing
a CCP interrupt (if enabled).
9.2.4 SPECIAL EVENT TRIGGER
In this mod e, an i nternal hardw a re trigger is g ener ated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the TMR1
register pair . This allows the CCPR1 register to effectively
be a 16-bit programmab le period register for Timer1.
The special event trigger output of CCP2 resets the
TMR1 regi ster pair and s tarts an A/D co nversio n (i f th e
A/D module is enabled).
9.3 PWM Mode (PWM)
In pulse width modulation mode, the CCPx pin pro-
duces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiple xed with the POR TC data latch, the
TRISC<2> bit must be cleared to make the CCP1 pin
an output.
Figure 9-3 shows a simplified block diagram of the CCP
module in PWM mode.
F or a step by step proced ure on ho w to s et up the C CP
module for PWM operation, see Section 9.3.3.
FIGURE 9-3: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM o utpu t (Fig ure 9-4) has a tim e ba se ( period) and
a time that the output stays high (duty cycle). The fre-
quency of the PWM is the inverse of the period (1/period).
FIGURE 9-4: PWM OUTPUT
Note: Clearing the CCP1CON register will force
the RC2/ CCP1 compare output latch to the
default low level. This is not the data latch.
Note: The special event trigger from the
CCP1a nd CCP2 mo dules will not se t inter-
rupt flag bit TMR1IF (PIR1<0>).
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
ROutput
Logic
Special Ev ent Trigger
Set flag bit CCP1IF
(PIR1<2>)
match
RC2/CCP1
TRISC<2> CCP1CON<3:0>
Mode Select
Output Enable
Pin
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
Note: Clear ing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
RQ
S
Duty cycle registers CCP1CON<5:4>
Clear Timer,
CCP1 pin and
latch D.C.
TRISC<2>
RC2/CCP1
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
1999 Microchip Technology Inc. Preliminary DS30605B-page 53
PIC16C63A/65B/73B/74B
9.3.1 PWM PER IOD
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
PWM period = [(PR2) + 1] 4 • TOSC
(TMR2 prescale value)
PWM frequency is defined as 1 / [PWM period].
When TMR 2 is equal to PR2, th e follo wing three e v ents
occur on t he next inc rement cyc le:
TMR2 is cl eare d
The CCP1 pin is set (exception: if PWM duty
cycl e = 0%, the CCP1 p in will not be set)
The PWM duty cycl e is latche d from CCPR1L i nto
CCPR1H
9.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available: the CCPR1L contains
the ei ght MSbs and the CCP 1CON<5:4 > contai ns the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycl e in time:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>)
Tosc • (TMR2 prescal e val ue)
CCPR1L and CC P1CON <5:4> c an be writ ten to at an y
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to d ouble b uffer the PWM du ty c yc le. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
Maximum PWM resolution (bits) for a given PWM
frequency:
9.3.3 SET-UP FOR PWM OPERATION
The followin g steps sh ould be ta ke n when co nfigur ing
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 register .
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4. Set the TMR2 prescale v alue and enable Timer2
by writing to T2CON.
5. Con figure the C CP1 module f or PW M operatio n.
Note: The Tim er2 p os tsc al er ( see Se cti on 8.1) is
not us ed in th e det ermi nati on of the PWM
frequenc y. The pos tscaler cou ld be used to
have a servo update rate at a different fre-
quency than the PWM output.
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
log(FPWM
log(2)
FOSC )bits
=
Resolution
PIC16C63A/65B/73B/74B
DS30605B-page 54 Preliminary 1999 Microchip Technology Inc.
TABLE 9-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
TABLE 9-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 —CCP2IF---- ---0 ---- ---0
8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 —CCP2IE---- ---0 ---- ---0
87h TRISC POR TC Data Direction Register 1111 1111 1111 1111
0Eh TMR 1L Holding register f or the Least Sign ificant Byte of th e 16- bit TMR1 regis ter xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significan t Byte o f the 16-bit T MR1 r egister xxxx xxxx uuuu uuuu
10h T1CON T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h CCPR1L Capture/Compare/PWM regis ter1 ( LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Comp are /PWM register 1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh CCPR 2L Capture/Compare/PWM regis ter2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM r egister2 ( MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by Capt ure and Timer1.
Note 1: The PSP is not implemented on the PIC16C63A/73B; always maintain these bits clear.
2: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits clear.
Add ress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 —CCP2IF
---- ---0 ---- ---0
8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 —CCP2IE
---- ---0 ---- ---0
87h TRISC PORTC Data Direct ion Regist er 1111 1111 1111 1111
11h TMR2 Timer2 module’ s register 0000 0000 0000 0000
92h PR2 Timer2 module’s period register 1111 1111 1111 1111
12h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L Capture/Compare/PWM registe r1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Co mpare/PWM register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh CCPR2L Capture/Compar e/PWM register2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Co mpare/PWM register2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
1999 Microchip Technology Inc. Preliminary DS30605B-page 55
PIC16C63A/65B/73B/74B
10.0 SYNCHR ONOUS SERIAL P ORT
(SSP) MODULE
10.1 SSP Module Overview
The Sy nchronous Seri al Por t (SSP) module i s a serial
interface useful for communicating with other peripheral
or microcontroller devices. These peripheral devices
may be Serial EEPROMs, shift registers, display driv-
ers, A/D conver te rs, et c. The SSP module can o perat e
in one of two modes:
Serial Peripheral Interface (SPI)
Inter-Integrated Circuit (I 2C)
An over vi ew o f I2C operations and additional informa-
tion on the SSP module can be foun d in the PICmicro™
Mid-Range MCU Family Reference Manual
(DS33023A).
10.2 SPI Mode.................. ..... ...... ............................ 58
10.3 SSP I2C Operati on.............. ............................ 61
Refer to Application Note AN578,
“Use of the SSP
Module in the I
2
C Multi-Master Environment.”
PIC16C63A/65B/73B/74B
DS30605B-page 56 Preliminary 1999 Microchip Technology Inc.
10.2 SPI Mode for PIC16C63A/65B/73B/74B
REGISTER 10-1: SSPSTAT: SYNC SERIAL PORT STATUS R EGISTER (ADDRESS 94h)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF R = Readable bit
W = Wri table bit
U = Unimplemented bit, read
as ‘0
- n =Value at POR reset
bit7 bit0
bit 7: SMP: SPI data input sample phase
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at mi ddle of data output time (Microwire®)
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
I2C Mode
This bit must be maintained clear
bit 6: CKE: SPI Clock Edge Select (Figure 10-2, Figure 10-3, and Figure 10-4)
SPI Mode
CKP = 0
1 = Data transmitted on rising edge of SCK (Microwire® alternate)
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK (Microwire® default)
0 = Data transmitted on r ising edge of SCK
I2C Mode
This bit must be maintained clear
bit 5: D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4: P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit is
detected la st. SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is ’0’ on RESET)
0 = Stop bit was not detected last
bit 3: S: Star t bit (I2C mode only. This bit is cleared when the SSP module is disabl ed, or when the Stop bit is
detected la st. SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is ’0’ on RESET)
0 = Start bit was not detected last
bit 2: R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next start bit, stop bit, or ACK bit.
1 = Read
0 = Writ e
bit 1: UA: Update Address (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0: BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1 = Transm it in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
1999 Microchip Technology Inc. Preliminary DS30605B-page 57
PIC16C63A/65B/73B/74B
REGISTER 10-2 : SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14 h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ‘0
- n =Value at POR reset
bit7 bit0
bit 7: WCOL: Write Collision Detect bit
1 = T he SSPBUF register is written wh ile it is still transmitting the previous word (must be cle ared in soft ware)
0 = No collision
bit 6: SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A ne w byte is received while the SSPBUF register is still holding the pre vious data. In case of o verflo w,
the data in SSPSR is lost. Ov erflo w can o nly occur in s lav e mode . The u ser must r ead the SSPB UF, ev en
if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not set since each
new reception (and transmission) is initiated by writing to the SSPBUF register.
0 = No overf l ow
In I2C mode
1 = A byte is received while the SSPBUF register is still holding the pre vious byte. SSPO V is a "don’t care"
in transmit mode. SSPOV must be cleared in software in either mode.
0 = No overf l ow
bit 5: SSPEN: Synchronous Serial Port Enable bit
In SPI mode
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
bit 4: CKP: Clock Polarity Select bi t
In SPI mode
1 = Idle state for clock is a high level (Microwire® default)
0 = Idle state for cl ock is a low level (Microwire® alternate)
In I2C mode
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
bit 3-0: SSPM3:SSPM0: Synchronous Seri al Port Mode Select bits
0000 = SPI master mode, clock = FOSC/4
0001 = SPI master mode, clock = FOSC/16
0010 = SPI master mode, clock = FOSC/64
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
0110 = I2C slave mode, 7-bit address
0111 = I2C slave mode, 10-bit address
1011 = I2C firmware controlled master mode (slave idle)
1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled
1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled
PIC16C63A/65B/73B/74B
DS30605B-page 58 Preliminary 1999 Microchip Technology Inc.
10.2.1 SPI MODE
This section contains register definitions and opera-
tional characteristics of the SPI module. Additional infor-
mation on the SPI module can be found in the
PICmicro™ Mid-Range MCU Family Reference Manual
(DS33023A).
SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. To accom-
plish communication, typically three pins are used:
Serial Data Out (SDO) RC5/SDO
Serial Data In (SDI) RC4/SDI/SDA
Serial Clock (SCK) RC3/SCK/SCL
Additionally, a four th pin may be used when in a slave
mode of operation:
•Slave Select (SS
) RA5/SS/AN4
When initializing the SPI, several options need to be
specif ied. This is don e by prog ramming the ap propriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the fol-
lowi ng to be specified:
Master Mode (SCK is the clock output)
Slave Mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Clock edge (output data on rising/falling edge of
SCK)
Clock Rate (Master mode only)
Slave Sel ect Mode (Slave mode only)
FIGURE 10-1: SSP BLOCK DIAGRAM
(SPI MODE)
To enable the serial port, SSP enable bit, SSPEN
(SSPCON<5>) m ust be set. To reset or recon figure SPI
mode, clear bit SSPEN, re-initi alize the SSPCON reg-
ister, and then set bi t SSPEN. Th is c on fig ures the SDI,
SDO , SCK, and SS pins as s erial port pins. For th e pins
to behave as the serial port function, they must have
their data direction bits (in the TRISC register) appro-
priat ely programmed. That is:
SDI must have TRISC<4> set
SDO must have TRISC<5> cleared
SCK (Master mode) must hav e TRISC<3> cleared
SCK (Slave mode) must have TRISC<3> set
•SS
must have TRISA<5> set
.Note 1: When the SPI is in slav e mode with SS pi n
control e nabled, (SSPCON<3:0> = 0100)
the SPI module will reset if the SS pin is
set to VDD.
2: If the SPI is used in slave mode with
CKE = '1', the n the S S pin control must be
enabled.
Read Write
Internal
data bus
RC4/SDI/SDA
RC5/SDO
RA5/SS/AN4
RC3/SCK/
SSPSR reg
SSPBUF reg
SSPM3:SSPM0
bit0 Shift
clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 output
TCY
Prescaler
4, 16, 64
TRISC<3>
2
Edge
Select
2
4
SCL
1999 Microchip Technology Inc. Preliminary DS30605B-page 59
PIC16C63A/65B/73B/74B
FIGURE 10-2: SPI MODE TIMING, MASTER MODE
FIGURE 10-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
FIGURE 10-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SCK (CKP = 0,
SDI (SMP = 0)
SSPIF
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SDI (SMP = 1)
SCK (CKP = 0,
SCK (CKP = 1,
SCK (CKP = 1,
SDO
bit7
bit7 bit0
bit0
CKE = 0)
CKE = 1)
CKE = 0)
CKE = 1)
SCK (CKP = 0)
SDI (SMP = 0)
SSPIF
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SCK (CKP = 1)
SDO
bit7 bit0
SS (optional)
SCK (CKP = 0)
SDI (SMP = 0)
SSPIF
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SCK (CKP = 1)
SDO
bit7 bit0
SS
PIC16C63A/65B/73B/74B
DS30605B-page 60 Preliminary 1999 Microchip Technology Inc.
TABLE 10-1: REGISTERS ASSOCIATED WITH SPI OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh.
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
87h T RI SC PORTC Data Direction Register 1111 1111 1111 1111
13h SSPBUF Synchronous Serial P ort Receiv e Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
85h TRISA P ORTA Data Direction Register --11 1111 --11 1111
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unc hanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: Bits PSPIE and PSPIF are reserved on t he PI C16C63A/73B; always maint ain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear .
1999 Microchip Technology Inc. Preliminary DS30605B-page 61
PIC16C63A/65B/73B/74B
10.3 SSP I2C Operation
The SSP mod ule in I2C mode fully i mplements all slav e
functions, except general call support, and provides
interrupts o n start and sto p bits i n hard ware to facilitate
firmware implementations of the master functions. The
SSP module im pl em ents the s tand ard mod e speci fic a-
tions as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the
RC3/SCK/SCL pin, which is the clock (SCL), and the
RC4/SDI/SDA pin, which is the data (SDA). The user
must configure these pins as inputs or outputs
through the TRISC<4:3> bits.
The SSP module functions are enabled by setting
SSP enable bit SSPEN (SSPCO N<5>).
FIGURE 10-5: SS P BLOCK DIAGRAM
(I2C MODE)
The SSP module has five registers for I2C operation.
These are the:
SSP Control Register (SSPCON)
SSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
SSP Shift Register (SSPSR) - Not di rectly accessib le
SSP Address Regi ster (SSPADD)
The SSPCON register allows c ontrol of the I2C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
•I
2C Slave mode (7-bit address)
•I
2C Slave mode (10-bit address)
•I
2C Slave mode (7-bit address), with start and
stop bit interrupts enabled to support firmware
Master mode
•I
2C Slave mode (10-bit address), with start and
stop bit interrupts enabled to support firmware
Master mode
•I
2C start and stop bit interrupts enabled to support
firmware Master mode, Slave is idle
Selection of any I2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits.
Additional information on SSP I2C operation can be
found in the PICmicro™ Mid-Range MCU Family R ef-
erence Manual (DS33023A).
10.3.1 SLAVE MODE
In slave mode, the SCL and SDA pins must be config-
ured as i nputs (TRISC<4:3> s et). Th e S SP m odu le w ill
override the input state with the output data when
required (sl a ve-trans mitter).
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse, and
then load the SSPBUF regi ste r with the rec ei ved valu e
currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to gi v e this A CK pulse. They include (either
or both):
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
b) The o v erflo w bit SSPOV (SSPCON<6>) was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 10-2 shows what happens when a data transfer
byte is receiv ed, given the status of bits BF and SSPOV.
The shaded cells show the condition where user soft-
ware did not properly clear the ov erflow condition. Flag
bit BF is cleared b y rea ding the SSPBUF register whil e
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper ope ra tio n. Th e hig h and lo w ti me s of th e
I2C specification, as well as the requirement of the SSP
module , is shown in timin g parameter #10 0 and param-
eter #101.
Read Write
SSPSR reg
Match detect
SSPADD reg
Start and
Stop bit detect
SSPBUF reg
Internal
Data Bus
Addr Match
Set, Rese t
S, P bit s
(SSPSTAT reg)
RC3/SCK/SCL
RC4/
shift
clock
MSb
SDI/ LSb
SDA
PIC16C63A/65B/73B/74B
DS30605B-page 62 Preliminary 1999 Microchip Technology Inc.
10.3.1.1 ADDRESSING
Once the SSP module has been enabled, it waits fo r a
START condition to occur. Following the START condi-
tion, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The va lue of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If t he addresses matc h, and the BF
and SSPOV bits are clear, the following events occur:
a) The SSPSR register value is loaded into the
SSPBUF register.
b) The buffer full bit, BF is set.
c) An ACK pulse is generated.
d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(inter rupt is gen erate d if en ab led) - on the f al ling
edge of the ninth SCL pulse.
In 10-bit address mode, two address bytes need to be
received by the slave (Figure 10-7). The five Most Sig-
nificant bits (MSbs) of the first address byte specify if
this is a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write so the slave device will receive the sec-
ond address byte. For a 10-bit address the first byte
wou ld equa l ‘1111 0 A9 A8 0’, where A9 and A8 a re
the two MSbs of the address. The sequence of events
for 10-bit address is as follows, with steps 7 - 9 for
slave-transmitter:
1. Receive first (high) byte of address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of address (bits
SSPIF, BF, and UA are set).
5. Update the SSPADD register with the fir st (hig h)
byte of address, if match releases SCL line, this
will clea r bit UA.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive repeated START condition.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
TABLE 10-2: DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
SSPSR SSPBUF Generate ACK
Pulse
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
BF SSPOV
00 Yes Yes Yes
10 No No Yes
11 No No Yes
0 1 No No Yes
Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
1999 Microchip Technology Inc. Preliminary DS30605B-page 63
PIC16C63A/65B/73B/74B
10.3.1.2 RECEPTION
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is clea red. The re ce ive d ad dress is lo aded in to
the SSPBUF register.
When the address byte overflow condition exists, then
no ac knowled ge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
An SSP interrupt is generated for each data transfer
by te. Fla g bit SSPIF (PI R1<3>) m ust be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
FIGURE 10-6: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
P
9
8
76
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1SDA
SCL 123456789123456789123
4
Bus Master
terminates
transfer
Bit SSPOV is set because the SSPBUF register is still full.
Cleared in software
SSPBUF register is read
ACK Receiving Data
Receiving Data D0
D1
D2
D3D4
D5
D6D7
ACK
R/W=0
Receiving Ad dr ess
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
ACK
ACK is not sent.
PIC16C63A/65B/73B/74B
DS30605B-page 64 Preliminary 1999 Microchip Technology Inc.
10.3.1.3 TRANSMISSION
When the R/W bit of the inc oming ad dress byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the SSP-
BUF register, which also loads the SSPSR register.
Then pin RC3/SCK/SCL should be enabled by setting
bit CKP (SSPCON<4>). The master must monitor the
SCL pin prior to asserting another clock pulse. The
slave de vices may be holding off the master by stretch-
ing the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the SDA
signal is valid during the SCL high time (Figure 10-7).
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to deter mine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SD A line was high (not A CK), then the
data transfer is complete. When the ACK is latched by
the sla v e , th e sla v e lo gic i s rese t (reset s SSPSTAT reg-
ister) and the slave then monitors for another occur-
rence of the START bit. If the SDA line was low (ACK),
the tr ansmit d ata must be load ed into t he SSPBUF re g-
ister, which also loads the SSPSR register. Then pin
RC3/SCK/SCL should be enabled by setting bit CKP.
FIGURE 10-7: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR 1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Transmitting DataR/W = 1Receiving Address
123456789 123456789 P
cleared in software
SSPBUF is written in software From SSP interrupt
service routine
Set bit after writing to SSPBUF
SData in
sampled SCL held low
while CPU
responds to SSPIF
(the SSPBUF must be written-to
before the CKP bit can be set)
1999 Microchip Technology Inc. Preliminary DS30605B-page 65
PIC16C63A/65B/73B/74B
10.3.2 MASTER MODE
Master mode of operation is supported in firmware
using interrupt generation on the detection of the
START and STOP conditions. The STOP (P) and
START (S) bits are cleared from a reset or when the
SSP module is disab led. The ST OP (P) and STAR T (S)
bits will toggle based on the START and STOP condi-
tions. Control of the I2C bus may be taken when the P
bit is set, or the bus is idle and both the S and P bits are
clear.
In master mode the SCL and SDA lines are manipu-
lated b y c learing the correspond ing TR ISC<4:3> b it(s).
The output level is always low, irrespective of the
v alu e(s ) in PORTC<4:3 >. So when transmitting d ata , a
1’ data bit must have the TRISC<4> bit set (input) and
a ’0’ data bit must have the TRISC<4> bit cleared (out-
put). The same scenario is true f or the SCL line with the
TRISC< 3> bit.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
START condition
STOP condition
Data transfer byte transmitted/received
Master mode of operation can be done with either the
slave mode idle (SSPM3:SSPM0 = 1011) or with the
slave active. When both master and slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
10.3.3 MU LTI-MASTER MODE
In multi-master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a reset or
when the SSP module is disabled. The STOP (P) and
START (S) bits will toggle based on the START and
STOP conditions. Control of the I2C bus may be ta ken
when bit P (SSPSTAT<4>) is set, or the bus is idle and
both the S and P bits clear. When the bus is busy,
enabling the SSP Interrupt will generate the interrupt
when the STOP condition occurs.
In multi-master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
le vel is outp ut. If a high le vel is e xpect ed and a low le ve l
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, these are:
Address Transfer
Data Transfer
When the slave logic is enabled, the slave continues to
receiv e . I f a rbitr atio n w as lo st du ring th e add ress tr ans -
fer stage, communication to the device may be in
prog ress. I f address ed an A C K pulse will be gene rate d.
If arbitr ation was lost during the data transf e r stage , the
device will need to re-transfer the data at a later time.
TABLE 10-3: REGISTERS ASSOCIATED WITH I2C OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
13h SSPBUF Synchronous Serial Port Receive B uffer/Transmit Register xxxx xxxx uuuu uuuu
93h SSPADD Synch ronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
94h SSPSTAT SMP(3) CKE(3) D/A PSR/WUA BF 0000 0000 0000 0000
87h TRISC PORTC Data Direction register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ’0’.
Shaded cells are not used by SSP module in I2C mode.
Note 1: PSPIF and PSPIE are reser ved on the PIC16C63A/73B; always maintain these bits clear.
2: ADIF and ADIE are reserved on the PIC16C63A/65B; always maintain these bits clear .
3: Maintain these bits clear in I2C mode.
PIC16C63A/65B/73B/74B
DS30605B-page 66 Preliminary 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. Preliminary DS30605B-page 67
PIC16C63A/65B/73B/74B
11.0 UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The Universal Synchronous Asynchronous Receiver
Transm itter (USART) module is one of the two serial I/
O modul es. (USAR T is also kno wn as a Serial Comm u-
nications Interface or SCI). The USART can be config-
ured as a full duplex asynchronous system that can
communicate with peripheral devices, such as CRT ter-
minals and person al compu ters, or it can b e configure d
as a half dup lex synchronous sy stem that can commu-
nicate w ith peripher al de vices , such as A/D or D /A inte-
grated circuits, Serial EEPROMs etc.
The USART can be configured in the following modes:
Asynchronous (full duplex)
Synchronous - Master (half duplex)
Synchronous - Slave (half duplex)
Bits SPEN (RCSTA<7>) and TRISC<7:6> have to be set
in order to configure pins RC6/TX/CK and RC7/RX/DT as
the universal synchronous asynchronous receiver
transmitter.
REGISTER 11-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC BRGH TRMT TX9D R = Readable bit
W = Writable bit
U = U nimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from exte rnal source)
bit 6: TX9: 9-bit Transmit Enable bit
1 = Sel ects 9 -bit transmission
0 = Sel ects 8 -bit transmission
bit 5: TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4: SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3: Unimplemented: Read as '0'
bit 2: BRGH: High Baud Rate Select bit
Asynchronous mode
1 = High speed
0 = Low speed
Synchronous mode
Unused in this mode
bit 1: TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0: TX9D: 9th bit of transm it data. Can be parity bit.
PIC16C63A/65B/73B/74B
DS30605B-page 68 Preliminary 1999 Microchip Technology Inc.
REGISTER 11-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R-0 R-x
SPEN RX9 SREN CREN FERR OERR RX9D R = Readable bit
W = Writable bit
U = Un implemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: SPEN: Serial Port Enable bit
1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6: RX9: 9-bit Receive Enable bit
1 = Sel ects 9-bit reception
0 = Sel ects 8-bit reception
bit 5: SREN: Single Receive Enable bit
Asynchronous mode
Don’t care
Synchronous mode - master
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complet e.
Synchronous mode - slave
Unused in this mode
bit 4: CREN: Continuous Receive Enable bit
Asynchronous mode
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode
1 = Enables continuous receive until enable bit CREN is cleared (CREN overr ides SREN)
0 = Disables continuous receive
bit 3: Unimplemented: Read as '0'
bit 2: FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1: OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
bit 0: RX9D: 9th bit of received data (Can be parity bit)
1999 Microchip Technology Inc. Preliminary DS30605B-page 69
PIC16C63A/65B/73B/74B
11.1 USART Baud Rate Generator (BRG)
The BRG supports both the asynchronous and syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In synchronous mode, bit BRGH is ignored.
Table 11-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in master mode (internal clock).
Giv en the desired baud r ate and Fo sc, the neare st inte-
ger value for the SPBRG register can be calculated
using the formula in Table 11-1. From this, the error in
baud rate can be determined.
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
becaus e the FOSC/(16(X + 1 )) eq uat ion ca n re duc e th e
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a ti mer overflow be for e outp ut-
ting the new baud rate.
11.1.1 SAMPLING
The data on th e RC7/RX/DT pi n is sampled three ti mes
near the cen ter of each bit tim e by a majo rity detect cir-
cuit to determine if a high or a low level is present at the
RX pin.
TABLE 11-1: BAUD RATE FORMULA
TABLE 11-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed)
0
1(Asynchron ous ) Baud Rate = FOSC/(64(SPBRG+1))
(Synchronous) Baud Rate = FOSC/(4(SPBRG+1)) Baud Rate= FOSC/(16(SPBRG+1))
NA
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
18h RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00x
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used by the BRG.
PIC16C63A/65B/73B/74B
DS30605B-page 70 Preliminary 1999 Microchip Technology Inc.
11.2 USART Asynchronous Mode
In this mode, the USART uses standard nonreturn-to-
zero (NRZ) format (one start bit, eight or nin e data b its ,
and one stop bit). The most common data format is 8
bits. An on-chip, dedicated, 8-bit baud rate generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LSb first. Th e USAR T’ s transmit ter and receive r are
functio nally in dependent, but use the s ame data fo rmat
and baud rate. The baud rate generator produces a
clock either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA<2>). Parity is not supported by
the hard ware , b ut can be implemen ted in s oftware (and
stored as the ninth data bit). Asynchronous mode is
stopped during SLEEP.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing important elements:
Baud Ra te Ge ner ator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
11.2.1 USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 11-1. The he art of the tra nsmitter i s the trans mit
(serial) shift register (TSR). The shift register obt ains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXRE G reg iste r tr ansfers t he data to th e TS R re giste r
(occurs in one TCY), the TXREG register is empty and
flag bit TXIF (PIR1<4>) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
( PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
wa re. It will reset onl y when ne w data is load ed into the
TXREG register. While flag bit TXIF indicated the sta-
tus of the TXREG register, another bit TRMT
(TXSTA<1>) sho ws the s tatus of the TS R registe r . Sta-
tus bit TRMT is a read only bit, whic h is set when the
TSR register is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift cl ock (Fi gure 11-2). The transm ission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
tran sfer to the TXR EG regi st er w il l res ul t in an i mmed i-
ate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 11-3).
Clearing enable bit TXEN during a transmission will
cause the trans missio n to be aborted and will res et the
transmitter. As a result, the RC6/TX/CK pin will revert
to hi-impedance.
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) shou ld be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can resul t in an immediate tran sf er of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit may be loaded in the TSR
register.
FIGURE 11-1: USART TRANSMIT BLOCK DIAGRAM
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TXI F is set when ena bl e bit TXEN
is set. TXIF is cleared by loading TXREG.
TXIF
TXIE
Interrupt
TXEN Baud Rate CLK
SPBRG
Baud Rate Generator TX9D
MSb LSb
Data Bus
TXREG register
TSR register
(8) 0
TX9
TRMT SPEN
RC6/TX/CK pin
Pin Buffer
and Control
8
• •
1999 Microchip Technology Inc. Preliminary DS30605B-page 71
PIC16C63A/65B/73B/74B
Steps to follow when setting up an Asynchronous
Transmission:
1. Initialize the SPBRG regis te r for the appro priate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 11.1)
2. Enable the a sy nc hro nou s s erial po rt by cle aring
bit SYNC and setting bit SPEN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired , th en s et transmit
bit TX9.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts trans-
mission).
FIGURE 11-2: ASYNCHRONOUS MASTER TRANSMISSION
FIGURE 11-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
TABLE 11-3: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
Resets
0Ch PIR1 PSPIF(1) ADIF(2)RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG US ART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE(2)RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission.
Note 1: Bits PSPIE and PSPIF are reserved on t he PI C16C63A/73B; always maint ain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear .
WORD 1 Stop Bit
WORD 1
Transmit Shift Reg
Start Bit Bit 0 Bit 1 Bit 7/8
Write to TXREG Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
TXIF bit
(Transmit buffer
reg. empty f lag)
TRMT b it
(Transmi t shi ft
reg. empty fl ag)
Transmit Shift Reg.
Write to TXREG
BRG output
(shift clock)
RC6/TX/CK (pin)
TXIF bit
(interrupt reg. flag)
TRMT bi t
(Transmi t shift
reg. empty flag)
Word 1 Word 2
WORD 1 WORD 2
Start Bit Stop Bit Start Bit
Transmit Shift Reg.
WORD 1 WORD 2
Bit 0 Bit 1 Bit 7/8 Bit 0
Note: This timing diagram shows two consecutive transmissions.
PIC16C63A/65B/73B/74B
DS30605B-page 72 Preliminary 1999 Microchip Technology Inc.
11.2.2 USART ASYNCHRONOUS RECEIVER
The receiver block diagram is shown in Figure 11-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actuall y a h igh s pee d s hi fter ope rating at x16 tim es th e
baud r ate, wherea s the main recei ve serial shif ter oper-
ates at the bit rate or at FOSC.
Once asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receiv e (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transf erred to the RCREG register (if
it is empty). If the transfer is complete, flag bit RCIF
(PIR1<5>) is set. The actual in terrupt can be enabled/
disab led by setting/clearing enab le bit RCIE (PIE1<5>).
Flag bit RCIF is a read only bit w hich is cleared by the
hardware. It is cleared when the RCREG register has
been read and is empty. The RCREG is a double buff-
ered r egiste r, i.e . it is a two deep FI FO. It is p ossib le for
two bytes of data to be received and transferred to the
RCREG FIFO and a third byte to begin shifting to the
RSR register. On the detection of the STOP bit of the
third b yte, if t he RCREG registe r is still full, then ov errun
error bit OERR (RCSTA<1>) will be set. The word in the
RSR will be lost. The RCREG register can be read
twice to retrieve the two bytes in the FIFO. Overrun bit
OERR has to be cleared in software. This is done by
resetting the receive logic (CREN is cleared and then
set). If bit OERR is set, tr ansfers from the RSR register
to the RCREG register are inhibited, so it is essential to
clear error b it OERR if it is set . Framin g error bit FERR
(RCS TA<2> ) is se t if a sto p bi t is de t ec ted as cl ea r. Bit
FERR and the 9th receive bit are buffered the same
wa y a s the rece iv e data. Read ing the R CREG, will load
bits RX9D and FERR with new values, therefore it is
essenti al f or the user to read the RCSTA register befo re
reading RCREG register in order not to lose the old
FER R and RX9D information.
FIGURE 11-4: USART RECEIVE BLOCK DIAGRAM
FIGURE 11-5: ASY NCHRONOUS RECEPTION
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR register
MSb LSb
RX9D RCREG register FIFO
Interrupt RCIF
RCIE Data Bus
8
³ 64
³ 16
or Stop Start
(8) 710
RX9
• • •
Start
bit bit7/8
bit1bit0 bit7/8 bit0Stop
bit
Start
bit Start
bit
bit7/8 Stop
bit
RX (pin)
reg
Rcv buffer reg
Rcv shift
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
WORD 1
RCREG WORD 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
1999 Microchip Technology Inc. Preliminary DS30605B-page 73
PIC16C63A/65B/73B/74B
Steps to follow when setting up an Asynchronous
Reception:
1. Initialize the SPBRG regis te r for the appro priate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 11.1).
2. Enable the a sy nc hro nou s s erial po rt by cle aring
bit SYNC, and setting bit SPEN.
3. If interrupts are desired, then set enable bit
RCIE.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
6. Flag bit RCIF wi ll be set when recept ion is com-
plete and an interrupt will be gene rated if e nab le
bit RCIE was set.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during rece ption.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
TABLE 11-4: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Addr e s s Nam e Bit 7 Bit 6 Bit 5 Bi t 4 Bi t 3 B it 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
Resets
0Ch PIR1 PSPIF(1) ADIF(2)RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE(2)RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on t he PIC16C73/ 73A/ 76; always maintain t hese bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear .
PIC16C63A/65B/73B/74B
DS30605B-page 74 Preliminary 1999 Microchip Technology Inc.
11.3 USART Synchronous Master Mode
In Sync hronous Maste r mode, t he data i s transmitte d in
a half-duplex manner, i.e., transmission and reception
do not oc cur at the same time . Whe n tran smitt ing dat a,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines respectively. The
Master mode in dicates that th e proces sor tran smits th e
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
11.3.1 USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 11-1. The he art of the tra nsmitter i s the trans mit
(serial) shift register (TSR). The shift register obt ains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXRE G reg iste r tr ansfers t he data to th e TS R re giste r
(occurs in one Tcycle), the TXREG is empty and inter-
rupt bit TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
wa re. It will reset only when ne w data is l oaded into th e
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not
available to the user.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The firs t data bit wi ll be shi fted out on the ne xt a v ailab le
rising edge of the clock on the CK line. Data out is sta-
ble around the falling edge of the synchronous clock
(Figure 11-6). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 11-7). This is advantageous when slow
baud ra tes are se lec ted, since the BRG is kept in reset
when bits TXEN, CREN and SREN are clear. Setting
enable bit TXEN will start the BRG, creating a shift
clock immediately. Normally, when transmission is first
started, the TSR register is empty, so a transfer to the
TXREG register will result in an immediate transfer to
TSR resulting in an empty TXREG. Back-to-back trans-
fers are possible.
Clearing enable bit TXEN, during a transmission, will
cause the trans missio n to be aborted and will res et the
tran smitter. The DT and CK pins will re v ert to hi-impe d-
ance. If either bit CREN or bit SREN is set during a
transmission, the transmission is aborted and the DT
pin reverts to a hi-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic, however, is not
reset, although i t is disconnected from the pins . In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SR EN is set (to interrupt an on-going transm ission
and rece ive a single w ord), then a fter the sin gle word i s
received, bit SREN will be cleared and the serial port
will revert back to transmitting, since bit TXEN is still
set. The DT line will immediately switch from hi-imped-
ance receive mode to transmit and start driving. To
avoid this, bit TXEN should be cleared.
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register . This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written bef ore writing the “new” TX9D ,
the “present” value of bit TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 11.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
1999 Microchip Technology Inc. Preliminary DS30605B-page 75
PIC16C63A/65B/73B/74B
TABLE 11-5: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
FIGURE 11-6: SYNCHRONOUS TRANSMISSION
FIGURE 11-7: SYNCHRONOUS TRANS MISSI ON (THROUGH TXE N)
Addr e s s Na m e Bit 7 B it 6 B it 5 Bit 4 Bit 3 Bit 2 Bit 1 B it 0 Va lue on:
POR,
BOR
Value on all
other Resets
0Ch PIR1 PSPIF(1) ADIF(2)RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE(2)RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 -010 0000 -010
99h SPB RG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission.
Note 1: Bits PSPIE and PSPIF are reserved on t he PI C16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
bit 0 bit 1 bit 7
WORD 1
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
bit 2 bit 0 bit 1 bit 7
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
(Inte rru pt flag)
TRMT
TXEN bit ’1 ’1
Note: Sync master mode; SPBRG = ’0’. Continuous transmission of two 8-bit words
WORD 2
TRMT bit
Write word1 Write word2
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
bit0 bit1 bit2 bit6 bit7
TXEN b it
PIC16C63A/65B/73B/74B
DS30605B-page 76 Preliminary 1999 Microchip Technology Inc.
11.3.2 USART SYNCHRONOUS MASTER
RECEPTION
Once synchronous mode is selected, reception is
enabled by setting either enable bit SREN (RCSTA<5>)
or enable bit CREN (RCSTA<4>). Data is sample d on the
RC7/RX/ DT p in on the falling edge of th e clo c k. If enab l e
bit SREN is set, then only a single word is received. If
enable bit C RE N i s s et, th e re ce pti on is co nt inu ou s u nt il
CREN is cleared. If both bits are set, CREN takes prece-
dence. After clocking the last bit, the received data in the
Receive Shift Register (RSR) is transferred to the
RCREG register (if it is empty). When the transf er is com-
plete, interrupt flag bit RCIF (PIR1<5>) is set. The actual
interrupt can be enabled/disabled by setting/clearing
enable bit RCIE (PIE1<5>). Flag bit RCIF is a read only
bit, whi ch is re set b y the ha rdware . In thi s case , it is reset
when the RCREG register has been read and is empty.
The RCREG is a double buffered register, i.e., it is a two
deep FIFO. It is possible for two bytes of data to be
receiv ed and transf erred to the RCREG FIFO and a third
by te to begi n shiftin g into the RSR re gister. On the cloc k-
ing of th e last bit of the third byte, if the RCREG register
is still full, then overrun error bit OERR (RCSTA<1>) is
set. The word in the RSR wi ll be lost. Th e RCREG regis-
ter can be read twice to retrieve the two bytes in the FIFO .
Bit OERR ha s to be cleared in software (by clea ring bit
CREN). If bi t OE RR i s set, t ransf ers fro m th e RSR to th e
RCREG are inhibite d, so it is essential to clear bit OERR
if it is set. The ninth receive bit is buffered the same way
as the receive data. Reading the RCREG register will
load bi t RX9D with a n ew va lue, ther efo re it is essenti al
for the user to read the RCSTA register before reading
RCREG in orde r not to lose the old RX 9D information.
Steps to follow when setting up a Synchronous Master
Reception:
1. Initialize the SPBRG register for the appropriate
baud rate. (Section 11.1)
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
7. Interrupt flag bit RCIF will be se t when receptio n
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during rece ption.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
TABLE 11-6: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
FIGURE 11-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other Resets
0Ch PIR1 PSPIF(1) ADIF(2)RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG US ART Receive Regis ter 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE(2)RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG B aud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unim plement ed read as '0'. Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on t he PI C16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear .
CREN bit
RC7/RX/DT pin
RC6/TX/CK pin
Wr it e to
bit SREN
SREN bit
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRG = '0'.
Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q2 Q1Q2Q3Q4Q1Q2Q3 Q4 Q1 Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3 Q4 Q1Q2Q3Q4
'0'
bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
'0'
Q1Q2Q3Q4
1999 Microchip Technology Inc. Preliminary DS30605B-page 77
PIC16C63A/65B/73B/74B
11.4 USART Synchronous Slave Mode
Synchron ous s la v e mo de dif f ers fro m the M aster mod e
in the fact that the shift clock is supplied externally at
the RC6/T X/CK pin (instead of being supplied internally
in master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
11.4.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the synchronous master and slave
modes are identical, except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register .
c) Flag bit TXIF will not be set.
d) When th e first wo rd has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the inter-
rupt vector (0004h).
Steps to follow when setting up a synchronous slave
transmission:
1. Enable the synchron ous sla v e serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
2. Clea r bits CREN a nd SREN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
11.4.2 USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the synchronous master and slave
modes is identical, except in the case of the SLEEP
mode. Also, bit SREN is a don’t care in slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enab le bit RCIE bit is set, the interrupt gener ated
will wake the chip from SLEEP. If the global interrupt is
enabled, the p rogram will branch to the interrupt vector
(0004h).
Steps to follow when setting up a Synchronous Slave
Reception:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
5. Flag bit RCIF wi ll be set when recept ion is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during rece ption.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
PIC16C63A/65B/73B/74B
DS30605B-page 78 Preliminary 1999 Microchip Technology Inc.
TABLE 11-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
TABLE 11-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value o n:
POR,
BOR
Value on all
other Resets
0Ch PIR1 PSPIF(1) ADIF(2)RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE(2)RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unim plement ed read as '0'. Shaded cells are not used for synchronous slave transmission.
Note 1: Bits PSPIE and PSPIF are reserved on t he PI C16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear .
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other Resets
0Ch PIR1 PSPIF(1) ADIF(2)RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE(2)RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unim plement ed read as '0'. Shaded cells are not used for synchronous slave reception.
Note 1: Bits PSPIE and PSPIF are reserved on t he PI C16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear .
1999 Microchip Technology Inc. Preliminary DS30605B-page 79
PIC16C63A/65B/73B/74B
12.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The 8-bit analog-to-digital (A/D) conver ter module has
five inputs for the PIC16C73B and eight for the
PIC16C74B.
The A/D allows conversion of an analog input signal to
a corresponding 8-bit digital number. The output of the
sample and hold is the input into the converter, which
genera tes the result via succes sive a pproxima tion. The
analog reference voltage is software selectable to
either the devices positive supply voltage (VDD) or the
voltage level on the RA3/AN3/VREF pin.
The A/D conv erter has a un ique f eature of bein g able to
oper ate while the de v ice is in SLEEP mode. To opera te
in sleep, the A/D conversion clock must be derived from
the A/D’s internal RC oscillator.
The A/D module has three registers. These registers
are: A/D Result Register (ADRES)
A/D Control Register 0 (ADCON0)
A/D Control Register 1 (ADCON1)
The ADCON0 register, shown in Register 12-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 12-2, configures the func-
tions of the por t pins. The port pins can be configured
as analo g inputs (RA3 ca n also be a v olta ge ref erence)
or as digital I/O.
Addition al information on us ing the A/D mo dul e c an b e
found in the PICmicro™ Mid-Range MCU Family R ef-
erence Manual (DS33023A) and in Application Note,
AN546.
REGISTER 12-1: ADCON0 REGISTER (ADDRESS 1Fh)
Note: The PIC16C63A and PIC16C65B do not
include A/D modules. ADCON0, ADCON1
and ADRES registers are not imple-
mente d. ADI F and ADI E bits are re ser ved
and should be maintained clear.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE ADON R =Readable bit
W =Writable bit
U =Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from an internal RC oscillator)
bit 5-3: CHS2:CHS0: Analog Channel Select bits
000 = channel 0, (RA0/AN0)
001 = channel 1, (RA1/AN1)
010 = channel 2, (RA2/AN2)
011 = channel 3, (RA3/AN3)
100 = channel 4, (RA5/AN4)
101 = channel 5, (RE0/AN5)(1)
110 = channel 6, (RE1/AN6)(1)
111 = channel 7, (RE2/AN7)(1)
bit 2: GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conver-
sion is comple te)
bit 1: Unimplemented: Read as '0'
bit 0: ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
Note 1: A/D channe ls 5, 6 and 7 are implemented on the PIC16C74B only.
PIC16C63A/65B/73B/74B
DS30605B-page 80 Preliminary 1999 Microchip Technology Inc.
REGISTER 12-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
PCFG2 PCFG1 PCFG0 R =Readable bit
W =Writable bit
U =Unimplemented bit,
read as ‘0
- n = Value at POR reset
bit7 bit0
bit 7-3: Unimplemented: Read as '0'
bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits
Note 1: RE0, RE1 and RE2 are implemented on the PIC16C74B only.
A = Analog input
D = Digital I/O
PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 RE0(1) RE1(1) RE2(1) VREF
000 AAAAAAAAVDD
001 AAAAVREF AAARA3
010 AAAAADDDV
DD
011 AAAAVREF DDDRA3
100 AADDADDDVDD
101 AADDVREF DDDRA3
11x DDDDDDDDVDD
1999 Microchip Technology Inc. Preliminary DS30605B-page 81
PIC16C63A/65B/73B/74B
The following steps should be followed for doing an A/D
conversion:
1. Co nfigure the A/D module:
Configure analog pins / voltage reference /
and digital I/O (ADCON1)
Select A/D input channel (ADCON0)
Select A/D conversion clock (ADCON0)
Turn on A/D module (ADCON0)
2. Co nfigure A/D inter rupt (if desired):
Clear ADIF bit
Set ADIE bit
Set GIE bit
3. W ait the requ ired acquis iti on tim e .
4. Start conversion:
Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
Polling fo r the GO/DONE bit to be cleared
OR
Waiting for the A/D interrupt
6. Read A/D result register (ADRES), clear bit
ADIF if required.
7. For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
FIGURE 12-1: A/D BLOCK DIAGRAM
(Input volt age)
VIN
VREF
(Reference
voltage)
VDD
PCFG2:PCFG0
CHS2:CHS0
000 or
010 or
100 or
001 or
011 or
101
RE2/AN7(1)
RE1/AN6(1)
RE0/AN5(1)
RA5/AN4
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
111
110
101
100
011
010
001
000
A/D
Converter
Note 1: Not available on PIC16C73B.
11x
PIC16C63A/65B/73B/74B
DS30605B-page 82 Preliminary 1999 Microchip Technology Inc.
12.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 12-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impeda nc e varies ov er the device v o ltage
(VDD), Figure 12-2. The source impedance affects the
offset voltage at the analog input (due to pin leakage
current).
The maximum recommended impedance for ana-
log sour ces is 10 k. After the analog input c hannel i s
selected (changed), the acquisition must pass before
the conversion can be started.
To calculate the minimum acquisition time,
Equation 12-1 may be used. This equation assumes
that 1/2 LSb error is used (512 steps for the A/D). The
1/2 LS b er ror i s th e max imum error allowed fo r the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the PICmicro™ Mid-Range MCU Family Reference
Manu al (DS33023 A). In gener al , how e v er, give n a max
of 10kand a worst case temperature of 100°C, TACQ
will be no more than 16µsec.
FIGURE 12-2: ANALOG INPUT MODEL
EQUATION 12-1: ACQUISITION TIME
CPIN
VA
Rs ANx
5 pF
VDD
VT = 0.6V
VT = 0.6V I leakage
RIC 1k
Sampling
Switch
SS RSS
CHOLD
= DAC capacitance
VSS
6V
Sampling Switch
5V
4V
3V
2V
567891011
(k)
VDD
= 51.2 pF
± 500 nA
Legend CPIN
VT
I leakage
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various jun ction s
TACQ =
=
Amplifie r Settling Time +
Hold Capa cit or Ch argi ng Tim e +
Temperature Co eff ici ent
TAMP + TC + TCOFF
TAMP = 5µS
TC = - (51.2pF)(1k + RSS + RS) In(1/511)
TCOFF = (Temp -25°C)(0.05µS/°C)
1999 Microchip Technology Inc. Preliminary DS30605B-page 83
PIC16C63A/65B/73B/74B
12.2 Selecting the A/D Conversion Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.5TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selectable. The four possible options for TAD are:
•2T
OSC
•8TOSC
•32TOSC
Internal RC oscillator
Fo r cor rect A /D co nver sions, the A/ D conversion cl ock
(TAD) must be s elect ed to ens ure a minimu m TAD time
of 1.6 µs.
12.3 Configuring Analog Port Pins
The ADCON1, TRISA and TRISE regi sters control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must ha ve th eir correspondin g
TRIS bits set (input). If the TRIS bit is cleared (output),
the digital output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
12.4 A/D Conversions
Clearing the GO/DONE bit during a conversion will
abort the current conversion . The ADRES register will
NOT be updated with the par tially completed A/D con-
version sample. That is, the ADRES register will con-
tinue to contain the value of the last completed
con v ersi on (or the l ast v alue written to the ADRES re g-
ister). After the A/D conversion is aborted, a 2TAD wa i t
is required before the next acquisition is star ted. After
this 2TAD wait, an acquisition is automatically started on
the selected channel.
12.5 A/D Operation During Sleep
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
s witc hing no ise from the co n v er sion. Wh en the con ver-
sion is completed, the GO/DONE bit will be cleared,
and the res ult loaded into the ADRES register. If the A/
D interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enab led, the A/D mod-
ule will then be tur ned off, although the ADON bit will
remain set.
When the A/ D clo c k sou rce is a nother c loc k o ption (n ot
RC), a SLEEP instruction w ill cause the present con v er-
sion to b e aborted an d the A/D modul e to be turned off ,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
12.6 Effects of a RESET
A device reset forces all registers to their reset state.
The A/D module is disabled and any conversion in
progress is abor ted. All pins with analog functions are
configured as available inputs.
The A DRES regis ter will cont ain unk nown dat a af ter a
power-on reset.
12.7 Use of the CCP Trigger
An A/D conversion can be star ted by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as 1011 and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/DONE
bit will be set, starting the A/D conversion, and the Timer1
counter will be reset t o zero. Timer1 is reset to automati-
cally repeat the A /D acquisition per iod with mini mal soft-
ware overhead (moving the ADRES to the desired
location). T he approp riate a nalog input channel must be
selected and the minimum acquisition done before the
“special event trigger” sets the GO/DONE bit (starts a
conversion).
If the A/D module is not enabled (ADON is cleared),
then t he “spe cial event tr igger” will be ignore d by th e
A/D module, but will still reset the Timer1 counter.
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as dig ital input s will c onver t an a na-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
2: Analog levels on an y pin that is defi ned as
a digital input, but not as an analog input,
may cause the input buffer to consume
current t hat is ou t of the devices speci fica-
tion.
3: The TRISE register is not provided on the
PIC16C73B.
Note: The GO/DONE bit should NOT be set in
the same instruction that turn s on the A/D.
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in SLEEP, ensure the SLEEP
instruction immediately follows the instruc-
tion that sets the GO/DONE bit.
PIC16C63A/65B/73B/74B
DS30605B-page 84 Preliminary 1999 Microchip Technology Inc.
TABLE 12-1: SUMMARY OF A/D REGISTERS (PIC16C73B/74B ONLY)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other
Resets
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/
DONE —ADON0000 00-0 0000 00-0
9Fh ADCON1 PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
05h PORTA RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA PORTA Data Direction Register --11 1111 --11 1111
09h PORTE RE2 RE1 RE0 ---- -xxx ---- -uuu
89h TRISE IBF OBF IBOV PSP-
MODE PORTE Data Direction Bits 0000 -111 0000 -111
Legend: x = unknown, u = unc hanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: Bits PSPIE and PSPIF are reserved on t he PI C6C63A/73B ; alway s maintain these bits clear.
1999 Microchip Technology Inc. Preliminary DS30605B-page 85
PIC16C63A/65B/73B/74B
13.0 SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other proces-
sors are special circuits to deal with the needs of real-
time applications. The PIC 16CXX family has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external compo-
nents , pro vide po wer savi ng opera ting mo des and off er
code protection. These are:
Oscillator selection
Reset
- Power-on Reset (POR)
- P o wer-up Timer (PWR T)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
Interrupts
Watchdog Timer (WDT)
SLEEP
Code protection
ID locations
In-Circuit Serial Programming (ICSP)
The PIC16CXX has a Watchdog Timer which can be
shut off only through configuration bits. It runs off its own
RC oscill ator fo r added re liability. There are t wo timers
that offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), intended to keep the
chip in reset until the crystal oscillator is stable. The
other is t he Power-up Timer (PW RT), which provides a
fixed delay of 72 ms (nomi nal) on power-up only and is
designed to keep the part in reset, while the power sup-
ply stabilizes. With these two timers on-chip, most appli-
cations need no external reset circuitry.
SLEEP mode is designed to offer a very low current
pow er-down m ode. The user can w ake-up from SLEEP
through external reset, WDT wake-up or through an
interrupt. Several oscillator options are also made
available to allow t he p art to fit the a ppl ic atio n. T he R C
oscillator option sa ves system cost, whi le the LP crystal
option sa ve s powe r . A set of configur ation bits are use d
to select various options.
13.1 Configuration Bits
The con figur ati on bits c an be progr a mmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
The user will note that address 2007h is beyond the user
program memory space. In fact, it belongs to the special
test/configuration memory space (2000h - 3FFFh),
which can be accessed only during programming.
REGISTER 13-1: CONFIGURATION WORD
CP1 CP0 CP1 CP0 CP1 CP0 BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 Register: CONFIG
Address 2007h
bit13 bit0
bit 13-8 CP1:CP0: Code Protection bits (2)
5-4: 11 = Code protection off
10 = Upper half of program memory code protected
01 = Upper 3/4th of program memory code protect ed
00 = All memory is code protected
bit 7: Unimplemented: Read as ’1’
bit 6: BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3: PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selectio n bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Enabling brown-out reset automatically enables power-up timer (PWRT), regardless of the value of bit PWR T E.
2: All of the CP1:CP0 pairs have to be given the sam e value to enable the code protection scheme listed.
PIC16C63A/65B/73B/74B
DS30605B-page 86 Preliminary 1999 Microchip Technology Inc.
13.2 Oscillator Configurations
13.2.1 OSCILLATOR TYPES
The PIC16CXX can be operated in four different oscil-
lator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
LP Low Power Crystal
XT Crystal/Resonator
HS High Speed Crystal/Resonator
RC Resistor/Capacitor
13.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In XT, LP or HS modes, a cr ystal or ceramic resona tor
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 13-1). The
PIC16CXX oscillator design requires the use of a paral-
lel cut crystal. Use of a series cut crystal may giv e a fre-
quency out of t he crysta l manufact urers specificat ions.
When in XT, LP or HS modes, the device can have an
external clock source to drive the OSC1/CLKIN pin
(Figure 13-2). See the PICmicro™ Mid-Range MCU
Reference Manual (DS33023A) for details on building
an external oscillator.
FIGURE 13-1: CR YS TAL/CERAMI C
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
FIGURE 13-2: EXTERN AL CLOCK I NPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
TABLE 13-1: CERAMIC RESONATORS
TABLE 13-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
C1
C2
XTAL
OSC2
Note1
OSC1
RFSLEEP
To internal
logic
PIC16CXX
RS
See Table 13-1 and Table 13-2 for recommended values
of C1 and C2.
Note 1: A series resistor may be required for AT strip
cut cr ystals.
OSC1
OSC2
Open
Clock from
ext. syst em PIC16CXX
Ranges Tested:
Mode Freq OSC1 OSC2
XT 455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
HS 8.0 MHz
16.0 MHz 10 - 68 pF
10 - 22 pF 10 - 68 pF
10 - 22 pF
These values are for design guidance only. See notes at
bottom of page.
Resonators Used:
455 kHz Panasonic EFO-A455K04B ± 0.3%
2.0 MHz Murata Er ie CSA2. 00MG ± 0.5%
4.0 MHz Murata Er ie CSA4. 00MG ± 0.5%
8.0 MHz Murata Er ie CSA8. 00MT ± 0.5%
16.0 MHz Murata Erie CSA16.00MX ± 0.5%
Resonators used did not have built-in capacitors.
Osc Type Crystal
Freq Cap. Range
C1 Cap. Range
C2
LP 32 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
XT 200 kHz 47-68 pF 47-68 pF
1 MHz 15 pF 15 pF
4 MHz 15 pF 15 pF
HS 4 MHz 15 pF 15 pF
8 MHz 15-33 pF 15-33 pF
20 MHz 15-33 pF 15-33 pF
These values are for design guidance only. See notes at
bottom of page.
Crystals Used:
32 kHz Epson C-001R32.768K-A ± 20 PPM
200 kHz STD XTL 200.000KHz ± 20 PPM
1 MHz ECS ECS-10-13-1 ± 50 PPM
4 MHz ECS ECS-40-20-1 ± 50 PPM
8 MHz EPSON CA-301 8.000M-C ± 30 PPM
20 MHz EPSON CA- 301 20.000M-C ± 30 PPM
Note 1: Higher capacitance increases the stability of
the oscillator , b ut also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropriate
values of external components.
3: Rs may be required in HS mode, as well as
XT mode to avoid overdriving crystals with low
drive le v el specification.
4: When mig rating f rom ot her PICmicro devices ,
oscillator p erf ormance should be v erified.
1999 Microchip Technology Inc. Preliminary DS30605B-page 87
PIC16C63A/65B/73B/74B
13.2.3 RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the suppl y voltage, the res is-
tor (Rext) and capacitor (Cext) values, and the operat-
ing tempe ratur e. The oscil lator frequen cy will v ary from
unit to uni t due to normal process para meter variation.
The difference in lead frame capacitance between
pac k age type s w il l als o af fect the osc il lat ion fr equ enc y,
especially for low Cext values. The user also needs to
take into account variation due to tolerance of external
R and C components used. Figure 13-3 shows how the
R/C combination is connected to the PIC16CXX.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test pur-
poses or to synchronize other logic (see Figure 3-2 for
waveform).
FIGURE 13-3: RC OSCILLATOR MODE
13.3 Reset
The PIC1 6CXX differentiates between var ious kinds of
reset:
Power-on Reset (POR)
•MCLR
reset during normal operation
•MCLR reset during SLEEP
WDT Reset (normal operation)
Brown-out Reset (BOR)
Some registers are not affected in any reset condition;
their statu s is unk nown on POR and unch an ged in any
other reset. Most other registers are reset to a “reset
state” on POR, on the MCLR and WDT Reset, on
MCLR reset during SLEEP, and on BOR. The TO and
PD bits are set or cleared differently in different reset
situations as indicated in Table 13-4. These bits are
used in software to determine the nature of the reset.
See Table 13-6 for a full description of reset states of all
registers.
A simplifi ed b loc k diag ram of the on-ch ip res et circui t is
shown in Figure 13-4.
The PICmicro devices have a MCLR noise filter in the
MCLR reset path. The filter will de tect a nd ign ore sm all
pulses.
It should be noted that a WDT reset
does not drive
MCLR pin low.
OSC2/CLKOUT
Cext
VDD
Rext
VSS
PIC16CXX
OSC1
Fosc/4
Internal
clock
Recommended Values: REXT = 3k to 100k
CEXT = 20 pf to 30 pf
PIC16C63A/65B/73B/74B
DS30605B-page 88 Preliminary 1999 Microchip Technology Inc.
FIGURE 13-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External
Reset
MCLR
VDD
OSC1
WDT
Module
VDD rise
detect
OST/PWRT
On-chip
RC OSC
WDT
Time-out
Power-on Reset
OST
10-bit Ripple counter
PWRT
Chip Reset
10-bit Ripple counter
Reset
Enable OST
Enable PWRT
SLEEP
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
Brown-out
Reset BODEN
(1)
1999 Microchip Technology Inc. Preliminary DS30605B-page 89
PIC16C63A/65B/73B/74B
13.4 Resets
13.4.1 POWER-ON RESET (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will elimi-
nate e xternal RC componen ts usually needed to create
a POR. A maximum rise time for VDD is speci fie d. S ee
Electrical Specifications for details.
When the device starts normal operation (exits the
reset co ndi tion), dev ice op erating param ete rs (voltage,
frequency, temperature) must be met to ensure opera-
tion. If these c onditions are not met, the de vice m ust be
held in reset until the operating conditions are met.
Brown- o ut r e se t m ay be u se d to me et th e s t artu p c on -
ditions.
For additional information, refer to Application Note
AN607, “
Power-up Trouble Shooting
.”
13.4.2 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up from the POR. The PWRT oper-
ates on an internal RC oscillator. The device is kept in
reset as long as the PWRT is active. The PWRT’s time
delay allows VDD to rise to an acceptable level. A con-
figuration bit is provided to enable/disable the PWRT.
The po wer-up tim e dela y will vary from chip to chip due
to VDD, temperature and process variation. See DC
parameters for details (TPWRT, parameter #33).
13.4.3 OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer provides a delay of 1024
oscillator cycles (from OSC1 input) after the PWRT
dela y. This ensures that the crystal os cillator or resona-
tor has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on power-on reset or wake-up from
SLEEP.
13.4.4 BROWN-OUT RESET (BOR)
The c onfiguration b it, BODEN , can enable or di sable
the Brown-out Reset circuit. If VPP falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(parameter #35, about 100µS), the brown-out situa-
tion will reset the device. If VDD falls below VBOR for
less than T BOR, a r ese t may not occur.
Once the brown-out occ urs, the device will remain in
brown-out reset until VDD rises above VBOR. The
power-up timer then keeps the device in reset for
TPWRT (parameter #33, about 72mS). If VDD should
fall below VBOR during TPWRT, the brown-out reset
process w ill restar t whe n VDD r ises above VBOR with
the power-up timer reset. The power-up timer is
always enabled when the brown-out reset circuit is
enabled re ga rdless of th e sta te o f the PW RT config u-
ration bit.
13.4.5 TIME-OUT SEQUENCE
On po w e r-up, the time-out sequen ce is as follo ws: The
PWRT delay starts (if enabled) when a POR reset
occurs. Then OST starts counting 1024 oscillator
cycles when PWRT ends (LP, XT, HS). When the OST
ends, the devi ce comes out of RESET.
If MCLR is kept low long enough, the time-outs will
expire. Bringing MCLR high wi ll beg in execution im m e-
diately. This is useful for testing purposes or to synchro-
nize more than one PIC16CXX device operating in
parallel.
Table 13-5 shows the reset conditions for the STATUS,
PCON and PC registers, while Table 13-6 shows the
reset conditions for all the registers.
13.4.6 POWER CONTROL/STATUS REGISTER
(PCON)
The Bro wn-out Reset Sta tus bit, BOR, i s unkno wn on a
POR. I t must be set b y th e user an d chec k ed on su bse-
quent res ets to see if bit BO R was c leare d, indi cating a
BOR occurred. The BOR bit is not predictable if the
brown-out reset circuitry is disabled.
The Power-on Reset Status bit, POR, is cleared on a
POR and unaffected otherwise. The user must set this
bit following a POR and check it on subsequent resets
to see if it has been cleared.
TABLE 13-3: TIME-OUT IN VARIOUS SITUATIONS
Oscillator Configur ation Power-up Brown-out Wake-up from SLEEP
PWRTE = 0 PWRTE = 1
XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC
RC 72 ms 72 ms
PIC16C63A/65B/73B/74B
DS30605B-page 90 Preliminary 1999 Microchip Technology Inc.
TABLE 13-4: STATUS BITS AND THEIR SIGNIFICANCE
TABLE 13-5: RESET CONDITION FOR SPECIAL REGISTERS
Status Register
PCON Register
POR BOR TO PD
0x11Power-on Reset
0x0xIllegal, TO is set on POR
0xx0Illegal, PD is set on POR
1011Brown-out R eset
1101WDT Reset
1100WDT Wake-up
11uuMCLR Reset dur ing normal operation
1110MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Condition Program
Counter STATUS
Register PCON
Register
Pow e r-on Reset 000h 0001 1xxx ---- --0x
MCLR Reset during normal operation 000h 000u uuuu ---- --uu
MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu
WDT R eset 000h 0000 1uuu ---- --uu
WDT Wake-u p PC + 1 uuu0 0uuu ---- --uu
Brown-out R eset 000h 000x xuuu ---- --u0
Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit read as ’0’.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
IRP RP1 RP0 TO PD ZDC C
POR BOR
1999 Microchip Technology Inc. Preliminary DS30605B-page 91
PIC16C63A/65B/73B/74B
TABLE 13-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Applicable Devices Power-on Res et
Brown-out Reset MCLR Resets
WDT Reset W ake-up via WDT or
Interrupt
W 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu
INDF 63A 65B 73B 74B N/A N/A N/A
TMR0 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu
PCL 63A 65B 73B 74B 0000h 0000h PC + 1(2)
STATUS 63A 65B 73B 74B 0001 1xxx 000q quuu(3) uuuq quuu(3)
FSR 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 63A 65B 73B 74B --0x 0000 --0u 0000 --uu uuuu
PORTB 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu
PORTD 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu
PORTE 63A 65B 73B 74B ---- -xxx ---- -uuu ---- -uuu
PCLATH 63A 65B 73B 74B ---0 0000 ---0 0000 ---u uuuu
INTCON 63A 65B 73B 74B 0000 000x 0000 000u uuuu uuuu(1)
PIR1
63A 65B 73B 74B -0-- 0000 -0-- 0000 -u-- uuuu(1)
63A 65B 73B 74B -000 0000 -000 0000 -uuu uuuu(1)
63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu(1)
63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu(1)
PIR2 63A 65B 73B 74B ---- ---0 ---- ---0 ---- ---u(1)
TMR1L 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 63A 65B 73B 74B --00 0000 --uu uuuu --uu uuuu
TMR2 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu
T2CON 63A 65B 73B 74B -000 0000 -000 0000 -uuu uuuu
SSPBUF 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu
SSPCON 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu
CCPR1L 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1H 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 63A 65B 73B 74B --00 0000 --00 0000 --uu uuuu
RCSTA 63A 65B 73B 74B 0000 -00x 0000 -00x uuuu -uuu
TXREG 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu
RCREG 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu
CCPR2L 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2H 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu
ADRES 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 63A 65B 73B 74B 0000 00-0 0000 00-0 uuuu uu-u
OPTION_REG 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on c ondition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be aff ected (to cause wak e-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
3: See Table 13-5 for reset value for specific condition.
PIC16C63A/65B/73B/74B
DS30605B-page 92 Preliminary 1999 Microchip Technology Inc.
TRISA 63A 65B 73B 74B --11 1111 --11 1111 --uu uuuu
TRISB 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu
TRISC 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu
TRISD 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu
TRISE 63A 65B 73B 74B 0000 -111 0000 -111 uuuu -uuu
PIE1
63A 65B 73B 74B --00 0000 --00 0000 --uu uuuu
63A 65B 73B 74B 0-00 0000 0-00 0000 u-uu uuuu
63A 65B 73B 74B -000 0000 -000 0000 -uuu uuuu
63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu
PIE2 63A 65B 73B 74B ---- ---0 ---- ---0 ---- ---u
PCON 63A 65B 73B 74B ---- --0q(3) ---- --uu ---- --uu
PR2 63A 65B 73B 74B 1111 1111 1111 1111 1111 1111
SSPADD 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 63A 65B 73B 74B --00 0000 --00 0000 --uu uuuu
TXSTA 63A 65B 73B 74B 0000 -010 0000 -010 uuuu -uuu
SPBRG 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu
ADCON1 63A 65B 73B 74B ---- -000 ---- -000 ---- -uuu
TABLE 13-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on Res et
Brown-out Reset MCLR Resets
WDT Reset W ake-up via WDT or
Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on c ondition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be aff ected (to cause wak e-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
3: See Table 13-5 for reset value for specific condition.
1999 Microchip Technology Inc. Preliminary DS30605B-page 93
PIC16C63A/65B/73B/74B
13.5 Interrupts
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared ) all in terrupts . W hen bit GIE is enab le d, and a n
interrupt’ s flag bit and mas k bit are set, the interrupt wil l
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB po rt change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The per i pheral interrupt flags are contained in the spe-
cial fu nctio n registers PIR1 and PIR2. The corres pond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2 and the peripheral
inter rupt enab le bit is co ntaine d in spec ial function reg-
ister INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is push ed onto th e stac k, and the PC is lo aded
with 0004h. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interr upt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the s am e for one or t w o cy cl e in struction s . Indi vi dual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit or the GIE bit.
Note: Indiv idual interrupt flag bits are set, regard-
les s of the status of their c orrespondi ng
mask bit or the GIE bit.
Note: If an interrupt occurs while the Global
Interrupt Enab le (GIE) bit is being c leared,
the GIE bit may unintentionally be re-
enabled by the user’s Interrupt Service
Routine (the RETFIE instruction). The
events that would cause this to occur are:
1. An instruction clears the G IE bit while
an interrupt is acknowledged.
2. The program branches to the inter-
rupt ve ctor and ex ecute s the interrupt
service routine.
3. The interrupt service routine com-
pletes the execution of the RETFIE
inst ruction. This causes the GIE b it to
be set (enables interrupts), and the
program returns to the instruction
after the one w hich was meant to dis-
able interrupts.
Perform the following to ensure that inter-
rupts are global ly disa b l ed:
LOOP BCF INTCON, GIE ; Disable global
; interrupt bit
BTFSC INTCON, GIE ; Global interrupt
; disabled?
GOTO LOOP ; NO, try again
: ; Yes, continue
; with program
; flow
PIC16C63A/65B/73B/74B
DS30605B-page 94 Preliminary 1999 Microchip Technology Inc.
FIGURE 13-5: INTE RRUPT LOGIC
13.5.1 INT INTERRUPT
The external interrupt on RB0/INT pin is edge trig-
gered: either rising, i f bit I NTEDG ( OPTION_REG<6>)
is set o r falling , if t he INTEDG bit is cl ear. When a valid
edge appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be clea red in s oftware i n the in terrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can w ake-up the proces sor from SLEE P, if bit INT E was
set prior to goin g into SLEEP. The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor b ra nch es t o t he in t errupt vec tor followin g wake-u p.
See Section 13.8 for details on SLEEP mode.
13.5.2 TMR0 INTERRUPT
An overf l ow (F F h 00h) in the TMR0 register will se t
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 6.0)
13.5.3 PORT B INTERRUPT ON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 5.2)
13.6 Context Saving During Interrupts
During an interr upt, only the return PC value is saved
on the stac k. U sers ma y wish to sa ve ke y regist ers dur-
ing an interrupt i.e., W register and STATUS register.
This will have to be implemented in software.
Example 13-1 st ores and restore s the STATUS, W, and
PCLATH registers. The register W_TEMP must be
defined in each bank and must be defined at the same
offset from the bank base address (i.e., if W_TEMP is
defined at 0x20 in bank 0, it must also be defined at
0xA0 in bank 1) .
The example:
a) Stores the W register.
b) Stores the STATUS register in bank 0.
c) Stores the PCLATH register.
d) Executes the ISR code.
e) Restores the STATUS register
(and bank select bit).
f) Restores the W and PCLATH registers.
PSPIF
PSPIE ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
T0IF
T0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (If in SLEEP mode )
Interrupt to CPU
CCP2IE
CCP2IF
The following table shows which devices have which interrupts.
Device T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF CCP2IF
PIC16C63A Yes Yes Yes - - Yes Yes Yes Yes Yes Yes Yes
PIC16C65B Yes Yes Yes Yes - Yes Yes Yes Yes Yes Yes Yes
PIC16C73B Yes Yes Yes - Yes Yes Yes Yes Yes Yes Yes Yes
PIC16C74B Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Note: If a change on the I/O pin should occur
when t he read operati on i s bei ng executed
(start of the Q 2 cycle), t hen the RBIF inter-
rupt flag may not get set.
1999 Microchip Technology Inc. Preliminary DS30605B-page 95
PIC16C63A/65B/73B/74B
EXAMPLE 13-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero
SWAPF STATUS,W ;Swap status to be saved into W
CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3
MOVWF PCLATH_TEMP ;Save PCLATH into W
:
(ISR)
:
MOVF PCLATH_TEMP, W ;Restore PCLATH
MOVWF PCLATH ;Move W into PCLATH
SWAPF STATUS_TEMP, W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W
13.7 Watchdog Timer (WDT)
The w at ch dog tim er is a fre e runnin g on-chip RC osci l-
lator, which does not requ ire an y e x ternal comp one nts.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. The WDT will run, even if the
clock on the OSC1/CLKIN and OSC2/CLKOUT pins of
the de vice has been stopped, f or example , by e xecution
of a SLEEP instruction.
During nor mal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the de vice is
in SLEEP m ode, a WDT time-out causes the device to
wake-up and resume normal operation (Watchdog
Timer Wake-up).
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 13.1).
13.7.1 WDT PERIOD
The WDT has a nominal time-out period of 18 ms
(parameter #31, TWDT). The time-out periods var y with
temperature, VDD and process variations. If longer
time-out periods are desired, a prescaler with a division
ratio of up to 1:128 can be assigned to the WDT under
software control by writing to the OPTION register.
Time-out periods up to 128 TWDT can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assi gned to the WDT. In additio n,
the SLEEP instruction prevents the WDT from generat-
ing a reset, but will allow the WDT to wake the device
from sleep mode.
The TO bit in the STATUS register w il l be cle ared upo n
a WDT time-out.
13.7.2 WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., and
max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
presc al er ass ig nme nt is not changed.
PIC16C63A/65B/73B/74B
DS30605B-page 96 Preliminary 1999 Microchip Technology Inc.
FIGURE 13-6: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 13-7: SUMMARY OF WATCHDOG TIMER REGISTERS
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2007h Config. bits -BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 13-1 for operation of these bits.
From TMR0 Clock Source
(Figure 6-1)
To TMR0 MUX
(Figure 6-1)
Postscaler
WDT Timer
WDT
Enable Bit
0
1M
U
X
PSA
8 - to - 1 MUX PS2:PS0
01
MUX PSA
WDT
Time-out
Note: PSA and PS2:PS 0 are bits in the OPTION register.
8
1999 Microchip Technology Inc. Preliminary DS30605B-page 97
PIC16C63A/65B/73B/74B
13.8 Power-Down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the WDT will be cleared but keeps running,
the PD bit (STATUS<3>) is cleared, the TO (STA-
TUS<4>) bit is set, and the oscillator driver is turned off.
The I/O ports maintain the status they had, before the
SLEEP instruction was executed (driving high, low, or
hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D, and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low exter nally, to
avoid switching c urre nts ca us ed by floating inp uts. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
13.8.1 WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1. External reset input on MCLR pin.
2. W atchdog Timer W ak e-up (if WDT was e nabled).
3. Interrupt from INT pin, RB port change or some
Peripheral Interrupts.
External MCL R reset will cause a device reset. All other
events are considered a continuation of program exe-
cution and cause a “wake-up”. The TO and PD bits in
the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred (and caused
wake-up).
The following peripheral interrupts can wake the device
from SLEEP:
1. TMR1 interrupt. Timer1 m ust be operat ing as a n
asynchronous counter.
2. SSP (Start/Stop) bit detect interrupt.
3. SSP transmit or receive in slave mode
(SPI / I2C).
4. CCP capture mode interrupt.
5. Parallel slave port read or write.
6. A/D conversion (when A/D clock source is RC).
7. USART TX or RX (sy nchronous slave mode).
Other pe ripherals can not gener ate interrupts si nce dur-
ing SLEEP, no on-chip Q clocks are present.
When th e SLEEP instruction is being ex ecuted, the ne xt
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
inte rrup t ena ble bit mus t be set (enabled ). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instr uct ion . If t he GIE bi t is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
ru pt ad dress (00 04h ). In ca ses wh ere the execution of
the instruction following SLEEP is not desirable, the
user shoul d have a NOP after the SLEEP instruction.
13.8.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and inte rrupt flag bit se t, one o f the f o llo wing w ill o ccur:
If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruct ion wi ll com -
plete as a NOP. Therefore, the WDT and WDT
pos tscaler will not be clear ed, the TO bit will not
be set and PD bit will not be cleared.
If the interrupt occurs during or after the execu-
tion of a SLEEP instruction, the device wil l imme-
diately wake up from slee p. The SLEEP instruction
will be completely executed before the wake -up.
Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP ins truc tion exec uted, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT in stru c-
tion should be executed before a SLEEP instruction.
PIC16C63A/65B/73B/74B
DS30605B-page 98 Preliminary 1999 Microchip Technology Inc.
FIGURE 13-7: WAKE-UP FROM SLEEP THROUGH INTERRUPT
13.9 Program Verification/Code Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
13.10 ID Locations
F our memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are read-
able and writable during program/verify. It is recom-
mended that o nly th e f ou r le ast sign ifican t bits of the ID
location are used.
13.11 In-Circuit Serial Programming
PIC16CXX microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done wit h two lines f or c lock a nd dat a, and thre e
other lines f or po wer , g round and the prog ramming volt-
age. This al lows customers to manufacture boards wi th
unprogrammed devices, and then program the micro-
controller just before shipping the product. This also
allows the most recent fir mware or a custom firmware
to be programmed.
The device is placed into a program/verify mode by
holding the RB6 and RB7 pins low, while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). RB6 becomes the programming clock
and RB7 becomes the programming data. Both RB6
and RB7 are Schmitt Trigger inputs in this mode.
After reset, to place the de vice into programming/verify
mode, the program counter (PC) is at location 00h. A
6-bit command is then supplied to the de vice. Depend-
ing on the command, 14 bits of program data are then
supplied to or from the device, depending if the com-
mand was a load or a read. For complete details of
serial programming, please refer to the PIC16C6X/7X
Programming Specifications (Literature #DS30228).
FIGURE 13-8: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
CONNECTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
PC PC+1 PC+2
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 1)
SLEEP
Processor in
SLEEP
Interrupt Latency(2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2 0004h 0005h
Dummy cycle
TOST(2)
PC+2
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale). This delay is not present in RC osc mode.
3: GIE = ’1’ assumed. After wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.
4: CLKOUT is not available in these osc modes, b ut shown here for timing reference.
Note: Microchip does not reco mmend code pro-
tecting windowed devic es. De vices that a re
code prot ected may be erased, but not pro-
gr am m ed aga in.
External
Connector
Signals
To Normal
Connections
To Normal
Connections
PIC16CXX
VDD
VSS
MCLR/VPP
RB6
RB7
+5V
0V
VPP
CLK
Data I/O
VDD
1999 Microchip Technology Inc. Preliminary DS30605B-page 99
PIC16C63A/65B/73B/74B
14.0 INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided
into an OPCO DE, which specifies the instruction type
and one or more operands, which further specify the
oper at ion of the instructio n. The PIC 16CXX ins tructio n
set summary in Table 14-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 14-1
shows the opcode field descriptions.
For byte-oriented instructions, ’f’ represents a file reg-
ister designator andd’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The desti nation designator specifies where the result of
the operation is to be placed. If ’d’ is zero, the result is
placed in the W registe r . If ’d ’ is one , the result i s placed
in the file register specified in the instruction.
For bit-oriented instructions, b’ represents a bit field
design ator which selec ts the number of th e b it affecte d
by the operation, while ’frepresents the number of the
file in which the bit is located.
For literal and control operations, ’k’ represents an
eigh t or eleven bit co nstant or literal value.
TABLE 14-1: OPCODE FIELD
DESCRIPTIONS
The instruction set is highly or thogonal and is grouped
into three basic categories:
Byte-oriented ope ra tio ns
Bit-oriented operations
Literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is tr ue or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. O ne i n struc-
tion cycle consists of four oscillator periods. Thus, for
an osci llator frequ ency of 4 MHz, t he normal instructio n
e xecution tim e is 1 µs . If a condit ional te st is true or th e
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.
Table 14-2 lists the instructions recognized by the
MPASM assembler.
Figur e 14-1 sh ows the g eneral f ormats that th e instruc-
tions can have.
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 14-1: GENERAL FORMAT FOR
INSTRUCTIONS
Field Description
fRegister file address (0x00 to 0x7F)
WWorking register (accumulator)
bBit address within an 8-bit file r egister
kLiteral field, constant data or label
x
Don’t care location (= 0 or 1)
The assembler will generat e code with x = 0. I t is t he
recommended f orm of use for compatibility with all
Microchip software tools.
dDestination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
label Label name
TOS Top of Stack
PC Program Counter
PCLATH Program Counter High Latch
GIE Global Interrupt Enable bit
WDT Watchdog Timer/Counter
TO Time-out bit
PD Power-down bit
dest Destination either the W register or the specified
register file location
[ ] Options
( ) Contents
Assigned to
< > Regis ter bit field
In the set of
i
talics
User defined term (font is courier)
Note: To maintain upward compatibility with
future PIC16CXX products, do not use the
OPTION and TRIS instructions.
Byte-oriented file register operations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE # )
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9 7 6 0
OPCODE b (BIT # ) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control opera tions
13 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
General
CALL and GOTO instructions only
PIC16C63A/65B/73B/74B
DS30605B-page 100 Preliminary 1999 Microchip Technology Inc.
TABLE 14-2: PIC16CXX INSTRUCTION SET
Mnemonic,
Operands Description Cycles 14-Bit Opcode Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Compleme nt f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
0011
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if C l ear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERAT IONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move lit eral to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves . For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
devi ce , the data will be written back with a ’ 0’.
2: If this instruction is e x ecuted on the T MR0 register (and, where applicable , d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Addit ional inf ormation on the mid-range instruction set is av ailable in the PICmic ro Mid-Range MCU F amily
Reference Manual (DS33023).
1999 Microchip Technology Inc. Preliminary DS30605B-page 101
PIC16C63A/65B/73B/74B
14.1 Instruction Descriptions
ADDLW Add Literal and W
Syntax: [
label
] ADDLW k
Operands: 0 k 255
Operat ion: (W) + k (W)
Status Affected: C, DC, Z
Description: The contents of the W register are
added to the eight bit literal ’ k’ and the
result is placed in the W register.
ADDWF Add W and f
Syntax: [
label
] ADDWF f,d
Operands: 0 f 127
d ∈ [0,1]
Operation: (W) + (f) (destination)
Status Affected: C, DC, Z
Description: Add the contents of the W register
with register ’f’. If ’d’ is 0, the result is
stored in the W register. If ’d’ is 1, the
result is stored back in register ’f’.
ANDLW AND Li teral with W
Syntax: [
label
] ANDLW k
Operands: 0 k 255
Operation: (W) .AND. (k) (W)
Status Affected: Z
Description: The contents of W register are
AND’ed with the eight bit literal 'k'.
The result is placed in the W register.
ANDWF AND W with f
Syntax: [
label
] ANDWF f,d
Operands: 0 f 127
d ∈ [0,1]
Operation: (W) .AND. (f) (destination)
Status Affected: Z
Description: AND the W register with register 'f'. If
'd' is 0, the result is stored in the W
register. If 'd' is 1, the result is stored
back in register 'f'.
BCF Bit Clear f
Syntax: [
label
] BCF f,b
Operands: 0 f 127
0 b 7
Operation: 0 (f<b>)
Status Affected: None
Description: Bit 'b' in register 'f' is cleared.
BSF Bit Set f
Syntax: [
label
] BSF f,b
Operands: 0 f 127
0 b 7
Operation: 1 (f<b>)
Status Affected: None
Description: Bit 'b' in register 'f' is set.
PIC16C63A/65B/73B/74B
DS30605B-page 102 Preliminary 1999 Microchip Technology Inc.
BTFSS Bit Test f, Skip if Set
Syntax: [
label
] BTFSS f,b
Operands: 0 f 127
0 b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Description: If bit ’b’ in register ’f’ is ’0’, the next
instruction is executed.
If bit ’b’ is ’1’, then the nex t instr uction
is discarded and a NOP is executed
instead making this a 2TCY instruction.
BTFSC Bit Test, Skip if Clear
Syntax: [
label
] BTFSC f,b
Operands: 0 f 127
0 b 7
Operation: skip if (f<b>) = 0
Status Affected: None
Description: If bit ’ b’ in register ’f’ is ’1’, the next
instruction is executed.
If b it ’b ’, i n r egist er ’f’, is ’0 ’, the next
instruction is discarded, and a NOP is
executed instead, making this a 2TCY
instruction.
CALL Call Subroutine
Syntax: [
label
] CALL k
Operands: 0 k 2047
Operation: (PC)+ 1 TOS ,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Status Affected: None
Description: Call Subroutine. First, return address
(PC+1) is pushed onto the stack. The
elev en bit immediate address is loaded
into PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALL is a two cycle in st ruction.
CLRF Clear f
Syntax: [
label
] CLRF f
Operands: 0 f 127
Operat ion: 00h (f)
1 Z
Status Affected: Z
Description: The contents of register ’f’ are cleared
and the Z bit is set.
CLRW Clear W
Syntax: [
label
] CLRW
Operands: None
Operation: 00h (W)
1 Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z) is
set.
CLRWDT Clear Watchdog Timer
Syntax: [
label
] CLRWDT
Operands: None
Operation: 00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Affected: TO, PD
Description: CLRWDT instruction resets the Watc h-
dog Timer . It also resets the prescaler
of the WDT. Status bits TO and PD
are set.
1999 Microchip Technology Inc. Preliminary DS30605B-page 103
PIC16C63A/65B/73B/74B
COMF Complement f
Syntax: [
label
] COMF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (destination)
Status Affected: Z
Description: The contents of regist er ’f’ are comple-
mented. If ’d’ is 0, the result is stored
in W. If ’d’ is 1, the result is stored
back in register ’f’.
DECF Decrement f
Syntax: [
label
] DECF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination)
Status Affected: Z
Description: Decrement register ’f’. If d’ is 0, the
result is stored in the W register. If ’ d’
is 1, the result is stored back in regis-
ter ’f’ .
DECFSZ Decrement f, Skip if 0
Syntax: [
label
] DECFSZ f,d
Operands: 0 f 127
d [0,1]
Operation : (f) - 1 (destination);
skip if result = 0
Status Affected: None
Description: Th e contents of register ’f’ are decr e-
mented. If d’ is 0, the result is placed in
the W register. If ’d’ is 1, the result is
placed back in register ’f’.
If the result is 1, the ne xt inst ruction is
e xecuted. If the result is 0, then a NOP is
execute d instead making it a 2TCY
instruction.
GOTO Unconditional Branch
Syntax: [
label
] GOTO k
Operands: 0 k 2047
Operation: k PC<10:0>
PCLATH<4:3> PC<12:11>
Status Affected: None
Description: GOTO is an unconditional branch. The
eleven bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTO is a two cycle instruct ion.
INCF Increment f
Syntax: [
label
] INCF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination)
Status Affected: Z
Description: The contents of register ’f are incre-
mented. If ’d’ is 0, the result is placed
in the W register . If ’ d’ is 1, the result is
placed back in register ’f’.
INCFSZ Increment f, Skip if 0
Syntax: [
label
] INCFSZ f,d
Operands: 0 f 127
d [0,1]
Operat ion: ( f) + 1 (destination),
skip if result = 0
Status Affected: None
Description: The cont ents of register ’f’ are incre-
mented. If ’d’ is 0, the result is placed
in the W register . If ’d’ is 1, the result is
placed back in register ’f’.
If the result is 1, the next instruction is
executed. If the result is 0, a NOP is
executed instead making it a 2TCY
instruction.
PIC16C63A/65B/73B/74B
DS30605B-page 104 Preliminary 1999 Microchip Technology Inc.
IORLW Inclusive OR Literal with W
Syntax: [
label
] IORLW k
Operands: 0 k 255
Operat ion: (W) .OR. k (W)
Status Affected: Z
Description: The contents of the W register are
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
IORWF Inclusive OR W with f
Syntax: [
label
] IORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .OR. (f) (destinatio n)
Status Affected: Z
Description: Inclusive OR the W register with regis-
ter 'f'. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
MOV F Move f
Syntax: [
label
] MOVF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (destination )
Status Affected: Z
Description: The contents of register f are moved
to a destination dependant upon the
status of d. If d = 0, destination is W
register. If d = 1, the destination is file
register f itself. d = 1 is useful t o test a
file register since status flag Z is
affected.
MOVLW Move Literal to W
Syntax: [
label
] MOVLW k
Operands: 0 k 255
Operation: k (W)
Status Affected: None
Description: The eight bit liter al ' k' is loaded int o W
register. The don’t cares will assem-
ble as 0’s.
MOVWF Move W to f
Syntax: [
label
] MOVWF f
Operands: 0 f 127
Operat ion: (W) (f)
Status Affected: None
Description: Move data from W register to register
'f'.
NOP No Operation
Syntax: [
label
] NOP
Operands: None
Operation: No operation
Status Affected: None
Description: No operation.
1999 Microchip Technology Inc. Preliminary DS30605B-page 105
PIC16C63A/65B/73B/74B
RETFIE Return from Interrupt
Syntax: [
label
] RETFIE
Operands: None
Operation: TOS PC,
1 GIE
Status Affected: None
RETLW Return with Literal in W
Syntax: [
label
] RETLW k
Operands: 0 k 255
Operation: k (W);
TOS PC
Status Affected: None
Description: The W register is loaded with the eight
bit literal ’k’. The program counter is
loaded from the top of the stack (the
return address). This is a two cycle
instruction.
RETURN Return from Subroutine
Syntax: [
label
] RETURN
Operands: None
Operation: TOS PC
Status Affected: None
Description: Return from subroutine. The stack is
POPed and the t op of the stack (T OS)
is loaded into the program counter.
This is a two cycle instruction.
RLF Rotate Left f through Carry
Syntax: [
label
] RLF f,d
Operands: 0 f 127
d [0,1]
Operation: See descr iption below
Status Affected: C
Description: The contents of register ’f’ are rotated
one bit to the left through the Carry
Flag. If ’d’ is 0, the result is placed in
the W register. If ’d’ is 1, the result is
stored back in register ’f’.
RRF Rotate Right f through Car ry
Syntax: [
label
] RRF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ’f’ are rotated
one bit to the right through the Carry
Flag. If ’d’ is 0, the result is placed in
the W register. If ’d’ is 1, t he result is
placed back in register ’f ’.
SLEEP
Syntax: [
label
] SLEEP
Operands: None
Operation: 00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Status Affected: TO, P D
Description: The power-down status bit, PD is
cleared. Time-out status bit, TO is
set. Wat chdog Timer and its pres-
caler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
See Section 13. 8 for more details.
Register fC
Register fC
PIC16C63A/65B/73B/74B
DS30605B-page 106 Preliminary 1999 Microchip Technology Inc.
SUBLW Subtract W from Literal
Syntax: [
label
]SUBLW k
Operands: 0 k 255
Operation: k - (W) → (W)
Status Affected: C, DC, Z
Description: The W register is subtracted (2’s com-
plement method) from the eight bit lit-
eral 'k'. The result is placed in the W
register.
SUBWF Subtract W from f
Syntax: [
label
]SUBWF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - (W) → (destination)
Status
Affected: C, DC, Z
Description: Subtract (2’s complement method) W
register from register 'f'. If 'd' is 0, the
result is stored in the W register. If 'd' is
1, the result is stored back in register 'f'.
SWAPF Swap Nibbles in f
Syntax: [
label
] SWAPF f,d
Operands: 0 f 127
d [0,1]
Operation: (f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Affected: None
Description: The upper and lower nibbles of regis-
ter 'f' are exchange d. If 'd' is 0, t he
result is placed in W register . If 'd' is 1,
the result is placed in register 'f'.
XORLW Exclusive OR Literal with W
Syntax: [
label
]XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k → (W)
Status Affected: Z
Description: The contents of the W register are
XOR’ed with the eight bit literal 'k '.
The result is placed in the W regis-
ter.
XORWF Exclusive OR W with f
Syntax: [
label
] XORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .XOR. (f) → (destination)
Status Affected: Z
Description: Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0, the
result is stored in the W register. If 'd'
is 1, the result is stored back in regis-
ter 'f'.
1999 Microchip Technology Inc. DS30605B-page 107
PIC16C63A/65B/73B/74B
15.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full r an ge of hardw are and softw are d e velopment tools :
Integrated Development Environment
- MPLAB™ IDE Software
Assemblers/Compilers/Linkers
- MPASM Assembler
- MPLAB-C17 and MPLAB-C18 C Compilers
- MPLINK/MPLIB Linker/Librarian
Simulators
- MPLAB-SIM Software Simulator
•Emulators
- MPLAB-ICE Real-Time In-Circuit Emulator
- PICMASTER®/PICMASTER-CE In-Circui t
Emulator
-ICEPIC™
In-Circuit Debugger
- MPLAB-ICD for PIC16F 877
Device Programmers
-PRO MATE
II Universal Programmer
- PICSTART Plus Entry-Level Prototype
Programmer
Low-Cost Demonstration Boards
- SIMICE
- PICDEM-1
- PICDEM-2
- PICDEM-3
- PICDEM-17
- SEEVAL
-KEELOQ
15.1 MPLAB Integrated Development
Environment Software
- The MPLAB IDE software brings an ease of
software development previously unseen in
the 8-bit microc ontroll er market. MPLAB is a
Windows-based application which contains:
Multiple functionality
-editor
- simulator
- programmer (sold separately)
- emulator (sold separately)
A full featured editor
A project manager
Customizable tool bar and key mapping
A status bar
On-line help
MPLAB allows you to:
Edit your source files (either assembly or ‘C’)
One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
proje ct information)
Debug using:
- source files
- abs olute listin g file
- object code
The ability to use MPLAB with Microchip’s simulator,
MPLAB-SIM, allows a con si stent pl atform and the abil-
ity to easily switch from the cost-effective simulator to
the full featured emulator with minimal retraining.
15.2 MPASM Assembler
MPASM is a full f eatured unive rsal macr o assembl er for
all PICmicro MCU’s. It can produce absolute code
directly in the form of HEX files for device program-
mers, or it can generate relocatable objects for
MPLINK.
MPASM has a command line interface and a Windows
shell and c an be u sed a s a stand alone appli catio n o n a
Windows 3.x or greater system. MPASM generates
relocatable object files, Intel standard HEX files, MAP
files to detail memory usage and symbol reference, an
absolute LST file whi ch con tains source li nes an d ge n-
erated machine code, and a COD file for MPLAB
debugging.
MPASM feature s includ e:
MPASM and MPLINK are integrated into MPLAB
projects.
MPASM allows user defined macros to be created
for streamlined assembly.
MPASM allows conditional assembly for multi pur-
pose source files.
MPASM directiv es a llow c omplete c ontrol o ve r the
assem b l y proces s .
15.3 MPLAB-C17 and MPLAB-C18
C Compilers
The MPLAB-C 17 and MPLAB -C18 Code De v elop ment
Systems are complete ANSI ‘C’ compilers and inte-
grated development environments for Microchip’s
PIC17CXXX and PIC18CXXX family of microcontrol-
lers, respectively. These compilers provide powerful
integration capabilities and ease of use not found with
other co mpi le rs .
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memor y display.
PIC16C63A/65B/73B/74B
DS30605B-page 108 1999 Microchip Technology Inc.
15.4 MPLINK/MPLIB Linker/Librarian
MPLINK is a relocatable linker for MPASM and
MPLAB-C17 and MPLAB-C18. It can link relocatable
objects from assembly or C source files along with pre-
compiled libraries using directives from a linker script.
MPLIB is a librarian for pre-compiled code to be used
with MPLINK. When a routine from a library is called
from another source file, only the modules that cont ains
that routine will be linked in with the application. This
allows l arg e li brarie s t o b e use d e ffi ci en tl y i n ma ny di f-
ferent applications. MPLIB manages the creation and
modification of library files.
MPLINK features includ e:
MPLINK works with MPASM and MPLAB-C17
and MPLAB-C18.
MPLINK allows all memory areas to be defined as
sections to provide link-time flexibility.
MPLIB features incl ude:
MPLIB makes linking easier becau se single libr ar-
ies can be included instead of many smaller files.
MPLIB hel ps k ee p code main tainab l e b y g roupin g
related modules together.
MPLIB commands allow libraries to be created
and modules to be added, listed, replaced,
deleted, or extracted.
15.5 MPLAB-SIM Software Simulator
The MPLAB-SIM Software Simulator allows code
development in a PC host environment by simulating
the PICmicro series mi crocontrollers on an instruction
leve l. On any g ive n instr uction , the da ta area s can be
examined or modified and stimuli can be applied from
a file or user-defined key press to any of the pins. The
e xecution can be perf ormed in singl e step, e xecute until
break, or trace mode.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPLAB-C18 and MPASM. The Soft-
ware Simulator offers the flexibility to develop and
deb ug code outside of the laboratory enviro nment mak-
ing it an excellent multi-project software development
tool.
15.6 MPLAB-ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is
inte nded to provi de t he pr oduc t developm ent en gin eer
with a complete microcontroller design tool set for
PICmicro microcontrollers (MCUs). Software control of
MPLAB-ICE is provided by the MPLAB Integrated
Developm ent Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different pro-
cessors. The universal arch itecture of the MPLAB-ICE
allows expansion to support new PICmicro microcon-
trollers.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced fea-
tures that are generally found on more expensive devel-
opment tools. The PC platf orm and Microsoft® Windows
3.x/95/98 en vironment w ere chosen to best mak e these
features available to you, the end user.
MPLAB-ICE 2000 is a full-featured emulator system
with enhanced trac e, trigger, and data monitoring fea-
tures. Both systems use the same processor modules
and will operate across the full operating speed range
of the PICmicro MCU.
15.7 PICMASTER/PICMASTER CE
The PICMASTER system from Microchip Technolog y is
a full-featured, professional quality emulator system.
This flexible in-circuit emulator provides a high-quality,
universal platform for emulating Microchip 8-bit
PICmicro microcontrollers (MCUs). PICMASTER sys-
tems are sold worldwide, with a CE compliant model
available for European Union (EU) countries.
15.8 ICEPIC
ICEPIC is a lo w-cost in-circ uit emula tion solution f o r the
Microchip Technology PIC16 C5X, PIC16C6X,
PIC16C7X, and PIC16CXXX fam ilies of 8-bit on e-time-
progr amma b le (OTP) microcontrollers . The modula r
system can suppo rt different subsets of PIC16C5X or
PIC16CXXX products through the use of
interchangeab le persona lity modules or daughter
boards. The em ulator is capable of emulating without
target application circuitry being present.
15.9 MPLAB-ICD In-Circuit Debugger
Microc hip’s In-C ircuit Deb ugger , MPLAB-ICD, is a pow -
erful, low-cost run-time development tool. This tool is
based on the flash PIC16F877 and can be used to
develop for this and other PICmicro microcontrollers
from the PIC16CXXX family. MPLAB-ICD utilizes the
In-Circuit Debugging capability built into the
PIC16F8 7X. This f eature, alon g with Microchip’ s In-C ir-
cuit Serial Programming protocol, offers cost-effective
in-circuit flash programming and debugging from the
graphical user interface of the MPLAB Integrated
Developm ent Environment. This enables a designer to
de velop and deb u g sourc e code by w atching variabl es ,
single-stepping and setting break points. Running at
full speed enables testing hardware in real-time. The
MPLAB-ICD is also a programmer for the flash
PIC16F87X family.
1999 Microchip Technology Inc. DS30605B-page 109
PIC16C63A/65B/73B/74B
15.10 PRO MATE II Universal Programmer
The PRO MATE II Universa l Programmer is a full-fea-
ture d programme r capable of operati ng in stand -alo ne
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memor y
at VDD min and VDD max for maximum reliability. It has
an LCD display for instructions and error messages,
keys to enter commands and a modular detachable
socket assembly to suppor t various package types. In
stand-al on e m ode the PRO MATE II can read, verify or
program PICmicro devices. It can also set code-protect
bits in this mode.
15.11 PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient.
PICSTART Pl us supp o rts all P ICmi cro device s wit h up
to 40 pins. Larger pin count devices such as the
PIC16C92X, and PIC17C76X may be supported with
an adapter socket. PICSTART Plus is CE compliant.
15.12 SIMICE Entry-Level
Hardwa re Simulator
SIMICE is an entry-level hardware development sys-
tem designed to operate in a PC-based environment
with Microchip’s simulator MPLAB-SIM. Both SIMICE
and MPLAB-SIM run under Microchip Technology’s
MPLAB Integrated Development Environment (IDE)
software. Specifically, SIMICE provides hardware sim-
ulation for Micro chip’s PIC12C5XX, PIC 12CE5 XX, an d
PIC16C5X families of PICmicro 8-bit microcontrollers.
SIMICE wor ks in conjunction with MPLAB-SIM to pro-
vide non- real-time I/O port emulation. SIMIC E ena bles
a developer to run simulator code for driving the target
system . In addition, the target system can provi de input
to the simulator code. This capability allows for simple
and interactive debugging without having to manually
generate MPLAB-SIM stimulus files. SIMICE is a valu-
able debugging tool for entry-level system develop-
ment.
15.13 PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board whic h demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and downl o a d t h e
firmware to the emulator for testing. Additional proto-
type area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
15.14 PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTAR T-Plus , and eas ily tes t firmware .
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional ha rdware and connectin g it to the mic rocontroll er
soc ket (s). Some of the f eatures include a RS-232 int er-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
usage of th e I2C bu s and separ ate hea ders f or connec -
tion to an LCD module and a keypad.
15.15 PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microc ont roll ers wi th a LCD Mo dul e . All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM -3 bo ard, on a P RO MAT E II pr ogra m-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firm-
ware. Addit ional protot ype a rea h as been provided to
the us er for adding ha rdware and con necti ng it to the
microcontroller sock et(s). Some of the f eatures inc lude
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a k e y pad. Als o pro vide d on th e PICDEM -3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the we ek . Th e PICDEM-3 provides an add i-
tional RS-232 interface and Windows 3.1 software for
showing the demultiple xed LCD signals on a PC. A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
PIC16C63A/65B/73B/74B
DS30605B-page 110 1999 Microchip Technology Inc.
15.16 PICDEM-17
The PICDEM-17 is an evaluation board that demon-
strates the capabilities of several Microchip microcon-
trollers, including PIC17C752, PIC17C756,
PIC17C762, and PIC17C766. All necessar y hardware
is incl uded to run bas ic demo prog rams, which are su p-
plied on a 3.5-inch disk. A programmed sample is
includ ed, and the us er ma y eras e it an d prog ram it wi th
the other sample programs using the PRO MATE II or
PICSTART Plus device programmers and easily debug
and test the sample code . In additio n, PICDEM-17 su p-
ports down-loa ding of progr ams to and e xec uting out of
e xt ernal FLASH memory on board. The PICD EM -17 i s
also usab le with th e MPL AB-ICE or PI CMASTER em u-
lator, and all of the sample programs can be run and
modified using either emulator. Additionally, a gener-
ous prototype area is available for user hardware.
15.17 SEEV AL Evaluation and Programming
System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes ever ything necessar y to read, write, eras e or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in trade-
off analy sis a nd relia bility calc ulatio ns . The tota l kit ca n
significantly reduce time-to-market and result in an
optimized system.
15.18 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microc hips HCS Secure D ata Product s. The HC S ev al-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
1999 Microchip Technology Inc. DS30605B-page 111
PIC16C63A/65B/73B/74B
TABLE 15-1: DEVELOPMENT TOOLS FROM MICROCHIP
PIC12CXXX
PIC14000
PIC16C5X
PIC16C6X
PIC16CXXX
PIC16F62X
PIC16C7X
PIC16C7XX
PIC16C8X
PIC16F8XX
PIC16C9XX
PIC17C4X
PIC17C7XX
PIC18CXX2
24CXX/
25CXX/
93CXX
HCSXXX
MCRFXXX
MCP2510
Soft w ar e To ol s
MPLABIntegrated
Develo pm en t Envi ro nm e nt
á
á
á
á
á
á
á
á
á
á
á
á
á
á
MPLAB C17 Compiler
á
á
MPLAB C18 Compiler
á
MPASM/MPLINK
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
Emulators
MPLAB™-ICE
á
á
á
á
á
á
**
á
á
á
á
á
á
á
á
PICMASTER/PICMASTER-CE
á
á
á
á
á
á
á
á
á
á
á
ICEPICLow-Cost
In-Circuit Emulator
á
á
á
á
á
á
á
á
Debugger
MPLAB-ICD In-Circuit Debugger
á
*
á
*
á
Programmers
PICSTARTPlus
Low-Cost Universal Dev. Kit
á
á
á
á
á
á
**
á
á
á
á
á
á
á
á
PRO MATE II
Universal Programmer
á
á
á
á
á
á
**
á
á
á
á
á
á
á
á
á
á
Demo Boards and Eval Kits
SIMICE
á
á
PICDEM-1
á
á
á
á
á
PICDEM-2
á
á
á
PICDEM-3
á
PICDEM-14A
á
PICDEM-17
á
KEELOQ® Evaluation Kit
á
KEELOQ Transponder Kit
á
microID™ Programmer’s Kit
á
125 kHz microID Developer’s Kit
á
125 kHz Anticollision microID
Developer’s Kit
á
13.56 MHz Anticollision microID
Developer’s Kit
á
MCP2510 CAN Developer’s Kit
á
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB-ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77
** Contact Microchip Technology Inc. for availability date.
Development tool is available on select devices.
PIC16C63A/65B/73B/74B
DS30605B-page 112 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. Preliminary DS30605B-page 113
PIC16C63A/65B/73B/74B
16.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature.............................................................................................................................. -65°C to +150°C
Voltage on any pin with res pect to VSS (except VDD, MCLR and RA4)...........................................-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) .........................................................................................0V to +13.25V
Voltage on RA4 with respect to Vss............................................................................................................... 0V to +8.5V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current i nto VDD pin..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................±20 mA
Maximu m out put current sunk by an y I/O pin................. ..... ............................ ............................ ............................25 mA
Maximu m out put current sourced by an y I/O pin ...................... ...... ..... ............................ .......................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (Note 3) (combined) ...................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined)..............................................200 mA
Maximum current sunk by PORTC and PORTD (Note 3) (combined)....... ............................ ..... ..........................200 mA
Maximum current sourced by PORTC and PORTD (Note 3) (combined).............................................................200 mA
Note 1: Power dissipation is calculated as fo llows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL)
2: Voltage s pi kes below VSS at the MCLR/VPP pin, in duc in g c urren ts greater than 80 mA, ma y cau se latch-up .
Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP pin rather
than pulling this pin directly to VSS.
3: PORTD an d PORTE not available o n the PIC16C63A/ 73B.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
de vic e. Th is is a s tress r ating o nly and functional oper atio n of the device at those or an y o ther cond itions abo v e thos e
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
PIC16C63A/65B/73B/74B
DS30605B-page 114 Preliminary 1999 Microchip Technology Inc.
FIGURE 16-1: PIC16C63A/65B/73B/74B VOLTAGE-FREQUENCY GRAPH
FIGURE 16-2: PIC16LC63A/65B/73B/74B VOLTAGE-FREQUENCY GRAPH
Frequency
Voltage
6.0 V
5.5 V
4.5 V
4.0 V
2.0 V
20 MHz
5.0 V
3.5 V
3.0 V
2.5 V
PIC16CXXX-20
Frequency
Voltage
6.0 V
5.5 V
4.5 V
4.0 V
2.0 V
5.0 V
3.5 V
3.0 V
2.5 V
FMAX = (12.0 MHz/V) (VDDAPPMIN - 2.5 V) + 4 MHz
Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
4 MHz 10 MHz
Note 2: FMAX has a maximum frequency of 10MHz.
PIC16LCXXX-04
1999 Microchip Technology Inc. Preliminary DS30605B-page 115
PIC16C63A/65B/73B/74B
FIGURE 16-3: PIC16C63A/65B/73B/74B VOLTAGE-FREQUENCY GRAPH
Frequency
Voltage
6.0 V
5.5 V
4.5 V
4.0 V
2.0 V
5.0 V
3.5 V
3.0 V
2.5 V
PIC16CXXX-04
4 MHz
PIC16C63A/65B/73B/74B
DS30605B-page 116 Preliminary 1999 Microchip Technology Inc.
16.1 DC Characteristics: PIC16C63A/65B/73B/74B-04 (Commercial, Industrial, Extended)
PIC16C6A/65B/73B/74B-20 (Commercial, Industrial, Extended)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C TA +70°C for commercial
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Sym Characteristic Min Typ† Max Units Conditions
D001
D001A VDD Supply Voltage 4.0
4.5
VBOR*
5.5
5.5
5.5
V
V
V
XT, RC and LP osc mode
HS osc mode
BOR enabled (Note 7)
D002* VDR RAM Data Retention
Voltage (Note 1) 1.5 V
D003 VPOR VDD Start Voltage to
ens ure internal
Power-on Reset signal
VSS V See section on Power-on Reset for details
D004*
D004A* SVDD VDD Rise Rate to
ens ure internal
Power-on Reset signal
0.05
TBD
V/mS
V/mS PWRT enabled (PWRTE bit clear)
PWRT disabled (PWRTE bit set)
See section on Power-on Reset for details
D005 VBOR Bro w n-out Rese t
voltage trip point 3.65 4.35 V BODEN bit set
D010
D013
IDD Supply Current
(Note 2, 5)
2.7
10
5
20
mA
mA
XT, RC osc modes
FOSC = 4 MHz, VDD = 5.5V (Note 4)
HS osc mode
FOSC = 20 MHz, VDD = 5.5V
D020
D021
D021B
IPD Power-down Current
(Note 3, 5)
10.5
1.5
1.5
2.5
42
16
19
19
µA
µA
µA
µA
VDD = 4.0V, WDT enabled,-40°C to +85°C
VDD = 4.0V, WDT disabled, 0°C to +70°C
VDD = 4.0V, WDT disabled, -40°C to +85°C
VDD = 4.0V, WDT disabled, -40°C to +125°C
D022*
D022A* IWDT
IBOR
Module Differential
Current (Note 6)
Watchdog Timer
Brown-out Reset
6.0
100 20
150 µA
µAWDTE bit set, VDD = 4.0V
BODEN bit set, VDD = 5.0V
* These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating volt age and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, inter nal code execution pattern and temperature also have an impact on the current con-
sumption.
The test conditions for all IDD measurements in active oper ati on mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by the formula
Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds appro x imately 20 µA to the specification. This value is from characterization and is
for design guidance only. This is not tested.
6: The current is the additional current consumed when this peripheral is enabled. This current should be added to the
base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
1999 Microchip Technology Inc. Preliminary DS30605B-page 117
PIC16C63A/65B/73B/74B
16.2 DC Characteristics: PIC16LC63A/65B/73B/74B-04 (Commercial, Industrial)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C TA +70°C for commercial
-40°C TA +85°C for industrial
Param
No. Sym Characteristic Min Typ† Max Units Conditions
D001 VDD Supply Voltage 2.5
VBOR*
5.5
5.5 V
VLP, XT, RC osc modes (DC - 4 MHz)
BOR enabled (Note 7)
D002* VDR RAM Data Retention
Voltage (Note 1) 1.5 V
D003 VPOR VDD Start Voltage to
ens ure internal
Power-on Reset signal
VSS V See section on Power-on Reset for details
D004*
D004A* SVDD VDD Rise Rate to
ens ure internal
Power-on Reset signal
0.05
TBD
V/mS
V/mS PWRT enabled (PWRTE bit clear)
PWRT disabled (PWRTE bit set)
See section on Power-on Reset for details
D005 VBOR Bro w n-out Rese t
voltage trip point 3.65 4.35 V BODEN bit set
D010
D010A
IDD Supply Current
(Note 2, 5)
2.0
22.5
3.8
48
mA
µA
XT, RC osc modes
FOSC = 4 MHz, VDD = 3.0V (Note 4)
LP osc mode
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D020
D021
D021A
IPD Power-down Current
(Note 3, 5)
7.5
0.9
0.9
30
5
5
µA
µA
µA
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
D022*
D022A* IWDT
IBOR
Module Differential
Current (Note 6)
Watchdog Timer
Brown-out Reset
6.0
100 20
150 µA
µAWDTE bit set, VDD = 4.0V
BODEN bit set, VDD = 5.0V
*These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating volt age and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, inter nal code execution pattern and temperature also have an impact on the current con-
sumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down curr ent in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by the formula
Ir = VDD/2Rext (m A) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds appro x imately 20 µA to the specification. This value is from characterization and is
for design guidance only. This is not tested.
6: The current is the additional current consumed when this peripheral is enabled. This current should be added to the
base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
PIC16C63A/65B/73B/74B
DS30605B-page 118 Preliminary 1999 Microchip Technology Inc.
16.3 DC Characteristics: PIC16C63A/65B/73B/74B-04 (Commercial, Industrial, Extended)
PIC16C63A /65B/73B/74B-20 (Com mercial, Industrial, Extended)
PIC16LC63A/65B/73B/74B-04 (Commercial, Industrial)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature C TA +70°C for commercial
-40°C TA +85°C for industria l
-40°C TA +125°C for extended
Operating voltage VDD range as described in DC spec Section 16.1
and Sect ion 16.2
Param
No. Sym Characteristic Min Typ† Max Units Conditions
Input Low Voltage
VIL I/O ports
D030
D030A with TTL buffer VSS
VSS -
-0.15VDD
0.8V V
VFor entire VDD range
4.5V VDD 5.5V
D031 with Schmitt Trigger buffer VSS -0.2VDD V
D032 MCLR, OSC1 (in RC mode) Vss - 0.2VDD V
D033 OSC1 (in XT, HS and LP
modes) Vss - 0.3VDD VNote 1
Input High Voltage
VIH I/O ports -
D040 with TTL buffer 2.0 - VDD V4.5V VDD 5.5V
D040A 0.25VDD + 0.8V - VDD V For entire VDD range
D041 with Schmitt Trigger buffer 0.8VDD -VDD V For entire VDD range
D042 MCLR 0.8VDD -VDD V
D042A OSC1 (XT, HS and LP modes) 0.7VDD -VDD VNote 1
D043 OSC1 (in RC mode) 0.9VDD -VDD V
Input Leakage Current
(Notes 2, 3)
D060 IIL I/O ports - - ±1µAVss VPIN VDD,
Pin at hi-impedance
D061 MCLR, RA4/T0CKI - - ±5µAVss VPIN VDD
D063 OSC1 - - ±5µAVss VPIN VDD,
XT, HS and LP osc modes
D070 IPURB PORT B weak pull-up current 50 250 400 µAVDD = 5V, VPIN = VSS
*These parameters are character ized but not t est ed.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be
driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels repre-
sent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
1999 Microchip Technology Inc. Preliminary DS30605B-page 119
PIC16C63A/65B/73B/74B
DC Characteristics: PIC16C63A/65B/73B/74B-04 (Commercial, Industrial, Extended)
PIC16C63A /65B/73B/74B-20 (Com mercial, Industrial, Extended)
PIC16LC63A/65B/73B/74B-04 (Commercial, Industrial) (CONTINUED)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C TA +70°C for comm erc ial
-40°C TA +85°C for industrial
-40°C TA +125°C for e x ten ded
Operating voltage VDD range as described in DC spec
Section 16.1 and Section 16.2
Param
No. Sym Characteristic Min Typ† Max Units Conditions
Output Low Voltage
D080 VOL I/O ports - - 0.6 V IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
--0.6VIOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
D083 OSC2/CLKOUT (RC osc mode) - - 0.6 V IOL = 1.6 mA , VDD = 4.5V,
-40°C to +85°C
--0.6VIOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
Output High Voltage
D090 VOH I/O ports (Note 3) VDD-0.7 - - V IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
VDD-0.7 - - V IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
D092 OSC2/CLKOUT (RC osc mode) VDD-0.7 - - V IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
VDD-0.7 - - V IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
D150* VOD Open-Drain High Voltage - - 8.5 V RA4 pin
Capacitive Loading Specs on
Output Pins
D100 COSC2 OSC2 pin - - 15 pF In XT, HS and LP modes
when external clock is used to
drive OSC 1 .
D101 CIO All I/O pins and OSC2 (in RC mode) - - 50 pF
D102 Cb SCL, SDA in I2C mode --400pF
*These parameters are character ized but not t est ed.
Data in “Typ” column is at 5V, 25°C unle ss other wise s tated. These pa rame ters are f or desi gn guid ance o nly an d are not teste d.
Note 1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be
driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels repre-
sent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
PIC16C63A/65B/73B/74B
DS30605B-page 120 Preliminary 1999 Microchip Technology Inc.
16.4 AC (Timing) Characteristics
16.4.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
TFFrequency TTime
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppe rcase letters and their meanings:
SFFall PPeriod
HHigh RRise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-impedance
I2C only
AA output access High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT DATA input hold STO STOP condition
STA START condition
1999 Microchip Technology Inc. Preliminary DS30605B-page 121
PIC16C63A/65B/73B/74B
16.4.2 TIMING CONDITIONS
The temperature and voltages specified in Table 16-1
apply to all timing specifications unless otherwise
noted. Figure 16-4 specifies the load conditions for the
timing specification s .
TABLE 16-1: TEMPERATURE AND VOLTA GE SPECIFICATIONS - AC
FIGURE 16-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C TA +70° C for commercial
-40°C TA +85°C for i ndustr ial
-40°C TA +125°C for extended
Operating voltage VDD range as described in DC spec Section 16.1 and
Section 16.2. LC parts operate for commercial/i ndustrial temperatures only.
VDD/2
CL
RL
Pin
Pin
VSS
VSS
CL
RL= 464
CL= 50 pF for all pins except OSC2/CLKOUT
but including D and E outputs as ports
CL= 15 pF for OS C2 output
Load condition 1 Load condition 2
Note 1: PORTD and PORTE are not implemented on the PIC16C63A/73B.
PIC16C63A/65B/73B/74B
DS30605B-page 122 Preliminary 1999 Microchip Technology Inc.
16.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 16-5: EXTERNAL CLOCK TIMING
TABLE 16-2: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
1A Fosc External C LKIN Frequency
(Note 1) DC 4 MHz RC and XT osc modes
DC 4 MHz HS osc mode (- 04)
DC 20 MHz HS osc mode (-20)
DC 200 kHz LP osc mode
Oscilla tor Frequency
(Note 1) DC 4 MHz RC o sc mode
0.1 4 MHz XT osc mode
4 20 MHz HS osc mode
5 200 kHz LP osc mode
1Tosc External CLKIN Period
(Note 1) 250 ns RC and XT osc modes
250 ns HS osc mode (-04)
50 ns HS osc mode (-20)
5— µsLP osc mode
Oscilla tor Period
(Note 1) 250 ns RC osc mode
250 10,000 ns XT osc mod e
250 250 ns HS osc mode (-04)
50 250 ns HS osc mode (-20)
5— µsLP osc mode
2TCY Instruction Cycle Time (Note 1) 200 DC ns TCY = 4/FOSC
3* TosL,
TosH External Clock in (OSC 1) Hig h or
Low Time 100 ns XT oscillator
2.5 µs LP oscillator
15 ns HS oscillator
4* TosR,
TosF External Clock in (OSC1) Rise or
Fall Time 25 ns XT osc il la tor
50 ns LP oscillator
15 ns HS oscilla tor
* These parameters are characterized but not tested.
†Data in “Ty p” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Ins truc tion cyc le period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device e xecuting code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI N pin. When
an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) f or all devices.
3
344
1
2
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
CLKOUT
1999 Microchip Technology Inc. Preliminary DS30605B-page 123
PIC16C63A/65B/73B/74B
FIGURE 16-6: CLKOUT AND I/O TIMING
TABLE 16-3: CLK OUT AND I/O TIMING REQUIREMENTS
Param
No. Sym Characteristic Min Typ Max Units Conditions
10* TosH2ckL OSC1 to CLKOUT 75 200 ns Note 1
11* TosH2ckH OSC1 to CLKOUT 75 200 ns Note 1
12* TckR CLKO UT rise time 35 100 ns Note 1
13* TckF CLKOUT fall time 35 100 ns Note 1
14* TckL2ioV CLKOUT to Port out valid 0.5TCY + 20 ns Note 1
15* TioV2ckH Port in valid before CLKOUT Tosc + 200 ns Note 1
16* TckH2ioI Port in hold after CLKOUT 0—nsNote 1
17* TosH2ioV OSC1 (Q1 cycle) to Port out valid 50 150 ns
18* TosH2ioI OSC1 (Q2 cycle) to P o rt
input invalid (I/O in hold
time)
PIC16CXX 100 ns
18A* PIC16LCXX 200 ns
19* TioV2osH Port input valid to OSC1(I/O in setup
time) 0—ns
20* TioR Port out put rise time PIC16CXX 10 40 ns
20A* PIC16LCXX 80 ns
21* TioF Port output fall time PIC16CXX 10 40 ns
21A* PIC16LCXX 80 ns
22††* Tinp INT pin high or low time TCY ——ns
23††* Trbp RB7:RB4 change INT high or low time TCY ——ns
* These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
††These parameters are asynchronous events not related to any internal clock edge.
Note 1: Measur ements are taken in RC Mode where CLKOUT output is 4 x TOSC.
Note: Refer to Figur e 16-4 for load conditions.
OSC1
CLKOUT
I/O Pin
(input)
I/O Pin
(output)
Q4 Q1 Q2 Q3
10
13 14
17
20, 21
19 18
15
11
12
16
old value new value
PIC16C63A/65B/73B/74B
DS30605B-page 124 Preliminary 1999 Microchip Technology Inc.
FIGURE 16-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
FIGURE 16-8: BROWN-OUT RESET TIMING
TABLE 16-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
30 TmcL MCLR Pulse Width (low) 2 ——µsVDD = 5V, -40°C to +125°C
31* Twdt Watchdog Timer Time -out
Period (No Prescaler) 71833msVDD = 5V, -40°C to +125°C
32 Tost Oscillation Start-up Timer
Period 1024
TOSC ——TOSC = OSC1 period
33* Tpwrt Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +125°C
34 TIOZ I/O Hi-impedance from
MCLR Low or WDT reset ——2.1µs
35 TBOR Brown-out Res et Pu lse
Width 100 µsVDD BVDD (D005)
* These parameters are character i zed but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are f or design guidance only and are not tested.
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
33
32
30
31
34
I/O Pins
34
Note: Refer to Figure 16-4 for load conditions.
VDD BVDD
35
1999 Microchip Technology Inc. Preliminary DS30605B-page 125
PIC16C63A/65B/73B/74B
FIGURE 16-9: TIME R0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 16-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 ns Must also meet
parameter 42
With Prescaler 10 ns
41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 ns Must also meet
parameter 42
With Prescaler 10 ns
42* Tt0P T0CKI Period No Prescaler TCY + 40 ns
With Prescaler Gr eater of:
20 or TCY + 40
N
ns N = prescale value
(2, 4,..., 256)
45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5T CY + 20 ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
PIC16CXX 15 ns
PIC16LCXX 25 ns
Asynchronous PIC16CXX 30 ns
PIC16LCXX 50 ns
46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0. 5TCY + 20 ns Mus t also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
PIC16CXX 15 ns
PIC16LCXX 25 ns
Asynchronous PIC16CXX 30 ns
PIC16LCXX 50 ns
47* Tt1P T1CKI input
period Synchronous PIC16CXX Greater of:
30 OR TCY + 40
N
ns N = prescale value
(1, 2, 4, 8)
PIC16LCXX Greater of:
50 OR TCY + 40
N
N = prescale value
(1, 2, 4, 8)
Asynchronous PIC16CXX 60 ns
PIC16LCXX 100 ns
Ft1 Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN) DC — 200 kHz
48 TCKEZtmr1 Delay from external clock edge to t imer increm ent 2Tosc 7Tosc
* These parameters are characterized but not tested.
Data i n “Typ” co lum n i s at 5V, 25°C un l ess ot her wi se s tat ed . T hes e pa r ameters are for de sig n gui da nce on l y an d ar e not te st ed .
Note: Refer to Figure 16-4 for load conditions.
46
47
45
48
41
42
40
T0CKI
T1OSO/T1CKI
TMR0 or
TMR1
PIC16C63A/65B/73B/74B
DS30605B-page 126 Preliminary 1999 Microchip Technology Inc.
FIGURE 16-10: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
TABLE 16-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Param
No. Sym Characteristic Min Typ† Max Units Conditions
50* TccL CCP1 and CCP2
input low time No Prescaler 0.5TCY + 20 ——ns
With Presca ler PIC16CXX 10 ns
PIC16LCXX 20 ns
51* TccH CCP1 and CCP2
input high time No Prescaler 0.5TCY + 20 ns
With Presca ler PIC16CXX 10 ns
PIC16LCXX 20 ns
52* TccP CCP1 and CCP2 input period 3TCY + 40
N ns N = prescal e
value (1,4, or
16)
53* TccR CCP1 and CCP2 output rise
time PIC16CXX 10 25 ns
PIC16LCXX 25 45 ns
54* TccF CCP1 and CCP2 output fall time PIC16CXX 10 25 ns
PIC16LCXX 25 45 ns
* These parameters are character i zed but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note: Refe r to Figure 16-4 for load conditions.
CCPx
(Capture Mode)
50 51
52
CCPx
53 54
(Compare or PWM Mode)
1999 Microchip Technology Inc. Preliminary DS30605B-page 127
PIC16C63A/65B/73B/74B
FIGURE 16-11: PARALLEL SLAVE PORT TIMING (PIC16C65B/74B)
TABLE 16-7: P ARALLEL SLAVE PORT REQUIREMENTS (PIC16C65B/74B)
Param No. Sym Characteristic Min Typ† Max Units Conditions
62* TdtV2wrH Data in valid before WR or CS (setup tim e) 20 ——ns
63* TwrH2dtI WR or CS to data–in
invalid (hold time) PIC16CXX 20 ns
PIC16LCXX 35 ns
64 TrdL2dtV RD and CS to data–out valid 80 ns
65* TrdH2dtI RD or CS to data–out invalid 10 30 ns
*These parameters are character ized but not t est ed.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note: Refer to Figure 16-4 for load conditions.
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
62
63
64
65
PIC16C63A/65B/73B/74B
DS30605B-page 128 Preliminary 1999 Microchip Technology Inc.
FIGURE 16-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
TABLE 16-8: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
70 TssL2scH,
TssL2scL SS to SCK or SCK inp ut TCY ——ns
71 TscH SCK input high time
(slave mode) Continuous 1.25TCY + 30 ns
71A Single Byte 40 ns Note 1
72 TscL SCK input low time
(slave mode) Continuous 1.25TCY + 30 ns
72A Single Byte 40 ns Note 1
73 TdiV2scH ,
TdiV2scL Setup time of SDI data input to SCK edge 100 ns
73A TB2BLast clock edge of Byte1 to the 1st clock
edge of Byte2 1.5TCY + 40 ns Note 1
74 TscH2diL,
TscL2diL Hold time of SDI data input to SCK edge 100 ns
75 TdoR SDO data output rise time PIC16CXX 10 25 ns
PIC16LCXX 20 45 ns
76 TdoF SDO data output fa ll time 10 25 ns
78 TscR SCK output rise time
(master mo de) PIC16CXX 10 25 ns
PIC16LCXX 20 45 ns
79 TscF SCK output fall time (master mode) 10 25 ns
80 TscH2doV,
TscL2doV SDO data output valid
after SCK edge PIC16CXX 50 ns
PIC16LCXX 100 ns
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76
78
79
80
79
78
MSb LSb
BIT6 - - - - - -1
MSb IN LSb IN
BIT6 - - - -1
Note: Refer to Figure 16-4 for load conditions.
1999 Microchip Technology Inc. Preliminary DS30605B-page 129
PIC16C63A/65B/73B/74B
FIGURE 16-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
TABLE 16-9: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
71 TscH SCK input high time
(slave mode) Continuous 1.25TCY + 30 ——ns
71A Single Byte 40 ns Note 1
72 TscL SCK input low time
(slave mode) Continuous 1.25TCY + 30 ns
72A Single Byte 40 ns Note 1
73 TdiV2scH,
TdiV2scL Setup time of SDI data input to SCK
edge 100 ns
73A TB2BLast clock edge of Byte1 to the 1st clock
edge of Byte2 1.5TCY + 40 ns Note 1
74 TscH2diL,
TscL2diL Hold time of SDI data input to SCK edge 100 ns
75 TdoR SDO data output rise
time PIC16CXX 10 25 ns
PIC16LCXX 20 45 ns
76 TdoF SDO data output fall time 10 25 ns
78 TscR SCK output rise time
(master mo de) PIC16CXX 10 25 ns
PIC16LCXX 20 45 ns
79 TscF SCK output fall time (master mode) 10 25 ns
80 TscH2doV,
TscL2doV SDO data output valid
after SCK edge PIC16CXX 50 ns
PIC16LCXX 100 ns
81 TdoV2scH,
TdoV2scL SDO data output setup to SCK edge TCY ——ns
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb IN
BIT6 - - - - - -1
LSb IN
BIT6 - - - -1
LSb
Note: Refer to Figure 16-4 for load conditions.
PIC16C63A/65B/73B/74B
DS30605B-page 130 Preliminary 1999 Microchip Technology Inc.
FIGURE 16-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
TABLE 16-10: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
70 TssL2scH,
TssL2scL SS to SCK or SCK inp ut TCY ——ns
71 TscH SCK input high time
(slave mode) Continuous 1.25TCY + 30 ns
71A Single Byte 40 ns Note 1
72 TscL SCK input low time
(slave mode) Continuous 1.25TCY + 30 ns
72A Single Byte 40 ns Note 1
73 TdiV2scH,
TdiV2scL Setup time of SDI data input to SCK edge 100 ns
73A TB2BLast clock edge of Byte1 to the 1st clock
edge of Byte2 1.5TCY + 40 ns Note 1
74 TscH2diL,
TscL2diL Hold time of SDI data input to SCK edge 100 ns
75 TdoR SDO data output rise time PIC16CXX 10 25 ns
PIC16LCXX 20 45 ns
76 TdoF SDO data output fa ll time 10 25 ns
77 TssH2doZ SS to SDO output hi-impedance 10 50 ns
78 TscR SCK output rise time
(master mo de) PIC16CXX 10 25 ns
PIC16LCXX 20 45 ns
79 TscF SCK output fall time (master mode) 10 25 ns
80 TscH2doV,
TscL2doV SDO data output valid
after SCK edge PIC16CXX 50 ns
PIC16LCXX 100 ns
83 TscH2ssH,
TscL2ssH SS after SCK edge 1.5TCY + 40 ns
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76 77
78
79
80
79
78
SDI
MSb LSb
BIT6 - - - - - -1
MSb IN BIT6 - - - -1 LSb IN
83
Note: Refer to Figure 16-4 for load condit ions.