 
  
FEATURES
APPLICATIONS
DESCRIPTION
Lch In
Rch In Analog Front-End Delta-Sigma
Modulator
Digital
Decimation
Filter Serial Interface
and
Mode Control
Digital Out
Mode Control
System Clock
B0006-03
Digital In
Digital
Interpolation
Filter
Lch Out
Rch Out
Low-Pass Filter
and
Output Buffer
Multilevel
Delta-Sigma
Modulator
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
18-BIT STEREO AUDIO CODEC, SINGLE-ENDED ANALOG INPUT/OUTPUT
•Single 5-V Power Supply•Monolithic 18-Bit ∆ Σ ADC and DAC
•Small Package: SSOP-28•16- or 18-Bit Input/Output Data•Accepts Seven Alternate Formats
•Sampling Keyboards•Stereo ADC:
•Digital Mixers– Single-Ended Voltage Input
•Mini-Disk Recorders– 64 ×Oversampling Digital Filter
•Hard-Disk Recorders•Pass-Band Ripple: ±0.05 dB
•Karaoke Systems•Stop-Band Attenuation: –65 dB
•DSP-Based Car Stereo– High Performance:
•DAT Recorders•THD+N: –88 dB
•Video Conferencing•SNR: 94 dB•Dynamic Range: 94 dB– Digital High-Pass Filter The PCM3000/3001 is a low-cost, single-chip stereoaudio codec (analog-to-digital and digital-to-analog•Stereo DAC
converter) with single-ended analog voltage input and– Single-Ended Voltage Outut
output.– Analog Low-Pass Filter
Both ADCs and DACs employ delta-sigma modu-– 8 ×Oversampling Digital Filter
lation with 64-times oversampling. The ADCs include•Pass-Band Ripple: ±0.17 dB a digital decimation filter and the DACs include an8-times oversampling digital interpolation filter. The•Stop-Band Attenuation: 35 dB
DACs also include digital attenuation, de-emphasis,– High Performance:
infinite zero detection and soft mute to form a•THD+N: –90 dB
complete subsystem. The PCM3000/3001 operateswith left-justified, right-justified, I
2
S or DSP data•SNR: 98 dB
formats.•Dynamic Range: 97 dB
The PCM3000 can be programmed with a three-wire•Special Features (PCM3000)
serial interface for special features and data formats.– Digital De-Emphasis
The PCM3001 can be pin-programmed for data– Digital Attenuation (256 Steps)
formats.– Soft Mute
The PCM3000 and PCM3001 are fabricated using a– Digital Loopback highly advanced CMOS process and are available ina small 28-pin SSOP package. The PCM3000/3001•Sample Rate: 4 kHz to 48 kHz
are suitable for a wide variety of cost-sensitive•System Clock: 256 f
s
, 384 f
s
, 512 f
s
consumer applications where good performance isrequired.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.System Two, Audio Precision are trademarks of Audio Precision, Inc.All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ELECTRICAL CHARACTERISTICS
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integratedcircuits be handled with appropriate precautions. Failure to observe proper handling and installationprocedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precisionintegrated circuits may be more susceptible to damage because very small parametric changes couldcause the device not to meet its published specifications.
All specifications at T
A
= 25 °C, V
DD
= V
CC
= 5 V, f
S
= 44.1 kHz, SYSCLK = 384 f
S,
CLKIO input, and 18-bit data, unlessotherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUT/OUTPUT
Input Logic
V
IH
(1)
2Input logic level VDCV
IL
(1)
0.8I
IN
(2)
±1Input logic current µAI
IN
(3)
–120V
IH
(4)
0.64 V
DD
VDCInput logic levelV
IL
(4)
0.28 V
DD
I
IN
(4)
Input logic current ±40 µA
Output Logic
V
OH
(5)
I
OUT
= –1.6 mA 4.5Output logic levelV
OL
(5)
I
OUT
= 3.2 mA 0.5
VDCV
OH
(6)
I
OUT
= –3.2 mA 4.5Output logic levelV
OL
(6)
I
OUT
= 3.2 mA 0.5
Clock Frequency
f
S
Sampling frequency 4
(7)
44.1 48 kHz256 f
S
1.024 11.2896 12.288System clock frequency 384 f
S
1.536 16.9344 18.432 MHz512 f
S
2.048 22.5792 24.576
ADC CHARACTERISTICS
Resolution 18 Bits
DC Accuracy
Gain mismatch, channel-to-channel ±1±5
% of FSRGain error ±2±5Gain drift ±20 ppm of FSR/ °CBipolar zero error High-pass filter off
(8)
±1.7 % of FSRBipolar zero drift High-pass filter off
(8)
±20 ppm of FSR/ °C
(1) Pins 16, 17, 18, 22, 25, 26, 27, 28: LRCIN, BCKIN, DIN, CLKIO, MC/FMT2, MD/FMT1, ML/FMT0, RSTB(2) Pins 16, 17, 18, 22: LRCIN, BCKIN, DIN, CLKIO (Schmitt-trigger input)(3) Pins 25, 26, 27, 28: MC/FMT2, MD/FMT1, ML/FMT0, RSTB (Schmitt-trigger input, 70-k Ωinternal pullup resistor)(4) Pin 20: XTI(5) Pins 19, 22: DOUT, CLKIO(6) Pin 21: XTO(7) Refer to Application Bulletin SBAA033 for information relating to operation at lower sampling frequencies.(8) High-pass filter disabled (PCM3000 only) to measure dc offset
2
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PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS (continued)All specifications at T
A
= 25 °C, V
DD
= V
CC
= 5 V, f
S
= 44.1 kHz, SYSCLK = 384 f
S,
CLKIO input, and 18-bit data, unlessotherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Dynamic Performance
(9)
f = 1 kHz, V
IN
= –0.5 dB –88 –80THD+N dBf = 1 kHz, V
IN
= –60 dB –31Dynamic range f = 1 kHz, A-weighted 90 94 dBSignal-to-noise ratio f = 1 kHz, A-weighted 90 94 dBChannel separation 88 92 dB
Digital Filter Performance
Pass band 0.454 f
S
HzStop band 0.583 f
S
HzPass-band ripple ±0.05 dBStop-band attenuation –65 dBDelay time (latency) 17.4/f
S
s
Digital High-Pass Filter Response
Cutoff frequency –3 dB 0.019 f
S
mHz
ANALOG INPUT
Voltage range 0 dB (full scale) 2.9 Vp-pCenter voltage 2.1 VDCInput impedance 15 k Ω
Antialiasing Filter
Cutoff frequency –3 dB, C
EXT
= 470 pF 170 kHz
DAC CHARACTERISTICS
Resolution 18 Bits
DC Accuracy
Gain mismatch, channel-to-channel ±1±5 % of FSRGain error ±1±5 % of FSRGain drift ±20 ppm of FSR/ °CBipolar zero error ±1 % of FSRBipolar zero drift ±20 ppm of FSR/ °C
Dynamic Performance
(9)
V
OUT
= 0 dB (full scale) –90 –80THD+N dBV
OUT
= –60 dB –34Dynamic range EIAJ A-weighted 90 97 dBSignal-to-noise ratio (idle channel) EIAJ A-weighted 92 98 dBChannel separation 90 95 dB
Digital Filter Performance
Pass band 0.445 f
S
HzStop band 0.555 f
S
HzPass-band ripple ±0.17 dBStop-band attenuation –35 dBDelay time 11.1/f
S
s
(9) f
IN
= 1 kHz, using the System Two™ audio measurement system by Audio Precision™, rms mode with 20-kHz LPF, 400-Hz HPFused for performance calculation or measurement.
3
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ABSOLUTE MAXIMUM RATINGS
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS (continued)All specifications at T
A
= 25 °C, V
DD
= V
CC
= 5 V, f
S
= 44.1 kHz, SYSCLK = 384 f
S,
CLKIO input, and 18-bit data, unlessotherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Analog Output
Voltage range 0.62 V
CC
Vp-pCenter voltage 0.5 V
CC
VDCLoad impedance AC load 5 k Ω
Analog Low-Pass Filter
Frequency response f = 20 kHz –0.16 dB
POWER SUPPLY REQUIREMENTS
V
CC
4.5 5 5.5 VDCVoltage rangeV
DD
4.5 5 5.5 VDCI
CC
, I
DD
(10)
Supply current V
CC
= V
DD
= 5 V 32 50 mAPower dissipation V
CC
= V
DD
= 5 V 160 250 mW
TEMPERATURE RANGE
T
A
Operation –25 85 °CT
stg
Storage –55 125 °Cθ
JA
Thermal resistance 100 °C/W
(10) With no load on XTO and CLKIO
PACKAGE/ORDERING INFORMATION
PACKAGE PACKAGE ORDERING TRANSPORTPRODUCT PACKAGE QUANTITYCODE MARKING NUMBER MEDIA
PCM3000E Rails 47PCM3000E PCM3000E
PCM3000E/2K Tape and reel 200028-pin SSOP DB
PCM3001E Rails 47PCM3001E PCM3001E
PCM3001E/2K Tape and reel 2000
over operating free-air temperature range (unless otherwise noted)
Supply voltage: V
DD
, V
CC
1, V
CC
2 –0.3 V to 6.5 VSupply voltage differences ±0.1 VGND voltage differences ±0.1 VDigital input voltage –0.3 to V
DD
+ 0.3 V, < 6.5 VAnalog input voltage –0.3 to V
CC
1, V
CC
2 + 0.3 V, < 6.5 VPower dissipation 300 mWInput current (any pins except supplies) ±10 mAOperating temperature –25 °C to 85 °CStorage temperature –55 °C to 125 °CLead temperature, soldering 260 °C, 5 sPackage temperature (IR reflow, peak) 235 °C
4
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RECOMMENDED OPERATING CONDITIONS
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Analog supply voltage, V
CC
1, V
CC
2 4.5 5 5.5 VDCDigital supply voltage, V
DD
4.5 5 5.5 VDCAnalog input voltage, full scale (–0 dB) 2.9 Vp-pDigital input logic family TTLSystem clock 8.192 24.576 MHzDigital input clock frequency
Sampling clock 32 48 kHzAnalog output load resistance 5 k ΩAnalog output load capacitance 50 pFDigital output load capacitance 10 pFOperating free-air temperature, T
A
–25 85 °C
5
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VINL
VCC1
AGND1
VREFL
VREFR
VINR
CINPR
CINNR
CINNL
CINPL
VCOM
VOUTR
AGND2
VCC2
RSTB
ML
MD
MC
DGND
VDD
CLKIO
XTO
XTI
DOUT
DIN
BCKIN
LRCIN
VOUTL
PCM3000
(TOP VIEW)
P0007-01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VINL
VCC1
AGND1
VREFL
VREFR
VINR
CINPR
CINNR
CINNL
CINPL
VCOM
VOUTR
AGND2
VCC2
RSTB
FMT0
FMT1
FMT2
DGND
VDD
CLKIO
XTO
XTI
DOUT
DIN
BCKIN
LRCIN
VOUTL
PCM3001
(TOP VIEW)
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
PIN CONFIGURATION—PCM3000/3001
PIN ASSIGNMENTS—PCM3000
NAME PIN I/O DESCRIPTION
AGND1 3 – ADC analog groundAGND2 13 – DAC analog groundBCKIN 17 I Bit clock input
(1)
C
IN
NL 9 – ADC antialias filter capacitor (–), LchC
IN
NR 8 – ADC antialias filter capacitor (–), RchC
IN
PL 10 – ADC antialias filter capacitor (+), LchC
IN
PR 7 – ADC antialias filter capacitor (+), RchCLKIO 22 I/O Buffered oscillator output or external clock input
(1)
DGND 24 – Digital groundDIN 18 I Data input
(1)
DOUT 19 O Data outputLRCIN 16 I Sample rate clock input (f
S
)
(1)
MC 25 I Serial mode control, bit clockMD 26 I Serial mode control, dataML 27 I Serial mode control, strobe pulseRSTB 28 I Reset, active-low
(1) (2)
V
CC
1 2 – ADC analog power supplyV
CC
2 14 – DAC analog power supplyV
DD
23 – Digital power supplyVCOM 11 – DAC output commonV
IN
L 1 I ADC analog input, LchV
IN
R 6 I ADC analog input, RchV
OUT
L 15 O DAC analog output, LchV
OUT
R 12 O DAC analog output, RchV
REF
L 4 – ADC input reference, LchV
REF
R 5 – ADC input reference, Rch
(1) Schmitt-trigger input(2) With 70-k Ωtypical internal pullup resistor
6
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PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
PIN ASSIGNMENTS—PCM3000 (continued)
NAME PIN I/O DESCRIPTION
XTI 20 I Oscillator inputXTO 21 O Oscillator output
PIN ASSIGNMENTS—PCM3001
NAME PIN I/O DESCRIPTION
AGND1 3 – ADC analog groundAGND2 13 – DAC analog groundBCKIN 17 I Bit clock input
(1)
C
IN
NL 9 – ADC antialias filter capacitor (–), LchC
IN
NR 8 – ADC antialias filter capacitor (–), RchC
IN
PL 10 – ADC antialias filter capacitor (+), LchC
IN
PR 7 – ADC antialias filter capacitor (+), RchCLKIO 22 I/O Buffered oscillator output or external clock input
(1)
DGND 24 – Digital groundDIN 18 I Data input
(1)
DOUT 19 O Data outputFMT0 27 I Audio data format control 0
(1) (2)
FMT1 26 I Audio data format control 1
(1) (2)
FMT2 25 I Audio data format control 2
(1) (2)
LRCIN 16 I Sample rate clock input (f
S
)
(1)
RSTB 28 I Reset, active-low
(1) (2)
V
CC
1 2 – ADC analog power supplyV
CC
2 14 – DAC analog power supplyV
DD
23 – Digital power supplyVCOM 11 – DAC output commonV
IN
L 1 I ADC analog input, LchV
IN
R 6 I ADC analog input, RchV
OUT
L 15 O DAC analog output, LchV
OUT
R 12 O DAC analog output, RchV
REF
L 4 – ADC input reference, LchV
REF
R 5 – ADC input reference, RchXTI 20 I Oscillator inputXTO 21 O Oscillator output
(1) Schmitt-trigger input(2) With 70-k Ωtypical internal pullup resistor
7
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TYPICAL PERFORMANCE CURVES OF ADC SECTION
0.002
0.004
0.006
0.008
0.010
−25 0 25 50 75 100
TA − Free-Air Temperature − °C
THD+N − Total Harm. Dist. + Noise at FS − %
FS
4
3
2
0
1
−60 dB
G001
THD+N − Total Harm. Dist. + Noise at −60 dB − %
0.002
0.004
0.006
0.008
0.010
4.25 4.50 4.75 5.00 5.25 5.50 5.75
VCC − Supply V oltage − V
THD+N − Total Harm. Dist. + Noise at FS − %
4
3
2
0
1
THD+N − Total Harm. Dist. + Noise at −60 dB − %
G002
−60 dB
FS
90
92
94
96
98
4.25 4.50 4.75 5.00 5.25 5.50 5.75
VCC − Supply Voltage − V
Dynamic Range − dB
98
96
94
90
92
SNR − Signal-to-Noise Ratio − dB
G004
Dynamic Range
SNR
0.002
0.004
0.006
0.008
0.010
System Clock
THD+N − Total Harm. Dist. + Noise at FS − %
4
3
2
0
1
G003
THD+N − Total Harm. Dist. + Noise at −60 dB − %
512 fS
256 fS384 fS
44.1 kHz
FS
−60 dB
48 kHz
48 kHz
44.1 kHz
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
All specifications at T
A
= 25 °C, V
CC
= V
DD
= 5 V, f
IN
= 1 kHz, f
S
= 44.1 kHz, 18-bit data, V
IN
= 2.9 Vp-p, and SYSCLK = 384 f
S
,unless otherwise noted
THD+N THD+Nvs vsTEMPERATURE POWER SUPPLY
Figure 1. Figure 2.
THD+N SNR AND DYNAMIC RANGEvs vsSYSTEM CLOCK AND SAMPLING FREQUENCY POWER SUPPLY
Figure 3. Figure 4.
8
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0.002
0.004
0.006
0.008
0.010
Resolution
THD+N − Total Harm. Dist. + Noise at FS − %
4
3
2
0
1
G005
THD+N − Total Harm. Dist. + Noise at −60 dB − %
−60 dB
18-Bit16-Bit
FS
TYPICAL PERFORMANCE CURVES OF DAC SECTION
0.002
0.004
0.006
0.008
0.010
−25 0 25 50 75 100
TA − Free-Air Temperature − °C
THD+N − Total Harm. Dist. + Noise at FS − %
FS
4
3
2
0
1
G006
THD+N − Total Harm. Dist. + Noise at −60 dB − %
−60 dB
0.002
0.004
0.006
0.008
0.010
4.25 4.50 4.75 5.00 5.25 5.50 5.75
VCC − Supply V oltage − V
THD+N − Total Harm. Dist. + Noise at FS − %
4
3
2
0
1
THD+N − Total Harm. Dist. + Noise at −60 dB − %
G007
−60 dB
FS
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF ADC SECTION (continued)All specifications at T
A
= 25 °C, V
CC
= V
DD
= 5 V, f
IN
= 1 kHz, f
S
= 44.1 kHz, 18-bit data, V
IN
= 2.9 Vp-p, and SYSCLK = 384 f
S
,unless otherwise noted
THD+N
vsOUTPUT DATA RESOLUTION
Figure 5.
All specifications at T
A
= 25 °C, V
CC
= V
DD
= 5 V, f
IN
= 1 kHz, f
S
= 44.1 kHz, 18-bit data, and SYSCLK = 384 f
S
, unlessotherwise noted
THD+N THD+Nvs vsTEMPERATURE POWER SUPPLY
Figure 6. Figure 7.
9
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92
94
96
98
100
4.25 4.50 4.75 5.00 5.25 5.50 5.75
VCC − Supply Voltage − V
Dynamic Range − dB
100
98
96
92
94
SNR − Signal-to-Noise Ratio − dB
G009
Dynamic Range
SNR
0.002
0.004
0.006
0.008
0.010
System Clock
THD+N − Total Harm. Dist. + Noise at FS − %
4
3
2
0
1
G008
THD+N − Total Harm. Dist. + Noise at −60 dB − %
512 fS
256 fS384 fS
FS
−60 dB
48 kHz
48 kHz
44.1 kHz
44.1 kHz
0.002
0.004
0.006
0.008
0.010
Resolution
THD+N − Total Harm. Dist. + Noise at FS − %
4
3
2
0
1
G010
THD+N − Total Harm. Dist. + Noise at −60 dB − %
−60 dB
18-Bit16-Bit
FS
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF DAC SECTION (continued)All specifications at T
A
= 25 °C, V
CC
= V
DD
= 5 V, f
IN
= 1 kHz, f
S
= 44.1 kHz, 18-bit data, and SYSCLK = 384 f
S
, unlessotherwise noted
THD+N SNR AND DYNAMIC RANGEvs vsSYSTEM CLOCK AND SAMPLING FREQUENCY POWER SUPPLY
Figure 8. Figure 9.
THD+N
vsINPUT DATA RESOLUTION
Figure 10.
10
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TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs)
DECIMATION FILTER
Normalized Frequency [× fS Hz]
−200
−150
−100
−50
0
0 8 16 24 32
Amplitude − dB
G011
Normalized Frequency [× fS Hz]
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
0.0 0.1 0.2 0.3 0.4 0.5
Amplitude − dB
G013
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
All specifications at T
A
= 25 °C, V
CC
= V
DD
= 5 V, and SYSCLK = 384 f
S
, unless otherwise noted
OVERALL CHARACTERISTICS STOP-BAND ATTENUATION CHARACTERISTICS
Figure 11. Figure 12.
PASS-BAND RIPPLE CHARACTERISTICS
Figure 13.
11
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HIGH-PASS FILTER
Normalized Frequency [× fS/1000 Hz]
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
0 1 2 3 4
Amplitude − dB
G014
ANTIALIASING FILTER
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
f − Frequency − Hz
Amplitude − dB
110 100 100k1k 10k
G015
470 pF
1000 pF
−50
−40
−30
−20
−10
0
f − Frequency − Hz
Amplitude − dB
110 100 10M1k 10k
G016
100k 1M
470 pF
1000 pF
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs) (continued)All specifications at T
A
= 25 °C, V
CC
= V
DD
= 5 V, and SYSCLK = 384 f
S
, unless otherwise noted
HIGH-PASS FILTER RESPONSE
Figure 14.
ANTIALIASING FILTER PASS-BAND ANTIALIASING FILTER OVERALLFREQUENCY RESPONSE (C
EXT
= 470 pF, 1000 pF) FREQUENCY RESPONSE (C
EXT
= 470 pF, 1000 pF)
Figure 15. Figure 16.
12
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TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs)
DIGITAL FILTER
DE-EMPHASIS FILTER
−12
−10
−8
−6
−4
−2
0
Level − dB
f − Frequency − Hz
5k
G019
0 25k10k 15k 20k
−0.6
−0.4
−0.2
0.0
0.2
0.4
0.6
Error − dB
f − Frequency − Hz
3628
G020
0 145127256 10884
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
All specifications at T
A
= 25 °C, V
CC
= V
DD
= 5 V, and SYSCLK = 384 f
S
, unless otherwise noted
OVERALL FREQUENCY CHARACTERISTIC PASS-BAND RIPPLE CHARACTERISTIC
DE-EMPHASIS FREQUENCY RESPONSE (32 kHz) DE-EMPHASIS ERROR (32 kHz)
13
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−12
−10
−8
−6
−4
−2
0
Level − dB
f − Frequency − Hz
5k
G021
0 25k10k 15k 20k
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued)All specifications at T
A
= 25 °C, V
CC
= V
DD
= 5 V, and SYSCLK = 384 f
S
, unless otherwise noted
DE-EMPHASIS FREQUENCY RESPONSE (44.1 kHz) DE-EMPHASIS ERROR (44.1 kHz)
DE-EMPHASIS FREQUENCY RESPONSE (48 kHz) DE-EMPHASIS ERROR (48 kHz)
14
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ANALOG LOW-PASS FILTER
−60
−55
−50
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
5
10
f − Frequency − Hz
Level − dB
10 100 10M1k 10k
G026
100k 1M
−1.0
−0.5
0.0
0.5
1.0
f − Frequency − Hz
Level − dB
20 100 24k1k 10k
G025
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued)All specifications at T
A
= 25 °C, V
CC
= V
DD
= 5 V, and SYSCLK = 384 f
S
, unless otherwise noted
INTERNAL ANALOG FILTER FREQUENCY RESPONSE INTERNAL ANALOG FILTER FREQUENCY RESPONSE(20 Hz–24 kHz, EXPANDED SCALE) (10 Hz–10 MHz)
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MC(FMT2)(1)
MD(FMT1)(1)
Analog
Front-End
Circuit LRCIN
VINL
Reference
VREFL
VREFR
VINR
Delta-Sigma
Modulator
Delta-Sigma
Modulator
Decimation
and
High-Pass Filter
Power Supply
Reset
Serial Data
Interface
DOUT
(+)
(−)
(−)
(+)
Mode
Control
Interface
Analog
Front-End
Circuit
Decimation
and
High-Pass Filter
ADC
BCKIN
DIN
Analog
Low-Pass
Filter
VOUTLMultilevel
Delta-Sigma
Modulator
Interpolation
Filter
8× Oversampling
Analog
Low-Pass
Filter
VOUTRMultilevel
Delta-Sigma
Modulator
Interpolation
Filter
8× Oversampling
DAC
ML(FMT0)(1)
RSTB
Clock/OSC Manager
CLKIOAGND2 VCC2 AGND1 VCC1 DGND VDD
B0004-05
CINNL
CINPL
CINNR
CINPR
VCOM
XTO XTI
Loop Control
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
Block Diagram
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15 kΩ
1 kΩ
470 pF
910
VINL
VREFL
CINPL CINNL
1
4
Delta-Sigma
Modulator
(+)
VREF
+
2.2 µF
4.7 µF+
+
−
(−)
+
−
1 kΩ
S0011-04
PCM AUDIO INTERFACE
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
Figure 17. Analog Front-End (Single-Channel)
The four-wire digital audio interface for the PCM3000/3001 is on LRCIN (pin 16), BCKIN (pin 17), DIN (pin 18),and DOUT (pin 19). The PCM3000/3001 can operate with seven different data formats. For the PCM3000, theseformats are selected through program register 3 in the software mode. For the PCM3001, data formats areselected by pin-strapping the three format pins. Figure 18 , Figure 19 , Figure 20 and Figure 21 illustrate the audiodata input/output format. Figure 22 shows the audio data input/output timing. The PCM3000/3001 can accept 32,48, or 64 bit clocks (BCKIN) during one clock of LRCIN. Only formats 0, 2, and 6 can be selected when 32 bitclocks/LRCIN are applied.
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DAC: 16-Bit, MSB-First, Right-Justified
FORMAT 0: FMT[2:0] = 000
LRCIN Right-ChannelLeft-Channel
BCKIN
DIN
MSB LSB MSB LSB
321 16151416 321 161514
BCKIN
LRCIN Right-ChannelLeft-Channel
DOUT 1
14 15 16321
MSB LSB MSB LSB
14 15 16321
ADC: 16-Bit, MSB-First, Left-Justified
LRCIN Right-ChannelLeft-Channel
BCKIN
DIN
MSB LSB MSB LSB
16 17 18321 16 17 1832118
DAC: 18-Bit, MSB-First, Right-Justified
FORMAT 1: FMT[2:0] = 001
BCKIN
LRCIN Right-ChannelLeft-Channel
DOUT 1
16 17 18321
MSB LSB MSB LSB
16 17 18321
ADC: 18-Bit, MSB-First, Left-Justified
T0016-07
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
Figure 18. Audio Data Input/Output Format (Formats 0 and 1)
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DAC: 16-Bit, MSB-First, Right-Justified
FORMAT 2: FMT[2:0] = 010
LRCIN Right-ChannelLeft-Channel
BCKIN
DIN
MSB LSB MSB LSB
321 16151416 321 161514
ADC: 16-Bit, MSB-First, Right-Justified
LRCIN Right-ChannelLeft-Channel
BCKIN
DIN
MSB LSB MSB LSB
16 17 18321 16 17 1832118
DAC: 18-Bit, MSB-First, Right-Justified
FORMAT 3: FMT[2:0] = 011
ADC: 18-Bit, MSB-First, Right-Justified
T0016-08
LRCIN Right-ChannelLeft-Channel
BCKIN
DOUT
MSB LSB MSB LSB
321 16151416 321 161514
LRCIN Right-ChannelLeft-Channel
BCKIN
DOUT
MSB LSB MSB LSB
16 17 18321 16 17 1832118
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
Figure 19. Audio Data Input/Output Format (Formats 2 and 3)
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DAC: 18-Bit, MSB-First, Left-Justified
FORMAT 4: FMT[2:0] = 100
ADC: 18-Bit, MSB-First, Left-Justified
DAC: 18-Bit, MSB-First, I2S
FORMAT 5: FMT[2:0] = 101
T0016-09
BCKIN
LRCIN Right-ChannelLeft-Channel
DIN 1
16 17 18321
MSB LSB MSB LSB
16 17 18321
BCKIN
LRCIN Right-ChannelLeft-Channel
DOUT 1
16 17 18321
MSB LSB MSB LSB
16 17 18321
LRCIN Right-ChannelLeft-Channel
BCKIN
DIN
MSB LSB MSB LSB
16 17 18321 16 17 18321
LRCIN Right-ChannelLeft-Channel
BCKIN
DOUT
MSB LSB MSB LSB
16 17 18321 16 17 18321
ADC: 18-Bit, MSB-First, I2S
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
Figure 20. Audio Data Input/Output Format (Formats 4 and 5)
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DAC: 16-Bit, MSB-First, DSP-Frame
FORMAT 6: FMT[2:0] = 110
LRCIN Right-ChannelLeft-Channel
BCKIN
DIN
MSB LSB MSB LSB
321 16151416 321 161514
ADC: 16-Bit, MSB-First, DSP-Frame
T0016-10
1
LRCIN Right-ChannelLeft-Channel
BCKIN
DOUT
MSB LSB MSB LSB
321 16151416 321 161514 1
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
Figure 21. Audio Data Input/Output Format (Format 6)
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BCKIN
LRCIN
DIN
t(BCH)
t(BCL)
t(LRP)
t(LB)
t(BCY)
1.4 V
t(BL)
DOUT
t(BDO) t(LDO)
0.5 VDD
t(DIS) t(DIH)
1.4 V
1.4 V
T0021−02
SYSTEM CLOCK
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
BCKIN pulse cycle time t
(BCY)
300 ns (min)BCKIN pulse duration, HIGH t
(BCH)
120 ns (min)BCKIN pulse duration, LOW t
(BCL)
120 ns (min)BCKIN rising edge to LRCIN edge t
(BL)
40 ns (min)LRCIN edge to BCKIN rising edge t
(LB)
40 ns (min)LRCIN pulse duration t
(LRP)
t
(BCY)
(min)DIN setup time t
(DIS)
40 ns (min)DIN hold time t
(DIH)
40 ns (min)DOUT delay time to BCKIN falling edge t
(BDO)
40 ns (max)DOUT delay time to LRCIN edge t
(LDO)
40 ns (max)Rising time of all signals t
(RISE)
20 ns (max)Falling time of all signals t
(FALL)
20 ns (max
Figure 22. Audio Data Input/Output Timing
The system clock for the PCM3000/3001 must be either 256 f
S
, 384 f
S
, or 512 f
S
, where f
S
is the audio samplingfrequency. The system clock can be either a crystal oscillator placed between XTI (pin 20) and XTO (pin 21), oran external clock input. If an external clock is used, the clock is provided to either XTI or CLKIO (pin 22), andXTO is open. The PCM3000/3001 has an XTI clock detection circuit which senses if an XTI clock is operating.When the external clock is delivered to XTI, CLKIO is a buffered output of XTI. When XTI is connected toground, the external clock must be tied to CLKIO. For best performance, the external-clock-input-2 circuit inFigure 23 is recommended.
The PCM3000/3001 also has a system-clock detection circuit which automatically senses if the system clock isoperating at 256 f
S
, 384 f
S
, or 512 f
S
. When a 384-f
S
or 512-f
S
system clock is used, the clock is divided into256 f
S
automatically. The 256-f
S
clock is used to operate the digital filters and the modulators.
Table 1 lists the relationship of typical sampling frequencies and system clock frequencies, and Figure 23 andFigure 24 illustrate the typical system clock connections and external system clock timing.
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CLKIO
Clock Divider
S0017−01
R
256-fS Internal System Clock
PCM3000/3001
XTI
XTO
Xtal
C1
C2
Crystal Resonator Connection (Xtal must be fundamental mode, parallel resonant)
CLKIO
Clock Divider
R
256-fS Internal System Clock
PCM3000/3001
XTI
XTO
External Clock
(CMOS I/F)
External Clock Input 1 : (XTO is open)
CLKIO
Clock Divider
R
256-fS Internal System Clock
PCM3000/3001
XTI
XTO
External Clock Input 2 : (XTO is open)
External Clock
(TTL I/F)
C1 = C2 = 10 to 33 pF
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
Figure 23. System Clock Connections
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t(CLKIH)
XTI or CLKIO 1.4 V
3.2 V
t(CLKIL) T0005-06
XTI
0.8 V
2.0 V
CLKIO
POWER-ON RESET
1024 System Clock Periods
Reset Reset Removal
4.4 V
4.0 V
3.6 V
VDD
Internal Reset
System Clock
(XTI or CLKIO)
T0014-04
3 Clocks Minimum
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
Table 1. System Clock Frequencies
SAMPLING RATE FREQUENCY (kHz) SYSTEM CLOCK FREQUENCY (MHz)
256 f
S
384 f
S
512 f
S
32 8.1920 12.2880 16.384044.1 11.2896 16.9344 22.579248 12.2880 18.4320 24.5760
System clock pulse duration, HIGH t
(CLKIH)
12 ns (min)System clock pulse duration, LOW t
(CLKIL)
12 ns (min)
Figure 24. External System Clock Timing
The PCM3000/3001 has internal power-on reset circuitry. Power-on reset occurs when the system clock (XTI orCLKIO) is active and V
DD
> 4 V. For the PCM3001, the system clock must complete a minimum of 3 completecycles prior to V
DD
> 4 V to ensure proper reset operation. The initialization sequence requires 1024 systemcycles for completion, as shown in Figure 25 . Figure 26 shows the state of the DAC and ADC outputs during andafter the reset sequence.
Figure 25. Internal Power-On Reset Timing
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T0019-03
Reset
Internal Reset
DAC VOUT
32/fS
Reset Removal or Power Down(1) Off
ADC DOUT Zero Data Normal Data(2)
VCOM
(0.5 VCC2)
4096/fS
Zero Data
Ready/Operation
EXTERNAL RESET
t(RST)
Reset Removal
1024 System Clock Periods
RSTB
Internal Reset
System Clock
(XTI or CLKIO)
t(RST) = 40 ns (min)
Reset
T0015-04
RSTB Pulse Duration
SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
(1) Power down is for PCM3000 only.(2) The HPF transient response (exponentially attenuated signal from ±1.5% dc with 200-ms time constant) appearsinitially.
Figure 26. DAC Output and ADC Output for Reset and Power Down
The PCM3000/3001 includes a reset input, RSTB (pin 28). As shown in Figure 27 , the external reset signal mustdrive RSTB low for a minimum of 40 nanoseconds while the system clock is active in order to initiate the resetsequence. Initialization starts on the rising edge of RSTB, and requires 1024 system clock cycles for completion.Figure 26 shows the state of the DAC and ADC outputs during and after the reset sequence.
Figure 27. External Forced-Reset Timing
The PCM3000/3001 operates with LRCIN synchronized to the system clock. The codec does not require anyspecific phase relationship between LRCIN and the system clock, but there must be synchronization of LRCINand the system clock. If the synchronization between the system clock and LRCIN changes more than 6 bitclocks (BCKIN) during one sample (LRCIN) period because of phase jitter on LRCIN, internal operation of theDAC stops within 1/f
S
, and the analog output is forced to bipolar zero (V
CC
2/2) until the system clock isresynchronized to LRCIN. Internal operation of the ADC also stops within 1/f
S
, and the digital output codes areset to bipolar zero until resynchronization occurs. If LRCIN is synchronized within 5 or fewer bit clocks to thesystem clock, operation remains normal.
Figure 28 illustrates the effects on the output when synchronization is lost. Before the outputs are forced tobipolar zero (<1/f
S
seconds), the outputs are not defined and some noise may occur. During the transitionsbetween normal data and undefined states, the output has discontinuities, which cause output noise.
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Within 1/fS
Normal Data
VCOM
(0.5 VCC2)
Undefined
Data
Normal Data
SynchronousAsynchronousSynchronous
Resynchronization
Synchronization Lost
DAC VOUT
State of Synchronization
T0020-04
Normal Data(1)
Zero DataNormal Data
ADC DOUT Undefined
Data
32/fS
Undefined
Data
22.2/fS
OPERATIONAL CONTROL
B8
B15
ML
MC
MD B9B10B11B12B13B14 B0
B7 B1B2B3B4B5B6
T0023-01
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
(1) The HPF transient response (exponentially attenuated signal from ±1.5% dc with 200-ms time constant) appearsinitially.
Figure 28. DAC Output and ADC Output For Loss of Synchronization
The PCM3000 can be controlled in the software mode with a three-wire serial interface on MC (pin 25),MD (pin 26), and ML (pin 27). Table 2 indicates selectable functions, and Figure 29 and Figure 30 illustratecontrol data input format and timing. The PCM3001 only allows for control of data format.
Table 2. Selectable Functions
FUNCTION ADC/DAC DEFAULT (PCM3000)
Audio data format (7 selectable formats) ADC/DAC DAC: 16-bit, MSB-first, right-justifiedADC: 16-bit, MSB-first, left-justifiedLRCIN polarity ADC/DAC Left/right = high/lowLoopback control ADC/DAC OFFLeft-channel attenuation DAC 0 dBRight-channel attenuation DAC 0 dBAttenuation control DAC Left channel and right channel = individual controlInfinite zero detection DAC OFFDAC output control DAC Output enabledSoft mute control DAC OFFDe-emphasis (OFF, 32 kHz, 44.1 kHz, 48 kHz) DAC OFFPower-down control ADC OFFHigh-pass filter operation ADC ON
Figure 29. Control Data Input Format
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t(MCH)
ML
LSB
t(MCL)
t(MHH)
t(MCY)
t(MDH)
t(MDS)
MC
MD
t(MLS)
t(MLL)
t(MLH)
T0024-01
1.4 V
1.4 V
1.4 V
MAPPING OF PROGRAM REGISTERS
PROGRAM REGISTER (PCM3000)
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
MC pulse cycle time t
(MCY)
100 ns (min)MC pulse duration, LOW t
(MCL)
40 ns (min)MC pulse duration, HIGH t
(MCH)
40 ns (min)MD setup time t
(MDS)
40 ns (min)MD hold time t
(MDH)
40 ns (min)ML low-level time t
(MLL)
40 ns + 1 SYSCLK
(1)
(min)ML high-level time t
(MHH)
40 ns + 1 SYSCLK
(1)
(min)ML setup time
(2)
t
(MLS)
40 ns (min)ML hold time
(3)
t
(MLH)
40 ns (min)SYSCLK (period): 1/256 f
S
or 1/384 f
S
or 1/512 f
S
(1) SYSCK: system clock cycle(2) ML rising edge to the next MC rising edge(3) MC rising edge for LSB-to-ML rising edge
Figure 30. Control Data Input Timing
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0REGISTER 0 res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
REGISTER 1 res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
REGISTER 2 res res res res res A1 A0 PDWN BYPS res ATC IZD OUT DEM1 DEM0 MUT
REGISTER 3 res res res res res A1 A0 res res res LOP FMT2 FMT1 FMT0 LRP resNOTE: res indicates a reserved bit, which should be set to 0.
The software mode allows the user to control special functions. The PCM3000 special functions are controlledusing four program registers which are each 16 bits long. There are four distinct registers, with bits 9 and 10determining which register is in use. Table 3 describes the functions of the four registers.
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PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
Table 3. Functions of the Registers
REGISTER NAME REGISTER BIT(S) BIT NAME DESCRIPTION
Register 0 15–11 res Reserved, should be set to 010–9 A[1:0] Register address 008 LDL DAC attenuation data load control forLch7–0 AL[7:0] DAC attenuation data for LchRegister 1 15–11 res Reserved, should be set to 010–9 A[1:0] Register address 018 LDR DAC attenuation data load control forRch7–0 AR[7:0] DAC attenuation data for RchRegister 2 15–11 res Reserved, should be set to 010–9 A[1:0] Register address 108 PDWN ADC power-down control7 BYPS ADC high-pass filter bypass control6 res Reserved, should be set to 05 ATC DAC attenuation data mode control4 IZD DAC infinite zero detection circuit control3 OUT DAC output enable control2–1 DEM[1:0] DAC de-emphasis control0 MUT DAC Lch and Rch soft mute controlRegister 3 15–11 res Reserved, should be set to 010–9 A[1:0] Register address 118–6 res Reserved, should be set to 05 LOP ADC/DAC analog loopback control4–2 FMT[2:0] ADC/DAC audio data format selection1 LRP ADC/DAC polarity of LR-clock selection0 res Reserved, should be set to 0
PROGRAM REGISTER 0
res: Bits 15:11 – ReservedThese bits are reserved and should be set to 0.
A[1:0]: Bits 10:9 – Register Address
These bits definte the address for REGISTER 0:A1 A0
0 0 Register 0
LDL: Bit 8 – DAC Attenuation Data Load Control for Left ChannelThis bit is used to simultaneously set the analog outputs of the left and right channels. The outputlevel is controlled by AL[7:0] attenuation data when this bit is set to 1. When set to 0, the newattenuation data is stored into a register, and the output level remains at the previous attenuationlevel. The LDR bit in REGISTER 1 has the equivalent function as LDL. When either LDL or LDR isset to 1, the output levels of the left and right channels are simultaneously controlled.
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PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
AL[7:0]: Bits 7:0 – DAC Attenuation Data for Left Channel
AL7 and AL0 are the MSB and LSB, respectively. The attenuation level (ATT) is given by
ATT = 20 ×log
10
(AL[7:0]/256) (dB), except AL[7:0] = FFhAL[7:0] ATTENUATION LEVEL
00h – ∞dB (mute)01h –48.16 dB: :FEh –0.07 dBFFh 0 dB (default)
PROGRAM REGISTER 1
res: Bits 15:11 – ReservedThese bits are reserved and should be set to 0.
A[1:0]: Bits 10:9 – Register Address
These bits definte the address for REGISTER 1.A1 A0
0 1 Register 1
LDR: Bit 8 – DAC Attenuation Data Load Control for Right ChannelThis bit is used to simultaneously set the analog outputs of the left and right channels. The outputlevel is controlled by AR[7:0] attenuation data when this bit is set to 1. When set to 0, the newattenuation data is stored into a register, and the output level remains at the previous attenuationlevel. The LDL bit in REGISTER 0 has the equivalent function as LDR. When either LDL or LDR isset to 1, the output levels of the left and right channels are simultaneously controlled.
AR[7:0]: Bits 7:0 – DAC Attenuation Data for Right Channel
AR7 and AR0 are the MSB and LSB, respectively. The attenuation level (ATT) is given by
ATT = 20 ×log
10
(AR[7:0]/256) (dB), except AR[7:0] = FFhAR[7:0] ATTENUATION LEVEL
00h – ∞dB (mute)01h –48.16 dB: :FEh –0.07 dBFFh 0 dB (default)
PROGRAM REGISTER 2
res: Bits 15:11 – ReservedThese bits are reserved and should be set to 0.
A[1:0]: Bits 10:9 – Register Address
These bits define the address for REGISTER 2:A1 A0
1 0 Register 2
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PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
PDWN: Bit 8 – ADC Power-Down Control
This bit places the ADC section in a power-down mode, forcing the output data to all zeroes. This has no effecton the DAC section or the contents of the mode registers.PDWN
0 Power-down mode disabled (default)1 Power-down mode enabled
BYPS: Bit 7 – ADC High-Pass Filter Bypass Control
This bit enables or disables the high-pass filter for the ADC.BYPS
0 High-pass filter enabled (default)1 High-pass filter disabled (bypassed)
res: Bit 6 – Reserved
This bit is reserved and should be set to 0.
ATC: Bit 5 – DAC Attenuation Data Mode Control
When set to 1, the REGISTER 0 attenuation data is used for both DAC channels. In this case, the REGISTER 1attenuation data is ignored.ATC
0 Individual channel attenuation data control (default)1 Common channel attenuation data control
IZD: Bit 4 – DAC Infinite Zero Detection Circuit Control
This bit enables the infinite zero detection circuit in the PCM3000. When enabled, this circuit disconnects theanalog output amplifier from the delta-sigma DAC when the input is continuously zero for 65,536 consecutivecycles of BCKIN.
IZD
0 Infinite zero detection disabled (default)1 Infinite zero detection enabled
OUT: Bit 3 – DAC Output Enable Control
When set to 1, the outputs are forced to V
CC
/2 (bipolar zero). In this case, all registers in the PCM3000 hold thepresent data. Therefore, when set to 0, the outputs return to the previous programmed state.OUT
0 DAC outputs enabled (default normal operation)1 DAC outputs disabled (forced to BPZ)
DEM[1:0]: Bits 2:1 – DAC De-Emphasis Control
These bits select the de-emphasis mode as shown.DEM1 DEM0
0 0 De-emphasis OFF (default)0 1 De-emphasis 48 kHz ON1 0 De-emphasis 44.1 kHz ON1 1 De-emphasis 32 kHz ON
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PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
MUT: Bit 0 – DAC Soft Mute Control
When set to 1, both left- and right-channel DAC outputs are muted at the same time. This muting is done byattenuating the data in the digital filter, so that there is no audible click noise when soft mute is turned on.MUT
0 Mute disabled (default)1 Mute enabled
PROGRAM REGISTER 3
res: Bits 15:11 – ReservedThese bits are reserved and should be set to 0.
A[1:0]: Bits 10:9 – Register Address
These bits define the address for REGISTER 3.A1 A0
1 1 Register 3
res: Bits 8:6 – ReservedThese bits are reserved and should be set to 0.
LOP: Bit 5 – ADC to DAC Loopback Control
When this bit is set to 1, the ADC audio data is sent directly to the DAC. The data format defaults to I
2
S; DOUTis still available in loopback mode.LOP
0 Loopback disabled (default)1 Loopback enabled
FMT[2:0]: Bits 4:2 – Audio Data Format Select
These bits determine the input and output audio data formats. (default: FMT[2:0] = 000
b
)FM2 FMT1 FMT0 DAC DATA FORMAT ADC DATA FORMAT
0 0 0 16-bit, MSB-first, right-justified 16-bit, MSB-first, left-justified0 0 1 18-bit, MSB-first, right-justified 18-bit, MSB-first, left-justified0 1 0 16-bit, MSB-first, right-justified 16-bit, MSB-first, right-justified0 1 1 18-bit, MSB-first, right-justified 18-bit, MSB-first, right-justified1 0 0 16-/18-bit, MSB-first, left-justified 18-bit, MSB-first, left-justified1 0 1 16-/18-bit, MSB-first, I
2
S 18-bit, MSB-first, I
2
S1 1 0 16-bit, MSB-first, DSP-frame 16-bit, MSB-first, DSP-frame1 1 1 Reserved Reserved
LRP: Bit 1 – ADC-to-DAC LRCK Polarity Select
Polarity of LRCIN applies only to formats 0 through 4.LOP
0 Left channel is H, right channel is L (default).1 Left channel is L, right channel is H.
res: Bit 0 – Reserved
This bit is reserved and should be set to 0.
PCM3001 DATA FORMAT CONTROL
The input and output data formats are controlled by pins 27 (FMT0), 26 (FMT1), and 25 (FMT2). Set these pinsto the same values shown for the bit-mapped PCM3000 controls in program register 3.
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THEORY OF OPERATION
ADC SECTION
1st
SW-CAP
Integrator
Analog
In
X(z) +
−
+−2nd
SW-CAP
Integrator
3rd
SW-CAP
Integrator
+−4th
SW-CAP
Integrator
++++
++++
5th
SW-CAP
Integrator
Digital
Out
Y(z)
Comparator
Qn(z)
H(z)
1-Bit
DAC
STF(z) = H(z) / [1 + H(z)]
NTF(z) = 1 / [1 + H(z)]
Y(z) = STF(z) * X(z) + NTF(z) * Qn(z)
Signal Transfer Function
Noise Transfer Function B0005-01
DAC SECTION
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
The PCM3000/3001 ADC consists of a band-gap reference, a stereo single-to-differential converter, a fullydifferential 5th-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interfacecircuit. The block diagram in this data sheet illustrates the architecture of the ADC section. Figure 17 shows thesingle-to-differential converter, and Figure 31 illustrates the architecture of the 5th-order delta-sigma modulatorand transfer functions.
An internal high-precision reference with two external capacitors provides all reference voltages required by theADC, which defines the full scale range for the converter. The internal single-to-differential voltage convertersaves the space and extra parts needed for external circuitry which is required by many delta-sigma converters.The internal full-differential signal processing architecture provides a wide dynamic range and excellent powersupply rejection performance.
The input signal is sampled at a 64 ×oversampling rate, eliminating the need for a sample-and-hold circuit, andsimplifying antialias filtering requirements. The 5th-order delta-sigma noise shaper consists of five integratorswhich use a switched-capacitor topology, a comparator, and a feedback loop consisting of a one-bit DAC. Thedelta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain.The high order of the modulator enables it to randomize the modulator outputs, reducing idle tone levels.
The 64-f
S
1-bit data stream from the modulator is converted to 1-f
S
, 18-bit data words by the decimation filter,which also acts as a low-pass filter to remove the shaped quantization noise. The dc components are removedby a high-pass filter function contained within the decimation filter.
Figure 31. Simplified Fifth-Order Delta-Sigma Modulator
The delta-sigma DAC section of the PCM3000/3001 is based on a 5-level amplitude quantizer and a 3rd-ordernoise shaper. This section converts the oversampled input data to a 5-level delta-sigma format. A block diagramof the 5-level delta-sigma modulator is shown in Figure 32 . This 5-level delta-sigma modulator has the advantageof improved stability and reduced clock-jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modulator and the internal 8 ×interpolation filter is 64 f
S
for a256-f
S
system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator isshown in Figure 33 .
32
www.ti.com
+
+−Z−1
+ +
+
+−Z−1
In
8 fS
18-Bit
Out
64 fS
+
+Z−1
B0008-02
+
5-Level Quantizer
0
1
2
3
4
f − Frequency − kHz
−150
−140
−130
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 5 10 15 20 25 30
Gain − dB
G027
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
Figure 32. 5-Level ∆ Σ Modulator Block Diagram
Figure 33. Quantization Noise Spectrum
33
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APPLICATION INFORMATION
APPLICATION AND LAYOUT CONSIDERATIONS
TYPICAL CONNECTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
470 pF
470 pF
+
4.7 µF
4.7 µF
+
2.2 µF(2)
+
2.2 µF(2)
+
10 to 33 pF
4.7 µF+
Register Control
Interface
Reference
Bias
Analog
Front-End
Decimation
Filter
Interpolation
Filter
LPF and
Buffer
Digital
Audio
Interface
CLK/OSC
Manager
Delta-Sigma
Delta-Sigma
Post
Low-Pass
Filter
(1)
(1)
(1)
Serial
Control
or
Format
Control
Digital
Audio
Data
Reset
Line In Left-Channel
+5V
Line In Right-Channel
Line Out Right-Channel
Line Out Left-Channel
S0018-01
Post
Low-Pass
Filter
Analog
Front-End
LPF and
Buffer
POWER SUPPLY BYPASSING
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
A typical connection diagram for the PCM3000/3001 is shown in Figure 34 .
(1) Bypass capacitor = 0.1 µF and 10 µF.(2) The input capacitor affects the pole of the HPF. Example: 2.2 µF sets the cutoff frequency to 4.8 Hz, with a 66-mstime constant.
Figure 34. Typical Connection Diagram for PCM3000/3001
The digital and analog power-supply lines to the PCM3000/3001 should be bypassed to the correspondingground pins with both 0.1- µF ceramic and 10- µF tantalum capacitors as close to the device pins as possible tomaximize the performance of the ADC and DAC. Although the PCM3000/3001 has three power supply lines tooptimize dynamic performance, the use of one common power supply is generally recommended to avoidunexpected latch-up or pop noise due to power-supply sequencing problems. If separate power supplies areused, back-to-back diodes between the two power sources near the device are recommended to avoid latch-upproblems.
34
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GROUNDING
VOLTAGE INPUTS
V
REF
INPUTS
C
IN
P AND C
IN
N INPUTS
VCOM INPUT
SYSTEM CLOCK
RSTB CONTROL
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
APPLICATION INFORMATION (continued)
In order to optimize dynamic performance of the PCM3000/3001, the analog and digital grounds are notinternally connected. PCM3000/3001 performance is optimized with a single ground plane for all returns. It isrecommended to tie all PCM3000/3001 ground pins to the analog ground plane using low-impedanceconnections. The PCM3000/3001 should reside entirely over this plane to avoid coupling high-frequency digitalswitching noise into the analog ground plane.
A tantalum or aluminum electrolytic capacitor, between 2.2 µF and 10 µF, is recommended as an ac-couplingcapacitor at the inputs. Combined with the 15-k Ωcharacteristic input impedance, a 2.2- µF coupling capacitorestablishes a 4.8-Hz cutoff frequency for blocking dc. The input voltage range can be increased by adding aseries resistor on the analog input line. This series resistor, when combined with the 15-k Ωinput impedance,creates a voltage divider and enables larger input ranges.
A 4.7- µF to 10- µF tantalum capacitor is recommended between V
REF
L, V
REF
R, and AGND1 to ensure low sourceimpedance for the ADC references. These capacitors should be located as close as possible to the referencepins to reduce dynamic errors on the ADC reference.
A 470-pF to 1000-pF film or NPO ceramic capacitor is recommended between C
IN
PL and C
IN
NL, and alsobetween C
IN
PR and C
IN
NR to create an antialias filter that has a 170-kHz to 80-kHz cutoff frequency. Thesecapacitors should be located as close as possible to the C
IN
P and C
IN
N pins to avoid introducing undesirablenoise or dynamic errors into the delta-sigma modulator.
A 4.7- µF to 10- µF tantalum capacitor is recommended between VCOM and AGND2 to ensure low sourceimpedance of the DAC output common. This capacitor should located as close as possible to the VCOM pin toreduce dynamic errors on the DAC common.
The quality of the system clock can influence the dynamic performance of both the ADC and DAC in thePCM3000/3001. The duty cycle, jitter, and threshold voltage at the system clock input pin should be carefullymanaged. When power is supplied to the part, the system clock, bit clock (BCKIN), and word clock (LCRIN) mustalso be supplied simultaneously. Failure to supply the audio clocks results in a power dissipation increase of upto three times normal dissipation and may degrade long-term reliability if the maximum power dissipation limit isexceeded.
If capacitors greater than 4.7 µF are used on V
REF
and VCOM, an external reset control with delay timecorresponding to the V
REF
, VCOM response is required.
35
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
PCM3000E ACTIVE SSOP DB 28 47 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM3000E/2K ACTIVE SSOP DB 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM3000E/2KG4 ACTIVE SSOP DB 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM3000EG4 ACTIVE SSOP DB 28 47 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM3001E ACTIVE SSOP DB 28 47 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM3001E/2K ACTIVE SSOP DB 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM3001E/2KG4 ACTIVE SSOP DB 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM3001EG/2K ACTIVE Pb-Free
(RoHS) CU SNBI Level-1-260C-UNLIM
PCM3001EG4 ACTIVE SSOP DB 28 47 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
PCM3000E/2K SSOP DB 28 2000 330.0 17.4 8.5 10.8 2.4 12.0 16.0 Q1
PCM3001E/2K SSOP DB 28 2000 330.0 17.4 8.5 10.8 2.4 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jun-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCM3000E/2K SSOP DB 28 2000 336.6 336.6 28.6
PCM3001E/2K SSOP DB 28 2000 336.6 336.6 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jun-2008
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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