LINEAR TECHNOLOGY FEBRUARY 1998 IN THIS ISSUE... COVER ARTICLE Universal Continuous-Time Filter Challenges Discrete Designs .......... 1 Max Hauser Issue Highlights ............................ 2 LTC(R) in the News ........................... 2 DESIGN FEATURES An SMBus-Controlled 10-Bit, Current Output, 50 A, Full-Scale DAC ........ 6 Ricky Chow Micropower 600kHz Fixed-Frequency DC/DC Converters Step Up from a 1-Cell or 2-Cell Battery .................. 8 Steve Pietkiewicz New 333ksps, 16-Bit ADC Offers 90dB SINAD and -100dB THD .............. 11 Marco Pan Ultralow Power 14-Bit ADC Samples at 200ksps .................................. 14 Dave Thomas A 10MB/s Multiple-Protocol Chip Set Supports Net1 and Net2 Standards ................................................... 17 David Soo DESIGN IDEAS High Clock-to-Center Frequency Ratio LTC1068-200 Extends Capabilities of Switched Capacitor Highpass Filter ................................................... 23 Frank Cox LT1533 Ultralow Noise Switching Regulator for High Voltage or High Current Applications .......... 24 Jim Williams A Complete Battery Backup Solution Using a Rechargeable NiCd Cell .. 26 L.Y. Lin and S.H. Lim Zero-Bias Detector Yields High Sensitivity with Nanopower Consumption ............................... 28 Mitchell Lee DESIGN INFORMATION Micropower Octal 10-Bit DAC Conserves Board Space with SO-8 Footprint ..................................... 29 Kevin R. Hoskins Tiny MSOP Dual Switch Driver is SMBus Controlled ........................ 31 Peter Guan New Device Cameos ..................... 34 Design Tools ................................ 35 Sales Offices ............................... 36 VOLUME VIII NUMBER 1 Universal Continuous-Time Filter Challenges Discrete Designs by Max Hauser The LTC1562 is the first in a new family of tunable, DC-accurate, continuous-time filter products featuring very low noise and distortion. It contains four independent 2nd order, 3-terminal filter blocks that are resistor programmable for lowpass or bandpass filtering functions up to 150kHz, and has a complete PC board footprint smaller than a dime. Moreover, the part can deliver arbitrary continuous-time pole-zero responses, including highpass, notch and elliptic, if one or more programming resistors are replaced with capacitors. The center frequency (f0) of the LTC1562 is internally trimmed, with an absolute accuracy of 0.5%, and can be adjusted independently in each 2nd order section from 10kHz to 150kHz by an external resistor. Other features include: Rail-to-rail inputs and outputs Wideband signal-to-noise ratio (SNR) of 103dB Total harmonic distortion (THD) of -96dB at 20kHz, -80dB at 100kHz Built-in multiple-input summing and gain features; capable of 118dB dynamic range Single- or dual-supply operation, 4.75V to 10.5V total "Zero-power" shutdown mode under logic control No clocks, PLLs, DSP or tuning cycles required The LTC1562, in the SSOP package, provides eight poles of programmable continuous-time filtering in a total surface mount board area (including the programming resistors) of 0.24 square inches (155 mm2 )--smaller than a U.S. 10-cent coin. This filter can also replace op amp-R-C active filter circuits and LC filters in applications requiring compactness, flexibility, high dynamic range or fewer precision components. What's Inside? As shown in Figure 1, the LTC1562 includes four identical 3-terminal blocks. Each contains active circuitry, precision capacitors and precision resistors, forming a flexible 2nd order filter core. These blocks are designed to make filters as easy to configure as op amps. The 3-terminal arrangement minimizes the number of external parts necessary for a complete 2nd order filter with arbitrarily programmable f0, Q and gain. Figure 2 shows the contents of one block, along with three external resistors, forming a complete lowpass/bandpass filter (the most basic application of the LTC1562). In Figure 2, a lowpass response appears between the VIN source and the LP output pin, and simultaneously a bandpass response is available at the BP output pin. Both outputs have rail-to-rail capability for the maximum possible signal swing, and hence, maximum signalto-noise ratio (SNR). continued on page 3 , LTC and LT are registered trademarks of Linear Technology Corporation. Adaptive Power, Burst Mode, C-Load, FilterCAD, Linear View, Micropower SwitcherCAD, Operational Filter and SwitcherCAD are trademarks of Linear Technology Corporation. Other product names may be trademarks of the companies that manufacture the products. EDITOR'S PAGE Issue Highlights LTC in the News... LTC Reports Another Strong Quarter Our cover article for this issue introduces a new filter product, the LTC1562. The LTC1562 is the first in a new family of tunable, DC-accurate, continuous-time filter products featuring very low noise and distortion. It contains four independent 2nd order, 3-terminal filter blocks that are resistor programmable for lowpass or bandpass filtering functions up to 150kHz, and has a complete PC board footprint smaller than a dime. Data converters are strongly represented in this issue, with a new DAC and several new ADCs: The LTC1427-50 is a 10-bit, current-source-output DAC with an SMBus interface. This device provides precision, full-scale current of 50A 1.5% at room temperature (3% over temperature), wide output voltage DC compliance (from -15V to [VCC - 1.3V]) and guaranteed monotonicity over a wide supply-voltage range. It is an ideal part for applications in contrast/brightness control or voltage adjustment in feedback loops. We also introduce the LTC1604, a fast, high performance 16-bit sampling ADC in a tiny 36-pin SSOP package. This device runs at 333ksps and delivers excellent DC and AC performance. It operates on 5V supplies and typically draws only 220mW. It is a complete differential, high speed, low power, 16-bit sampling ADC that requires no external components. The LTC1604 also provides two powershutdown modes, NAP and SLEEP, to reduce power consumption during inactive periods. It not only offers the performance of the best hybrids but also provides low power, small size, an easy-to-use interface and the low cost of a monolithic part. A new, versatile 14-bit ADC, the LTC1418, can digitize at 200ksps while consuming only 15mW from a single 5V supply. The LTC1418 is designed to be easy to use and adaptable, requiring little or no support circuitry in a wide variety of applica2 tions. It features 0.25LSB INL max and 1LSB DNL max, parallel and serial data output modes and NAP and SLEEP power-shutdown modes. In the power conversion arena, we debut two new micropower DC/DC converters designed to provide power from a single-cell or higher input voltage, the LT1308 and the LT1317. The LT1308 is intended for generating power on the order of 2W-5W, for RF power amplifiers in GSM or DECT terminals or for digital-camera power supplies. The LT1317, intended for lower power requirements, operates from an input voltage as low as 1.5V. It can generate 100mW to 2W of power. Both devices feature Burst ModeTM operation for high efficiency at light loads. Both devices switch at 600kHz; this high frequency keeps associated power components small and flat. On the interface front, we present a new multiprotocol chip set that is guaranteed to be Net1 and Net2 compliant. The LTC1543/LTC1544/ LTC1344A chip set creates a complete software-selectable serial interface using an inexpensive DB25 connector. The LTC1543 is a dedicated data/clock chip and the LTC1544 is a control-signal chip. The chip set supports the V.28 (RS232), V.35, V.36, RS449, EIA-530, EIA-530A and X.21 protocols in either DTE or DCE mode. In the Design Ideas section, we feature a 1kHz, 8th order Butterworth highpass filter, power gain stages to extend the output-power capability of the LT1533 ultralow noise switching regulator, a nanopower zero-bias detector and a complete battery backup solution based on a single NiCd cell and the LT1558 batterybackup controller. We conclude with Design Information on the LTC1660 10-bit octal DAC and the LTC1632 SMBus switch controller and a pair of New Device Cameos. "Demand for our products remained strong and well diversified across end markets," said Robert Swanson, president and CEO of Linear Technology Corporation. "We had another strong quarter, achieving record levels for sales and profits. The turmoil in the Asian financial markets did not have a material impact on our business in this quarter, although we continue to closely monitor this geographical area for its impact in the future." Douglas Lee, an analyst at NationsBanc Montgomery Securities in San Francisco, predicts that Linear Technology will "see a sequential sales growth of about 7% for the March quarter." This was reported in the January 19, 1998 issue of Electronic Buyers' News. Net sales for the second quarter ended December 28, 1997 were $117,004,000, an increase of 30% over net sales of $90,080,000 for the second quarter of the previous year. The Company also reported net income for the quarter of $43,582,000, an increase of 38% over the $31,631,000 reported for the second quarter of last year. Diluted earnings per share (EPS) were $0.55 compared to $0.40 for the similar quarter last year. This is the first quarter that earnings per share (EPS) are reported in compliance with the new Financial Accounting Standards Board pronouncement No. 128. Diluted EPS is analogous to the methodology the Company used in the past in reporting EPS. During the quarter, Linear Technology purchased 1,002,500 shares of its stock for $56.4 million, $5.9 million of which was paid after quarter end. A cash dividend of $0.40 will be paid on February 11, 1998 to shareholders of record on January 23, 1998 Linear Technology Magazine * February 1998 DESIGN FEATURES INV V+ BP LP INV BP LP *R1 AND C ARE PRECISION INTERNAL COMPONENTS 1 sR1C* V+ SHUTDOWN SWITCH V- A C B - 2ND ORDER SECTIONS SHUTDOWN SWITCH SHDN AGND D + C LP V- INV INV BP LP INV BP BP RQ R2 LP 1562 F01 RIN 1562 F02 + - Figure 1. LTC1562 block diagram VIN LTC1562, continued from page 1 The LTC1562 is versatile; it is not limited to the lowpass/bandpass filter of Figure 2. Cascading multiple sections, of course, yields higherorder filters (Figure 3a). A highpass response results if the external input resistor (RIN of Figure 2) is replaced by a capacitor, CIN, which sets only gain, not critical frequencies (Figure 3b). Responses with arbitrary zeroes (for example, elliptic or notch responses) are implemented with feedforward connections with multiple 2nd order blocks, as shown in the application circuit in Figure 8. Moreover, the virtual-ground INV input gives each 2nd-order section the built-in capability for analog operations such as gain (preamplification), summing and weighting of multiple inputs, or accepting current or charge signals directly. These flexible 3-terminal elements are Operational FilterTM blocks. Although the LTC1562 is offered in a 20-pin SSOP package, the LTC1562 is a 16-pin circuit; the extra pins are connected to the die substrate and should be returned to the negative power supply. In single-supply appli- Figure 2. Single 2nd order section, illustrating connection with external resistors R2, RIN and RQ cations, these extra V- pins should be connected directly to a PC board's ground plane for the best grounding and shielding of the filter. 16-pin plastic DIP packaging is also available (consult the factory). DC Performance and Power Shutdown The LTC1562 operates from single or dual supply voltages, nominally 5V to 10V total. It generates an internal half-supply reference point (the AGND pin), establishing a reference voltage for the inputs and outputs in single-supply applications. In these applications, the AGND pin should be bypassed with a capacitor to the ground plane (at V-); the pin can be connected directly to ground when a split supply is used. The DC offset voltage from the filter input to the LP output for a typical 2nd order section (unity DC gain) is typically 5mV. Both outputs swing to within approximately 100mV of each supply rail with loads of 5k and 30pF. VIN To save power in a "sleep" situation, a logic high input on the SHDN pin will put the LTC1562 into its shutdown mode, in which the chip's power supply current is reduced to only junction leakage (typically 2A from a single 5V supply). The shutdown pin is designed to accept CMOS levels with 5V swing, for example, 0V and 5V logic levels when the LTC1562 is powered from either a single 5V or a split 5V supply. Note that in the LTC1562, unlike some other products, a small bias current source (approximately 2A) at the SHDN pin causes the chip to default to the shutdown state if this pin is left open. Therefore, the user must remember to connect the SHDN pin to a logic low for normal operation if the shutdown feature is not used. (This default-toshutdown convention saves system power in the shutdown state, since it eliminates even the microampere current that would otherwise flow from the driving logic to the bias-current source.) VIN CIN VOUT INV BP LP 2ND ORDER INV BP LP 2ND ORDER Figure 3a. Two 2nd order sections cascaded for higher order response Linear Technology Magazine * February 1998 VOUT INV BP LP 2ND ORDER Figure 3b. 2nd order section configured for highpass output 3 DESIGN FEATURES 1 RQ1, 5.62k R21, 10k 2 3 4 5V 0.1F 5 R23, 10k RIN3 10k VIN1 6 7 RQ3, 5.62k 8 INV B INV C BP B BP C LP B LP C V- V + LTC1562 SHDN AGND LP A LP D BP A BP D INV D INV A 0 16 -10 15 RQ2, 13k -20 14 R22, 10k GAIN (dB) VIN2 10 RIN2, 10k RIN1 10k VOUT2 -5V 13 0.1F 12 -40 -50 VOUT1 11 -30 10 R24, 10k -60 RQ4, 13k -70 9 -80 10k RIN4, 10k 1562 TA01 100k FREQUENCY (Hz) 1M 1562 TA02 Figure 4. Dual, matched 4th order 100kHz Butterworth lowpass filter Frequency Responses Lowpass filters with standard all-pole responses (Butterworth, Chebyshev, Bessel, Gaussian and so on) of up to 8th order (eight poles) can be realized with LTC1562 sections connected as in Figures 2 and 3a; practical examples appear later in this article. Resistor ratios program the standard filter parameters f0, Q and gain; required values of these filter parameters can be found from tables or from software such as FilterCADTM for Windows(R), available free from LTC. The "LP" and "BP" outputs of each 2nd order section, although named after their functions in Figure 2, can display other responses than lowpass and bandpass, respectively, if the external components are not all resistors. The highpass configuration of Figure 3b has a passband gain set by the ratio CIN/C, where C is an internal 160pF capacitor in the LTC1562. The two resistors in Figure 3b control f0 and Q, as in the other modes. The LTC1562 is the first truly compact universal active filter, yet it offers instrumentation-grade performance rivaling much larger discrete-component designs. Bandpass applications can use the LTC1562 in either of two ways. In the basic configuration, with the only external components being resistors (Figure 2), the BP output has a bandpass response from VIN. With an input capacitor, as in Figure 3b, the BP output has a highpass response as noted above and the LP pin shows a bandpass response. The f 0 range is approximately 10kHz-150kHz, limited mainly by the magnitudes of the external resistors required. At high f0 these resistors fall below 5k, heavily loading the outputs of the LTC1562 and leading to increased THD and other effects. A lower Figure 5. Frequency response of Figure 4's circuit f0 limit of 10kHz reflects an arbitrary resistor magnitude limit of 1 Megohm. The LTC1562's MOS input circuitry can accommodate higher resistor values than this, but junction leakage current from the input-protection circuitry may cause DC errors. Design formulas and further details on frequency-response programming appear in the LTC1562 data sheet. Low Noise and Distortion The active (that is, amplifier) circuitry in the LTC1562 was designed expressly for filtering. Because of this, filter noise is due primarily to the circuit resistors rather than to the amplifiers. The amplifiers also exhibit exceptional linearity, even at high frequencies (patents pending). The noise and distortion performance for filters built with the LTC1562 compares favorably with filters using expensive, high performance, off-theshelf op amps that demand many more external parts and far more board area (we know, because we've 10 TO CIN3 CIN1 150pF RQ1, 10.2k 2 R21, 35.7k 3 4 5V 0.1F 5 6 CIN3 150pF FROM HP C R23, 107k RQ3, 54.9k 7 8 INV B INV C BP B BP C LP C LP B V + LTC1562 -10 15 RQ2, 22.1k 14 R22, 66.5k 13 V- SHDN AGND LP A LP D BP A BP D INV A INV D 12 CIN2 150pF -5V 0.1F -20 -30 -40 -50 -60 11 10 R24, 127k 9 RQ4, 98.9k CIN4 150pF -70 -80 -90 VOUT 1562 TA08 Figure 6. 8th order Chebyshev highpass filter with 0.05dB ripple (fCUTOFF = 30kHz) 4 0 16 GAIN (dB) 1 CIN 1k 10k 100k FREQUENCY (Hz) 1M 1562 TA09 Figure 7. Frequency response of Figure 6's circuit Linear Technology Magazine * February 1998 DESIGN FEATURES 10 RFF1, 10k CIN1, 87pF RIN1, 19.6k RQ1, 13k 2 R21, 8.87k 3 4 5V 0.1F 5 6 R23, 8.87k RIN3, 69.8k 7 RQ3, 28k 8 -10 INV C INV B BP C BP B LP C LP B SHDN AGND LP A LP D BP D INV D INV A CIN3, 47pF -20 15 RQ2, 8.87k 14 R22, 12.1k 13 V- V + LTC1562 BP A 16 12 GAIN (dB) 1 VIN 0 RIN2, 8.06k -5V -30 -40 -50 -60 0.1F -70 11 10 R24, 17.8k 9 RQ4, 6.98k -80 -90 RIN4, 7.32k 1k 10k 100k FREQUENCY (Hz) 1M 1562 TA04 Figure 9. Frequency response of Figure 8's circuit. VOUT RFF2, 17.8k 1562 TA03 ALL RESISTORS = 1% METAL FILM Figure 8. 8th order 100kHz elliptic lowpass filter built them). The details of this performance depend on Q and other parameters and are reported for specific application examples below. As with other low distortion circuits, accurately measuring distortion performance requires both an input signal and distortion-analyzing equipment with adequately low distortion floors. Low level signals can exploit a low noise preamplification feature in the LTC1562. A 2nd order section operated with unity gain, Q = 1 and f0 = 100kHz shows a typical output noise of 24VRMS, which gives a 103dB SNR with full-scale output from a 10V total supply. However, reducing the value of RIN in Figure 2 increases the gain without a proportional increase in the output noise (unlike many active filters). A gain of 100 (40dB) with the same Q and f0 gives a measured output RIN1A 6.19k CIN1 680pF RQ1, 10k 2 R21, 10k 3 4 0.1F 5 R23, 10k RIN3B 3.83k VIN3 The practical circuit in Figure 4 is a dual lowpass filter with a Butterworth (maximally-flat-passband) frequency response. Each half gives a DC-accurate, unity-passband-gain lowpass response with rail-to-rail input and output. With a 10V total power supply, the measured output noise for one filter is 36VRMS in a 200kHz bandwidth, and the largeVOUT2 1 5V RIN3A 6.19k Dual 4th Order 100kHz Butterworth Lowpass Filter VOUT1 RIN1B 3.83k VIN1 noise of 449VRMS or an input-referred noise of 4.5VRMS--a 78dB output SNR with an input that is 40dB down. Thus, the same circuit can handle a wide range of input levels with high SNR by changing (or switching) the input resistor. In the example just cited, the ratio of maximum input signal to minimum input noise, by changing RIN, is 118dB. 6 7 RQ3, 10k CIN3 680PF 8 INV B INV C BP B BP C LP B LP C V + LTC1562 AGND LP A LP D BP A BP D INV A VOUT3 15 14 13 V- SHDN INV D RIN2B 3.83k 16 12 RQ2, 10k RIN2A 6.19k VIN2 -5V 0.1F 11 10 R24, 10k 9 RQ4, 10k RIN4B 3.83k VOUT4 RIN4A 6.19k VIN4 CIN4 680pF 1562 TA07 ALL RESISTORS = 1% METAL FILM Figure 10. Quad 3-pole 100kHz Butterworth lowpass filter Linear Technology Magazine * February 1998 8th Order 30kHz Chebyshev Highpass Filter Figure 6 shows a straightforward use of the highpass configuration in Figure 3b with some practical values. Each of the four cascaded 2nd order sections has an external capacitor in the input path, as in Figure 3b. The resistors in Figure 6 set the f0 and Q values of the four sections to realize a Chebyshev (equiripple-passband) response with 0.05dB ripple and a 30kHz highpass corner. Figure 7 shows the frequency response. Total output noise for this circuit is 40VRMS. 8th Order 100kHz Elliptic Lowpass Filter CIN2 680pF R22, 10k signal output SNR is 100dB. Measured THD at 1VRMS input is -83.5dB at 50kHz and -80dB at 100kHz. Figure 5 shows the frequency response of one filter. Figure 8 illustrates how sharp-cutoff filtering can exploit the Operational Filter capabilities of the LTC1562. In this design, two external capacitors are added and the virtual-ground inputs of the LTC1562 sum parallel paths to obtain two notches in the stopband of a lowpass filter, as plotted in Figure 9. This response falls 80dB in one octave; the total output noise is 46VRMS and the Signal/ continued on page 32 5 DESIGN FEATURES An SMBus-Controlled 10-Bit, Current Output, 50A Full-Scale DAC by Ricky Chow 6 precision full-scale current is trimmed to 1.5% at room temperature and 2.5% over the commercial temperature range. There are two ways to shut down the LTC1427 (see Figure 2). A logic low at the SHDN pin or a logic high at bit 7 of the command byte sent through the SMBus interface will put the LTC1427 into shutdown mode. In shutdown mode, the digital data is retained internally and the supply current drops to only 12A typically. SMBus WRITE BYTE PROTOCOL, WITH SMBus ADDRESS = 0101111B, COMMAND BYTE = 0XXXXX11B AND DATA BYTE = 11111111B, AD1 = 0, AD0 =1 SDA COMMAND BYTE 0 1 0 1 1 1 1 1 2 3 4 5 6 7 8 X X X X X DATA BYTE 1 1 1 1 1 1 1 1 1 1 ACK SMBus ADDRESS ACK The LTC1427-50 communicates with external circuitry using the standard 2-wire I2C or SMBus interface. The operating sequence (Figure 1) shows the signals on the SMBus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors are required on these lines. The LTC1427-50 is a receiveonly (slave) device; the system master must apply the Write Byte protocol (Figure 1) to communicate with the LTC1427-50. The master places the LTC142750 in a START condition and transmits a 7-bit address. The write bit is then made 0. The LTC1427-50 acknowledges and the master transmits the command byte. The LTC1427 again acknowledges and latches the active bits of the command byte into register A (see the block diagram in Figure 2) at the falling edge of the acknowledge pulse. The master then sends the data byte; the LTC1427-50 acknowledges receipt of the data byte; and, finally, the 8-bit data byte and the last two output bits (the two MSBs of the 10-bit input data) from register A are latched into the register C at the falling edge of the final acknowledge and the DAC current output assumes the new 10-bit value. A stop condition is optional. The LTC1427-50 can respond to one of four 7-bit addresses. The first five bits have been factory pro- SHDN Description grammed and are always 01011. The last two LSB address bits are programmed by the user via AD1 and AD0 (Table 1). When AD1 and AD0 are both connected to VCC, upon power up, the 10-bit internal register C is reset to 1000000000B and the DAC output is set to midrange. If either AD1 or AD0 is connected to ground, at power-up, register C resets to 0000000000B and the DAC output is set to zero. For the LTC1427-50, the source current output (IOUT) can be biased from -15V to (VCC - 1.3V); WR ACK The LTC1427-50 is a 10-bit, current-output DAC with an SMBus interface. This device provides precision, full-scale current of 50A 1.5% at room temperature (2.5% over temperature), wide output voltage DC compliance (from -15V to (VCC - 1.3V)) and guaranteed monotonicity over a wide supply-voltage range. It is an ideal part for applications in contrast/brightness control or voltage adjustment in feedback loops. SCL S 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 IOUT S = START P = STOP *OPTIONAL P FULL-SCALE CURRENT ZERO-SCALE CURRENT 1427_01.EPS Figure 1. LTC1427-50 operating sequence SHDN POWER-ON RESET SHDN SCL SDA SMBus INTERFACE 3 REGISTER A 3-BIT LATCH EN1 1 REGISTER B 1-BIT LATCH SD EN2 2 REGISTER C 8 SD VOLTAGE REFERENCE RADJ 10-BIT LATCH SD 10 EN2 AD0 AD1 10-BIT CURRENT DAC IOUT 1427_02.EPS Figure 2. LTC1427-50 block diagram Table 1. LTC1427-50 function table AD1 AD0 SMBus Address Location DAC Power-Up Value Application L L 0101101 Zero-scale LCD Backlight Control L H 0101111 Zero-scale General Purpose H L 0101110 Zero-scale General Purpose H H 0101100 Mid-scale LCD Contrast Control Linear Technology Magazine * February 1998 DESIGN FEATURES D1 L1 VOUT* 6 5 VIN 2-4 CELLS R1 226k 1% SW LT1317 SHDN 1F 3 SHDN FB GND 4 LTC1427-50 2 1 R2 12.1k 1% VC 1 2 3 C1 1F 4700pF 100k Digitally Controlled CCFL Current Using the SMBus Interface VCC = 3.3V 4 Figure 4 is a schematic of a 90% efficient, digitally controlled floating CCFL lamp supply using the SMBus serial interface. The DAC current output is connected to the ICCFL pin of LT1184F. With the DAC output current range of 0A to 50A, this circuit gives 0mA to 6mA lamp current for a typical display. Varying the lamp current from its minimum to maximum level adjusts the lamp intensity, and hence, the display brightness. P SHDN VCC AD1 IOUT AD0 SCL GND SDA 8 (e.g., 8051) 7 6 P1.2 5 P1.1 P1.0 *VOUT = 12.7V-24V IN 11mV STEPS 15mA FROM 2 CELLS 35mA FROM 3 CELLS L1 = 10H (SUMIDA CD43 MURATA-ERIE LQH3C OR COILCRAFT DO1608) D1 = MBR0530 Figure 3. Digitally controlled LCD bias generator Conclusion Digitally Controlled LCD Bias Generator Figure 3 is a schematic of a digitally controlled LCD bias generator using a standard SMBus 2-wire interface. The LT1317 is configured as a boost converter, with the output voltage (VOUT) determined by the values of the feedback resistors, R1 and R2. The LTC1427-50's DAC current output is connected to the feedback node of the LT1317. The LTC1427-50's DAC current output increases or decreases according to the data sent via the SMBus. As the DAC output current varies from 0A to 50A, the output voltage is controlled over the range of 12.7V to 24V. A 1LSB change in the DAC output current corresponds to an 11mV change in the output voltage. LAMP AN ALUMINUM ELECTROLYTIC WITH AN ESR 0.5 IS RECOMMENDED FOR C3B TO PREVENT DAMAGE TO THE LT1184F HIGH-SIDE SENSE RESISTOR DUE TO SURGE CURRENTS AT TURN-ON. R3 100k Q2* C1* 0.1F 1 CCFL PGND 12 VIN 3 DIO C7 4 CCFL VC 1F 5 AGND 7 NC 8 NC 9 NC CCFL 16 VSW 15 BULB 14 BAT 13 ROYER 11 REF 10 NC 6 SHDN 2 ICCFL VCC 3.3V + VBAT C3A 8V-28V 2.2F 35V R1 750 D1 1N5818 LTC1427-50 1 7 2 3 SHDN 5 Q1* L2 100H LT1184F 4 C3B 2.2F 35V R2 220k *DO NOT SUBSTITUTE COMPONENTS + 1 + L1 = COILTRONICS CTX210605 L2 = COILTRONICS CTX100-4 COILCTRONICS (561) 241-7876 C4 2.2F 0A-50A ICCFL CURRENT GIVES 0mA-6mA LAMP CURRENT FOR A TYPICAL DISPLAY L1 2 3 Q1, Q2 = ZETEX ZTX849 OR ROHM C5 2SC5001 1000pF VIN 3.3V C2 27pF 3kV 6 10 C1 MUST BE A LOW LOSS CAPACITOR (WIMA MKP-20) D5 BAT85 The LTC1427-50 is a precision 10-bit, 50A full-scale DAC that communicates directly with an I2C or SMBus interface. It operates from a wide supply range, consumes low power, has guaranteed monotonicity and is packaged in a popular SO-8. It is ideal for applications such as contrast/ brightness controls, output voltage adjustment in power supplies and other potentiometer applications. SHDN SDA IOUT SCL AD1 GND AD0 VCC 5 6 4 } SMBus TO HOST 8 C6 0.1F Figure 4. 90% efficient digitally controlled floating CCFL supply using the SMBus serial interface Linear Technology Magazine * February 1998 7 DESIGN FEATURES Micropower 600kHz Fixed-Frequency DC/DC Converters Step Up from a 1-Cell or 2-Cell Battery by Steve Pietkiewicz Linear Technology introduces two new micropower DC/DC converters designed to provide power from a single-cell or higher input voltage. The LT1308 features an onboard switch capable of handling 2A with a voltage drop of 300mV and operates from an input voltage as low as 1V. The LT1317, intended for lower power requirements, operates from an input voltage as low as 1.5V. Its internal switch handles 600mA with a drop of 360mV. Both devices feature Burst Mode operation at light load; efficiencies are above 70% for load currents of 1mA. Both devices switch at 600kHz; this high frequency keeps associated power components small and flat; additionally, troublesome interference problems in the sensitive 455kHz IF band are avoided. The LT1308 is intended for generating power on the order of 2W-5W. This is sufficient for RF power amplifiers in GSM or DECT terminals or for digitalcamera power supplies. The LT1317, with its smaller switch, can generate 100mW to 2W of power. The LT1317 is available in LTC's smallest 8-lead package, the MSOP. This package is approximately one-half the size of a standard 8-lead SO package. The LT1308 is available in the 8-lead SO package. Single Li-Ion Cell to 5V/1A DC/DC Converter for GSM GSM terminals have emerged as a worldwide standard. A common requirement for these products is an efficient, compact, step-up converter to develop 5V from a single Li-Ion cell to power the RF amplifier. The LT1308 performs this function with a minimum of external components. The circuit is detailed in Figure 1. Many designs use a large aluminum electrolytic capacitor (1000F to 3300F) at the DC/DC converter output to hold up the output voltage during the transmit time slice, since the amplifier can require more than 1A. The 3V TO 4.2V SHDN VIN LBI SW C1 100F LBO NiCD CELL 5V 1A FB VC C1 10F LBO R2 100k + + C2 100F 3.3V 400mA R2 100k + C1: CERAMIC C2: AVX TPS SERIES D1: IR 10BQ015 L1: COILTRONICS CTX5-1 COILCRAFT DO3316-472 1308_01,eps Figure 1. Single Li-Ion cell to 5V/1A DC/DC converter C2 100F 1308_04.eps Figure 4. Single NiCd cell to 3.3V/400mA DC/DC converter 90 95 V IN = 3.6V VIN = 1.2V VOUT = 3.3V R1 = 169k 85 V IN = 4.2V 80 VOUT 200mV/DIV AC COUPLED 85 EFFICIENCY (%) 90 EFFICIENCY (%) D1 GND RC 47k CC 22nF 2200F C1,C2: AVX TPS SERIES D1: INTERNATIONAL RECTIFIER 10BQ015 L1: COILTRONICS CTX5-1 COILCRAFT DO3316-472 80 V IN = 3V 75 INDUCTOR CURRENT 1A/DIV 70 75 70 65 60 1ms/DIV 65 R1 169k FB VC GND RC 47k CC 22nF SW LT1308 D1 L1 4.7H VIN SHDN LBI R1 301k LT1308 Li-Ion CELL L1 4.7H 55 50 1 10 100 LOAD CURRENT (mA) 1 1000 10 100 LOAD CURRENT (mA) 1000 1308 G01 1308 F01a Figure 2. Efficiency of Figure 1's circuit reaches 90% 8 Figure 3. Transient response of DC/DC converter: VIN = 3V, 0A-1A load step Figure 5. Efficiency of Figure 4's circuit reaches 81% Linear Technology Magazine * February 1998 DESIGN FEATURES VOUT 200mV/DIV AC COUPLED VOUT 200mV/DIV AC COUPLED IL1 1A/DIV ILOAD 400mA 50mA ILOAD 400mA 50mA 100s/DIV 20ms/DIV Figure 6. DECT load transient response: with a single NiCd cell, the LT1308 provides 3.3V with a 400mA pulsed load. The pulse width = 416s. output capacitor, along with the LT1308 compensation network, serves to smooth out the input current demanded from the Li-Ion cell. Efficiency, which reaches 90%, is shown in Figure 2. Transient response of a 0A to 1A load step with typical GSM profiling (1:8 duty cycle, 577s pulse duration) is depicted in Figure 3. Voltage droop (top trace) is 200mV. Inductor current (bottom trace) increases to 1.7A peak; the input capacitor supplies some of this current, with the remainder drawn from the Li-Ion cell. Efficiency, reaching 81% from a 1.2V input, is pictured in Figure 5. Transient response of a typical DECT load of 50mA to 400mA is detailed in Figure 6. Output voltage droop (top trace) is under 200mV. Figure 7 zooms in on a single pulse to show the output voltage and inductor current responses more clearly. 2-Cell Digital Camera Supply Produces 3.3V, 5V, 18V and -10V Power supplies for digital cameras must be small and efficient while generating several voltages. The DSP and logic need 3.3V, the ADC and LCD display need 5V and biasing for the CCD element requires 18V and -10V. The power supplies must also be free of low frequency noise, so that postfiltering can be done easily. The obvious approach, to use a separate DC/DC converter IC for each output voltage, is not cost-effective. A single Single NiCd Cell to 3.3V/ 400mA Supply for DECT Only minor changes are required in Figure 1's circuit to construct a singlecell NiCd to 3.3V converter. The large output capacitor is no longer required as the output current can be handled directly by the LT1308. Figure 4 shows the DECT DC/DC converter circuit. 8 VIN C1 + 100F C6 10F 2 SW VC C8 1nF R4 47k C7 22nF 90 3 L1C 3 N = 0.3 R3 340k SHDN LT1308 85 L1B N = 0.7 D1 D2 4 FB GND R1 100k R2 2.01M 80 5V 200mA + C2 100F + 3.3V 200mA C3 100F D3 CCD BIAS 18V 10mA 7 L1D N = 3.5 + 6 D1, D2 = IR 10BQ015 D3, D4 = BAT-85 L1 = COILTRONICS CTX02-13973 + L1E N=2 5 1308_08.eps D4 Figure 8. This digital camera power supply delivers 5V/200mA, 3.3V/200mA, 18V/ 10mA and -10V/10mA from two AA cells. Linear Technology Magazine * February 1998 C4 10F 100mA LOADS 75 70 65 150mA LOADS 60 6 C1, C2, C3 = AVX TPS C4, C5 = AVX TAJ C6 = CERAMIC LT1308, along with an inexpensive transformer, generates 3.3V/200mA, 5V/200mA, 18V/10mA and -10V/ 10mA from a pair of AA or AAA cells. Figure 8 shows the circuit. A coupledflyback scheme is used, actually an extension of the SEPIC (single ended primary inductance converter) topology. The addition of capacitor C6 clamps the SW pin, eliminating a snubber network. Both the 3.3V and 5V outputs are fed back to the LT1308 FB pin, a technique known as split feedback. This compromise results in better overall line and load regulation. The 5V output has more influence than the 3.3V output, as can be seen from the relative values of R2 and R3. Transformer T1 is available from Coiltronics, Inc. (561-241-7876). Efficiency vs input voltage for several load currents on both 3.3V and 5V outputs is pictured in Figure 9. The CCD bias voltages are loaded with 10mA in all cases. EFFICIENCY (%) VIN 1.6V TO 6V L1A N=1 10H 1 Figure 7. DECT load transient response: faster sweep speed (100s/DIV) details VOUT and inductor current of a single DECT transmit pulse. C5 10F CCD BIAS -10V 10mA 200mA LOADS 55 50 1 1.5 2 2.5 3 3.5 4 INPUT VOLTAGE (V) 4.5 5 1308_09.EPS Figure 9. Camera power supply efficiency reaches 78%. 9 DESIGN FEATURES LT1317 2-Cell to 5V DC/DC Converter Figure 10 shows a simple 2-cell to 5V DC/DC converter using the LT1317. This device generates a clean, low ripple output from an input voltage as low as 1.5V. Designed for 2-cell applications, it offers better performance than its 1-cell predecessor, the LT1307. More gain in the error amplifier results in lower Burst Mode ripple, and an internal preregulator eliminates oscillator variation with input voltage. For comparison, Figure 11 details transient responses of both the LT1307 and the LT1317 generating 5V from a 3V input. The load step is 5mA to 200mA. Output capacitance in both cases is 33F. The LT1307 has low frequency ripple of 100mV, whereas the LT1317 Burst Mode ripple of 20mV is the same as the 600kHz ripple resulting from the output capacitor's ESR with a 200mA load. pass through C1. Since C1 is ceramic, its ESR is low and there is no appreciable efficiency loss. C5 is charged to -VOUT when the switch is off, then its bottom plate is grounded when the switch turns on. The negative output is fairly well regulated, since the diode drops tend to cancel. The circuit is switching continuously at rated load, where efficiency is 75%. Output ripple is under 40mV and can be reduced further with conventional postfiltering techniques. Single Li-Ion Cell to 4V DC/DC Converter By again employing the SEPIC topology, a 4V supply can be designed with one IC. Figure 12's circuit generates 4V at 70mA and -4V at 10mA from an input voltage ranging from 2.5V to over 5V. Maximum component height is 2mm. This converter uses two separate inductors (L1 and L2), so it is an uncoupled SEPIC converter. This reduces the overall cost, but requires that all output current Conclusion The LT1308 and LT1317 provide low noise compact solutions for contemporary portable-product power supplies. SHUTDOWN SW LBI 2 CELLS C1 10F 10V VOUT LT1307 100mV/DIV 5V OFFSET L1 22H VIN SHDN R1 1M LT1317 LBO D1 VC VOUT LT1317 100mV/DIV 5V OFFSET 5V 200mA FB GND R2 324k 1% RC 100k CC 680pF + C2 33F ILOAD 200mA 5mA 500s/DIV C1: CERAMIC D1: MOTOROLA MBRO520L L1: 22 H SUMIDA CD43-220 1308_10.eps Figure 11. The LT1317 has reduced Burst Mode ripple compared to the LT1307. Figure 10. 2-cell to 5V boost converter using the LT1317 D2A D2B -VOUT -4V/10mA VIN 2.5V-5V C5 1F SHDN SHUTDOWN C1 10F SW VIN C3 15F LB1 LT1317 D1 R1 1M +VOUT 4V/70mA FB LB0 VC C4 1F + L1 22H GND + R3 47k R2 442k C2 33F L2 22H C6 680pF L1, L2 =MURATA LQH3C220 C1 =MURATA GRM235Y5V106Z01 D1 =MBR0520 D2 =BAT54S (DUAL DIODE) C2 =AVX TAJB33M6010 C3 =AVX TAJA156MO1O C4, C5 =CERAMIC Figure 12. This single Li-Ion cell to 4V DC/DC converter has a maximum height of 2mm. 10 Linear Technology Magazine * February 1998 DESIGN FEATURES New 333ksps, 16-Bit ADC Offers 90dB SINAD and -100dB THD by Marco Pan 333ksps throughput 16 bits with no missing codes and 2LSB INL Low power dissipation and power shutdown Excellent AC and DC performance Small package--36-pin SSOP These features of the LTC1604 can simplify, improve, and lower the cost 2.0 1.5 INL (LSB) 1.0 0.5 0.0 -0.5 PRECISION 16-BIT DAC COMPARATOR +AIN SAMPLE/ HOLD CIRCUIT - AIN VREF (2.50V) 7.5k SAR -1.5 -16384 0 16384 32767 CODE 1604_02. eps Figure 2. The LTC1604 is very accurate, as shown in the INL error plot. This accuracy is achieved without autocalibration and its associated overhead. Accuracy relies on capacitor matching, which is very stable over temperature and time. Linear Technology Magazine * February 1998 OUTPUT BUFFER 16 16 LOW DRIFT VOLTAGE REFERENCE REFCOMP (4.375V) CLOCK CONTROL LOGIC SHDN RD BUSY CONVST CS Figure 1. LTC1604 block diagram of current data acquisition systems and open up new applications that were not previously possible because no similar part was available. Fast Architecture To achieve 333ksps with outstanding AC and DC performance at the 16-bit level, careful design is required. Figure 1, the LTC1604 block diagram, illustrates the design of this part. A high performance differential sampleand-hold circuit, combined with an extremely fast successive-approximation ADC and an on-chip reference, delivers an excellent combination of AC and DC performance. A digital interface allows easy connection to microprocessors, FIFOs or DSPs. Outstanding AC and DC Performance -1.0 -2.0 -32768 LTC1604 The DC specifications include 16 bits with no missing codes and 2LSB integral nonlinearity error guaranteed over temperature. The gain of the ADC is held nearly constant over temperature with an on-chip 10ppm/C (typical) curvature-corrected bandgap reference. Figures 2 and 3 show INL and DNL error plots, respectively, for the LTC1604. The sample-and-hold circuit determines the dynamic performance of the ADC. The LTC1604 has a wide bandwidth, very low distortion, differential sample-and-hold. Fast Fourier transform (FFT) test techniques are used to test the LTC1604's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral 1.0 0.8 0.6 0.4 DNL (LSB) The fastest, highest performance 16-bit sampling ADC is now available in a tiny 36-pin SSOP package from Linear Technology. It is the LTC1604. This device runs at 333ksps and delivers excellent DC and AC performance. The LTC1604 operates on 5V supplies and typically draws only 220mW. It is a complete differential, high speed, low power, 16-bit sampling ADC that requires no external components. The LTC1604 also provides two power shutdown modes, NAP and SLEEP, to reduce power consumption during inactive periods. This 333ksps, 16-bit device not only offers the performance of the best hybrids but also provides low power, small size, an easy-to-use interface and the low cost of a monolithic part. Some of the key features of this new device include: 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -32768 -16384 0 16384 32767 CODE 1604_03. eps Figure 3. The differential nonlinearity error plot shows the excellent performance of the LTC1604. 11 DESIGN FEATURES 0 fSAMPLE = 333kHz -20 -40 SINAD = 90.2dB -60 THD = -103.2dB -80 2000 fIN = 97.152kHz AMPLITUDE (dB) fIN = 4.959kHz -40 SINAD = 89.0dB 1500 -60 COUNT -20 AMPLITUDE (dB) 2500 0 fSAMPLE = 333kHz THD = -96dB -80 -100 -100 -120 -120 1000 500 0 -140 0 20 40 60 80 100 120 140 160 FREQUENCY (kHz) 0 20 40 60 FREQUENCY (kHz) 1604_04.EPS Figure 4. This FFT of the LTC1604's conversion of a full-scale 5kHz sine wave shows outstanding response with a very low noise floor when sampling at 333ksps. content can be examined for frequencies other than the fundamental. Figures 4 and 5 show the excellent AC performance of the LTC1604 at 333ksps with fIN = 5kHz and 100kHz, respectively. The AC performance of the LTC1604 include total harmonic distortion of -100dB for a 5kHz input and -94dB for a 100kHz input and an input bandwidth of 15MHz for the sample-and-hold. Very Low Noise The noise of an ADC can be evaluated in two ways: by signal-to-noise ratio (SNR) in the frequency domain and by histogram in the time domain. The LTC1604 excels in both. Figure 4 demonstrates that the LTC1604 has a SNR of over 90dB in the frequency domain. The noise in the time-domain histogram is the transition noise associated with a high resolution ADC, which can be measured with a fixed DC signal applied to the input of the ADC. The resulting output codes are collected over a large number of conversions. The shape of the distribution of codes will give an indication of the magnitude of the transition noise. In AIN SINGLE-INPUT ADC 0 1 CODE 2 Figure 6, the distribution of output codes is shown for a DC input that has been digitized 4096 times. The distribution is Gaussian and the RMS code transition noise is about 0.66LSB. This corresponds to a noise level of 90.9dB relative to full scale. When added to the theoretical 98dB of quantization error for a 16-bit ADC, this yields an SNR of 90.1dB, which correlates very well with the frequency domain measurements. Differential Inputs Ignore Common Mode Noise Getting a clean signal to the input(s) of an ADC, especially a 16-bit ADC, is not an easy task in many systems. Large noise signals from EMI, the AC power line and digital circuitry are usually present. Filtering and shielding are the common techniques for reducing noise, but these are not always adequate (see "The Care and Feeding of High Performance ADCs: Getting All the Bits You Paid For"; Linear Technology VI:3 [August, 1996]). The LTC1604 offers another tool to fight noise: differential inputs. +AIN SIGNAL TO BE MEASURED LTC1604 AGND AGND 3 4 5 1604_06.eps 1604_05.EPS Figure 5. Even with inputs at 100kHz, the LTC1604's dynamic linearity remains robust. -AIN SIGNAL TO BE MEASURED -5 -4 -3 -2 -1 80 100 120 140 160 Figure 6. This histogram shows that the LTC1604 has an RMS code transition noise of 0.66dB. Figure 7a depicts a typical singleended sampling system with ground noise, which may be 60Hz noise, digital clock noise or some other type of noise. When a single-ended input is used, the ground noise adds directly to the input signal. By using the differential inputs of the LTC1604 the ground noise can be rejected by connecting the inputs directly across the signal of interest, as shown in Figure 7b. Ground noise becomes "common mode" and is rejected internally by the LTC1604 by virtue of its excellent common mode rejection ratio (CMRR). Figure 8 shows the CMRR of the LTC1604 versus frequency. Notice that the CMRR is constant over the entire Nyquist bandwidth and is only 6dB lower at 300kHz. This ability to reject high frequency common mode signals is very helpful in sampling systems, where noise often has high frequency components due to switching transients. 70 COMMON MODE REJECTION (dB) -140 60 50 40 30 20 10 0 GROUND NOISE Figure 7a. Single-input ADC measuring a signal riding on common mode noise. 12 GROUND NOISE Figure 7b. Differential-input ADC measuring a signal riding on common mode noise. 0 10 100 INPUT FREQUENCY (kHz) 1000 1604_08.eps Figure 8. LTC1604 CMRR vs frequency Linear Technology Magazine * February 1998 DESIGN FEATURES 98 The LTC1604 operates on 5V supplies, which makes the device easy to interface to 5V digital systems. This device can also talk to 3V digital systems: the digital input pins (SHDN, CS, CONVST and RD) of the LTC1604 recognize 3V or 5V inputs. The LTC1604 has a dedicated output supply pin (OVDD) that controls the output swings of the digital output pins (D0- D15, BUSY) and allows the part to talk to either 3V or 5V digital systems. 92 14 86 13 80 Low Power Dissipation and Shutdown The LTC1604 runs at full speed on 5V supplies and typically draws only 220mW. This power consumption can be reduced further by using the two power shutdown modes, NAP and SLEEP, during inactive periods. NAP mode cuts down the power to 8mW, leaving the reference and logic powered up. The ADC wakes up "instantly" (400ns) from NAP mode, so NAP mode can be invoked even during brief inactive periods with no penalty or delay when conversions must start again. SLEEP mode is used when there are extended inactive periods. In SLEEP mode, the ADC powers down all the circuitry, leaving the logic outputs in a high impedance state. The only current that remains is junction-leakage current (less than 1A). It takes much longer for the ADC to wake up from SLEEP mode because the reference circuit must power up EFFECTIVE BITS 16 15 12 74 11 68 10 62 9 56 8 0 10 100 FREQUENCY (kHz) SINAD (dB) 3V Input/Output Compatible 50 1000 1604_09.eps Figure 9. The LTC1604 has essentially flat SINAD and effective bits out to Nyquist. and settle to 0.0006% for full accuracy. The wake-up time also depends on the value of the compensation capacitor used on the REF COMP pin. With the recommended 47F capacitor, the wake-up time is 160ms. Applications The performance of the LTC1604 makes it very attractive to use in a wide variety of applications, such as digital signal processing, PC data acquisition cards, medical instrumentation and high resolution or multiplexed data acquisition. DSP applications often require excellent dynamic performance, since the ADC must sample high frequency AC signals. The LTC1604 is the right choice in these types of applications because of the performance of its sample-and-hold. Figure 9 shows how well the signal-to-noise plus distortion ratio and the spurious free dynamic range of the converter hold up as the input frequency is increased. Another common application is PC data acquisition cards. The high sample rate, the simple, complete configuration and excellent linearity of the LTC1604 make it an ideal choice here. Another advantage that the LTC1604 provides is the synchronized internal conversion clock, which is very useful in this application. This feature eliminates the second external clock required by other sampling ADCs to run conversion, in addition to the normal sample signal. Clearly, this feature makes the LTC1604 an outstanding choice for PC data acquisition cards. For single-channel or multiplexed high speed data acquisition systems, the LTC1604 has the high sample rate and high impedance inputs that help smooth the design of these applications. High sample rates allow more channels in the data acquisition system on a very low power and cost budget and the high impedance inputs of the ADC make them very easy to multiplex. Conclusion The new LTC1604 is a complete 16-bit ADC with a built-in sample-and-hold and reference. It samples at 333ksps and is the fastest device of its kind on the market. The excellent DC and AC performance of the LTC1604 not only make it extremely valuable in a wide variety of existing high resolution applications while also opening up new applications. for the latest information on LTC products, visit www.linear-tech.com Linear Technology Magazine * February 1998 13 DESIGN FEATURES Ultralow Power 14-Bit ADC Samples at 200ksps High Impedance Inputs A new, versatile 14-bit ADC, the LTC1418, can digitize at 200ksps while consuming only 15mW from a single 5V supply. The LTC1418 is designed to be easy to use and adaptable, requiring little or no support circuitry in a wide variety of applications. Some of the key features of this new device include: 200ksps throughput Low power--15mW Single 5V or 5V supplies 1.25LSB INL max and 1LSB DNL max Parallel and serial data output modes NAP and SLEEP power shutdown modes Small package--28-pin SSOP High Performance without High Power Figure 1 shows a block diagram of the LTC1418. This device includes a high performance differential sample-andhold circuit, an ultra-efficient successive approximation ADC, an on-chip reference and a digital interface that allows easy serial or parallel interface to a microprocessor, FIFO or DSP. The LTC1418 is factory calibrated, so a lengthy calibration cycle is not required to achieve 14-bit performance. DC specifications include a 1LSB max differential linearity error (no missing codes) and 1.25LSB max integral linearity error guaranteed over temperature. The gain of the ADC is controlled by an on-chip 10ppm/C reference that can be easily overdriven with an external reference if required. For AC applications, the dynamic performance of the LTC1418 is exceptional. The extremely low distortion differential sample-and-hold acquires input signals at frequencies up to 10MHz. At the Nyquist frequency, 100kHz, the spurious free dynamic range is typically 95dB. The noise is also low with a signal-tonoise ratio (SNR) of 82dB from DC to well beyond Nyquist. The superior AC and DC performance of the LTC1418 doesn't require a lot of power. In fact, the LTC1418 has the lowest power of any 14-bit ADC available, just 15mW at 200kHz (10mW at sample rates below 50kHz). Two shutdown modes make it possible to cut power further at lower sample rates. The LTC1418's high impedance inputs allow direct connection of high impedance sources without introducing errors. Many ADCs have a resistive input or input bias current that requires low source impedance to achieve low errors. Other ADCs with switched capacitor inputs exhibit large offset shifts when driven with high source impedance or a large sourceimpedance imbalance between their differential inputs. The unique sample-and-hold circuit of the LTC1418 has a low capacitance, high resistance (10M||25pF) switchedcapacitor input that has only 2LSB of offset shift with a source impedance imbalance between 0 and 1M (see Figure 2a). (There is no shift if the input impedance is equal for +AIN and 10 CHANGE IN OFFSET VOLTAGE (LSB) Introduction by Dave Thomas 8 5 4 2 0 100 10k 100k 1M 1k SOURCE IMPEDANCE MISMATCH (OHMS) 1418_02a.EPS 5V Figure 2a. Change in offset voltage with source impedance mismatch 10F VDD D13 AIN+ S/H 14-BIT ADC 14 AIN - 4.096V SELECTABLE SERIAL/ PARALLEL PORT BUFFER 8k VREF D3 (SCLK) D2 (CLKOUT) D0 (EXT/INT) TIMING AND LOGIC 2.5V REFERENCE 1F AGND VSS (0V OR - 5V) BUSY CS RD CONVST SHDN DGND Figure 1. LTC1418 block diagram 14 D4 (EXTCLKIN) D1 (DOUT) REFCOMP 10F D5 1418 TA01 MAXIMUM SAMPLE RATE (SAMPLES/SEC) SER/PAR LTC1418 200k 100k 10k 1k 1k 100k 10k SOURCE RESISTANCE (OHMS) 1M 1418_02b.EPS Figure 2b. Maximum sample rate vs unbuffered source resistance Linear Technology Magazine * February 1998 DESIGN FEATURES -AIN.) Connecting the ADC directly to a high impedance source avoids additional noise and offset errors that may be introduced by buffering circuitry. The only downside to directly connecting the ADC to a high source impedance is that the acquisition time will increase. The low input capacitance (20pF) of the LTC1418 allows full-speed operation with resistances up to 2k. Above 2k the sample rate must be lowered (see Figure 2b). Differential Inputs with Wideband CMRR On-Chip Reference The differential input of the LTC1418 has excellent common mode rejection, eliminating the need for some input-conditioning circuitry. Op amps and instrumentation amplifiers are often used to reject common mode noise from EMI, AC power and switching noise. Although these circuits perform well at low frequencies, their rejection at high frequencies deteriorates substantially. Figure 3 shows the CMRR of the LTC1418 vs frequency. Single-Supply or Dual-Supply Operation Single-supply ADCs can be cumbersome to work with in a dual-supply system. A signal with a common mode of zero volts has to be shifted up to the common mode of the ADC. Shifting the common mode can be accomplished with AC coupling, but DC information is lost. Alternatively, an op amp level shifter can be used, but this adds circuit complexity and COMMON MODE REJECTION (dB) The on-chip reference of the LTC1418 is a standard 2.5V and is compatible with many system references; it is available on the REF output (pin 3). An internal amplifier boosts the 2.5V reference up to 4.096V; this sets the span for the ADC. The 4.096V output is available on the REFCOMP output (pin4) and may be used as a reference for other external circuitry. With a temperature coefficient of 10ppm/C, both REF and REFCOMP are suited to serve as the master reference for the system. However, if an external reference circuit is required, its easy to overdrive either reference output. The 2.5V reference output is resistive (4k) and can be easily overdriven by any reference with low output impedance by directly connecting the external reference to the REF pin. If REFCOMP (the 4.096V reference) is to be overdriven, tie the REF pin to ground. This disables the output drive of the REFCOMP amplifier, allowing it to be easily overdriven. Parallel Data Output for High Speed 100 80 60 40 20 0 additional errors. The LTC1418 can operate with single or dual supplies and allows direct coupling to the inputs in both cases. The ADC is equipped with circuitry that automatically detects when -5V is present at the VSS pin. With a -5V supply, the ADC operates in bipolar mode and the full-scale range becomes 2.048V for +AIN with respect to -AIN. With a single supply, VSS = 0V and the ADC operates in unipolar mode with an input range of 0V to 4.096V. 1k 100k 10k INPUT FREQUENCY (Hz) 1M 1418_03.EPS Figure 3. Input common mode rejection vs input frequency Linear Technology Magazine * February 1998 The parallel output mode of the LTC1418 allows the lowest digital overhead. A microcontroller can strobe the ADC to start the conversion and perform other tasks while the conversion is running. The ADC will then signal the microcontroller after the conversion is complete with the BUSY signal, at which time valid data is available on the parallel output bus. BUSY may also be used to clock latches or a FIFO directly, since data is guaranteed to be valid with the rising edge of BUSY. Serial Data Output for Minimal Wiring The serial output mode of the LTC1418 is simple, requiring just three pins for data transfer: a data-out pin, a serial clock pin and a control pin. However, its simplicity doesn't sacrifice flexibility. Serial data can be clocked with the internal shift clock for minimal hardware or an external shift clock for synchronization. Additionally, data can be clocked out during the conversion for the highest throughput rate or after the conversion for maximum noise immunity. Perfect for Telecom: Wide Dynamic Range Telecommunications systems require wide dynamic range. With its low noise and low distortion, the LTC1418 offers extremely wide dynamic range over its entire Nyquist bandwidth. Spurious free dynamic range is typically 95dB and only starts to drop off at input frequencies above Nyquist. The ultralow jitter of the sample-andhold circuit, 5psRMS, keeps the SNR flat from DC to 1MHz, making this device useful for undersampling applications. Another important requirement for telecom systems is a low error rate. In any ADC, there is a finite probability that a large conversion error (greater than 1% of full scale) will occur. In video or flash converters, these large errors are called "sparkle codes." Large errors are a problem in telecom systems such as ISDN, because they result in errors in data transmission. All ADCs have a rate at which errors occur, referred to as the error rate. The error rate is dependent on the ADC architecture, design and process. Error rates vary greatly and can be as low as 1 in 10 billion to as high as 1 is 1 million. Telecom systems typically require error rates to be 1 in 1 billion or better. The LTC1418 is designed to have ultralow error rates. The error rate is so low that it is difficult to measure because of the time in between errors. To make measurement more practical, the error rate was measured at an elevated temperature of 150C, 15 DESIGN FEATURES 15mW 5V IDD CONVST = SHDN 0V CONVST IDD LTC1418 3mA SHDN POWER DISSIPATION 5V 0 CONVERSION TIME NAP CS NAP WAKE-UP AND AQUISITION TIME 2mW 1k 1418_04a.EPS 10k SAMPLE RATE (SPS) 100k 200k 1418_04b.EPS Figure 4a. NAP mode between conversions because error rate increases with temperature. Even at this high temperature, the error rate was 1 in 100 billion. The projected error rate at room temperature is 1 in 2,000,000 billion or about 1 error every 320 years if running at full conversion rate. Ideal for Low Power Applications LTC1418 is especially well suited for applications that require low power and high speed. The normal operating power is low--only 15mW. Power may be further reduced if there are extended periods of time between conversions. During these inactive periods when the ADC is not converting, the LTC1418 may be shut down. There are two power shutdown modes: NAP and SLEEP. NAP mode shuts down 85% of the power and leaves only the reference and logic powered up. The LTC1418 can wake up from NAP mode very quickly; in just 500ns it can be ready to start converting. In NAP mode, all data-output control is functional; data from the last conversion prior to starting NAP mode can be read during NAP mode. RD also controls the state of the output buffers. NAP mode is useful for applications that must be ready to immediately take data after long inactive periods. With slow sample rates, power can be saved by automatically invoking NAP mode between conversions. Referring to Figure 4, the SHDN pin and CONVST pin are driven together. A conversion will be started with the falling edge of this signal; once the conversion is completed, the ADC will automatically shut down. Before the next conversion can start, the CONVST and SHDN pins must be brought high early enough to allow for the 500ns wake-up time. Power drops with the sample frequency until it approaches the power of the reference circuit, about 2mW at frequencies less than 10kHz. The SLEEP mode is used when the NAP-mode current drain is too high or if wake-up time is not critical. In Figure 4b. Power dissipation vs sample rate with NAP mode between conversions SLEEP mode, all bias currents are shut down, the reference is shut down and the logic outputs are put in a high impedance state. The only current that remains is junction leakage current, less than 1A. Wake-up from the SLEEP mode is much slower, since the reference circuit must power up and settle to 0.01% for full accuracy. The wake-up time is also dependent on the value of the compensation capacitor used on the REFCOMP pin; with the recommended 10F capacitor the wake up time is 10ms. SLEEP mode is useful for long inactive periods, that is, times greater than 10ms. Conclusion The new LTC1418 low power, 14-bit ADC will find uses in many types of applications, from industrial instrumentation to telephony. The LTC1418's adaptable design reduces the need for expensive support circuitry. This can result in a smaller, lower cost system. Authors can be contacted at (408) 432-1900 16 Linear Technology Magazine * February 1998 DESIGN FEATURES A 10MB/s Multiple-Protocol Chip Set Supports Net1 and Net2 Standards by David Soo Introduction Typical Application With the increase in multinational computer networks comes the need for the network equipment to support different serial protocols. One solution is to provide a different serial interface board for each market. This can become unmanageable as product volume increases. The issues of board swapping and inventory are often discounted. Another solution is to place all of the serial interfaces, each isolated, on a single board. For example, when the product is sold with V.35, the serial cable is mapped to that section of the board. This requires a large connector plus signal routing and board space. The best solution is to support many different serial protocols on one connector, but that requires the circuitry for each serial protocol to share the same connector pins. At first glance this may not appear to be difficult. Further examination reveals conflicting line-termination standards that require resistors to be switched to the connector pins. As the designer becomes occupied with the details of the interface specification, there is always the possibility that one small detail will be missed. This compliance headache causes designers to seek out a cost-effective integrated solution. With the LTC1543, LTC1544 and LTC1344A, LTC has taken the integrated approach to multiple-protocol. It does not make sense to use a handful of standard interface parts when Net1 and Net2 compliance is guaranteed with the LTC1543, LTC1544 and LTC1344A. Detecon, Inc. documents this compliance in Test Report No. NET2/102201/97. With this chip set, network designers can concentrate on functions that increase the end-product value rather than on standards compliance. Like the LTC1343 software-selectable multiprotocol transceiver, introduced in the August, 1996 issue of Linear Technology , the LTC1543/LTC1544/ LTC1344A chip set creates a complete software-selectable serial interface using an inexpensive DB25 connector. The main difference between these parts is the division of functions: the LTC1343 can be configured as a data/clock chip or as a control-signal chip using the CTRL/ CLK pin, whereas the LTC1543 is a dedicated data/clock chip and the LTC1544 is a control-signal chip. The chip set supports the V.28 (RS232), V.35, V.36, RS449, EIA-530, EIA-530A and X.21 protocols in either DTE or DCE mode. Figure 1 shows a typical application using the LTC1543, LTC1544 and LTC1344A. By just mapping the chip pins to the connector, the design of the interface port is complete. The figure shows a DCE mode connection to a DB-25 connector. The LTC1543 contains three drivers and three receivers, whereas the LTC1544 contains four drivers and four receivers. The L TC1344A contains six switchable resistive terminators that are connected only to the high speed clock and data signals. When the interface protocol is Linear Technology Magazine * February 1998 Table 1. Mode pin functions LTC1543/LTC1544 Mode Name Not Used EIA-530A EIA-530 X.21 V.35 RS449/V.36 RS232/V.28 No Cable M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 changed via the mode selection pins, M2, M1 and M0, the drivers, receivers and line terminators are placed in their proper configuration. The mode pin functions are summarized in Table 1. There are internal 50A pullup current sources on the mode select pins, DCE/DTE and the INVERT pins. DTE vs DCE Operation The LTC1543/LTC1544/LTC1344A chip set can be configured for either DTE or DCE operation in one of two ways. The first way is when the chip set is a dedicated DTE or DCE port with a connector of appropriate gender. The second way is when the port has one connector that can be configured for DTE or DCE operation by rerouting the signals to the chip set using a dedicated DTE or DCE cable. Figure 1 is an example of a dedicated DCE port using a female DB-25 connector. The complement to this port is the DTE-only port using a male DB25 connector, as shown in Figure 2. If the port must accommodate both DTE and DCE modes, the mapping of the drivers and receivers to connector pins must change accordingly. For example, in Figure 1, driver 1 in the LTC1543 is connected to pin 3 and pin 16 of the DB-25 connector. In DTE mode, as shown in Figure 2, driver 1 is mapped to pins 2 and 14 of the DB25 connector. A port that can be configured for either DTE or DCE operation is shown in Figure 3. This configuration requires separate cables for proper signal routing. Cable-Selectable Multiprotocol Interface The interface protocol may be selected by simply plugging the appropriate interface cable into the connector. A cable-selectable multiprotocol DTE/ DCE interface is shown in Figure 4. text continued on page 32/figures on pp. 18-22 17 DESIGN FEATURES C6 100pF C8 100pF C7 100pF 8 3 11 12 13 LTC1344A 14 2 + 3 1 C3 C1 + 1.0F 1.0F C5 1F 2 4 + 5 RXD 6 RXC 7 8 TXC 9 SCTE TXD 10 11 12 13 14 NC 28 CHARGE PUMP D1 D2 27 26 5 4 6 7 9 10 16 15 18 17 19 20 22 23 24 MO M1 M2 VCC VEE 5.0V VCC DCE/DTE LATCH 21 VCC 1 + C2 1.0F DB-25 FEMALE CONNECTOR C4 + 3.3F 25 24 3 23 16 22 17 21 9 20 15 19 12 18 24 17 11 16 2 15 14 RXD A (104) RXD B RXC A (115) RXC B D3 R1 R2 R3 M0 M1 M2 DCE/DTE 7 1 LTC1543 TXC A (114) TXC B SCTE A (113) SCTE B TXD A (103) TXD B SGND (102) SHIELD (101) VCC 1 VCC 2 V DD CTS DSR 3 4 5 DCD DTR RTS LL 6 7 8 10 9 11 12 13 14 NC VEE GND D1 D2 28 27 26 5 25 13 24 6 23 22 CTS A (106) CTS B DSR A (107) DSR B D3 R1 R2 R3 R4 22 8 21 10 20 20 19 23 18 4 17 19 16 18 DCD A (109) DCD B DTR A (108) DTR B RTS A (105) RTS B LL A (141) D4 M0 15 M1 INVERT NC M2 DCE/DTE LTC1544 M2 M1 M0 1544_01.eps Figure 1. Controller-selectable DCE port with DB-25 connector 18 Linear Technology Magazine * February 1998 DESIGN FEATURES C6 100pF C8 100pF C7 100pF 8 3 11 12 13 LTC1344A 14 2 3 1 + C3 C1 + 1.0F 1.0F C5 1F 2 4 + CHARGE PUMP 27 26 5 6 SCTE 7 8 TXC 9 RXC 10 D1 D2 5 4 6 7 9 10 16 15 18 17 19 20 22 23 24 M1 MO 21 1 + C2 1.0F DB-25 MALE CONNECTOR C4 + 3.3F 25 TXD RXD 28 M2 VCC VEE 5.0V VCC DCE/DTE LATCH 24 2 23 14 22 24 21 11 20 15 19 12 18 17 17 9 16 3 15 16 TXD A (103) TXD B SCTE A (113) SCTE B D3 R1 R2 R3 11 M0 12 M1 13 M2 14 DCE/DTE 7 1 LTC1543 TXC A (114) TXC B RXC A (115) RXC B RXD A (104) RXD B SGND (102) SHIELD (101) VCC 1 VCC 2 V DD RTS DTR 3 D1 4 D2 5 DCD DSR CTS LL 28 27 26 4 25 19 24 20 23 23 RTS A (105) RTS B DTR A (108) DTR B D3 6 R1 7 R2 8 R3 10 R4 9 11 12 13 14 VEE GND 22 8 21 10 20 6 19 22 18 5 17 13 16 18 DCD A (109) DCD B DSR A (107) DSR B CTS A (106) CTS B LL A (141) D4 M0 15 M1 INVERT NC M2 DCE/DTE LTC1544 M2 M1 M0 1544_02.eps Figure 2. Controller-selectable multiprotocol DTE port with DB-25 connector Linear Technology Magazine * February 1998 19 DESIGN FEATURES C6 100pF C8 100pF C7 100pF 8 3 11 12 13 LTC1344A 14 2 + 3 1 C3 C1 + 1.0F 1.0F C5 1F 2 4 + 28 CHARGE PUMP 27 26 DTE_SCTE/ DCE_RXC 6 7 DTE_TXC/ DCE_TXC 8 DTE_RXC/ DCE_SCTE 9 DTE_RXD/ DCE_TXD 10 D1 D2 4 6 7 9 10 M1 MO 21 16 15 18 17 19 20 22 23 24 1 + C2 1.0F DB-25 CONNECTOR C4 + 3.3F 25 5 DTE_TXD/ DCE_RXD 5 M2 VEE VCC 5.0V VCC DCE/DTE LATCH 24 2 23 14 22 24 21 11 20 15 19 12 18 17 17 9 16 3 15 16 R1 R2 R3 7 1 LTC1543 1 VCC 2 V DD DTE_RTS/ DCE_CTS 3 DTE_DTR/ DCE_DSR 4 5 DTE_DCD/ DCE_DCD 6 DTE_DSR/ DCE_DTR 7 DTE_CTS/ DCE_RTS 8 DTE_LL/ DCE_LL 10 9 11 12 13 14 DCE RXD A TXD B RXD B SCTE A RXC A SCTE B RXC B TXC A TXC A TXC B TXC B RXC A SCTE A RXC B SCTE B RXD A TXD A RXD B TXD B D3 11 M0 12 M1 13 M2 14 DCE/DTE VCC DTE TXD A VEE GND D1 D2 SGND SHIELD 28 27 26 4 25 19 24 20 23 23 RTS A CTS A RTS B CTS B DTR A DSR A DTR B DSR B DCD A DCD A DCD B DCD B DSR A DTR A DSR B DTR B CTS A RTS A CTS B RTS B LL A LL A D3 R1 R2 R3 R4 22 8 21 10 20 6 19 22 18 5 17 13 16 18 D4 M0 15 M1 INVERT NC M2 DCE/DTE LTC1544 DCE/DTE M2 M1 M0 1544_03.eps Figure 3. Controller-selectable DTE/DCE port with DB-25 connector 20 Linear Technology Magazine * February 1998 DESIGN FEATURES CABLE WIRING FOR DTE/DCE SELECTION PIN 25 V.35 PIN 7 PIN 7 DTE PIN 7 RS449, V.36 NC PIN 7 DCE NC RS232 PIN 7 NC 8 VCC C3 C1 + 1.0F 1.0F C5 1F 28 2 4 CHARGE PUMP + 27 26 5 DTE_SCTE/ DCE_RXC 6 D1 D2 7 DTE_TXC/ DCE_TXC 8 DTE_RXC/ DCE_SCTE 9 DTE_RXD/ DCE_TXD 10 5 4 6 7 9 10 16 15 18 17 19 20 22 23 24 + C2 1.0F 21 1 VCC DB-25 CONNECTOR C4 + 3.3F 25 DTE_TXD/ DCE_RXD 13 LATCH 14 2 + 12 LTC1344A 5.0V VCC 3 1 11 M1 MO MODE 3 C8 100pF M2 PIN 18 PIN 21 C7 100pF DCE/DTE MODE C6 100pF VEE CABLE WIRING FOR MODE SELECTION 24 2 23 14 22 24 21 11 20 15 19 12 18 17 17 9 16 3 15 16 DTE TXD A DCE RXD A TXD B RXD B SCTE A RXC A SCTE B RXC B TXC A TXC A TXC B TXC B RXC A SCTE A RXC B SCTE B RXD A TXD A RXD B TXD B D3 R1 R2 R3 11 M0 12 M1 13 M2 NC 14 DCE/DTE 7 1 SG SHIELD LTC1543 25 VCC 1 VCC 2 V DD DTE_RTS/ DCE_CTS 3 DTE_DTR/ DCE_DSR 4 D1 D2 5 DTE_DCD/ DCE_DCD 6 DTE_DSR/ DCE_DTR 7 DTE_CTS/ DCE_RTS 8 21 18 26 4 25 19 24 20 23 23 DCE/DTE M1 M0 RTS A CTS A RTS B CTS B DTR A DSR A DTR B DSR B DCD A DCD A DCD B DCD B DSR A DTR A DSR B DTR B CTS A RTS A CTS B RTS B D3 R1 R2 R3 10 R4 9 11 12 13 14 VEE GND 28 27 22 8 21 10 20 6 19 22 18 5 17 13 16 D4 M0 15 M1 INVERT NC M2 DCE/DTE LTC1544 1544_04.eps Figure 4. Cable-selectable multiprotocol DTE/DCE port Linear Technology Magazine * February 1998 21 DESIGN FEATURES C6 100pF 3 C8 100pF 11 C7 100pF 8 12 13 LTC1344A 14 2 + C3 + C1 1.0F 1.0F C5 1F 1 2 4 3 + DTE_LL/ DCE_TM 5 DTE_TXD/ DCE_RXD 6 DTE_SCTE/ DCE_RXC 7 44 9 10 12 13 DTE_TXC/ DCE_TXC DTE_RXC/ DCE_SCTE 14 DTE_RXD/ DCE_TXD 15 DTE_TM/ DCE_LL 16 R1 100k LB VCC D3 4 5 DTE_DCD/ DCE_DCD 6 DTE_DSR/ DCE_DTR 7 8 10 9 10 16 15 18 17 19 20 22 23 24 MO 1 DB-25 CONNECTOR DTE 18 2 37 14 36 24 35 11 DCE LL A TM A TXD A RXD A TXD B RXD B SCTE A RXC A SCTE B RXC B TXC A TXC A TXC B TXC B RXC A SCTE A RXC B SCTE B RXD A TXD A RXD B TXD B TM A LL A 34 D4 33 32 15 31 12 30 17 29 28 9 3 27 16 26 25 21 DCE 19 M2 M1 18 M0 17 7 R1 R2 R3 1 VCC 2 V DD DTE_DTR/ DCE_DSR 7 38 40 GND EC 24 23 LB LTC1343 3 DTE_RL/ DCE_RL D2 R4 20 CTRL 22 LATCH 11 25 INVERT 423SET DTE_RTS/ DCE_CTS DTE_CTS/ DCE_RTS 39 8 6 C4 + 3.3F 41 D1 4 21 + C2 1.0F 43 42 CHARGE PUMP 5 M2 M1 VEE VCC 5.0V VCC DCE/DTE LATCH VEE GND D1 D2 SG VCC 1 SHIELD 28 27 26 4 25 19 24 20 23 23 RTS A CTS A RTS B CTS B DTR A DSR A DTR B DSR B DCD A DCD A DCD B DCD B DSR A DTR A DSR B DTR B CTS A RTS A CTS B RTS B RL A RL A D3 R1 R2 R3 R4 22 8 21 10 20 6 19 22 18 5 17 13 16 21 9 D4 11 M0 15 12 M1 INVERT NC 13 M2 14 DCE/DTE LTC1544 DCE/DTE M2 M1 M0 1544_05.eps Figure 5. Controller-selectable multiprotocol DTE/DCE port with RLL, LL, TM and DB-25 connector 22 Linear Technology Magazine * February 1998 DESIGN IDEAS High Clock-to-Center Frequency Ratio LTC1068-200 Extends Capabilities of Switched Capacitor Highpass Filter by Frank Cox continued on page 33 -10dB 10dB/DIV input signal too much you will also limit the passband of the filter, and hence its usefulness. What makes this filter different is the 200:1 clock-to-center frequency ratio (CCFR) and the internal sampling scheme of the LTC1068-200. Figure 2a shows the amplitude response of the filter plotted against frequency from 100Hz to 10kHz. For comparison, Figure 2b shows the same filter built with an LTC1068-25. This is a 25:1 CCFR part. The 200:1 CCFR filter delivers almost 30dB more ultimate attenuation in the stopband. A standard amplitude vs frequency plot of a highpass filter can be misleading because it masks some of the aforementioned spurious signals introduced into the passband. Figure 3a is a spectrum plot of the 200:1 filter with a single 10kHz tone on the input. This plot shows that the 100Hz 5kHz 10kHz DI_1068_02a. EPS Figure 2a. Amplitude vs frequency response of Figure 1's circuit -10dB 10dB/DIV The circuit in Figure 1 is a 1kHz 8th order Butterworth highpass filter built with the LTC1068-200, a switched capacitor filter (SCF) building block. In the past, commercially available switched capacitor filters have had limited use as highpass filters because of their sampled-data nature. Sampled-data systems generate spurious frequencies when the sampling clock of the filter and the input signal mix. These spurious frequencies can include sums and differences of the clock and the input, in addition to sums and differences of their harmonics. The input of the filter must be band limited to remove frequencies that will mix with the clock and end up in the passband of the filter. Unfortunately, the passband of a highpass filter extends upward in frequency by its very nature. If you have to band limit the RH2 10k RH3 1.47k 100Hz LTC1068-200 VIN R11 10k R31 10k 2 3 4 R41 20k 5 6 7 8 5V 9 0.1F 10 R43 11.3k R33 10k 11 12 13 R23 11.3k 14 INV C INV B HPB/NB HPC/NC BPB BPC LPB LPC SB SC NC V- NC AGND V+ CLK NC NC SA SD LPA LPD BPA BPD HPA/NA HPD/ND INV D INV A 28 27 10kHz DI_1068_02b. EPS Figure 2b. Amplitude vs frequency response of comparable filter using the LTC1068-25 R22 10k 26 R32 24.3k 25 24 R42 10k -10dB 23 -5V 22 0.1F 21 20 19 18 17 200kHz R44 16.9k 10dB/DIV 1 R21 20k 5kHz R34 10k 16 15 R24 16.9k RH4 14.7k VOUT 200Hz 100kHz 200kHz DI_1068_03a. EPS Figure 1. LTC1068-200 1kHz 8th order Butterworth highpass filter Linear Technology Magazine * February 1998 Figure 3a. Spectrum plot of Figure 1's circuit with a single 10kHz input 23 DESIGN IDEAS LT1533 Ultralow Noise Switching Regulator for High Voltage or High Current Applications by Jim Williams High Voltage Input Regulator The LT1533 switching regulator1, 2 achieves 100V output noise by using closed-loop control around its output switches to tightly control switching transition time. Slowing down switch transitions eliminates high frequency harmonics, greatly reducing conducted and radiated noise. The part's 30V, 1A output transistors limit available power. It is possible to exceed these limits while maintaining low noise performance by using suitably designed output stages. The LT1533's IC process limits collector breakdown to 30V. A complicating factor is that the transformer causes the collectors to swing to twice the supply voltage. Thus, 15V represents the maximum allowable input supply. Many applications require higher voltage inputs; the circuit in Figure 1 uses a cascoded3 output stage to achieve such high voltage capability. This 24V to 5V (VIN = 20V- 50V) converter is reminiscent of previous LT1533 circuits, except for 6 the presence of Q1 and Q2.4 These devices, interposed between the IC and the transformer, constitute a cascoded high voltage stage. They provide voltage gain while isolating the IC from their large drain voltage swings. Normally, high voltage cascodes are designed to simply supply voltage isolation. Cascoding the LT1533 presents special considerations because the transformer's instantaneous voltage and current information must be accurately transmitted, albeit at lower amplitude, to the LT1533. If this is not done, the regulator's slew-control T1 7 5 8 24VIN (20V TO 50V) + 4 10F 9 3 MBRS140 10 1 0.002F 220 10k Q3 MPSA42 Q4 2N2222 10k Q1 ( L3 OPTIONAL 100H SEE TEXT ) + 220F 100F 12 0.002F Q2 1k 5VOUT + 10k 220 L1 100H 1k 2 + 4.7F 2 14 4 3 1500pF 11 5 18k 6 15 COL A VIN 0.01F MBRS140 SYNC DUTY SHDN CT LT1533 L2 PGND RT NFB 10 11 COL B VC RVSL FB GND RCSL 9 12 13 12k 10k 16 8 7 7.5k 1% 2.49k 1% AN70 F40 L1, L3: COILTRONICS CTX100-3 L2: 22nH TRACE INDUCTANCE, FERRITE BEAD OR INDUCTOR COILCRAFT B-07T TYPICAL Q1, Q2: MTD6N15 T1: COILTRONICS VP4-0860 Figure 1. A low noise 24V to 5V converter (VIN = 20V-50V): cascoded MOSFETs withstand 100V transformer swings, permitting the LT1533 to control 5V/2A output. 24 Linear Technology Magazine * February 1998 DESIGN IDEAS A = 20V/DIV B = 5V/DIV (AC COUPLED) A = 5mV/DIV C = 100V/DIV B = 100V/DIV 10s/DIV 2s/DIV Figure 2. MOSFET-based cascode permits the regulator to control 100V transformer swings while maintaining a low noise 5V output. Trace A is Q1's source, Trace B is Q1's gate and Trace C is the drain. Waveform fidelity through cascode permits proper slew-control operation. Figure 4. Waveforms for Figure 3 at 10W output: Trace A shows fundamental ripple with higher frequency residue just discernible. The optional LC section results in Trace B's 180VP-P wideband noise performance. Current Boosting loops will not function, causing a dramatic output noise increase. The AC-compensated resistor dividers associated with the Q1-Q2 gate-drain biasing serve this purpose, preventing transformer swings coupled via gate-channel capacitance from corrupting the cascode's waveformtransfer fidelity. Q3 and associated components provide a stable DC termination for the dividers while protecting the LT1533 from the high voltage input. Figure 2 shows that the resultant cascode response is faithful, even with 100V swings. Trace A is Q1's source; traces B and C are its gate and drain, respectively. Under these conditions, at 2A output, noise is inside 400V peak. Figure 3 boosts the regulator's 1A output capability to over 5A. It does this with simple emitter followers (Q1- Q2). Theoretically, the followers preserve T1's voltage and current waveform information, permitting the LT1533's slew-control circuitry to function. In practice, the transistors must be relatively low beta types. At 3A collector current, their beta of 20 sources 150mA via the Q1-Q2 base paths, adequate for proper slew-loop operation.5 The follower loss limits efficiency to about 68%. Higher input voltages minimize follower-induced loss, permitting efficiencies in the low 70% range. Figure 4 shows noise performance. Ripple measures 4mV (Trace A) using a single LC section, with high fre- 1N4148 1N5817 0.05 T1 Q1 4.7F 14 11 3 1500pF 4 5 18k 6 0.003F VIN SHDN COL A DUTY COL B SYNC CT PGND LT1533 RVSL RT RCSL 10 0.01F VC Notes: 1 Witt, Jeff. The LT1533 Heralds a New Class of Low Noise Switching Regulators. Linear Technology VII:3 (August 1997). 2 Williams, Jim. LTC Application Note 70: A Monolithic Switching Regulator with 100 V Output Noise. October 1997. 3 The term "cascode," derived from "cascade to cathode," is applied to a configuration that places active devices in series. The benefit may be higher breakdown voltage, decreased input capacitance, bandwidth improvement or the like. Cascoding has been employed in op amps, power supplies, oscilloscopes and other areas to obtain performance enhancement. 4 This circuit derives from a design by Jeff Witt of Linear Technology Corp. 5 Operating the slew loops from follower base current was suggested by Bob Dobkin of Linear Technology Corp. 330 5V + quency content just discernible. Adding the optional second LC section reduces ripple to below 100V (trace B), and high frequency content is seen to be inside 180V (note x50 vertical scale-factor change). GND NFB 9 8 FB + 2 4.7F 15 Q2 0.05 330 16 L2 7 12V L3 33H + ( OPTIONAL FOR LOWEST RIPPLE ) + 100F 100F 1N5817 1N4148 13 10k 12 10k 680 L1 300H R1 21.5k 1% AN70 F42 R2 2.49k 1% L1: COILTRONICS CTX300-4 L2: 22nH TRACE INDUCTANCE, FERRITE BEAD OR INDUCTOR. COILCRAFT B-07T TYPICAL L3: COILTRONICS CTX33-4 Q1, Q2: MOTOROLA D45C1 T1: COILTRONICS CTX-02-13949-X1 : FERRONICS FERRITE BEAD 21-110J Figure 3. A 10W low noise 5V to 12V converter: Q1-Q2 provide 5A output capacity while preserving the LT1533's voltage/current slew control. Efficiency is 68%. Higher input voltages minimize follower loss, boosting efficiency above 71%. Linear Technology Magazine * February 1998 25 DESIGN IDEAS A Complete Battery Backup Solution Using a Rechargeable NiCd Cell by L.Y. Lin and S.H. Lim Battery-powered systems, including notebook computers, personal digital assistants (PDAs) and portable instruments, require backup systems to keep the memory alive while the main battery is being replaced. The most common solution is to use an expensive, nonrechargeable lithium battery. This solution requires lowbattery detection, necessitates battery access and invites inadvertent battery removal. The LTC1558 battery backup controller eliminates these problems by permitting the use of a single, low cost 1.2V rechargeable Nickel-Cadmium (NiCd) cell. The LTC1558 has a built-in fast-/tricklemode charger that charges the NiCd cell when main power is present. Figure 1 shows a typical application circuit with an LTC1558-3.3 providing backup power to an LTC1435 synchronous step-down switching regulator. The backup circuit components consist of the NiCd cell, R11-R14, C11-C12, L11 and Q11. SW11 and R15 provide a soft or hard reset function. FROM P OPEN DRAIN SOFT RESET L11 22H BACKUP BATTERY NiCd 1.2V + R14 10k 1 C11 47F 6.3V SW VCC VBAK 3 7 + C12 8 1F CTL LTC1558-3.3 5 2 RESET GND PUSH-BUTTON RESET 4 SW11 BKUP FB R15 12k TO P 6 R13 100k Q11 Si4431DY R11 51k 1% MAIN BATTERY 4.5V-10V R12 21.2k (20.0k 1% + 1.21k 1%) C2 0.1F 13 9 CSS 0.1F CC2 51pF C1 100pF RC 10k 16 TG SW 14 C4 15 BOOST 0.1F D1*** LTC1435 6 12 INTVCC VOSENSE 3 8 ITH SENSE+ C5 2 7 1000pF RUN/SS SENSE- Q2 1 C 11 BG OSC Si4412DY + C3 SGND PGND 4.7F 5 10 16V COSC 68pF 4 CC 330pF VIN EXTVCC Q1 Si4412DY SFB * ** *** + CIN 100F 16V x2 L1* 10H RSENSE** 0.033 + D2 MBRS140T3 SUMIDA CDRH125-100 IRC LR2010-01-R033-F CENTRAL CMDSH-3 SUMIDA CDRH73-220 SANYO CADNICA N-110AA COUT 100F 10V x2 VOUT 3.3V LOAD CURRENT 3A IN NORMAL MODE 30mA IN BACKUP MODE R1 35.7k 1% R5 20k 1% C6 100pF 1558 01.eps Figure 1. LTC1558 backup system with LTC1435 as main system regulator 26 Linear Technology Magazine * February 1998 DESIGN IDEAS OUTPUT POWER (mW) VBAK = 4V VOUT = 3.3V 140 120 100 80 60 40 20 0 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 BACKUP CELL VOLTAGE (V) 1558_02 Figure 2. 3.3V output power vs backup cell voltage Normal Mode (Operation from the Main Battery) During nor mal operation, the LTC1435 is powered from the main battery, which can range from 4.5V to 10V (for example, a 2-series or 2series x 2-parallel Li-Ion battery pack, or the like) and generates the 3.3V system output. The LTC1558 operates in standby mode. In standby mode, the LTC1558 BKUP (backup) pin is pulled low and P-channel MOSFET Q11 is on. The NiCd cell is fast charged by a 15mA current source connected between the LTC1558's VCC and SW pins. Once the NiCd cell is fully charged (according to the LTC1558's gas-gauge counter), the LTC1558 trickle charges the NiCd cell. R14 sets the trickle-charge current according to the formula I(TRICKLE) = 10 * (VNiCd - 0.5)/R14. The tricklecharge current is set to overcome the NiCd cell's self-discharge current, thereby maintaining the cell's full charge. Backup Mode (Operation from the Backup Battery) The main battery voltage is scaled down through resistor divider R11- R12 and monitored by the LTC1558 Authors can be contacted at (408) 432-1900 Linear Technology Magazine * February 1998 via the FB pin. If the voltage on the FB pin drops 7.5% below the internal 1.272V reference voltage (due to discharging or exchanging the main battery), the system enters backup mode. In backup mode, the LTC1558's internal switches and L11 form a synchronous boost converter that generates a regulated 4V at VBAK. The LTC1435 operates from this supply voltage to generate the 3.3V output voltage. The BKUP pin is pulled high by R13 and Q11 turns off , leaving its Battery-powered systems, including notebook computers, personal digital assistants (PDAs) and portable instruments, require backup systems to keep the memory alive while the main battery is being replaced. The most common solution is to use an expensive, nonrechargeable lithium battery. body diode reverse biased. The BKUP pin also alerts the system microprocessor. C11, a 47 F capacitor, provides a low impedance bypass to handle the boost converter's transient load current; otherwise, the voltage drop across the NiCd cell's internal resistance would activate the Table 1. VFB and VBAK voltages Relative % Below VR E F % of VR E F VF B VB A K -0% 100% 1.272V 4.332V -6% 94% 1.196V 4.073V -7.5% 92.5% 1.177V 4.008V 300 VBAK = 4V VOUT = 3.3V 250 BACKUP TIME (MINS) 180 160 200 150 100 50 0 0 5 10 15 20 LOAD CURRENT (mA) 25 30 1558_03 Figure 3. Backup time vs 3.3V output load current LTC1558's undervoltage-lockout function. Table 1 shows several values of VFB vs the VBAK voltage. Figure 2 shows the maximum output power available at the 3.3V output vs the NiCd cell voltage. Over 100mW of output power is achieved for a NiCd cell voltage greater than 1V. Figure 3 shows the backup time vs the 3.3V load current using a Sanyo Cadnica N-110AA cell (standard series with a capacity of 110mAhrs). Over one hour of backup time is realized for less than 80mW of 3.3V output power. Recovery from Backup Mode to Normal Mode When a new main battery pack is inserted into the system, Q11's body diode forward biases. Once the voltage at the FB pin increases to more than 6% below VREF, the boost converter is disabled and the system returns to normal mode. The BKUP pin pulls low and turns Q11 back on. This allows the new battery pack to supply input power to the LTC1435. The LTC1558 now accurately replenishes the amount of charge removed from the NiCd cell through the internal charger and gas-gauge counter. for the latest information on LTC products, visit www.linear-tech.com 27 DESIGN IDEAS Zero-Bias Detector Yields High Sensitivity with Nanopower Consumption by Mitchell Lee RF ID tags, circuits that detect a "wake-up" call and return a burst of data, must operate on very low quiescent current for months or years, yet have enough battery power in reserve to answer an incoming call. For smallest size, most operate in the ultrahigh frequency range, where the design of a micropower receiver circuit is problematic. Familiar techniques, such as direct conversion, super regeneration or superhetrodyne, consume far too much supply current for long battery life. A better method involves a technique borrowed from simple fieldstrength meters: a tuned circuit and a diode detector. Figure 1 shows the complete circuit, which was tested for proof-of-concept at 445MHz. This circuit contains a couple of improvements over the standard L/C-with-whip field-strength meter. Tuned circuits aren't easily constructed or controlled at UHF, so a transmission line is used to match the detector diode (1N5712) to a quarter-wave whip antenna. The 0.23 transmission-line section transforms the 1pF (350) diode junction capacitance to a virtual short at the base of the antenna. At the same time, it converts the received antenna current to a voltage loop at the diode, giving excellent sensitivity. Biasing the detector diode can improve sensitivity,1 but only when the diode is loaded by an external DC resistance. Careful curve-tracer examination of the 1N5712 at the origin reveals that it follows the ideal diode equation, with scales of millivolts and nanoamperes. To use a zero-bias diode at the origin, the external comparator circuitry must not load the rectified output. The LTC1540 nanopower comparator and reference is a good choice for this application because it not only presents no load to the diode, but also draws only 300nA from the battery. This represents a 10-times improvement in battery life over biased detector schemes. 2 The input is CMOS, and input bias current consists of leakage in a small ESDprotection cell connected between the input and ground. The input leakage measures in the picoampere range, whereas the 1N5712 leaks hundreds of picoamperes. Any rectified output from the diode is loaded by the diode itself, not by the LTC1540, and the sensitivity can match that of a loaded, biased detector. The rectified output is monitored by the LTC1540 comparator. The LTC1540's internal reference is used to set up a threshold of about 18mV 2V-11V /4 12M FB 10k 3 5 + 6 7 LTC1540 4 O.23 10nF at the inverting input. A rising edge at the comparator output triggers a oneshot, which temporarily enables answer-back and any other pulsed functions. Total supply current is 400nA, consuming just 7mAH battery life over a period of five years. Monolithic oneshots draw significant load current, but the '4047 is about the best in this respect. A one-shot constructed from discrete NAND gates draws negligible power. Sensitivity is excellent, and the circuit can detect about 200mW from a reference dipole at 100 feet. Range, of course, depends on operating frequency, antenna orientation and surrounding obstacles. Sensitivity is independent of supply voltage; this receiver will work just as well with a 9V battery as with a single lithium cell. The length of the transmission line does not scale with frequency. Owing to a decrease in diode reactance, the electrical length will shorten as frequency increases. Adjust the line length for minimum feed-point impedance at the operating frequency. If an impedance analyzer is used to measure the line, a 1pF capacitor can be substituted for the diode to avoid large signal effects in the diode itself. Consult the manufacturer's data sheet for accurate characterization of diode impedance at the frequency of interest. - 2 1 8 CMOS ONE-SHOT (CD4047) 10nF 180k Q Q Notes: 1. Eccles, W.H. Wireless Telegraphy and Telephony, Second Edition. Ben Brothers Limited, London, 1918, page 272. 2. Lee, Mitchell. "Biased Detector Yields High Sensitivity with Ultralow Power Consumption." Linear Technology VII:1(February 1997), page 21. 1N5712 Figure 1. Nanopower field detector 28 Linear Technology Magazine * February 1998 DESIGN INFORMATION Micropower Octal 10-Bit DAC Conserves Board Space with SO-8 Footprint by Kevin R. Hoskins Introduction Rail-to-Rail Output Amplifiers Single Supply, 60A per DAC Historically, many circuits have relied on potentiometers for adjustment or control. Increasingly, microcontrollers and microprocessors are finding applications in these circuits. The inclusion of processors can eliminate potentiometers, replacing them with digital-to-analog converters (DACs). Fulfilling this need is the LTC1660. Each internal DAC has an amplifier that buffers its output. The amplifiers' output voltage can swing rail-to-rail; they can source or sink up to 5mA while maintaining guaranteed linearity and monotonicity performance. Additionally, the amplifiers can easily drive 1000pF and remain stable. Higher capacitive loads (such as 0.1F) can be driven by placing a small value resistor (100 typical) in series with the output pin. The LTC1660 maintains its specified operation over the wide supply range of 2.7V to 5.5V. To ensure efficient operation on this supply range, the total typical supply current drawn is just 480A. The wide supply range and low current requirements make this DAC ideal for battery-powered applications. Features Eight DACs in 0.045in2 The LTC1660 is the latest multichannel DAC from Linear Technology. This 10-bit, voltage-output, octal DAC is designed to conserve board space. Packaged in a 16-pin narrow SSOP, it has an 8-pin SO footprint. Figure 1 is a block diagram showing the LTC1660's major circuit features. LTC1660 2 VOUT A 3 VOUT B Inherent 10-Bit Monotonicity and Linearity (DNL) Performance The LTC1660 uses a DAC architecture that features excellent 0.5dB differential linearity accuracy, ensuring inherently monotonic performance. This is important for closed-loop control applications, since nonmonotonic operation compromises loop stability. Figures 2a and 2b show the LTC1660's INL and DNL performance, respectively. 4 VOUT C 5 VOUT D 1 Reference Input The LTC1660 uses a single external reference voltage for all its internal DACs. This voltage sets its full-scale output range. The reference voltage magnitude has a range of 0V to VCC. Figure 3 shows a micropower LT14602.5 voltage reference setting the LTC1660's full-scale output to 2.5V. DAC A DAC H DAC B DAC G DAC C DAC F DAC D DAC E VOUT H 15 VOUT G 14 VOUT F 13 VOUT E 12 GND VCC 6 16 REF 7 CS/LD 8 CLK CONTROL LOGIC ADDRESS DECODER 11 CLR 9 DIN SHIFT REGISTER DOUT 10 Figure 1. LTC1660 block diagram Linear Technology Magazine * February 1998 29 DESIGN INFORMATION 1.00 1.00 0.75 0.75 0.25 0 -0.25 1660_XX.EPS 11 0.1F 7 -0.75 Figure 2a. LTC1660 integral nonlinearity error LT1460-2.5 -0.25 -0.75 128 256 384 512 640 768 896 1024 CODE 1 0 -0.50 0 16 6 0.25 -0.50 -1.00 LTC1660 0.1F 16k 0.50 DNL ERROR (LSB) INL ERROR (LSB) 0.50 5V -1.00 SERIAL INTERFACE 8 9 10 0 128 256 384 512 640 768 896 1024 CODE VCC REF GND CLR CS/LD CLK DIN DOUT VOUT A 2 3 VOUT B 4 VOUT C 5 VOUT D 12 VOUT E 13 VOUT F 14 VOUT G 15 VOUT H Figure 3. An LT1460 2.5V reference sets the LTC1660's full-scale output to 2.5V. 1660_YY.EPS Figure 2b. LTC1660 differential nonlinearity error Asynchronous CLEAR SLEEP Mode Further power saving is possible when the LTC1660 is placed in SLEEP mode. Activating SLEEP mode shuts off all internal bias currents and places the output amplifiers in a high impedance state. The SLEEP mode reduces current consumption to 1A or less. The digital circuitry remains active, retaining the stored values for each DAC. There are two ways to take the part out of SLEEP mode: loading any ADDRESS/CONTROL value other than SLEEP mode or applying a logic low to the CLR pin. The last technique awakens the LTC1660 and sets all eight outputs to 0V. multiple LTC1660s and other LTC DACs to the same serial data line. The daisy chain is linked by connecting a part's DOUT pin to the DIN pin of the next part in the chain. The advantages of the single serial data line include reduced circuit board space, reduced radiation that results from fewer circuit traces and conservation of limited microcontroller or microprocessor I/O lines. This active low input will asynchronously reset all eight DAC outputs to 0V when a logic low is applied to this pin. It also deactivates the SLEEP mode. Applications The LTC1660 shines brightly in applications that take advantage of its micropower, linearity and versatility. The applications include offset and gain adjust in industrial Power-On Reset control systems and AGC and transmit power adjustment in wireless The LTC1660's power-on reset encommunication. sures that the output voltage on each DAC is set to 0V when power (2.7V- continued on page 33 5.5V) is first applied to the VCC pin. Serial Interface The eight internal DACs are addressed individually over a 3-wire, SPI-compatible interface. The three signals are Chip Select/Load (CS/LD), Serial Clock (CLK) and Data In (DIN). Schmitt Trigger Inputs The LTC1660's Schmitt trigger digital inputs prevent false triggers when responding to noisy signals or those having slow rise or fall times. This quality makes the LTC1660 ideal for remote placement at the end of long serial transmission lines or lines that use optoisolators. DOUT Daisy Chain Another feature of the LTC1660's serial interface is its DOUT pin. The current contents of the internal shift register are shifted out on this pin as new data is shifted in on the DIN pin. This pin makes it possible to connect 30 Table 1. DAC address/control functions Bit14 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Address/Control Bit13 Bit12 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Bit11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Action No Update Load DAC A Load DAC B Load DAC C Load DAC D Load DAC E Load DAC F Load DAC G Load DAC H None None None None None SLEEP Mode Load all DACSs with the same 10-bit code Linear Technology Magazine * February 1998 DESIGN INFORMATION Tiny MSOP Dual Switch Driver is SMBus Controlled Introduction by Peter Guan VCC 2.7V TO 5.5V The LTC1623 SMBusTM switch controller offers an inexpensive, space-saving alternative for controlling peripherals in today's complex portable computer systems. Pin-topin connections between the system controller and each peripheral device not only result in complicated wiring, but also limit the number and type of peripheral devices connected to the system controller. Using the SMBus architecture, the LTC1623 eliminates these problems by requiring only two bus wires and allowing easy upgrades and additions of new peripherals. 10F VCC (FROM SMBus) 1k Q1 Si3442DV GA CLK DATA 0.1F Q1 Si3442DV 0.1F AD0 (PROGRAMMABLE) AD1 GND PRINTER DISPLAY 1623 F02 Figure 2. LTC1623 controlling two high-side switches 5V 10F VCC 1k The SMBus Q1 Si3442DV GA CLK DATA TO PC CARD VCC 0V/3.3V/5V 0.1F Q2* LTC1623 The SMBus is a low power serial bus developed by Intel and Duracell. Only two bus lines, DATA and CLK, are needed to establish a set of protocols for communication between the bus master and slaves. Using the SEND BYTE protocol of the SMBus to receive and execute commands from the bus master, each LTC1623 controls the operation of two independent external switches. To identify itself on the SMBus, the LTC1623 has two three-state address pins. In other words, up to eight LTC1623s can be programmed to control up to sixteen different switches. 1k LTC1623 GB AD0 1F 10k 1k 1623 TA02 Q3* GB AD1 GND 0.1F 3.3V *1/2 Si6926DQ Figure 3. PC Card 3.3V/5V switch matrix. bits and one read/write bit. If the address byte matches, the LTC1623 acknowledges the master and then shifts in the command byte whose two LSBs are the controlling signals for the two external switches. Afterwards, the LTC1623 again acknowledges the master so that the master can terminate the transaction by sending a Stop signal (a DATA transition from LTC1623 Design Information low to high while CLK is high). The LTC1623 adheres strictly to A timing diagram of the SEND BYTE protocol is shown in Figure 1. After the SMBus specification of 0.6V VIL detecting the Start signal from the and 1.4V VIH over the entire operating bus master (a high-to-low transition range of 2.7V to 5.5V. The two built-in on the DATA line while CLK is high), charge pump triplers with micropower the LTC1623 shifts in the address feedback networks guarantee full enbyte, which consists of seven address hancement of the two external logic-level MOSFET switches without excess gate overdrive. The output gatedrive voltage is regulated to a maximum of 6V above VIN. Applications The main application of the LTC1623 is to control two external high-side Nchannel switches (Figure 2). As seen in the figure, a 0.1F capacitor and a 1k resistor are placed on each gatedrive output to respectively slow down the turn-on time of the external switch and to eliminate any oscillations caused by the parasitic capacitance of the external switch and the parasitic inductance of the connecting wires. SMBus is a trademark of Intel Corp. CLK START 1 0 1 1 DATA 0 0 0 (PROGRAMMABLE) ADDRESS BYTE 0 ACK (WRITE) 0 0 0 0 0 0 1 1 ACK STOP (GB ON)(GA ON) COMMAND BYTE 1623 TD02 Figure 1. SMBus SEND BYTE protocol timing diagram Linear Technology Magazine * February 1998 31 CONTINUATIONS Tracking the growing popularity of portable communication systems, the LTC1623 makes a very handy singleslot 3.3V/5V PC Card switch matrix. As shown in Figure 3, this circuit enables a system controller to switch either a 3.3V or a 5V supply to any of its SMBus-addressed peripherals. Besides N-channel switches, the LTC1623 can also be used to control a P-channel switch, as shown in Figure 4. As a result, the load connected to the P-channel switch will be turned on upon power-up of the LTC1623, whereas the other load must wait for a valid address and command to be powered. VCC 2.7V TO 5.5V 10F VCC DATA Adding Optional Test Signal In some cases, the optional test signals local loopback (LL), remote loopback (RL) and test mode (TM) are required but there are not enough drivers and receivers available in the Q1 Si3442DV 0.1F 1k LTC1623 GB (PROGRAMMABLE) 0.1F AD0 Q2 Si6433DQ AD1 GND DISPLAY FAN 1623 F02 Figure 4. LTC1623 controlling a P-channel switch (Q2) Conclusion With a standby current of only 17A and a tiny 8-lead MSOP (or SO) footprint, the LTC1623 offers a simple and efficient solution for managing system peripherals using the SMBus architecture. Conclusion LTC1543, continued from page 17 The mode pins are routed to the connector and are left unconnected (1) or wired to ground (0) in the cable. The internal pull-up current sources ensure a binary 1 when a pin is left unconnected and also ensure that the LTC1543/LTC1544/LTC1344A enter the no-cable mode when the cable is removed. In the no-cable mode, the LTC1543/LTC1544 power supply current drops to less than 200 A and all of the LTC1543/ LTC1544 driver outputs will be forced into the high impedance state. 1k GA CLK (FROM SMBus) LTC1543/LTC1544 to handle these extra signals. The solution is to combine the LTC1544 with the LTC1343. By using the LTC1343 to handle the clock and data signals, the chip set gains one extra single-ended driver/ receiver pair. This configuration is shown in Figure 5. In the world of network equipment, the product differentiation is mostly in the software and not in the serial interface. The LTC1543, LTC1544 and LTC1344A provide a simple yet comprehensive solution to standards compliance for multiple-protocol serial interface. Compliance Testing A European standard EN 45001 test report is available for the LTC1543/ LTC1544/LTC1344A chip set. The report provides documentation on the compliance of the chip set to Layer 1 of the NET1 and NET2 standard. A copy of this test report is available from LTC or from Detecon, Inc. at 1175 Old Highway 8, St. Paul, MN 55112. Authors can be contacted at (408) 432-1900 LTC1562 continued from page 5 Quadruple 3rd Order 100kHz Butterworth Lowpass Filter Another example of the flexibility of the virtual-ground inputs is the ability to add an extra, independent real pole by replacing the input resistor in Figure 2 with an R-C-R "T" network. In Figure 10, a 10k input resistor has been split into two parts and the parallel combination of the two forms a 100kHz real pole with the 680pF 32 Conclusion external capacitor. Four such 3rd order Butterworth lowpass filters can be built from one LTC1562. The same technique can add additional real poles to other filter configurations as well, for example, augmenting Figure 4's circuit to obtain a dual 5th order filter from a single LTC1562. The LTC1562 is the first truly compact universal active filter, yet it offers instrumentation-grade performance rivaling much larger discrete-component designs. It serves applications in the 10kHz-150kHz range with an SNR as high as 100dB or more (16+ equivalent bits). The LTC1562 is ideal for modems and other communications systems and for DSP antialiasing or reconstruction filtering. Linear Technology Magazine * February 1998 CONTINUATIONS LTC1660 continued from page 30 Accessing the Functionality Table 1 shows the DAC ADDRESS/ CONTROL codes that update each of the DACs, activate the SLEEP mode, cause "No Update", or update all DACs with the same 10-bit value. The four MSBs (Bit15-Bit12) of the 16-bit data word sent to the LTC1660 select a DAC for updating or a control function such as SLEEP. The next ten bits (Bit11-Bit2) are the data that sets the selected DAC's output voltage. For example, with a 2.5V reference voltage applied to the LTC1660's pin 6, a value of 819 (1100110011) on Bit11-Bit2 sets the DAC's output voltage to 819/1024 * 2.5V, = 2.0V. The last two bits (Bit1-Bit0) are "don't care." When a 4-bit "no update" code is sent (Bit15-Bit12 = 0000 and 1001-1101), the contents of Bit11-Bit0 are ignored. The SLEEP mode is selected by sending Bit15-Bit12 = 1110. The LTC1660 is awakened by applying a logic low to the CLR pin or by completing a data load cycle. To awaken the part with a load cycle and return to the same output voltages as before SLEEP, use address/control locations Bit15-Bit12 = 0000 or 1001-1101. Using CLR to awaken the LTC1660 changes the contents of all DAC registers to zeros and the output voltage to 0V. Finally, all DACs can be forced to the same output voltage by using address/control location Bit15-Bit12 = 1111. Layout, Bypassing and Grounding Considerations Like all data converters, the LTC1660 performs best when it is properly grounded, bypassed and placed on a PCB layout optimized for low noise. Proper grounding is achieved by placing the part over an analog ground plane. Ideally, no traces should cut through the analog ground plane. If a digital ground plane is present, it should make contact with the analog ground plane at only one point, usually where the board is grounded to the power supply ground. If the board consists of multiple layers, the digital and analog ground planes should not overlap each other. The ground pin (pin 1) should be connected to the analog ground plane. Two 0.1 F bypass capacitors should be connected between the LTC1660 and the analog ground plane. One capacitor is connected to the VCC input (pin 16) and the other is connected to the reference input (pin 6). Lead lengths should be as short as possible. To help ensure that digital switching noise does not contaminate the analog output, pins 7-11 should be placed over the digital ground plane and not cross the analog ground plane. Conclusion The LTC1660 10-bit octal DAC features a very small narrow SSOP-16 package, micropower operation and power saving SLEEP mode. These features make this the ideal part for dense circuit boards and battery-powered applications. LTC1068-200 continued from page 23 200Hz 100kHz 200kHz DI_1068_03b. EPS Figure 3b. Spectrum plot of Figure 1's circuit with a single 150kHz input spurious free dynamic range (SFDR) of the LTC1068 highpass filter is in excess of 70dB. In fact, the filter has a 70dB SFDR for all input signals up to 100kHz. In a 200kHz sampleddata system, you would normally need to band limit the input below 100kHz, Linear Technology Magazine * February 1998 the Nyquist frequency. Because the LTC1068 uses double sampling techniques, its useful input frequency range extends to the Nyquist frequency and even above, albeit with some care. Figure 3b shows the LTC1068-200 highpass filter with an input frequency of 150kHz. There is a spurious signal at 50kHz, but even though there is no input filtering, the SFDR is still 60dB. For input signals from 100kHz to 150kHz, the filter demonstrates an SFDR of at least 60dB. The SFDR plot of the same filter built with the LTC1068-25 is shown in Figure 4. Note that the lower CCFR (25:1) part still manages a respectable 55dB SFDR with a 10kHz input. The LTC1068-25 is used primarily for band-limited applications, such as lowpass and bandpass filters. -10dB 10dB/DIV 10dB/DIV -10dB 100Hz 12.5kHz 25kHz DI_1068_04. EPS Figure 4. Spectrum plot of a comparable filter using the LTC1068-25 with a single 10kHz input shows a respectable 55dB SFDR. Note: The filters for this article were designed using Linear Technology's FilterCADTM (version 2.0) for Windows(R). This program made the design and optimization of these filters fast and easy. 33 NEW DEVICE CAMEOS New Device Cameos Ultralow IQ LTC1474, LTC1475 Stepdown DC/DC Converter Family Grows The LTC1474/LTC1475 family has been expanded to cover a complete range of output voltage, package and operating-temperature options. All members of the family feature 3V to 18V (20V Absolute Maximum) operation, 10A typical quiescent current and programmable peak inductor current. The LTC1474 is controlled by a run pin and features a low-battery comparator that remains active in shutdown. The LTC1475 adds an on/ off latch, allowing push-button control of power. Both the LTC1474 and LTC1475 are available with 3.3V, 5V or adjustable output voltages. All versions are offered in two packages: the industrystandard small outline 8-pin plastic package and the tiny 8-pin MSOP package. MSOP-packaged parts are specified for the commercial temperature range, whereas all LTC1474 S8 versions and the LTC1475 S8 adjustable version are also available specified for the industrial temperature range (see table). Option CMS8 CS8 IS8 LTC1474-ADJ LTC1474-3.3 LTC1474-5 LTC1475-ADJ LTC1475-3.3 LTC1475-5 Every member of the LTC1474/ LTC1475 family features operating efficiencies exceeding 90% and a combination of cycle-by-cycle inductor current control and ultralow quiescent current previously unavailable in switching regulators. Strapping two pins together defines a 400mA peak inductor current with no external current sense resistor, allowing up to 300mA output currents. Adding an inexpensive external resistor allows the user to program the peak inductor current to as low as 10mA for efficient low current operation with small inductors. The LTC1474/LTC1475 are ideal for many quiescent-current-sensitive applications, such as battery-powered, handheld devices, keep-alive power supplies and industrial 4-20mA loops. LT1534 Ultralow Noise 2A Regulator The LT1534 is the next in the line of "stealth switchers," DC/DC converters designed to significantly reduce conducted and radiated electromagnetic interference (EMC, EMI). By adjusting the output switch voltage and current slew rates, noise can be reduced to unprecedented levels. These converters can then be used to generate power in applications that previously excluded switchers, including precision instrumentation systems, medical instruments, singleboard data acquisition systems and wireless communications. The LT1534 is specifically designed for single-output topologies such as boost, SEPIC and Cuk. The LT1534 uses a current mode architecture; it includes a single 2A power switch along with all necessary oscillator, control and protection circuitry. Unique error amp circuitry can regulate both positive and negative voltages. The internal oscillator may be synchronized to an external clock. Protection features include cycle-by-cycle short-circuit protection, undervoltage lockout and thermal shutdown. Low shutdown current (12A typical) and low minimum input voltage requirements (2.7V) make this part suitable for battery-operated applications. The LT1534 is offered in an SO-16 package in a commercial temperature grade. The user can independently adjust the output switch current slew rate and voltage slew rate. This allows the user to optimally trade off noise and efficiency. Because the slew control reduces the source of switcher noise, it can reduce or eliminate the need for power supply shielding and filtering components. For further information on any of the devices mentioned in this issue of Linear Technology, use the reader service card or call the LTC literature service number: 1-800-4-LINEAR Ask for the pertinent data sheets and Application Notes. 34 Linear Technology Magazine * February 1998 DESIGN TOOLS DESIGN TOOLS Applications on Disk Noise Disk -- This IBM-PC (or compatible) program allows the user to calculate circuit noise using LTC op amps, determine the best LTC op amp for a low noise application, display the noise data for LTC op amps, calculate resistor noise and calculate noise using specs for any op amp. Available at no charge SPICE Macromodel Disk -- This IBM-PC (or compatible) high density diskette contains the library of LTC op amp SPICE macromodels. The models can be used with any version of SPICE for general analog circuit simulations. The diskette also contains working circuit examples using the models and a demonstration copy of PSPICETM by MicroSim. Available at no charge SwitcherCADTM -- The SwitcherCAD program is a powerful PC software tool that aids in the design and optimization of switching regulators. The program can cut days off the design cycle by selecting topologies, calculating operating points and specifying component values and manufacturer's part numbers. 144 page manual included. $20.00 SwitcherCAD supports the following parts: LT1070 series: LT1070, LT1071, LT1072, LT1074 and LT1076. LT1082. LT1170 series: LT1170, LT1171, LT1172 and LT1176. It also supports: LT1268, LT1269 and LT1507. LT1270 series: LT1270 and LT1271. LT1371 series: LT1371, LT1372, LT1373, LT1375, LT1376 and LT1377. Micropower SwitcherCADTM -- The MicropowerSCAD program is a powerful tool for designing DC/DC converters based on Linear Technology's micropower switching regulator ICs. Given basic design parameters, MicropowerSCAD selects a circuit topology and offers you a selection of appropriate Linear Technology switching regulator ICs. MicropowerSCAD also performs circuit simulations to select the other components which surround the DC/DC converter. In the case of a battery supply, MicropowerSCAD can perform a battery life simulation. 44 page manual included. $20.00 MicropowerSCAD supports the following LTC micropower DC/DC converters: LT1073, LT1107, LT1108, LT1109, LT1109A, LT1110, LT1111, LT1173, LTC1174, LT1300, LT1301 and LT1303. Technical Books 1990 Linear Databook, Vol I --This 1440 page collection of data sheets covers op amps, voltage regulators, references, comparators, filters, PWMs, data conversion and interface products (bipolar and CMOS), in both commercial and military grades. The catalog features well over 300 devices. $10.00 1992 Linear Databook, Vol II -- This 1248 page supplement to the 1990 Linear Databook is a collection of all products introduced in 1991 and 1992. The catalog contains full data sheets for over 140 devices. The 1992 Linear Databook, Vol II is a companion to the 1990 Linear Databook, which should not be discarded. $10.00 Linear Technology Magazine * February 1998 1994 Linear Databook, Vol III --This 1826 page supplement to the 1990 and 1992 Linear Databooks is a collection of all products introduced since 1992. A total of 152 product data sheets are included with updated selection guides. The 1994 Linear Databook Vol III is a companion to the 1990 and 1992 Linear Databooks, which should not be discarded. $10.00 receiver products for RS232, RS485, RS423, RS422, V.35 and AppleTalk(R) applications. Linear's particular expertise in this area involves low power consumption, high numbers of drivers and receivers in one package, mixed RS232 and RS485 devices, 10kV ESD protection of RS232 devices and surface mount packages. Available at no charge 1995 Linear Databook, Vol IV --This 1152 page supplement to the 1990, 1992 and 1994 Linear Databooks is a collection of all products introduced since 1994. A total of 80 product data sheets are included with updated selection guides. The 1995 Linear Databook Vol IV is a companion to the 1990, 1992 and 1994 Linear Databooks, which should not be discarded. $10.00 Power Solutions Brochure -- This 84 page collection of circuits contains real-life solutions for common power supply design problems. There are over 88 circuits, including descriptions, graphs and performance specifications. Topics covered include battery chargers, PCMCIA power management, microprocessor power supplies, portable equipment power supplies, micropower DC/DC, step-up and step-down switching regulators, off-line switching regulators, linear regulators and switched capacitor conversion. Available at no charge 1996 Linear Databook, Vol V --This 1152 page supplement to the 1990, 1992, 1994 and 1995 Linear Databooks is a collection of all products introduced since 1995. A total of 65 product data sheets are included with updated selection guides. The 1996 Linear Databook Vol V is a companion to the 1990, 1992, 1994 and 1995 Linear Databooks, which should not be discarded. $10.00 1997 Linear Databook, Vol VI --This 1360 page supplement to the 1990, 1992, 1994, 1995 and 1996 Linear Databooks is a collection of all products introduced since 1996. A total of 79 product data sheets are included with updated selection guides. The 1997 Linear Databook Vol VI is a companion to the 1990, 1992, 1994, 1995 and 1996 Linear Databooks, which should not be discarded. $10.00 1990 Linear Applications Handbook, Volume I -- 928 pages full of application ideas covered in depth by 40 Application Notes and 33 Design Notes. This catalog covers a broad range of "real world" linear circuitry. In addition to detailed, systems-oriented circuits, this handbook contains broad tutorial content together with liberal use of schematics and scope photography. A special feature in this edition includes a 22-page section on SPICE macromodels. $20.00 1993 Linear Applications Handbook, Volume II -- Continues the stream of "real world" linear circuitry initiated by the 1990 Handbook. Similar in scope to the 1990 edition, the new book covers Application Notes 40 through 54 and Design Notes 33 through 69. References and articles from non-LTC publications that we have found useful are also included. $20.00 1997 Linear Applications Handbook, Volume III -- This 976 page handbook maintains the practical outlook and tutorial nature of previous efforts, while broadening topic selection. This new book includes Application Notes 55 through 69 and Design Notes 70 through 144. Subjects include switching regulators, measurement and control circuits, filters, video designs, interface, data converters, power products, battery chargers and CCFL inverters. An extensive subject index references circuits in LTC data sheets, design notes, application $20.00 notes and Linear Technology magazines. Interface Product Handbook -- This 424 page handbook features LTC's complete line of line driver and High Speed Amplifier Solutions Brochure -- This 72 page collection of circuits contains real-life solutions for problems that require high speed amplifiers. There are 82 circuits including descriptions, graphs and performance specifications. Topics covered include basic amplifiers, video-related applications circuits, instrumentation, DAC and photodiode amplifiers, filters, variable gain, oscillators and current sources and other unusual application circuits. Available at no charge Data Conversion Solutions Brochure -- This 52 page collection of data conversion circuits, products and selection guides serves as excellent reference for the data acquisition system designer. Over 60 products are showcased, solving problems in low power, small size and high performance data conversion applications--with performance graphs and specifications. Topics covered include ADCs, DACs, voltage references and analog multiplexers. A complete glossary defines data conversion specifications; a list of selected application and design notes is also included. Available at no charge Telecommunications Solutions Brochure -- This 72 page collection of circuits, new products and selection guides covers a wide variety of products targeted for the telecommunications industry. Circuits solving real life problems are shown for central office switching, cellular phone, base station and other telecom applications. New products introduced include high speed amplifiers, A/D converters, power products, interface transceivers and filters. Reference material includes a telecommunications glossary, serial interface standards, protocol information and a complete list of key application notes and design notes. Available at no charge continued on page 40 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, Linear Technology makes no representation that the circuits described herein will not infringe on existing patent rights. 35 DESIGN TOOLS, continued from page 39 CD-ROM LinearView -- LinearViewTM CD-ROM version 2.0 is Linear Technology's latest interactive CD-ROM. It allows you to instantly access thousands of pages of product and applications information, covering Linear Technology's complete line of high performance analog products, with easy-to-use search tools. The LinearView CD-ROM includes the complete product specifications from Linear Technology's Databook library (Volumes I-V) and the complete Applications Handbook collection (Volumes I-III). Our extensive collection of Design Notes and the complete collection of Linear Technology magazine are also included. A powerful search engine built into the LinearView CDROM enables you to select parts by various criteria, such as device parameters, keywords or part numbers. All product categories are represented: data conversion, references, amplifiers, power products, filters and interface circuits. Up-to-date versions of Linear Technology's software design tools, SwitcherCAD, Micropower SwitcherCAD, FilterCAD, Noise Disk and Spice Macromodel library, are also included. Everything you need to know about Linear Technology's products and applications is readily accessible via LinearView. LinearView 2.0 runs under Windows (R) 3.1, Windows 95 and Macintosh (R) System 7.0 or later. Available at no charge. World Wide Web Site Linear Technology Corporation's customers can now quickly and conveniently find and retrieve the latest technical information covering the Company's products on LTC's new internet web site. Located at www.linear-tech.com, this site allows anyone with internet access and a web browser to search through all of LTC's technical publications, including data sheets, application notes, design notes, Linear Technology magazine issues and other LTC publications, to find information on LTC parts and applications circuits. Other areas within the site include help, news and information about Linear Technology and its sales offices. Linear Technology Corporation 1630 McCarthy Boulevard Milpitas, CA 95035-7417 Phone: (408) 432-1900 FAX: (408) 434-0507 Linear Technology Corporation Houston, TX 77478 Phone: (972) 733-3071 FAX: (972) 380-5138 U.S. Area Sales Offices Linear Technology Corporation 5510 Six Forks Road, Suite 102 Raleigh, NC 27609 Phone: (919) 870-5106 FAX: (919) 870-8831 Linear Technology Corporation 266 Lowell St., Suite B-8 Wilmington, MA 01887 Phone: (508) 658-3881 FAX: (508) 658-2701 The site is searchable by criteria such as part numbers, functions, topics and applications. The search is performed on a user-defined combination of data sheets, application notes, design notes and Linear Technology magazine articles. Any data sheet, application note, design note or magazine article can be downloaded or faxed back. (Files are downloaded in Adobe AcrobatTM PDF format; you will need a copy of Acrobat Reader to view or print them. The site includes a link from which you can download this program.) Acrobat is a trademark of Adobe Systems, Inc.; Windows is a registered trademark of Microsoft Corp.; Macintosh and AppleTalk are registered trademarks of Apple Computer, Inc. PSPICE is a trademark of MicroSim Corp. International Sales Offices World Headquarters NORTHEAST REGION Linear Technology Corporation 3220 Tillman Drive, Suite 120 Bensalem, PA 19020 Phone: (215) 638-9667 FAX: (215) 638-9764 Other web sites usually require the visitor to download large document files to see if they contain the desired information. This is cumbersome and inconvenient. To save you time and ensure that you receive the correct information the first time, the first page of each data sheet, application note and Linear Technology magazine is recreated in a fast, download-friendly format. This allows you to determine whether the document is what you need, before downloading the entire file. CENTRAL REGION Linear Technology Corporation 2010 E. Algonquin Road, Suite 209 Schaumburg, IL 60173 Phone: (847) 925-0860 FAX: (847) 925-0878 Linear Technology Corporation Kenosha, WI 53144 Phone: (414) 859-1900 FAX: (414) 859-1974 NORTHWEST REGION Linear Technology Corporation 1900 McCarthy Blvd., Suite 205 Milpitas, CA 95035 Phone: (408) 428-2050 FAX: (408) 432-6331 SOUTHWEST REGION Linear Technology Corporation 21243 Ventura Blvd., Suite 227 Woodland Hills, CA 91364 Phone: (818) 703-0835 FAX: (818) 703-0517 SOUTHEAST REGION Linear Technology Corporation 17000 Dallas Parkway, Suite 219 Dallas, TX 75248 Phone: (972) 733-3071 FAX: (972) 380-5138 Linear Technology Corporation 15375 Barranca Parkway, Suite A-211 Irvine, CA 92718 Phone: (714) 453-4650 FAX: (714) 453-4765 Linear Technology Corporation 9430 Research Blvd. Echelon IV Suite 400 Austin, TX 78759 Phone: (512) 343-3679 FAX: (512) 343-3680 (c) 1998 Linear Technology Corporation/Printed in U.S.A./ 41K 36 FRANCE Linear Technology S.A.R.L. Immeuble "Le Quartz" 58 Chemin de la Justice 92290 Chatenay Malabry France Phone: 33-1-41079555 FAX: 33-1-46314613 SINGAPORE Linear Technology Pte. Ltd. 507 Yishun Industrial Park A Singapore 768734 Phone: 65-753-2692 FAX: 65-754-4113 SWEDEN Linear Technology AB Sollentunavagen 63 S-191 40 Sollentuna Sweden Phone: (08)-623-1600 FAX: (08)-623-1650 GERMANY Linear Technology GmbH Oskar-Messter-Str. 24 D-85737 Ismaning Germany Phone: 49-89-962455-0 FAX: 49-89-963147 JAPAN Linear Technology KK 5F NAO Bldg. 1-14 Shin-Ogawa-cho Shinjuku-ku Tokyo, 162 Japan Phone: 81-3-3267-7891 FAX: 81-3-3267-8510 KOREA Linear Technology Korea Co., Ltd Namsong Building, #403 Itaewon-Dong 260-199 Yongsan-Ku, Seoul 140-200 Korea Phone: 82-2-792-1617 FAX: 82-2-792-1619 TAIWAN Linear Technology Corporation Rm. 602, No. 46, Sec. 2 Chung Shan N. Rd. Taipei, Taiwan, R.O.C. Phone: 886-2-521-7575 FAX: 886-2-562-2285 UNITED KINGDOM Linear Technology (UK) Ltd. The Coliseum, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone: 44-1276-677676 FAX: 44-1276-64851 LINEAR TECHNOLOGY CORPORATION 1630 McCarthy Boulevard Milpitas, CA 95035-7417 (408) 432-1900 FAX (408) 434-0507 www.linear-tech.com For Literature Only: 1-800-4-LINEAR Linear Technology Magazine * February 1998