MAX9959
25V Span, 800mA Device Power Supply (DPS)
________________________________________________________________
Maxim Integrated Products
1
19-3931; Rev 4; 2/11
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
General Description
The MAX9959 provides all the key features of a device
power supply (DPS) common to automatic test equip-
ment (ATE) and other instrumentation. Its small size,
high level of integration, and superb flexibility make the
MAX9959 ideal and economical for multisite systems
requiring many device power supplies.
The MAX9959 has multiple input control voltages that
allow independent setting of both the output voltage,
and the maximum and minimum (smallest positive or
most negative) voltage or current. The MAX9959 is a
voltage source when the load current is between the
two programmed limits, and transitions gracefully into a
precision current source/sink if a programmed current
limit is reached. The output features two independently
adjustable voltage clamps that limit both the negative
and positive output voltage values between levels
externally provided.
The MAX9959 can source voltages spanning 25V and
can source currents as high as ±800mA. The DPS can
support an external buffer for sourcing and sinking
higher currents. Multiple MAX9959s can be configured
in parallel to load-share, allowing higher output currents
with greater flexibility.
The MAX9959 features operation over a wide range of
loading conditions. Programmability allows optimizing
of settling time, over-/undershoot, and stability. Built-in,
configurable, range-change glitch-control circuits mini-
mize output glitches during range transitions.
The MAX9959 offers load regulation of 1mV at 800mA
load.
The MAX9959D features an internal 300kΩsense
resistor (RFS), between RCOMF and SENSE. The
MAX9959F does not include this sense resistor. Both
devices are available in the 100-pin TQFP package with
an exposed pad on the top for heat removal.
Applications
Memory Testers
VLSI Testers
System-On-a-Chip Testers
Industrial Systems
Structural Testers
Features
o25V Span Output Voltage
oProgrammable Current and Voltage Compliance
oProgrammable Current Ranges
±200µA
±2mA
±20mA
±800mA
oLoad Regulation of 1mV at 800mA
oExternal Buffer Support for Higher Currents
oParallel Multiple Devices for Higher Currents
oProgrammable Gain Allows a Wide Range of DACs
oDevice-Under-Test (DUT) Ground Sense
oProgrammable Compensation for Wide Range
of Loads
oIntegrated Go/No-Go Comparators
oIDDQ Test Mode
oRange-Change Glitch Control
oCompact (14mm x 14mm) Package
o3-Wire Compatible Serial Interface
oThermal Warning Flag and Thermal Shutdown
Ordering Information
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EPR = Exposed pad. Inverted die pad.
PA R T
T EM P RA N G E
PIN - PA C K A G E
M AX 9959D C C Q0°C to + 70°C 100 TQFP - E P R- ID P
*
M AX 9959D C C Q+
0°C to + 70°C 100 TQFP - E P R- ID P
*
M AX 9959FC C Q+
0°C to + 70°C 100 TQFP - E P R- ID P
*
Pin Configuration appears at end of data sheet.
MAX9959
25V Span, 800mA Device Power Supply (DPS)
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC = +12V, VEE = -12V, VL= +3.3V, TJ= +30°C to +100°C. Typical values are at TJ= +30°C, unless otherwise specified.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC to VEE …...................................................................... +31V
VCC to AGND...................................................................... +20V
VEE to AGND….................... .................................................-15V
VLto DGND .......................................................................... +6V
AGND to DGND.....................................................-0.5V to +0.5V
Digital Inputs ................................................-0.3V to (VL+ 0.3V)
All Other Pins ...................................(VEE - 0.3V) to (VCC + 0.3V)
Continuous Power Dissipation (TA= +70°C)
100-Pin TQFP-EPR-IDP (derated at 166.7mW/°C
above +70°C)........................................................13.33W
Junction Temperature..................................................... +150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................ +300°C
Soldering Temperature (reflow)
Lead(Pb)-Free Packages.............................................+260°C
Packages Containing Lead(Pb)...................................+240°C
PARAMETER
SYMBOL
CONDITIONS MIN
TYP
MAX
UNITS
VOLTAGE OUTPUT
DUT current below 10% of FSR current
VEE + 2.5 VCC - 2.5
D U T cur r ent = + 800m A, r ang e A ( N ote 2) 0 +7
DUT current = -800mA, range A (Note 2) -7 0Output Voltage Range VDUT
DUT current at full scale (IDUT = 200µA,
2mA, 20mA, or 200mA)
VEE + 5 VCC - 5
V
Output Offset VOS VIN = 0V, IOUT = 0A (no load), gain = +1 ±25 mV
Output-Voltage Temperature
Coefficient VOSTC
±50 µV/°C
Gain = +1 ±1.25
Gain = +2 ±1.25
Gain = +6 ±1.25
Gain = -1 ±1.25
Gain = -2 ±1.25
Voltage Gain Error VGE
Gain = -6 ±1.25
%
Voltage-Gain Temperature
Coefficient VGETC
±5 ppm/°C
Linearity Error VLER
Gai n and offset er r or s cal i b r ated out; IOU T =
0 for r ang es A, C , and D ; ± 20m A for r ang e
B; g ai n = + 1 ( N otes 3, 4, 5)
±0.02
%FSR
Off-State Leakage Current HIZFLK RCOMF = (VCC - 2.5V) to (VEE + 2.5V) -10 +10 nA
Force-to-Sense Resistor RFS “D” option only
300
kΩ
DUT GROUND SENSE
Voltage Range
ΔVDUTGND
VDUTGSNS - VAGND ±500
±700
mV
LOAD REGULATION (Note 6)
Voltage ΔVDUT
Range A, gain = +1, VIN = (VCC - 5V) to
(VEE + 5V), ±800mA current load step
(Note 5)
±1
±7 mV
MAX9959
25V Span, 800mA Device Power Supply (DPS)
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +12V, VEE = -12V, VL= +3.3V, TJ= +30°C to +100°C. Typical values are at TJ= +30°C, unless otherwise specified.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS MIN
TYP
MAX
UNITS
CURRENT OUTPUT
Range D, RD = 5000Ω
±200
µA
Range C, RC = 500Ω±2
Range B, RB = 50Ω±20
Output Current Range IDUT
Range A, RA = 1.25Ω
±800
mA
IOSI = AGND -4 +4
Inp ut V ol tag e Rang e
C or r esp ond i ng to the Ful l - S cal e
For ce C ur r ent
VINI
VIOSI = VAGND + 4V 0 +8
V
Current-Sense-Amp Offset
Voltage Input VIOSI Relative to AGND -0.2 +4.4 V
Output Current Offset IOS VRCOMF = 0V (Note 4)
±0.1
±0.5
%FSR
Force-Current Offset
Temperature Coefficient IOSTC
±20 ppm/°C
Gain Error IGE VRCOMF = 0V, IOUT = ±FSR ±1.0 %
Forced-Current Gain
Temperature Coefficient IGETC
±20 ppm/°C
Range D, IOUT = ±200µA ±135
±147 ±158
Range C, IOUT = ±2mA ±135
±147 ±158
Range B, IOUT = ±20mA ±135
±147 ±158
Output Over Current-Limit
Range (Note 4) IOCL
Range A, IOUT = ±800mA ±125
±138 ±150
%FSR
Linearity Error ILER
Gain, offset, and CMR errors calibrated
out; VIOSI = -0.2V and +4.4V; ranges B, C,
and D (Notes 4, 5, 7)
±0.02 %FSR
Rej ecti on of Outp ut E r r or D ue to
C om m on- M od e Load V ol tag e
CMROER
Rang e D, IOU T = 0, VRC OMF = ( V
E E
+ 2.5V)
and ( V
C C
- 2.5V) , measur ed acr oss RD
0.001 0.005 %FSR/V
CURRENT MONITOR
Range D
±200
µA
Range C ±2
Range B
±20
Measured Current Range IDUTM
Range A
±800
mA
IOSI = AGND -4 +4
Current-Sense-Amp Voltage
Range
VISENSE
VIOSI = VAGND + 4V 0 +8 V
Current-Sense-Amp Offset
Voltage Input VIOSI Relative to AGND -0.2 +4.4 V
Current-Sense-Amp Offset IMOS VRCOMF = 0V (Note 4)
±0.1
±0.5
%FSR
Measured-Current Offset
Temperature Coefficient
IMOSTC ±20 ppm/°C
Gain Error IMGE VRCOMF = 0V, IOUT = ±FSR ±1 %
MAX9959
25V Span, 800mA Device Power Supply (DPS)
4 _______________________________________________________________________________________
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +12V, VEE = -12V, VL= +3.3V, TJ= +30°C to +100°C. Typical values are at TJ= +30°C, unless otherwise specified.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS MIN
TYP
MAX
UNITS
Measured-Current Gain
Temperature Coefficient
IMGETC ±20 p p m /° C
Linearity Error IMLER Gain, offset, and CM R er r ors cal i b rated out;
V
IOSI = -0.2V and + 4.4V , r ang e B ( N otes 4, 5)
±0.02
%FSR
Rej ecti on of Outp ut E r r or D ue to
C om m on- M od e Load V ol tag e
CMRMOER
Range D, IOUT = 0A, VRCOMF =
(VEE + 2.5V) and (VCC - 2.5V)
0.001
0.005 %FSR/
V
VOLTAGE MONITOR
M easur ed Outp ut V oltag e Rang eV
DUTM Gain = +1, IOSV = AGND
VEE + 2.5 VCC - 2.5
V
Voltage-Sense-Amp Offset
Voltage Input VIOSV Relative to AGND -0.2 +4.4 V
Voltage-Sense-Amp Offset
VDUTMOS
Gain = +1 ±25 mV
Measured Voltage Offset
Temperature Coefficient
VDUTMOSTC ±10 µV/°C
Gain = +1 ±1
Gain = +1/2 ±1
V ol tag e- S ense- Am p G ai n E r r or
VDUTGE
Gain = +1/6 ±1
%
Measured-Voltage Gain
Temperature Coefficient
VDUTGETC ±10 p p m /° C
Linearity Error
VDUTLER
Gain and offset errors calibrated out,
VIOSV = -0.2V and +4.4V, IOUT = 0A, gain
= +1, range B (Note 4)
±0.02
%FSR
VOLTAGE/CURRENT CLAMPS (Note 8)
Input Control Voltage VCLLO,
VCLHI
VEE + 2.3 VCC - 2.3
V
DPS output current ≤ 10% of FSR
VEE + 2.5 VCC - 2.5
Voltage Clamp Range (Note 9)
VCRNG DPS output current at FSR
VEE + 5 VCC - 5
V
Voltage Clamp Gain
VCGAIN +1
V/V
Range A to D, IOUT ≤ 10% of FSR ±200
Voltage Clamp Accuracy
(Notes 2, 9) VCERR Range A to D, IOUT = ±FSR ±200 mV
Current Clamp Range ICRNG (Note 10)
VIOSI
±1.5 x
FSR
V
Current Clamp Gain ICGAIN 4
V/FSR
Range A, VOUT = ±FSR, IOUT = ±FSR
(Notes 2, 10) ±0.15
Current Clamp Accuracy ICERR Range B to D, VOUT = ±FSR, gain and
offset errors calibrated out (Note 10) ±0.05
%FSR
COMPARATOR INPUTS
Input Voltage Range
CMPIRG VEE + 3.5 VCC - 3.5
V
Input Offset Voltage
CMPIOS
VITHHI = VITHLO = 0V ±30 mV
MAX9959
25V Span, 800mA Device Power Supply (DPS)
_______________________________________________________________________________________ 5
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +12V, VEE = -12V, VL= +3.3V, TJ= +30°C to +100°C. Typical values are at TJ= +30°C, unless otherwise specified.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS MIN
TYP
MAX
UNITS
COMPARATOR OUTPUTS
Output High Voltage
CMPOH
VL = 2.375V to 3.3V, RPULLUP = 1kΩ
VL - 0.2
V
Output Low Voltage
CMPOL
VL = 2.375V to 3.3V, RPULLUP = 1kΩ0.4 V
High-Impedance State
Leakage Current
CMPOLK ±5
nA
High-Impedance Output
Capacitance
CMPOC
1pF
ANALOG INPUTS
Input Current IIN
±5
nA
Input Capacitance CIN 4pF
DIGITAL INPUTS
Input High Voltage VIH VTHR +
0.15 V
Input Low Voltage VIL VTHR -
0.15 V
VTHR Input Range VTHR 0.5
VL - 0.5
V
Input Current IIN
±25
µA
Input Capacitance CIN 4pF
DIGITAL OUTPUTS
Output High Voltage VOH VL = 2.375V to 3.3V, relative to DGND,
IOUT = +1.0mA
VL - 0.25
V
Output Low Voltage VOL VL = 2.375V to 3.3V, relative to DGND,
IOUT = -1.0mA 0.2 V
TEMPERATURE SENSOR
Analog Output Offset
VTSNSO
TJ = +28°C
3.01
V
Analog Output Gain
VTSNSG 10 mV/°C
Digital Output Temperature
Threshold
TTSNSR
(Note 11)
+130
°C
Thermal-Shutdown Temperature
TSDN
+140
°C
POWER SUPPLY
Positive Supply VCC (Note 12) 12 18 V
Negative Supply VEE (Note 12) -15 -12 V
Total Supply Voltage
VCC - VEE
+30 V
Logic Supply VL
+2.375 +3.300
V
Positive Supply Current ICC No load 20 22 mA
Negative Supply Current IEE No load 19 21 mA
Analog Ground Current IAGND No load
0.8
1.0 mA
Logic Supply Current ILNo load, all digital inputs at DGND
7.0
9.0 mA
Digital Ground Current
IDGND
No load, all digital inputs at DGND
7.0
9.0 mA
Power-Supply Rejection Ratio PSRR Each supply varied individually from min
to max, VDUT = 5.0V 80 dB
MAX9959
25V Span, 800mA Device Power Supply (DPS)
6 _______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS
(VCC = +12V, VEE = -12V, VL= +3.3V, CC1 = 350pF, CL= 100pF, CMEAS = 100pF, CIMEAS = 100pF, TJ= +30°C to +100°C. Typical
values are at TJ= +35°C, unless otherwise specified.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS MIN TYP
MAX
UNITS
FORCE VOLTAGE (Notes 13, 14)
Range D = ±200µA, RL = 35kΩ to AGND 30
Range C = ±2mA, RL = 3.5kΩ to AGND 20
Range B = ±20mA, RL = 350Ω to AGND 30 50
Settling Time FVST
Range A = ±800mA, RL = 8.75Ω to AGND 25
µs
LOAD REGULATION SETTLING TIME (Note 14)
Settling Time LRST Range A, VIN = ±7V, RL = 8.75Ω switched
between open circuit to AGND, CL = 10µF 100 µs
FORCE VOLTAGE/MEASURE CURRENT (Notes 13, 14, 15)
Range D = ±200µA, RL = 35kΩ to AGND 50
Range C = ±2mA, RL = 3.5kΩ to AGND 20
Range B = ±20mA, RL = 350Ω to AGND 25 50
Settling Time
FVMIST
Range A = ±800mA, RL = 8.75Ω to AGND 35
µs
FORCE CURRENT (Notes 13, 14)
Range D = ±200µA, RL = 35kΩ to AGND 100
Range C = ±2mA, RL = 3.5kΩ to AGND 35
Range B = ±20mA, RL = 350Ω to AGND 25 50
Settling Time FIST
Range A = ±800mA, RL = 8.75Ω to AGND 20
µs
FORCE CURRENT/MEASURE VOLTAGE (Notes 13, 14, 15)
Range D = ±200µA, RL = 35kΩ to AGND 100
Range C = ±2mA, RL = 3.5kΩ to AGND 35
Range B = ±20mA, RL = 350Ω to AGND 25 50
Settling Time
FIMVST
Range A = ±800mA, RL = 8.75Ω to AGND 40
µs
FORCE OUTPUT
Output Slew Rate
FOSLEW
CL = 0F (Note 16) 0.7 2.1 V/µs
S tab l e Load C ap aci tance Rang eFO
SLC
(Notes 17, 18)
1000
µF
Output Overshoot
FOOSHT
CL < 20µF, CB1 = 3nF 0 %
MEASURE OUTPUT
S tab l e Load C ap aci tance Rang eMO
SLC
(Note 17)
1000
pF
COMPARATORS (CILIMHI/ILIMLO = 20pF, RPULLUP = 1kΩ) (Note 19)
Propagation Delay
CMPPD
100mV overdrive, 1VP-P, measured from
input threshold zero crossing to 50% of
output voltage
100 ns
Rise Time
CMPTR
20% to 80% 80 ns
Fall Time
CMPTF
20% to 80% 5 ns
Disable True to High
Impedance
CMPHIZT
Measured from 50% of digital input voltage
to 10% of output voltage 100 ns
Disable False to Active
CMPHIZF
Measured from 50% of digital input voltage
to 90% of output voltage 100 ns
MAX9959
25V Span, 800mA Device Power Supply (DPS)
_______________________________________________________________________________________ 7
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +12V, VEE = -12V, VL= +3.3V, CC1 = 350pF, CL= 100pF, CMEAS = 100pF, CIMEAS = 100pF, TJ= +30°C to +100°C. Typical
values are at TJ= +35°C, unless otherwise specified.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS MIN TYP MAX
UNITS
SERIAL PORT TIMING CHARACTERISTICS (VL = 3.0V, CDOUT = 10pF) (Figure 4)
Serial Clock Frequency fSCLK 20 MHz
SCLK Pulse-Width High tCH 12 ns
SCLK Pulse-Width Low tCL 12 ns
SCLK Fall to DOUT Valid tDO 25 ns
CS Low to S C LK H i g h S etup
tCSS0 10 ns
S C LK H i g h to CS H i g h H ol d
tCSH1 22 ns
S C LK H i g h to CS Low H ol d tCSH0 ( N ote 17) 0 ns
CS H ig h to S CLK Hi g h S etup
tCSS1 5ns
DIN to SCLK High Setup tDS 10 ns
DIN to SCLK High Hold tDH 0ns
CS Pulse-Width High
tCSWH
10 ns
CS Pulse-Width Low tCSWL 10 ns
LOAD Pulse-Width Low tCLL 20 ns
Power-On Reset POR 50 µs
Note 1: All minimum and maximum test limits are 100% production tested at TJ= +35°C ±15°C at nominal supplies.
Specifications over the full operating temperature range are guaranteed by design and characterization.
Note 2: Exercise care not to exceed the maximum power dissipation specifications listed in the
Absolute Maximum Ratings
section. With drive current of ±800mA limit DPS operation to two quadrants (i.e., when sourcing current limit VDUT to
below +7V, when sinking current limit VDUT to above -7V). With drive current below ±800mA and four-quadrant opera-
tion, limit DPS power dissipation to below the allowed maximum.
Note 3: VIN swept to achieve an output voltage of (VEE + 2.5V) to (VCC - 2.5V), with IOUT = 0.
Note 4: Parameters expressed in terms of %FSR (percent of full-scale range) are as a percent of the end-point-to-end-point range.
Note 5: Case must be maintained to within ±5°C for linearity specifications to apply.
Note 6: Load regulation is defined at a single programmed output voltage (force voltage mode), independent of linearity specification,
with a 0 to 100% current step.
Note 7: To maintain linearity, keep the clamps at least 700mV away from VRCOMF.
Note 8: In the force-current and force-voltage modes, the reference-clamping voltage CLH must be greater than 0V, and CLL must
be less than 0V. For high clamping accuracy, CLH-CLL is > 1V. To maintain 0.02% force-voltage linearity when the pro-
grammable current clamps are enabled, two conditions must be met: 1) CLH and CLL must be set 12.5% FSR higher than
the forced current and 2) CLH and CLL must be set such that CLH is ≥1.6V + IOSI and CLL is ≤-1.6V + IOSI (e.g., if driving
±1mA in the 2mA range, the current clamps must be set to a minimum of ±1.5mA, or CLH = 3V, CLL = -3V, and IOSI = 0V).
Note 9: DPS in force current mode.
Note 10: DPS in force voltage mode.
Note 11: The temperature threshold may vary up to ±10°C from the specified threshold.
Note 12: The device operates properly within absolute specifications, for varying supply voltages with equally varying output voltage settings.
Note 13: Settling times are for a full-scale voltage or current step. FVST measured from VIN to VDUT, FVMIST from VIN to IMEAS,
FIST from VIN to VDUT, and FIMVST from VIN to VMEAS.
Note 14: Settling times are to 0.1% of FSR.
Note 15: The actual settling time of the measure path (sense input to measure output) is less than 1µs. However, the RC time constant
of the sense resistor and the load capacitance causes a longer overall settling time of VDUT. This settling time is a function
of the current range resistor.
Note 16: Slew rate is measured from the 20% to 80% points.
Note 17: Guaranteed by design and characterization.
Note 18: Range A.
Note 19: The propagation delay time is measured by holding the current constant, and transitioning ITHHI or ITHLO.
MAX9959
25V Span, 800mA Device Power Supply (DPS)
8 _______________________________________________________________________________________
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
TRANSIENT RESPONSE
FVMI MODE, RANGE A
MAX9959 toc01
t = 10
µ
s/div
VIMEAS
VDUT
2V/div
0
VIN
TRANSIENT RESPONSE
FVMI MODE, RANGE B
MAX9959 toc02
t = 10
µ
s/div
VIMEAS
VDUT
2V/div
0
VIN
TRANSIENT RESPONSE
FVMI MODE, RANGE C
MAX9959 toc03
t = 10
µ
s/div
VIMEAS
VDUT
2V/div
0
VIN
TRANSIENT RESPONSE
FVMI MODE, RANGE D
MAX9959 toc04
t = 15
µ
s/div
VIMEAS
VDUT
2V/div
0
VIN
TRANSIENT RESPONSE
FVMV MODE, RANGE C
MAX9959 toc05
t = 5
µ
s/div
VVMEAS
VDUT
2V/div
0
VIN
TRANSIENT RESPONSE
FIMV MODE, RANGE A
MAX9959 toc06
t = 10
µ
s/div
VVMEAS
VDUT
2V/div
0VIN
TRANSIENT RESPONSE
FIMV MODE, RANGE B
MAX9959 toc07
t = 10
µ
s/div
VVMEAS
VDUT
2V/div
0VIN
TRANSIENT RESPONSE
FIMV MODE, RANGE C
MAX9959 toc08
t = 10
µ
s/div
VVMEAS
VDUT
2V/div
0VIN
TRANSIENT RESPONSE
FIMV MODE, RANGE D
MAX9959 toc09
t = 25
µ
s/div
VVMEAS
VDUT
2V/div
0VIN
MAX9959
25V Span, 800mA Device Power Supply (DPS)
_______________________________________________________________________________________ 9
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
TRANSIENT RESPONSE
FIMI MODE, RANGE C
MAX9959 toc10
t = 10
µ
s/div
2V/div
0VIN
VIMEAS
VDUT
7V
MAX9959 toc11
t = 100µs/div
VDUT = 50mV/div
LOAD REGULATION
TRANSIENT RECOVERY
VDUT = 7V
LOAD = 0 TO 800mA TO 0
CLOAD = 47µF
7V
MAX9959 toc12
t = 50µs/div
VDUT = 300mV/div
LOAD REGULATION
TRANSIENT RECOVERY
VDUT = 7V
LOAD = 0 TO 800mA TO 0
CLOAD = 10µF
RESPONSE TO CAPACITIVE LOAD
RISING EDGE
MAX9959 toc13
t = 10µs/div
2V/div
0
CLOAD = 0.47µF
100pF LEAD
CB1 = 3000pF
NO COMPENSATION
VIN
RESPONSE TO CAPACITIVE LOAD
FALLING EDGE
MAX9959 toc14
t = 10
µ
s/div
2V/div
0
CLOAD = 0.47µF
100pF LEAD
CB1 = 3000pF
NO COMPENSATION
VIN
RESPONSE TO CAPACITIVE LOAD
POSITIVE SIGNAL
MAX9959 toc15
t = 1ms/div
1V/div
0
VIN
CB3 = 0.025µF
CLOAD = 1000µF
RESPONSE TO CAPACITIVE LOAD
NEGATIVE SIGNAL
MAX9959 toc16
t = 1ms/div
1V/div
0
CLOAD = 1000µF
VIN
CB3 = 0.025µF
RANGE-CHANGE
GLITCH
MAX9959 toc17
t = 10
µ
s/div
25mV/div
0
IDDQSEL = LOW TO HIGH
FV RANGE A TO D
CT = 250pF
CT = 0
RANGE-CHANGE
GLITCH
MAX9959 toc18
t = 5
µ
s/div
50mV/div
0
CT = 0
CT = 250pF
IDDQSEL = HIGH TO LOW
FV RANGE D TO A
MAX9959
25V Span, 800mA Device Power Supply (DPS)
10 ______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1–8 RA Range A Outputs. Connect together and to a range-setting resistor.
9
BIFRCA
Positive Current-Sense-Amplifier Input. Used in range A to provide a Kelvin connection to range-
setting resistor.
10 RB Range B Output. Connect to a range-setting resistor.
11
BIFRCB
Positive Current-Sense-Amplifier Input. Used in range B to provide a Kelvin connection to range-
setting resistor.
12 RC Range C Output. Connect to a range-setting resistor.
13 RD Range D Output. Connect to a range-setting resistor.
14
RCOMF
Sense Resistors Kelvin Connection. The Kelvin connection for the sense resistors that connect to
the DUT. RCOMF provides a feedback point for current sensing.
15
SENSE
Sense Input. Kelvin connection to the DUT. Provides the feedback signal for FVMI and the
measured signal for FIMV.
16
D U TGS N S
DUT Ground Sense. In force voltage mode, senses the error between AGND and DUTGND and
adjusts the output voltage to achieve the desired voltage drop across the DUT with respect to
DUTGND.
17, 18, 25, 49,
77–84, 93, 99 VCC Positive Analog Supply
19, 20, 26, 50, 76,
85–92, 95, 100 VEE Negative Analog Supply
21 VRXP Positive Current-Sense-Amplifier Input. Used in the external range to provide a Kelvin connection
to the range-setting resistor.
22 VRXM Negative Current-Sense-Amplifier Input. Used in the external range to provide a Kelvin connection
to the range-setting resistor.
23 CT1 Range-Change Glitch-Control Capacitor Connection. Connect optional capacitor from CT1 to
DGND.
24 CT2 Range-Change Glitch-Control Capacitor Connection. Connect optional capacitor from CT2 to
DGND.
27, 28, 45–48,
96, 97, 98 N.C. No Connection. Make no connection to these pins.
29, 38, 44
DGND
Digital Ground
30
HIZMP
High-Impedance Control Input. Places current and voltage measure outputs into a high-
impedance state.
31
IDDQSEL
IDDQ Test Select. In FV mode, switches between the programmed current range and range D, the
lowest current range.
32 DIN Data Input. Serial interface data input.
33 LOAD Load D ata Inp ut. A fal l i ng ed g e at LO AD tr ansfer s d ata fr om the i np ut r eg i ster s to the D P S r eg i ster s.
34 SCLK Serial Clock Input. Serial interface clock.
35 CS Chip-Select Input
36 VTHR Threshold Voltage Input. Sets the input logic threshold level of all digital inputs. Defaults to 1/2 VL
if unconnected.
37 VLLogic Power Supply
MAX9959
25V Span, 800mA Device Power Supply (DPS)
______________________________________________________________________________________ 11
Pin Description (continued)
PIN
NAME
FUNCTION
39
DOUT
Data Output. Serial interface data output.
40
EXTSEL
External Select Output. Selects the external range.
41
HITEMP
High Temperature Indicator Output. Open-collector output goes low when the temperature of the
die is above the specified safe operating temperature.
42
ILIMLO
Low Current-Limit Output. A sensed current below the ITHLO level forces the ILIMLO output low.
ILIMLO is an open-drain output.
43
ILIMHI
High Current-Limit Output. A sensed current above the ITHHI level forces the ILIMHI output low.
ILIMHI is an open-drain output.
51
ITHLO
Low Current-Limit Input. Voltage input that sets the lower threshold for the sense current
comparator.
52 ITHHI High Current-Limit Input. Voltage input that sets the upper threshold for the sense current
comparator.
53 IOSI Current-Sense Offset Voltage Input. Voltage input that sets an offset voltage for the current-sense
amplifier in either FI or MI mode.
54 IOSV Measure Offset Voltage Input. Voltage input that sets an offset voltage for the measure voltage
amplifier.
55 VINS Forced-Current Input. Voltage input that sets the forced current in FI slave mode.
56 VIN Forced-Current/Voltage Input. Voltage input that sets the forced current in FI mode or forced
voltage in FV mode.
57
AGND
Analog Ground
58 CLL Compliance Low Input. Voltage input that sets the low-side voltage/current compliance.
59 CLH Compliance High Input. Voltage input that sets the high-side voltage/current compliance.
60 IPAR C ur r ent- C ontr ol l ed P r op or ti onal V ol tag e O utp ut. IP AR outp uts a vol tag e that i s p r op or ti onal to the D U T
cur r ent. U sed to sl ave ad d i ti onal p ar al l el D P S s to p r ovi d e i ncr eased outp ut cur r ent.
61
IMEAS
Current-Controlled Proportional Voltage Output. IMEAS outputs a voltage that is proportional to the
DUT current. High impedance when HIZMP is forced low.
62
VMEAS
Voltage-Controlled Proportional Voltage Output. VMEAS outputs a voltage equal to 1x, 1/2x, or
1/6x the voltage present at SENSE. High impedance when HIZMP is forced low.
63 TEMP Tem p er atur e M oni tor O utp ut. TE M P outp uts a vol tag e p r op or ti onal to d i e tem p er atur e of 10m V /K.
64 CBC CB Common. Common point for bypass capacitor connections CB1, CB2, and CB3.
65 CB1 Bypass Capacitor 1. Compensation capacitor 1 connection.
66 CB2 Bypass Capacitor 2. Compensation capacitor 2 connection.
67 CB3 Bypass Capacitor 3. Compensation capacitor 3 connection.
68 CC1 Main Compensation Capacitor. Compensation capacitor connection 1.
69 CC2 Main Compensation Capacitor. Compensation capacitor connection 2.
70 CCHL Clamp Compensation Capacitor Common. Common connection for CCL and CCH.
71 CCH H i g h C l am p Com p ensati on C ap aci tor . Hi g h- si d e vol tag e cl am p com p ensati on cap aci tor connecti on.
72 CCL Low C l am p C om p ensati on C ap aci tor . Low - si d e vol tag e cl am p comp ensati on cap aci tor connecti on.
73
SAMPO
Lead Compensation Capacitor Common. Common connection for CCOMP1 and CCOMP2.
74
CCOMP1
Compensation Capacitor 1. Lead compensation capacitor 1 connection.
75
CCOMP2
Compensation Capacitor 2. Lead compensation capacitor 2 connection.
94
AMPOUT
Main Amplifier Output. Drives the external buffer when in external range mode.
—EP
Exposed pad. Internally connected to VEE. Connect to a large VEE power plane or heatsink to
maximize thermal performance. Not intended as an electrical connection point.
MAX9959
25V Span, 800mA Device Power Supply (DPS)
12 ______________________________________________________________________________________
Detailed Description
The MAX9959 device power supply (DPS) is a voltage
source when the load current is between the two pro-
grammed limits and transitions gracefully into a preci-
sion current source/sink if a programmed current limit is
reached. It provides voltage-control inputs that allow
independent setting of the output voltage, the maximum
voltage (current), and the minimum (smallest positive or
most negative) voltage (current), and it can source volt-
ages over a span of 25V at up to ±800mA of current.
For currents less than ±200mA, the MAX9959 provides
full four-quadrant operation. It supports the addition of
an external buffer for sourcing and sinking higher cur-
rents, and multiple MAX9959s can be paralleled to
load-share, thus realizing higher total current capability
with greater flexibility. Additionally, the output features
two independently adjustable clamps that limit both the
negative and positive output voltages or currents to
externally provided limits. It offers voltage and current
measurement outputs, a window comparator for go/no-
go testing, a temperature monitor, a high-temperature
warning flag, and a high-temperature shutdown.
The MAX9959D features an internal 300kΩsense resis-
tor, RFS, between RCOMF and SENSE. The MAX9959F
version does not include this sense resistor.
Analog Signal Polarities
In force-voltage mode the output voltage (SENSE/
RCOMF in Figure 1, the
Functional Diagram
) is proportional
to the input control voltage and determined by the choice
CLH
IMEAS
HIZM
BIFRCA
AMPOUT
1kΩ
VRXP
RCOMF
AGND
DUT
NODE
FIMODE
FVMODE
CLL
VMEAS
HIZM
SENSE
SAMPO
CCOMP1
CCOMP2
DUTGSNS
(8x)
IOSI
ITHLO
ITHHI
ILIMHI
ILIMLO
BIFRCB
IPAR
IOSV
VRXM
CLEN
VL
VL
CB1
CB2
CB3
CBC
A1
ICLMP
VCLMP
CCH
CCL
CCHL
CC2
RA
RB
RC
RD
CS
SCLK
LOAD
DIN
DOUT
HIZMP HIZM
SERIAL INTERFACE
CONTROL AND CONFIGURATION
REGISTERS
HITEMP
TEMP
IDDQSEL EXTSEL
RFS
("D" VERSION ONLY)
GAIN
SELECT
HIZF
COMPENSATION
SELECT
LEAD
COMPENSATION
SELECT
TEMPERATURE
SUPERVISOR
WATCHDOG
POWER-ON
RESET CT1
CT2
SWITCH
CONTROL
DGND
VTHR
VCC
VEE
VL
DGND
VIN
VINS
FISLAVE
MODE
GAIN
SELECT
CC1 AGND HIZF
AGND
DUT
4x
CC
MAX9959
VL
HIZCMP
Figure 1. Functional Diagram
MAX9959
25V Span, 800mA Device Power Supply (DPS)
______________________________________________________________________________________ 13
of one of three +/- gain settings controlled through the seri-
al interface.
In force-current mode, the output current is proportional
to the input control voltage and behaves according to
the formula:
Positive current is defined as flowing out of the
MAX9959 DPS.
In high-impedance mode, outputs RA, RB, RC, and RD
are high impedance.
Current-Sense-Amplifier Offset
Voltage Input
The current-sense amplifier monitors the voltage across
the output resistors connected to RA, RB, RC, and RD
in Figure 1. The current-sense offset voltage input, IOSI,
introduces an offset to the current-sense amplifier.
When IOSI is zero relative to AGND, the nominal output
voltage range of the current-sense amplifier, corre-
sponding to a +/- full-scale output current, is -4V to
+4V. Voltage applied to IOSI adds directly to this output
voltage. For example, if +4V is applied to IOSI, the volt-
age range corresponding to +/- full-scale current
becomes 0 to +8V, within the range allowed by the
power-supply rails.
Measure Voltage-Sense-Amplifier Offset
Voltage Input
The measure voltage-sense amplifier monitors the out-
put voltage of the MAX9959. The measure offset volt-
age input, IOSV, introduces an offset to the measure
voltage amplifier. Voltage applied to IOSV adds directly
to this output voltage.
External Mode Support
The MAX9959 includes resources to drive an external
amplifier to provide a current range beyond the highest
range (or below the lowest current range) included
within the device. A voltage output, AMPOUT, is provid-
ed for the input of the external amplifier, and a digital
output, EXTSEL, goes high to activate the external
amplifier. Feedback inputs VRXP and VRXM connect
across the external amplifier’s current-sense resistor.
The external amplifier must have a high-impedance out-
put when not selected (EXTSEL = low), if connected as
shown in Figure 1.
Parallel DPS Operation
The MAX9959 allows multiple devices to be configured
in parallel to increase the available DUT drive current.
One DPS must be configured as the master (in FV
mode), and the parallel devices must be configured as
slaves (in FI slave mode). The connection between the
master and slaves is made using the IPAR output and
VINS input. IPAR outputs a voltage that is proportional
to the DUT current and VINS provides a proportional
force-current/voltage input. Up to 16 MAX9959s can be
placed in parallel.
Voltage Clamps
Internal programmable voltage clamps limit the output
voltage to the programmed values when in FI mode.
Set the clamp voltage limits with inputs CLH and CLL.
The clamps handle the full ±800mA and are triggered
by the voltage at RCOMF independent of the voltage at
SENSE. Clamp enable bit, CLEN, in the serial control
word, enables the voltage clamps.
Current Limit
Programmable and default current limits are available
at the output in the FI and FV modes. When program-
mable current compliance is enabled, the DPS output
current limits at the preprogrammed setting for each
current range. When the current limit is disabled, the
DPS output current limits at the default value, 147%
FSR (typ), of the selected current ranges for range B,
C, and D. In range A, under FI or FV conditions, the
DPS output current limits at 138% FSR (typ). For currents
within each selected range, the FV output behaves as a
constant voltage source. When the default or pro-
grammed current compliance limits are reached, the
DPS transitions to constant current mode.
Current-Limit Flags
The MAX9959 can flag currents within user-specified
limits. This allows fast go/no-go testing in production
environments. The window comparator continuously
monitors the load current and compares it to inputs
ITHHI and ITHLO. The comparator outputs are open
collector and can be made high impedance with the
serial interface.
Measure Amplifier High-Impedance Modes
Measure outputs VMEAS and IMEAS can be placed in
a high-impedance state with logic input HIZMP or serial
interface bit HIZMS. This allows busing of the measure
outputs with other DPS measure outputs.
Ground and DUT Ground Sense
Two ground connections, AGND (analog ground) and
DGND (digital ground), are both local grounds. Connect
these grounds together on the printed circuit board
(PCB). DUT ground-sense input, DUTGSNS, allows
sensing with respect to the DUT in force voltage mode.
IV
R
OUT IN
SENSE
=4
MAX9959
25V Span, 800mA Device Power Supply (DPS)
14 ______________________________________________________________________________________
Short-Circuit Protection
RA, RB, RC, RD, AMPOUT, and SENSE withstand a short to
any voltage between and including the supply rails.
Temperature Sensor and Over-
Temperature Protection
The MAX9959 outputs a voltage proportional to its die
temperature, at TEMP, of 10mV/K (or 10mV/°C) with the
nominal output voltage being 3.43V at 343K (+70°C). If
the temperature of the die enters the range of +120°C to
+140°C, the open-collector output HITEMP goes low. If
the die temperature exceeds +140°C, the temperature
sensor issues a power-on reset, placing the DPS into its
high-impedance state. A reduction in temperature after
a temperature-initiated reset does not return the DPS to
its original operating state; reprogramming is required.
Mode and Range-Change Transients
Glitch minimization measures in the MAX9959 employ
make-before-break switching and internal clamps to
reduce output glitches. To guarantee minimum glitches
between range changes, change between adjacent
ranges, e.g., RA to RB, RD to RC. Do not switch to anoth-
er range until the present range-change operation has
been completed. In addition to the make-before-break
measures, connections CT1 and CT2 are provided for
optional capacitors that control the edge rate of the gate
drive to the range-change switches. Two capacitors of
150pF each provide a reasonable balance between glitch
control and range-change transition time.
DUT Voltage Swing vs. DUT Current and
Power-Supply Voltages
The DUT voltage that the MAX9959 can deliver is limited
by two main and two lesser factors:
1) The 2.5V overhead from each supply rail required
by the amplifiers and other on-chip circuitry.
2) The voltage drop across the sense resistor and
internal circuitry in series with the sense resistor.
At full current the combined voltage drop is 2.5V,
1V across the resistor and 1.5V across the switches.
This voltage is not all in addition to the overhead
requirement. There is some overlap of the two
effects; see Figure 2.
3) Variations in the system power-supply voltages.
4) Variations between the ground voltage of the
device-under-test and AGND.
Neglecting the effects of items 3 and 4, the output
capabilities of the DPS are demonstrated by Figure 2.
Figure 2 shows that for zero DUT current, the DUT volt-
age swing is from (VEE + 2.5V) to (VCC - 2.5V). For pos-
itive DUT currents, the maximum voltage drops off
linearly until it reaches VCC - 5V at full current. Similarly
for negative DUT currents, the magnitude of the nega-
tive voltage drops off linearly until it reaches VEE + 5V.
When the DPS is driving more than ±200mA output cur-
rent, the power dissipated by the DPS must be limited
to below the power limit of the package (see the
Absolute Maximum Ratings
and Note 2). For example,
when the DPS is driving ±800mA in range A, the VCC
supply must not exceed +12V, and the VEE supply
must not exceed -12V. When the DPS is sourcing cur-
rent, the DUT node must not be driven below zero volts.
When the DPS is sinking current, the DUT node must
not be driven above zero volts (two-quadrant opera-
tion). When operating below ±800mA, four-quadrant
operation may be possible depending on the power
dissipation of the DPS. Power dissipation analysis must
consider variations in the power-supply voltage and the
voltage difference between the device-under-test
ground and the DPS AGND (items 3 and 4 above).
Since the maximum output voltage range is relative to
the supply voltage, any decrease in a supply voltage
from nominal proportionally decreases the range. The
maximum output voltage range is also reduced by the
difference between the DUT ground and the analog
ground potentials (DUTGSNS - AGND). Note that within
these limitations, the forced DUT voltage is equal to
DUT ground plus the input control voltage. Similarly,
when measuring a voltage, the measured voltage is
equal to the difference between the DUT voltage and
DUT ground.
VDUT
IDUT
IMIN IMAX
VCC - 2.5V
VCC - 5V
VEE + 5V
VEE + 2.5V
Figure 2. Output Swing
MAX9959
25V Span, 800mA Device Power Supply (DPS)
______________________________________________________________________________________ 15
Configuration and Control
Configuration of the MAX9959 is achieved through the
serial interface, and through the dedicated logic-control
inputs HIZMP, LOAD, and IDDQSEL.
The serial interface has a shift register, an input regis-
ter, and a DPS register (Figure 3). Serial data do not
directly affect the DPS until the data reach the DPS reg-
ister. Control of data flow to the DPS register is through
two control bits (A0 and C0) and logic input LOAD.
LOAD asynchronously transfers data from the input
register into the DPS register. If LOAD is held low when
data are latched into the input register, then the data
transfer directly (transparently) into the DPS register.
This allows changing the state of the DPS coincident
with the end of serial-port data communication, or asyn-
chronously with respect to serial-port communications.
Asynchronous update using LOAD facilitates simultane-
ous updates of multiple daisy-chained DPS devices.
DPS Data Control Bits
An 18-bit word programs the MAX9959. Table 1 outlines
the 18-bit control word structure.
Serial Interface Data Flow Control Bits
Bits 0 and 1 (C0 and A0) specify if and how data trans-
fers from the shift register to the input and DPS regis-
ters. The specified actions shown in Table 2 occur
when CS goes high (Figures 5 and 6).
When A0 = C0 = 0 (NOP), data move through the shift
register to DOUT without change in mode or operation.
This is useful when daisy-chaining devices to shift oper-
ational data through a number of devices to a specific
device without altering some or all the device’s opera-
tional data. To update multiple daisy-chained devices
simultaneously use A0 = 1 and C0 = 0 to load the input
register of the devices to be updated and activate
LOAD after CS goes high (Figure 5). If LOAD is held
low while CS is raised, data latched to the input register
are also latched to the DPS register, independent of the
state of C0.
CONTROL
DECODE
DPS REGISTER
CS
SCLK
DIN
TO DPS
DOUT
LOAD
16
2
INPUT REGISTER
SHIFT REGISTER
16
MAX9959
Figure 3. DPS Serial Port Block Diagram
DATA BIT
NAME
FUNCTION
17
FMODE
Mode Select
16 G2
15 G1 Gain and Polarity Select
14 G0
13 RS2
12 RS1 Range Select
11 RS0
10
CLEN
Clamp Enable
9RESERV Reserved. Set this bit to zero.
8
HIZFRC
Force High-Impedance Select
7
HIZMS
Measure High-Impedance Select
6
HIZCMP
Comparator High-Impedance Select
5
LCOMP1
4
LCOMP0
3
BCOMP1
2
BCOMP0
Compensation Select
1A0
0C0
Serial Interface Data Flow Control
Table 1. Data Control Bits and Bit Order
DATA BITS
A0 (D1)
C0 (D0)
OPERATION
00
NOP: Input and DPS registers remain
unchanged
0 1 Load DPS register from input register
1 0 Load input register from shift register
11
Load input register and DPS register from
shift register
Table 2. Serial Interface Data Flow
Control Bits
MAX9959
25V Span, 800mA Device Power Supply (DPS)
16 ______________________________________________________________________________________
“Quick Load” Using Chip Select
Latching data from the input register to the DPS register
under standard operation of the MAX9959 requires an
additional command, and/or use of LOAD. An alternative
“shortcut” is to take CS low, satisfy the minimum CS low
pulse-width specification, and then return it high without
any coincident clock activity. Data in the input register are
latched to the DPS register on the rising edge of CS.
Programmable Analog Modes
Current Range Selection
Bits D11 to D13 of the control word (RS0, RS1, and RS2)
control the full-scale current range for either FI (force cur-
rent) or MI (measure current) mode. Nominal current moni-
tor resistor values and current ranges are listed in Table 3.
VIN and Measure Voltage, Variable-Gain
Amplifier Selection
Bits D14 to D16 of the control word (G0, G1, and G2)
control the gain and polarity of the variable-gain ampli-
fiers (VGAs). These bits also control the gain of the
measure amplifier, allowing a 1:1 input-to-output volt-
age transfer function when in the FVMV mode. The set-
tings are detailed in Table 4.
Mode Selection
Bits D8 and D17 in the control word (HIZFRC and
FMODE) select the mode of operation of the MAX9959,
indicated in Table 5. FMODE selects whether the DPS
forces a voltage or a current. HIZFRC determines if the
driver amplifier is placed in a high-output-impedance
state, or if VINS is selected as the input to the amplifier
(FI slave mode).
In FV and FI modes, IMEAS and VMEAS outputs pro-
vide measurement of the DUT sense voltage or current,
allowing flexible modes of operation beyond the tradi-
tional force-voltage/measure-current (FVMI) and force-
current/measure-voltage (FIMV) modes. The modes
supported are:
FVMI: Force-voltage/measure-current
FIMV: Force-current/measure-voltage
FVMV: Force-voltage/measure-voltage
FIMI: Force-current/measure-current
FNMV: Force-nothing/measure-voltage
In the FV or FI modes, VIN is selected to control the
forced voltage or forced current. In the FI slave mode,
VINS is selected. This allows connecting a master DPS
to its slaves without using external relays.
Digital Interface Operation
A 3-wire SPI™/QSPI™/MICROWIRE™-compatible serial
interface is used for command and control of the
MAX9959. The serial interface operates with clock
speeds up to 20MHz. Additionally, a few logic inputs
control special functions, sometimes working with the
serial interface control data, sometimes overriding it.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
DATA BITS
RS2
(D13)
RS1
(D12)
RS0
(D11)
RANGE
MAXIMUM
CURRENT
NOMINAL
SENSE
RESISTOR
VALUE (Ω)
000 D
±200µA
5000
0 0 1 C ±2mA 500
0 1 0 B ±20mA 50
011 A
±800mA
1.25
1XX
External
——
Table 3. Range Select Bits and Nominal
Sense Resistor Values
DATA BITS*
G2 (D16)
G1 (D15) G0 (D14)
VIN VGA
MEASURE
VOLTAGE
VGA
000 +1 +1
0 0 1 +2 +1/2
0 1 0 +6 +1/6
100 -1 +1
1 0 1 -2 +1/2
1 1 0 -6 +1/6
Table 4. VGA Gain and Polarity Select Bits
*
States 011 and 111 are unused.
DATA BITS
HIZFRC
(D8)
FMODE
(D17)
DPS MODE
AMP
INPUT
OUTPUTS
RA, RB, RC,
AND RD
00 High
Impedance AGND
High
Impedance
0 1 FI Slave VINS Current
1 0 FV VIN Voltage
1 1 FI VIN Current
Table 5. DPS Mode Select Bits
X = Don’t care.
MAX9959
25V Span, 800mA Device Power Supply (DPS)
______________________________________________________________________________________ 17
Logic Inputs and Shared Control Functions
Control of the measure output high-impedance state is
shared between the HIZMS bit (D7) and the logic input
HIZMP. Data transfer operations from the input shift
register to the two internal control registers, input and
DPS, are shared between the control word’s A0 and C0
bits, and logic input LOAD (see the
Configuration and
Control
section).
Digital Inputs
Digital inputs SCLK, DIN, CS, LOAD, HIZMP, and
IDDQSEL incorporate hysteresis to mitigate noise and to
provide compatibility with opto-isolators. Voltage thresh-
old levels for digital inputs are determined by VTHR,
and default to 1/2 VLif VTHR is left unconnected.
Digital Output (DOUT)
When the input data register is full, the data become
available at DOUT in a first-in-first-out fashion, allowing
multiple devices to be daisy-chained. Data at DOUT
follow DIN with a delay of 18 clock cycles per chained
unit. The digital output is clocked on the falling edge of
the input clock, allowing daisy-chained devices to use
the same clock signal.
Serial-Port Timing
Timing of the serial port is detailed in timing Figures 4,
5, and 6, and in the serial port timing characteristics
section of the
AC Electrical Characteristics
table.
SCLK
CS
DIN D17 D16 D15 D14 D13 D12 D1 D0
tCH
tCL
tCSHO
tCSS1
tCSH1
tDH
tCSWH
D17LAST
tDO tCLL
DOUT
LOAD
tDS
tCSSO
D16LAST D15LAST D14LAST D13LAST D12LAST D1LAST D0LAST D17
Figure 4. Serial Interface Timing
MAX9959
25V Span, 800mA Device Power Supply (DPS)
18 ______________________________________________________________________________________
CS
SCLK
DIN
INPUT
REGISTERS
UPDATED
DOUT
LOAD DPS
REGISTERS
UPDATED
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 D17
FIRST BIT
FROM
PREVIOUS
WRITE
LAST BIT
FROM
PREVIOUS
WRITE
Figure 5. Serial Interface Timing with Asynchronous Loading of the DPS Register
CS
SCLK
DIN
INPUT
AND DPS
REGISTERS
UPDATED
DOUT
LOAD = 0
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 D17
FIRST BIT
FROM
PREVIOUS
WRITE
LAST BIT
FROM
PREVIOUS
WRITE
Figure 6. Serial Interface Timing with Synchronous Loading of the DPS Register
Bypass Compensation Capacitor Selection
In addition to lead compensation, the DPS also imple-
ments bypass compensation, which may be required
under conditions of heavy capacitive loading. Depending
on the mode selected, FV or FI, control bits D3 and D2
(BCOMP1 and BCOMP0) select different capacitors.
In the FV mode, one of three bypass capacitors (CB1,
CB2, and CB3), or none is selected, as shown in Table 7.
Table 8 presents the recommended CB1, CB2, and CB3
capacitor values for various load conditions.
MAX9959
Applications Information
Exposed Pad
Leave EP unconnected or connect to VEE. Do not con-
nect EP to ground.
Lead Compensation Capacitor Selection
The MAX9959 can drive widely varying load capaci-
tances. As the load capacitance increases, the output
of the DPS tends to overshoot. To counter this, lead
compensation capacitor network connections are pro-
vided, each with dedicated internal switches control-
lable through the serial interface (Figure 1). The
networks can be tailored to specific needs, such as set-
tling time vs. overshoot, with combinations of capaci-
tors. Control bits D5 and D4 (LCOMP1 and LCOMP0)
configure compensation capacitor connections as
shown in Table 6.
DATA BITS
LCOMP1 (D5)
LCOMP0 (D4)
COMPENSATION
CAPACITOR SELECT
MINIMUM CAPACITOR
VALUE (pF)
MAXIMUM CAPACITOR
VALUE (pF)
0 0 None — —
0 1 CCOMP1 27 330
1 0 CCOMP2 27 330
1 1 CCOMP1 and CCOMP2 27 each 330 each
Table 6. Lead Compensation Capacitor Selection
LOAD
RANGE
≥ 1nF ≥ 10nF ≥ 100nF ≥ 1µF ≥ 10µF ≥ 100µF ≤ 1000µF
A——
CB1 = 2.7nF CB1 = 2.7nF CB2 = 10nF CB3 = 22nF
CB3 = 22nF
B——
CB1 = 2.7nF CB1 = 2.7nF CB2 = 10nF CB3 = 22nF
—
C—
CB1 = 2.7nF CB1 = 2.7nF CB2 = 10nF CB3 = 22nF
——
D
CB1 = 2.7nF CB1 = 2.7nF
CB2 = 10nF
CB3 = 22nF
———
Table 8. CB1, CB2, and CB3 Recommended Values
In FI mode, the bypass capacitor combination (CCH/
CCL), or none, is selected (Table 9). Table 10 presents
the recommended CCH and CCL capacitor values for
various load conditions. These compensation capacitors
provide improved stability for the voltage clamp circuit
when driving heavy loads.
DATA BITS
BCOMP1 (D3)
BCOMP0 (D2)
FORCE-CURRENT MODE
COMPENSATION
CAPACITOR SELECT
0 0 None
X 1 CCL/CCH
1 X CCL/CCH
Table 9. FI Mode Voltage Clamp
Compensation Capacitor Selection
25V Span, 800mA Device Power Supply (DPS)
______________________________________________________________________________________ 19
DATA BITS
BCOMP1 (D3) BCOMP0 (D2)
BYPASS
CAPACITOR SELECT
0 0 None
0 1 CB1
1 0 CB2
1 1 CB3
Table 7. FV Mode Bypass Capacitor
Selection
X = Don’t care.
MAX9959
25V Span, 800mA Device Power Supply (DPS)
20 ______________________________________________________________________________________
Measure Output High-Impedance Control
Place the measure output into a low-leakage, high-
impedance state in either of two ways: with the HIZMS
control bit (D7), or the digital input HIZMP. The two con-
trols are logically AND ed, as shown in Table 11. Digital
input HIZMP allows multiplexing between several DPS
measure outputs without using the serial interface.
Voltage (Current) Clamp Enable
Control word bit CLEN (D10) enables the output clamps
when high and disables the clamps when low, as indicat-
ed in Table 12. In FV mode, current compliance is active.
In FI mode, voltage compliance is active.
IDDQ Test Mode
While in FV mode, asserting digital input IDDQSEL
switches the DPS to the minimum current range (range
D), engaging the IDDQ test mode as shown in Table 13.
Switching to the minimum current range through exter-
nal control allows low-current IDDQ measurements
without reprogramming the DPS through the serial inter-
face. When IDDQSEL is deasserted the current range
switches back to its programmed value.
LOAD
RANGE
≥ 100pF ≥ 1nF ≥ 10nF ≥ 100nF ≥ 1µF ≥ 10µF ≥ 100µF ≤ 1000µF
A— — — 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF
B— — 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF —
C— 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF — —
D4.7nF 4.7nF 4.7nF 4.7nF 4.7nF — — —
Table 10. CCH and CCL Recommended Values (CCH = CCL)
CONTROL BIT CLEN
(D10) CLAMP MODE
1 Clamps Enabled
0 Clamps Disabled
Table 12. Clamp Enable Control
DIGITAL INPUT IDDQSEL
MODE
1 IDDQ Test
0 Normal
Table 13. IDDQ Test Select
DATA BIT
HIZMS
(D7)
DIGITAL
INPUT HIZMP
MEASURE OUTPUT
(VMEAS, IMEAS)
MODE
1 1 Measure Output Enabled
1 0 High Impedance
0 1 High Impedance
0 0 High Impedance
Table 11. Measure Output High-
Impedance Control
MAX9959
25V Span, 800mA Device Power Supply (DPS)
______________________________________________________________________________________ 21
RC
RB
RA
RD
BIFRCA
VRXP
RCOMF
BIFRCB
VRXM
DUT
RD
RC
RB
RA
AMPOUT
SENSE
EXTSEL
DUTGND
DUTGSNS
EXTERNAL BUFFER
ADC
IMEAS
VMEAS
VIN
CLH
CLL
IOSI
IOSV
ITHHI
ITHLO
CS
SCLK
LOAD
DIN
DOUT
HIZMP
ILIMHI
ILIMLO LOGIC
GREF
AGND
DAC
GREF
AGND
I/O
LOGIC
V1
V2
V3
V4
V5
V6
V7
MAX9959
Figure 7. Single DPS Configuration
Power-Up Configuration
At power-up all analog outputs except TEMP default to high impedance.
Applications Circuits
MAX9959
25V Span, 800mA Device Power Supply (DPS)
22 ______________________________________________________________________________________
Applications Circuits (continued)
RC
RB
RA
RD
BIFRCB
RCOMF
BIFRCA
DUT
RD
RC
RB
RA
SENSE
DUTGND
DUTGSNS
ADC
GREF
IMEAS
VMEAS
VIN
CLH
CLL
IOSI
IOSV
ITHHI
ITHLO
CS
SCLK
LOAD
DIN
DOUT
HIZMP
ILIMHI
ILIMLO LOGIC
AGND
DAC
GREF
AGND
I/O
LOGIC
V1
V2
V3
V4
V5
V6
V7
RCOMF
ADC
GREF
IMEAS
VMEAS
VIN
CLH
CLL
IOSI
IOSV
ITHHI
ITHLO
CS
SCLK
LOAD
DIN
DOUT
HIZMP
ILIMHI
ILIMLO LOGIC
AGND
DAC
GREF
AGND
V1
V2
V3
V4
V5
V6
V7
DPS1
DPS2
DPS3
DPSn
BIFRCB
BIFRCA
RD
RC
RB
RA
IPAR
VINS
RC
RB
RA
RD
MAX9959
MAX9959
Figure 8. Parallel DPS Configuration Achieves Higher Output Current
MAX9959
25V Span, 800mA Device Power Supply (DPS)
______________________________________________________________________________________ 23
Pin Configuration
VEE
100
N.C.
99
N.C.
98
DGND
97
HIZMP
96 95
IDDQSEL
94
DIN
93
LOAD
92
SCLK
91 90
VTHR
89
VL
88
DGND
87
DOUT
86
EXTSEL
85 84
ILIMLO
83
ILIMHI
82
DGND
81
N.C.
N.C.
80
N.C.
79
N.C.
78
VCC
77
VEE
76
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
RA
RA
RA
RA
RA
RA
RA
RA
BIFRCA
RB
BIFRCB
RC
RD
RCOMF
SENSE
DUTGSNS
VCC
VCC
VEE
VEE
VRXP
VRXM
CT1
CT2
VCC
*EP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CCOMP2
CCOMP1
SAMPO
CCL
CCH
CCHL
CC2
CC1
CB3
CB2
CB1
CBC
TEMP
VMEAS
IMEAS
IPAR
CLH
CLL
AGND
VIN
VINS
IOSV
IOSI
ITHHI
ITHLO
*EP = EXPOSED PAD
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
MAX9959
HITEMP
CS
VEE
VCC
N.C.
N.C.
N.C.
VEE
AMPOUT
TOP VIEW
TQFP-EPR-IDP
VCC
VEE
VEE
VEE
VEE
VEE
VEE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VEE
VEE
VEE
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
100 TQFP-EPR-IDP C100E-8R 21-0148 90-0159
MAX9959
25V Span, 800mA Device Power Supply (DPS)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
2 3/07 -— 1, 6, 23
3 3/09 Added exposed pad information 1, 11, 12, 19, 23
4 2/11 Updated Absolute Maximum Ratings and DC Electrical Characteristics, and
corrected pins 42 and 43 in Pin Description 2, 4, 11
