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TVS Diode Arrays
SP720
The SP720 is an array of SCR/Diode bipolar str uctures for ESD and
over-voltage protection to sensitive input circuits. The SP720 has 2
protection SCR/Diode device structures per input. A total of 14 available
inputs can be used to protect up to 14 external signal or bus lines.
Over-voltage protection is from the IN (pins 1-7 and 9-15) to V+ or V-.
The SCR structures are designed for fast tr iggering at a threshold of one
+VBE diode threshold above V+ (Pin 16) or a -VBE diode threshold
below V- (Pin 8). From an IN input, a clamp to V+ is activated if a tran-
sient pulse causes the input to be increased to a voltage level greater
than one VBE above V+. A similar clamp to V- is activated if a negative
pulse, one VBE less than V-, is applied to an IN input. Standard ESD
Human Body Model (HBM) Capability is:
Features
• ESD Interface Capability for HBM Standards
- MIL STD 3015.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15kV
- IEC 61000-4-2, Direct Discharge,
Single Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV (Level 2)
Two Inputs in Parallel . . . . . . . . . . . . . . . . . . . . . . . . 8kV (Level 4)
- IEC 61000-4-2, Air Discharge. . . . . . . . . . . . . . . . . 15kV (Level 4)
• High Peak Current Capability
- IEC 61000-4-5 (8/20µs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3A
- Single Pulse, 100µs Pulse Width. . . . . . . . . . . . . . . . . . . . . . . ±2A
- Single Pulse, 4µs Pulse Width. . . . . . . . . . . . . . . . . . . . . . . . . ±5A
• Designed to Provide Over-Voltage Protection
- Single-Ended Voltage Range to . . . . . . . . . . . . . . . . . . . . . . +30V
- Differential Voltage Range to. . . . . . . . . . . . . . . . . . . . . . . . . ±15V
• Fast Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2ns Risetime
• Low Input Leakages . . . . . . . . . . . . . . . . . . . . . . . . . 1nA at 25oC (Typ)
• Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3pF (Typ)
• An Array of 14 SCR/Diode Pairs
• Operating Temperature Range . . . . . . . . . . . . . . . . . . . . -40oC to 105oC
Applications
• Microprocessor/Logic Input Protection
• Data Bus Protection
• Analog Device Input Protection
• Voltage Clamp
Functional Block Diagram
Refer to Figure 1 and Table 1 for further detail. Refer to Application Note
AN9304 and AN9612 for additional infor mation.
Ordering Information
HBM STANDARD MODE R C ESD (V)
IEC 61000-4-2 Air 330150pF >15kV
Direct 330150pF >4kV
Direct, Dual Pins 330150pF >8kV
MIL-STD-3015.7 Direct, In-circuit 1.5k100pF >15kV
PART NO. TEMP. RANGE
(oC) PACKAGE PKG. Min.
Order
NO.
SP720AP -40 to 105 16 Ld PDIP E16.3 1500
1970
2500
SP720AB -40 to 105 16 Ld SOIC M16.15
SP720ABT -40 to 105 16 Ld SOIC
Tape and Reel M16.15
Pinout
SP720 (PDIP, SOIC)
T OP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IN
IN
IN
IN
IN
IN
V-
IN
V+
IN
IN
IN
IN
IN
IN
IN
V+ 16
1
8
2
3 - 7
9 - 15
IN
IN
IN
V-
Electronic Protection Array for ESD and Overvoltag e Protection
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TVS DIODE ARRAYS
TVS Diode Arrays
SP720
Electronic Protection Array for ESD and Overvoltag e Protection
ESD Capability
ESD capability is dependent on the application and defined test
standard.The evaluation results for various test standards and methods
based on Figure 1 are shown in Table 1.
For the “Modified” MIL-STD-3015.7 condition that is defined as an
“in-circuit” method of ESD testing, the V+ and V- pins have a retur n path
to ground and the SP720 ESD capability is typically greater than 15kV
from 100pF through 1.5k. By str ict definition of MIL-STD-3015.7 using
“pin-to-pin” device testing, the ESD voltage capability is greater than 6kV.
The MIL-STD-3015.7 results were determined from AT&T ESD Test
Lab measurements.
The HBM capability to the IEC 61000-4-2 standard is greater than 15kV
for air discharge (Level 4) and greater than 4kV for direct discharge
(Level 2). Dual pin capability (2 adjacent pins in parallel) is well in excess
of 8kV (Level 4).
For ESD testing of the SP720 to EIAJ IC121 Machine Model (MM) standard,
the results are typically better than 1kV from 200pF with no series resistance.
Absolute Maximum Ratings
Continuous Supply Voltage, (V+) - (V-). ........................+35V
Forward Peak Current, IIN to VCC, IIN to GND
(Refer to Figure 6) . .................................±2A, 100µs
ESD Ratings and Capability (Figure 1, Table 1)
Load Dump and Reverse Batter y (Note 2)
Thermal Information
Thermal Resistance (Typical, Note 1). ....................θJA (oC/W)
PDIP Package . ............................................90
SOIC Package . ..........................................130
Maximum Storage Temperature Range . . . ................-65
oC to 150oC
Maximum Junction Temperature (Plastic Package) .....................150oC
Maximum Lead Temperature (Soldering 10s) . .........................300oC
(SOIC Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause per manent damage to the device.This is a stress only rating and operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications TA= -40oC to 105oC;VIN = 0.5VCC , Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Operating Voltage Range,
VSUPPLY = [(V+) - (V-)] VSUPPLY - 2 to 30 - V
Forward Voltage Drop:
IN to V-
IN to V+ VFWDL
VFWDH
IIN = 1A (Peak Pulse) -
-2
2-
-V
V
Input Leakage Current IIN -20 5 20 nA
Quiescent Supply Current IQUIESCENT - 50 200 nA
Equivalent SCR ON Threshold Note 3 - 1.1 - V
Equivalent SCR ON Resistance VFWD/IFWD; Note 3 - 1 -
Input Capacitance CIN 3pF
Input Switching Speed tON 2ns
NOTES:
2. In automotiv e and battery oper ated systems , the po wer supply lines should be e xternally protected f or load dump and re verse battery. When the
V+ and V- pins are connected to the same supply voltage source as the device or control line under protection, a current limiting resistor should
be connected in series between the external supply and the SP720 supply pins to limit reverse battery current to within the rated maximum
limits. Bypass capacitors of typically 0.01µF or larger from the V+ and V- pins to ground are recommended.
3. Refer to the Figure 3 gr aph for definitions of equivalent “SCR ON Threshold” and “SCR ON Resistance.These characteristics are given here
for thumb-rule information to determine peak current and dissipation under EOS conditions.
--
--
STANDARD TYPE/MODE RDCD±VD
MIL STD 3015.7 Modified HBM 1.5k100pF 15kV
Standard HBM 1.5k100pF 6kV
IEC 61000-4-2 HBM, Air Discharge 330150pF 15kV
HBM, Direct Discharge 330150pF 4kV
HBM, Direct Discharge,
Two Parallel Input Pins 330150pF 8kV
EIAJ IC121 Machine Model 0k200pF 1kV
H.V.
SUPPLY
°±VD
IN
DUT
CD
R1
IEC 1000-4-2: R150 to 100M
RD
CHARGE
SWITCH DISCHARGE
SWITCH
MIL STD 3015.7: R11 to 10M
FIGURE 1. ELECTROSTATIC DISCHARGE TEST
TABLE 1. ESD TEST CONDITIONS
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TVS Diode Arrays
Electronic Protection Array for ESD and Overvoltag e Protection
SP720
FIGURE 2. LOW CURRENT SCR FOR WARD V OLTAGE DR OP
CURVE FIGURE 3. HIGH CURRENT SCR FORW ARD V OLTAGE DROP
CURVE
600 800 1000 1200
FORWARD SCR VOLTAGE DROP (mV)
100
80
60
40
20
0
FORWARD SCR CURRENT (mA)
TA = 25oC
SINGLE PULSE
2.5
2
1.5
1
0.5
0
FORWARD SCR CURRENT (A)
TA = 25oC
SINGLE PULSE
VFWD
IFWD
0123
FORWARD SCR VOLTAGE DROP (V)
EQUIV. SAT. ON
THRESHOLD ~ 1.1V
FIGURE 4. TYPICAL APPLICATION OF THE SP720 AS AN INPUT CLAMP FOR OVER-V OLTAGE, GREATER THAN 1VBE ABOVE V+ OR
LESS THAN -1VBE BELOW V-
+VCC
+VCC
INPUT
DRIVERS
PROTECTION CIRCUIT
(1 OF 14 ON CHIP)
SP720 INPUT
OR
SIGNAL
SOURCES
IN 9-15IN 1-7
SP720
V-
TO +VCC
LINEAR OR
DIGITAL IC
INTERFACE
V+
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TVS DIODE ARRAYS
TVS Diode Arrays
SP720
Electronic Protection Array for ESD and Overvoltag e Protection
Peak Transient Current Capability of the SP720
The peak transient current capability rises shar ply as the width of the
current pulse narrows.Destr uctive testing was done to fully evaluate the
SP720’s ability to withstand a wide range of transient current pulses.The
circuit used to generate current pulses is shown in Figure 5.
The test circuit of Figure 5 is shown with a positive pulse input. For a
negative pulse input, the (-) current pulse input goes to an SP720 ‘IN’
input pin and the (+) current pulse input goes to the SP720 V- pin.The
V+ to V- supply of the SP720 must be allowed to float. (i.e., It is not tied
to the ground reference of the current pulse generator.) Figure 6 shows
the point of overstress as defined by increased leakage in excess of the
data sheet published limits.
The maximum peak input current capability is dependent on the V+ to V-
voltage supply level, improving as the supply voltage is reduced.Values
of 0, 5, 15 and 30 voltages are shown. The safe operating range of the
transient peak current should be limited to no more than 75% of the
measured overstress level for any given pulse width as shown in Figure 6.
When adjacent input pins are paralleled, the sustained peak current
capability is increased to nearly twice that of a single pin. For compari-
son, tests were run using dual pin combinations 1+2, 3+4, 5+6, 7+9,
10+11, 12+13 and 14+15.
The overstress curve is shown in Figure 6 for a 15V supply condition.The
dual pins are capable of 10A peak current for a 10µs pulse and 4A peak
current for a 1ms pulse. The complete for single pulse peak current vs.
pulse width time ranging up to 1 second are shown in Figure 6.
+
-CURRENT
SENSE
VOLTAGE
PROBE
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IN
IN
IN
IN
IN
IN
V-
IN
V+
IN
IN
IN
IN
IN
IN
IN
+
-
R1 ~ 10 TYPICAL
SP720
VG
VG ADJ. 10V/A TYPICAL
R1
(-)
(+)
C1 ~ 100µF
C1
VARIABLE TIME DURATION
CURRENT PULSE GENERATOR
FIGURE 5. TYPICAL SP720 PEAK CURRENT TEST CIRCUIT
WITH A VARIABLE PULSE WIDTH INPUT
0.001 0.01 0.1 1
PULSE WIDTH TIME (ms)
PEAK CURRENT (A)
10
7
6
5
4
3
2
1
0
0V
5V
15V
V+ TO V- SUPPLY
100 1000
10
9
30V
15V
CAUTION: SAFE OPERATING CONDITIONS LIMIT
OF THE VALUES SHOWN ON EACH CURVE.
PULSE WIDTH TO BE NO GREA TER THAN 75%
THE MAXIMUM PEAK CURRENT FOR A GIVEN
SINGLE PIN STRESS CURVES
DUAL PIN STRESS CURVE
8
FIGURE 6. SP720 TYPICAL SINGLE PULSE PEAK CURRENT CUR VES SHOWING THE MEASURED POINT OF OVER-STRESS IN
AMPERES vs PULSE TIME IN MILLISECONDS (T A = 25oC)
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TVS Diode Arrays
Electronic Protection Array for ESD and Overvoltag e Protection
SP720
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the pac kage seated in JE-
DEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendic-
ular to datum .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maxim um dimensions do not include dambar protrusions. Dambar
protrusions shall not e xceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will hav e a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 1 2 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AM BS
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N169
16
E16.3
(JEDEC MS-001 BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
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5
TVS DIODE ARRAYS
TVS Diode Arrays
SP720
Electronic Protection Array for ESD and Overvoltag e Protection
Small Outline Plastic P ackages (SOIC) M16.15
(JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.3859 0.3937 9.80 10.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N16 167
0o8o0o8o-
µ
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate b urrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamf er on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “Lis the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AM BS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
µ
0.25(0.010) BM M