PTFA181001E
PTFA181001F
Data Sheet 1 of 11 Rev. 02.1, 2009-02-20
All published data at TCASE = 25°C unless otherwise indicated
ESD: Electrostatic discharge sensitive device—observe handling precautions!
Description
The PTFA181001E and PTFA181001F are 100-watt LDMOS FETs
designed for EDGE and WCDMA power amplifier applications in the
DCS band. Features include input and output matching, and
thermally-enhanced packages with slotted or earless flanges.
Manufactured with Infineon's advanced LDMOS process, these
devices provide excellent thermal performance and superior
reliability.
PTFA181001E
Package H-36248-2
Thermally-Enhanced High Power RF LDMOS FETs
100 W, 1805 – 1880 MHz
2-Carrier WCDMA Drive-up
VDD = 28 V, IDQ
= 750 mA, ƒ = 1880 MHz, 3GPP WCDMA
signal, P/A R = 8 dB, 10 MHz carrier spacing
-53
-48
-43
-38
-33
-28
-23
34 36 38 40 42 44 46
Average Output Power (dBm)
IM3 (dBc), ACPR (dBc)
5
10
15
20
25
30
35
Drain Efficiency (%)
ACPR
Efficiency
IM3
RF Characteristics
EDGE Measurements (not subject to production test—verified by design/characterization in Infineon test fixture)
VDD = 28 V, IDQ = 750 mA, POUT = 45 W, ƒ = 1879.8 MHz
Characteristic Symbol Min Typ Max Unit
Error Vector Magnitude RMS EVM —1.8 —%
Modulation Spectrum @ 400 KHz ACPR —–61 —dBc
Modulation Spectrum @ 600 KHz ACPR —–73 —dBc
Gain Gps —16.5 —dB
Drain Efficiency ηD—36 —%
PTFA181001F
Package H-37248-2
Features
•Thermally-enhanced packages
•Broadband internal matching
•Typical EDGE performance at 1879.8 MHz, 28 V
- Average output power = 45 W
- Linear Gain = 16.5 dB
- Efficiency = 36%
- EVM RMS = 1.8%
•Typical CW performance, 1880 MHz, 28 V
- Output power at P–1dB = 120 W
- Gain 15.5 dB
- Efficiency = 52%
•Integrated ESD protection: Human Body Model,
Class 2 (minimum)
•Excellent thermal stability, low HCI drift
•Capable of handling 10:1 VSWR @ 28 V,
100 W (CW) output power
•Pb-free and RoHS compliant
*See Infineon distributor for future availability.
PTFA181001E
PTFA181001F
Data Sheet 2 of 11 Rev. 02.1, 2009-02-20
RF Characteristics (cont.)
Two-tone Measurements (tested in Infineon test fixture)
VDD = 28 V, IDQ = 750 mA, POUT = 100 W PEP, ƒ = 1850 MHz, tone spacing = 1 MHz
Characteristic Symbol Min Typ Max Unit
Gain Gps 16 16.5 —dB
Drain Efficiency ηD39 41 —%
Intermodulation Distortion IMD —–30 –28 dBc
DC Characteristics
Characteristic Conditions Symbol Min Typ Max Unit
Drain-Source Breakdown Voltage VGS = 0 V, IDS = 10 mA V(BR)DSS 65 — — V
Drain Leakage Current VDS = 28 V, VGS = 0 V IDSS — — 1.0 µA
VDS = 63 V, VGS = 0 V IDSS — — 10.0 µA
On-State Resistance VGS = 10 V, VDS = 0.1 V RDS(on) —0.85 —Ω
Operating Gate Voltage VDS = 28 V, ID = 750 mA VGS 2.0 2.5 3.0 V
Gate Leakage Current VGS = 10 V, VDS = 0 V IGSS — — 1.0 µA
Maximum Ratings
Parameter Symbol Value Unit
Drain-Source Voltage VDSS 65 V
Gate-Source Voltage VGS –0.5 to +12 V
Junction Temperature TJ200 °C
Total Device Dissipation PD407 W
Above 25°C derate by 2.33 W/°C
Storage Temperature Range TSTG –40 to +150 °C
Thermal Resistance (TCASE = 70°C, 100 W CW) RθJC 0.43 °C/W
Ordering Information
Type and Version Package Type Package Description Marking
PTFA181001E V4 H-36248-2 Thermally-enhanced slotted flange, single-ended PTFA181001E
PTFA181001F V4 H-37248-2 Thermally-enhanced earless flange, single-ended PTFA181001F
*See Infineon distributor for future availability.
PTFA181001E
PTFA181001F
Data Sheet 3 of 11 Rev. 02.1, 2009-02-20
Edge EVM and Modulation Spectrum
vs. Quiescent Current
VDD = 28 V, ƒ = 1879.8 MHz, POUT = 46.5 dBm
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
0.65 0.70 0.75 0.80 0.85 0.90
Quiescent Current (A)
EVM RMS (avg. %) .
-90
-80
-70
-60
-50
-40
-30
-20
-10
Modulation Spectrum (dBc)
EVM
400 kHz
600 kHz
EDGE Modulation Spectrum Performance
VDD = 28 V, IDQ = 750 mA, ƒ = 1879.8 MHz
-100
-80
-60
-40
-20
37 39 41 43 45 47 49
Output Power (dBm)
Modulation Spectrum (dBc)
5
15
25
35
45
Drain Efficiency (%)
Efficiency
400 kHz
600 kHz
Typical Performance (data taken in a production test fixture)
Intermodulation Distortion vs. Output Power
(as measured in a broadband circuit)
VDD = 28 V, IDQ = 750 mA, ƒ1 = 1879 MHz, ƒ2 = 1880 MHz
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
37 39 41 43 45 47 49
Output Power, Avg. (dBm)
IMD (dBc)
3rd Order
7th
5th
EDGE EVM Performance
VDD = 28 V, IDQ = 750 mA, ƒ = 1879.8 MHz
0
2
4
6
8
37 39 41 43 45 47 49
Output Power (dBm)
EVM RMS (avg. %) .
5
15
25
35
45
Drain Efficiency (%)
EVM
Efficiency
PTFA181001E
PTFA181001F
Data Sheet 4 of 11 Rev. 02.1, 2009-02-20
Linear Broadband Performance
VDD = 28 V, IDQ = 750 mA, POUT Avg = 47 dBm
20
25
30
35
40
45
50
55
1805 1818 1831 1844 1857 1870 1883
Frequency (MHz)
Efficiency (%)
-30
-20
-10
0
10
20
30
40
Gain, Return Loss (dB)
Gain
Return Loss
Efficiency
Power Sweep
VDD = 28 V, ƒ = 1880 MHz
14.0
14.5
15.0
15.5
16.0
16.5
17.0
17.5
36 38 40 42 44 46 48 50 52
Output Power (dBm)
Power Gain (dB)
IDQ = 1125 mA
IDQ = 375 mA
IDQ = 750 mA
IM3 vs. Output Power at Selected Biases
VDD = 28 V, ƒ1 = 1879, ƒ2 = 1880 MHz
-60
-55
-50
-45
-40
-35
-30
-25
-20
37 39 41 43 45 47 49
Output Power, Avg. (dBm)
IMD (dBc)
IDQ = 1125 mA
IDQ = 375 mA
IDQ = 750 mA
Broadband CW Performance (at P-1dB)
VDD = 28 V, IDQ = 750 mA
14
15
16
17
18
19
1805 1818 1831 1844 1857 1870 1883
Frequency (MHz)
Gain (dB)
35
40
45
50
55
60
Efficiency (%), Output Power (dBm)
Output Power
Gain
Typical Performance (cont.)
PTFA181001E
PTFA181001F
Data Sheet 5 of 11 Rev. 02.1, 2009-02-20
IS-95 CDMA Performance
VDD = 28 V, IDQ = 750 mA, ƒ = 1880 MHz
0
5
10
15
20
25
30
35
33 35 37 39 41 43 45 47
Output Power, Avg. (dBm)
Drain Efficiency (%)
-80
-70
-60
-50
-40
-30
-20
-10
Adj. Ch. Power Ratio (dBc)
Efficiency
TCASE = 25°C
TCASE = 90°C
ACP FC – 0.75 MHz
ACPR FC + 1.98 MHz
Bias Voltage vs. Temperature
Voltage normalized to typical gate voltage,
series show current
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
-20 0 20 40 60 80 100
Case Temperature (°C)
Normalized Bias Voltage (V)
0.15 A
0.44 A
0.73 A
1.10 A
2.20 A
3.30 A
4.41 A
5.51 A
Output Power (P–1dB) vs. Drain Voltage
IDQ = 750 mA, ƒ = 1880 MHz
49
50
51
52
24 26 28 30 32
Drain Voltage (V)
Output Power (dBm)
Gain & Efficiency vs. Output Power
VDD = 28 V, IDQ = 750 mA, ƒ = 1880 MHz
12
13
14
15
16
17
18
36 38 40 42 44 46 48 50 52
Output Power (dBm)
Gain (dB)
5
15
25
35
45
55
65
Drain Efficiency (%)
Efficiency
Gain
Typical Performance (cont.)
PTFA181001E
PTFA181001F
Data Sheet 6 of 11 Rev. 02.1, 2009-02-20
Broadband Circuit Impedance
Z Source Z Load
G
S
D
Frequency Z Source ΩZ Load Ω
MHz RjX RjX
1805 4.62 –6.23 1.71 2.79
1830 4.18 –6.10 1.41 2.92
1850 4.20 –6.13 1.47 3.05
1860 4.58 –6.20 1.99 3.13
1880 4.42 –6.36 1.91 3.16
0.1
0.1
0.1
-
W
AV
E
LE
N
GT
H
ST
O
W
AR
D
G
E
N
E
R
<
-
--
W
AV
E
LE
N
G
TH
S
T
O
W
AR
D
L
OA
D
-
0
.0
1880 MHz
1805 MHz
1805 MHz
Z Source
1880 MHz
Z Load
Z0 = 50 Ω
Three-Carrier CDMA2000 Performance
VDD = 28 V, IDQ = 750 mA, ƒ = 1880 MHz
0
5
10
15
20
25
30
35
40
33 35 37 39 41 43 45 47
Output Power, Avg. (dBm)
Drain Efficiency (%)
-75
-70
-65
-60
-55
-50
-45
-40
-35
Adj. Ch. Power Ratio (dBc)
ACP Low
ACP Up
ALT Up
Efficiency
Typical Performance (cont.)
PTFA181001E
PTFA181001F
Data Sheet 7 of 11 Rev. 02.1, 2009-02-20
Reference Circuit
Reference circuit schematic for ƒ = 1880 MHz
Circuit Assembly Information
DUT PTFA181001E or PTFA181001F LDMOS Transistor
PCB 0.76 mm [.030"] thick, εr = 4.5 Rogers TMM4 2 oz. copper
Microstrip Electrical Characteristics at 1880 MHz1Dimensions: L x W (mm) Dimensions: L x W (in.)
l10.314 λ, 50.0 Ω27.43 x 1.37 1.080 x 0.054
l20.172 λ, 38.0 Ω14.73 x 2.16 0.580 x 0.085
l30.016 λ, 11.4 Ω1.27 x 10.16 0.050 x 0.400
l40.024 λ, 60.0 Ω2.24 x 0.99 0.088 x 0.039
l50.218 λ, 60.0 Ω19.33 x 0.99 0.761 x 0.039
l60.019 λ, 6.9 Ω1.52 x 17.78 0.060 x 0.700
l70.044 λ, 6.9 Ω3.43 x 17.78 0.135 x 0.700
l8, l90.233 λ, 53.0 Ω20.45 x 1.24 0.805 x 0.049
l10 0.039 λ, 4.9 Ω3.10 x 25.65 0.122 x 1.010
l11 (taper) 0.037 λ, 4.9 Ω / 10.3 Ω2.92 x 25.65 / 11.43 0.115 x 1.010 / 0.450
l12 (taper) 0.033 λ, 10.3 Ω / 41.0 Ω2.79 x 11.43 / 1.91 0.110 x 0.450 / 0.075
l13 0.069 λ, 41.0 Ω6.35 x 1.91 0.250 x 0.075
l14 0.038 λ, 41.0 Ω3.25 x 1.91 0.128 x 0.075
l15 0.331 λ, 50.0 Ω28.98 x 1.37 1.141 x 0.054
1Electrical characteristics are rounded.
RF_IN
a181001ef_sch_06-04-18
RF_OUT
R3
2K V
C3
0.001µF
C2
0.001µF
Q1
BCP56
R2
1.3K V
QQ1
LM7805
C1
0.001µF
VDD
R5
10 V
R4
2K V
R1
1.2K V
C9
10pF
l1
R9
10 V
DUT
l5
C6
1µF
C5
0.1µF
C4
10µF
35V
C7
0.01µF
R8
2K V
C8
10pF
R7
5.1K V
C10
0.6pF
l2l3l6l7
l4
R6
5.1K V
C22
1.5pF
C21
1.5pF
C24
10pF
C23
0.6pF
l10 l11 l12 l13 l14
l8
l9
l15
VDD
L1
C11
1µF
C13
1µF
C12
10pF
C14
10µF
50V
C15
10µF
50V
C16
1µF
C18
1µF
C17
10pF
C19
10µF
50V
C20
10µF
50V
L2
PTFA181001E
PTFA181001F
Data Sheet 8 of 11 Rev. 02.1, 2009-02-20
Reference circuit assembly diagram (not to scale)
Reference Circuit (cont.)
Component Description Suggested Manufacturer P/N or Comment
C1, C2, C3 Capacitor, 0.001 µF Digi-Key PCC1772CT-ND
C4 Tantalum capacitor, 10 µF, 35 V Digi-Key 399-1655-2-ND
C5 Capacitor, 0.1 µF Digi-Key PCC104BCT-ND
C6, C11, C13, C16, C18 Capacitor, 1.0 µF ATC 920C105
C7 Capacitor, 0.01 µF ATC 200B 103
C8, C9, C12, C17, C24 Ceramic capacitor, 10 pF ATC 100B 100
C10, C23 Ceramic capacitor, 0.6 pF ATC 100B 0R6
C14, C15, C19, C20 Tantalum capacitor, 10 µF, 50 V Garrett Electronics TPSE106K050R0400
C21, C22 Ceramic capacitor, 1.5 pF ATC 100B 1R5
L1, L2 Ferrite, 8.9 mm Elna Magnetics BDS 4.6/3/8.9-4S2
Q1 Transistor Infineon Technologies BCP56
QQ1 Voltage regulator National Semiconductor LM7805
R1 Chip Resistor 1.2 k-ohms Digi-Key P1.2KGCT-ND
R2 Chip Resistor 1.3 k-ohms Digi-Key P1.3KGCT-ND
R3, R8 Chip Resistor 2 k-ohms Digi-Key P2KECT-ND
R4 Potentiometer 2 k-ohms Digi-Key 3224W-202ETR-ND
R5, R9 Chip Resistor 10 ohms Digi-Key P10ECT-ND
R6, R7 Chip Resistor 5.1 k-ohms Digi-Key P5.1KECT-ND
Gerber files for this circuit available on request
R4
Q1
QQ1
C3
C1
R2
C2
R1
R5
R3
C5
R8
C9
C10
R6
R7 C6
C4
R9
C8
C7
C16
C17
C18 C19 C20
C13 C14 C15
C11
C12
C24
C23
C21
C22
L2
L1
A181001_01
VDD
VDD
VDD
a181001ef_assy
a181001ef_dtl
R4
Q1
QQ1
C3
C1
R2
C2
R1
R5
R3
C5
R8
R6
R7 C6
C4
C8
C7
VDD
PTFA181001E
PTFA181001F
Data Sheet 9 of 11 Rev. 02.1, 2009-02-20
Package Outline Specifications
Package H-36248-2
Diagram Notes—unless otherwise specified:
1. Lead thickness: 0.10 +0.051/–0.025 [.004 +.002/–.001].
2. All tolerances ± 0.127 [.005] unless specified otherwise.
3. Pins: D = drain, S = source, G = gate.
4. Interpret dimensions and tolerances per ASME Y14.5M-1994.
5. Primary dimensions are mm. Alternate dimensions are inches.
6. Gold plating thickness:
S, D, G - flange & leads: 1.14 ± 0.38 micron [45 ± 15 microinch]
Find the latest and most complete information about products and packaging at the Infineon Internet page
http://www.infineon.com/products
C
L
34.04
[1.340]
19.81±0.20
[.780±.008]
1.02
[.040]
19.43 ±0.51
[.765±.020]
(45° X 2.72
[.107])
2X 12.70
[.500]
4.83±0.51
[.190±.020]
27.94
[1.100]
4X R1.52
[R.060]
2X R1.63
[R.064]
D
G
S
FLANGE 9.78
[.385]
0.0381 [.0015] -A-
071117_h-36248-2_po
C
L
C
L
3.61±0.38
[.142±.015]
SPH 1.57
[.062]
[.370 ]
+.004
–.006
LID 9.40 +0.10
–0.15
PTFA181001E
PTFA181001F
Data Sheet 10 of 11 Rev. 02.1, 2009-02-20
Package Outline Specifications (cont.)
Package H-37248-2
Diagram Notes—unless otherwise specified:
1. Lead thickness: 0.10 +0.051/–0.025 [.004 +.002/–.001].
2. All tolerances ± 0.127 [.005] unless specified otherwise.
3. Pins: D = drain, S = source, G = gate.
4. Interpret dimensions and tolerances per ASME Y14.5M-1994.
5. Primary dimensions are mm. Alternate dimensions are inches.
6. Gold plating thickness:
S, D, G - flange & leads: 1.14 ± 0.38 micron [45 ± 15 microinch]
Find the latest and most complete information about products and packaging at the Infineon Internet page
http://www.infineon.com/products
C
L
0.0381 [.0015]
2X 12.70
[.500]
19.43±0.51
[.765±.020]
19.81±0.20
[.780±.008]
SPH 1.57
[.062]
FLANGE 9.78
[.385]
S
G
D
( 45° X 2.72
[.107])
20.57
[.810]
-A-
3.61±0.38
[.142±.015]
1.02
[.040]
4.83±0.51
[.190±.020]
C
L
C
L
[R.020 ]
+.015
–.005
4X R0.508+0.381
–0.127
LID 9.40+0.10
–0.15
[.370 ]
+.004
–.006
071117_h-37248-2_po
Data Sheet 11 of 11 Rev. 02.1, 2009-02-20
PTFA181001E/F
Confidential, Limited Internal Distribution
Revision History: 2009-02-20 Data Sheet
Previous Version: 2006-04-14, Data Sheet
Page Subjects (major changes since last revision)
1, 2, 9, 10 Update to product V4, with new package technologies. Update package outline diagrams.
8Fixed typing error
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GOLDMOS® is a registered trademark of Infineon Technologies AG.
Edition 2009-02-20
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2009 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of
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Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
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Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
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