Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 LMP860x, LMP860x-Q1 60-V, Bidirectional, Low- or High-Side, Voltage-Output, Current-Sensing Amplifiers 1 Features 3 Description * * * * * * * * * * * * The LMP8601, LMP8602, LMP8603 (LMP860x) and LMP8601-Q1, LMP8602-Q1, LMP8603-Q1 (LMP860x-Q1) devices are fixed-gain, precision current-sense amplifiers (also referred to as currentshunt monitors). The input common-mode voltage range is -22 V to +60 V when operating from a single 5-V supply, or -4 V to +27 V with a 3.3-V supply. The LMP860x and LMP860x-Q1 are ideal parts for unidirectional and bidirectional current sensing applications. 1 Gain = 20x for LMP8601 and LMP8601-Q1 Gain = 50x for LMP8602 and LMP8602-Q1 Gain = 100x for LMP8603 and LMP8603-Q1 TCVOS: 10 V/C Maximum CMRR: 90-dB Minimum Input Offset Voltage: 1-mV Maximum CMVR at VS = 3.3 V: -4 V to 27 V CMVR at VS = 5 V: -22 V to 60 V Single-Supply Bidirectional Operation All Minimum and Maximum Limits 100% Tested Q1 Devices Qualified for Automotive Applications Q1 Devices ACE-Q100 Qualified With the Following Results: - Device Temperature Grade 1: -40C to 125C Ambient Operating Temperature Range - Device Temperature Grade 0: -40C to 150C (LMP8601EDRQ1 Only) - Device HBM ESD Classification Level 2 (3A on inputs) - Device CDM ESD Classification Level C6 - Device MM ESD Classification Level M2 * * * * * * The offset input pin enables these devices for unidirectional or bidirectional single supply voltage current sensing. The LMP860x-Q1 devices incorporate enhanced manufacturing and support processes for the automotive market and are compliant with the AECQ100 standard. 2 Applications * These devices have a precise gain of 20x (LPM8601, LPM8601-Q1), 50x (LPM8602, LPM8602-Q1), and 100x (LPM8603, LPM8603-Q1), and are adequate in most targeted applications to drive an ADC to fullscale value. The fixed gain is achieved in two separate stages: a preamplifier with a gain of 10x and an output stage buffer amplifier with a gain of 2x (LMP8601, LMP8601-Q1), 5x (LMP8602, LMP8602Q1), or 10x (LMP8603, LMP8603-Q1). The path between the two stages is brought out on two pins to enable the option of an additional filter network or modifying the gain. High-Side and Low-Side Driver Configuration Current Sensing Bidirectional Current Measurement Current Loop to Voltage Conversion Automotive Fuel Injection Control Transmission Control Power Steering Battery Management Systems Device Information(1) PART NUMBER PACKAGE LMP860x LMP860x-Q1 LMP8602, LMP8603 LMP8602-Q1, LMP8603-Q1 BODY SIZE (NOM) SOIC (8) 4.90 mm x 3.91 mm VSSOP (8) 3.00 mm x 3.00 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Typical Applications D +5V 48V - - + IC IL load G IB + + 48V Inductive Load +5V S +3.3V + D - + Charger - G + Inductive Load - S 24V 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 4 4 4 4 5 5 7 9 Absolute Maximum Ratings ...................................... ESD Ratings: LMP860x ............................................ ESD Ratings: LMP860x-Q1 ...................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics: VS = 3.3 V........................ Electrical Characteristics: VS = 5 V........................... Typical Characteristics .............................................. Detailed Description ............................................ 18 7.1 Overview ................................................................. 18 7.2 Functional Block Diagram ....................................... 18 7.3 Feature Description................................................. 19 7.4 Device Functional Modes........................................ 22 8 Application and Implementation ........................ 26 8.1 Application Information............................................ 26 8.2 Typical Applications ............................................... 26 9 Power Supply Recommendations...................... 31 10 Layout................................................................... 31 10.1 Layout Guidelines ................................................. 31 10.2 Layout Example .................................................... 31 11 Device and Documentation Support ................. 32 11.1 11.2 11.3 11.4 11.5 11.6 Device Support...................................................... Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 32 32 32 32 32 32 12 Mechanical, Packaging, and Orderable Information ........................................................... 32 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (July 2015) to Revision H Page * Added new temperature grade 0 version of LMP8601-Q1..................................................................................................... 1 * Added LMP8602, LMP8602-Q1, LMP8603, and LMP8603-Q1 devices and related information to data sheet .................... 1 * Changed Features bullets ..................................................................................................................................................... 1 * Changed text in Description section ....................................................................................................................................... 1 * Added new values to Thermal Information table .................................................................................................................... 5 * Changed RJA value in Thermal Information table.................................................................................................................. 5 * Deleted previous Note 1 from Electrical Characteristics tables.............................................................................................. 5 * Changed all AV1 to K1 throughout data sheet for consistency.............................................................................................. 6 * Changed all AV2 to K2 throughout data sheet for consistency.............................................................................................. 6 * Deleted previous Note 1 from Electrical Characteristics tables.............................................................................................. 7 * Deleted Related Documentation section; SNOSB36 data sheet content now combined with this data sheet .................... 32 Changes from Revision F (January 2014) to Revision G * Page Added ESD Ratings table, and Pin Configuration and Functions, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections. ............................................................................................... 1 Changes from Revision E (March 2013) to Revision F * Page Added four typical curves ..................................................................................................................................................... 17 Changes from Revision D (October 2009) to Revision E * 2 Page Changed layout of National Data Sheet to TI format ........................................................................................................... 30 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 www.ti.com SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 5 Pin Configuration and Functions D Package 8-Pin SOIC Top View DGK Package 8-Pin VSSOP Top View -IN 1 8 +IN GND 2 7 OFFSET A1 3 6 A2 4 5 -IN 1 8 +IN GND 2 7 OFFSET VS A1 3 6 VS OUT A2 4 5 OUT Pin Descriptions PIN NAME NO. A1 3 A2 GND TYPE DESCRIPTION O Preamplifier output 4 I Input from the external filter network and, or A1 2 P Power ground +IN 8 I Positive input -IN 1 I Negative input OFFSET 7 I DC offset for bidirectional signals OUT 5 O Single-ended output VS 6 P Positive supply voltage Copyright (c) 2008-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 3 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply voltage (VS - GND) -0.3 6 V Continuous input voltage (-IN and +IN) -22 60 V Transient (400 ms) -25 65 V VS + 0.3 GND - 0.3 V LMP8601EDRQ1 only -40 150 All other devices -40 125 -40 150 Maximum voltage at A1, A2, OFFSET and OUT pins Operating temperature, TA Junction temperature (2) Mounting temperature Infrared or convection (20 sec) 235 Wave soldering lead (10 sec) 260 Storage temperature, Tstg (1) (2) -65 C C C 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), RJA, and the ambient temperature, TA. The maximum allowable power dissipation PDMAX = (TJ(MAX) - TA) / RJA or the number given in Absolute Maximum Ratings, whichever is lower. 6.2 ESD Ratings: LMP860x VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) V(ESD) Electrostatic discharge All pins except 1 and 8 2000 Pins 1 and 8 4000 (2) 1000 Charged-device model (CDM), per JEDEC specification JESD22-C101 Machine model (1) (2) UNIT V 200 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 ESD Ratings: LMP860x-Q1 VALUE Human body model (HBM), per AEC Q100-002 (1) V(ESD) (1) Electrostatic discharge All pins except 1 and 8 2000 Pins 1 and 8 4000 Charged-device model (CDM), per AEC Q100-011 1000 Machine model 200 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX Supply voltage (VS - GND) 3 5.5 V OFFSET voltage (Pin 7) 0 VS V LMP8601EDRQ1 only -40 150 All other devices -40 125 Operating temperature, TA (1) 4 (1) UNIT C The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), RJA, and the ambient temperature, TA. The maximum allowable power dissipation PDMAX = (TJ(MAX) - TA) / RJA or the number given in Absolute Maximum Ratings, whichever is lower. Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 www.ti.com SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 6.5 Thermal Information LMP860x, LMP860x-Q1 THERMAL METRIC (1) LMP8602, LMP8602-Q1, LMP8603, LMP8603-Q1 UNIT D (SOIC) DGK (VSSOP) 8 PINS 8 PINS RJA Junction-to-ambient thermal resistance (2) 113.1 171.1 C/W RJC(top) Junction-to-case (top) thermal resistance 57.3 64.1 C/W RJB Junction-to-board thermal resistance 53.5 91.1 C/W JT Junction-to-top characterization parameter 11.1 9.4 C/W JB Junction-to-board characterization parameter 53.0 89.7 C/W RJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A C/W (1) (2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), RJA, and the ambient temperature, TA. The maximum allowable power dissipation PDMAX = (TJ(MAX) - TA) / RJA or the number given in Absolute Maximum Ratings, whichever is lower. 6.6 Electrical Characteristics: VS = 3.3 V at TA = 25C, VS = 3.3 V, GND = 0 V, -4 V VCM 27 V, RL = , OFFSET (pin 7) is grounded, and 10 nF between VS and GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT OVERALL PERFORMANCE (FROM -IN (PIN 1) AND +IN (PIN 8) TO OUT (PIN 5) WITH PINS A1 (PIN 3) AND A2 (PIN 4) CONNECTED) IS Supply current AV Total gain 1 Over full temperature range 19.9 20 20.1 LMP8602, LMP8602-Q1 49.75 50 50.25 LMP8603, LMP8603-Q1 99.5 100 100.5 -2.7 20 Gain Drift (3) Over full temperature range Slew rate (4) VIN = 0.165 V BW Bandwidth VOS Input offset voltage VCM = VS / 2 TCVOS Input offset voltage drift (5) Over full temperature range en Input-referred voltage noise PSRR Power-supply rejection ratio (3) (4) (5) mA V/V ppm/C 0.4 0.7 V/s 50 60 kHz 0.15 1 mV 2 10 V/C 0.1 Hz - 10 Hz, 6 sigma 16.4 VP-P Spectral density, 1 kHz 830 nV/Hz 86 3.0 V VS 3.6 V, DC, VCM = VS/2 Over full temperature range LMP8601, LMP8601-Q1 Input referred LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 (1) (2) 1.3 LMP8601, LMP8601-Q1 SR Midscale offset scaling accuracy 0.6 dB 70 0.15% 0.5% 0.413 0.25% 1% 0.45% 1.5% Input referred 0.33 Input referred 0.248 mV mV mV Data sheet min and max limits are specified by test. Typical values represent the most likely parameter norms at TA = 25C, and at the Recommended Operation Conditions at the time of product characterization. Both the gain of preamplifier K1 and the gain of buffer amplifier K2 are measured individually. The overall gain of both amplifiers (AV) is also measured to assure the gain of all parts is always within the AV limits. Slew rate is the average of the rising and falling slew rates. Offset voltage drift determined by dividing the change in VOS at temperature extremes into the total temperature change. Copyright (c) 2008-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 5 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 www.ti.com Electrical Characteristics: VS = 3.3 V (continued) at TA = 25C, VS = 3.3 V, GND = 0 V, -4 V VCM 27 V, RL = , OFFSET (pin 7) is grounded, and 10 nF between VS and GND (unless otherwise noted) PARAMETER MIN (1) TEST CONDITIONS TYP (2) MAX (1) UNIT PREAMPLIFIER (FROM INPUT PINS -IN, (PIN 1) AND +IN (PIN 8) TO A1 (PIN 3)) RCM Input impedance common mode -4 V VCM 27 V RDM Input impedance differential mode -4 V VCM 27 V VOS Input offset voltage VCM = VS / 2 DC CMRR DC common-mode rejection ratio AC CMRR AC common-mode rejection ratio (6) CMVR Input common-mode voltage range K1 Preamplifier gain (3) -2 V VCM 24 V 295 Over full temperature range 250 Over full temperature range 500 590 700 0.15 1 96 Over full temperature range f = 1 kHz 80 94 -4 9.95 27 10.0 k mV dB 85 Over full temperature range k dB 86 f = 10 kHz for 80-dB CMRR 350 V 10.05 V/V k 100 RF-INT Output impedance filter resistor TCRF-INT Output impedance filter resistor drift -40C TA 125C 99 101 -40C TA 150C, LMP8601EDRQ1 only 97 103 Over full temperature range VOL, RL = A1 VOUT A1 output voltage swing VOH, RL = 5 50 2 Over full temperature range 10 3.25 Over full temperature range 3.2 Over full temperature range -2.5 ppm/C mV V OUTPUT BUFFER (FROM A2 (PIN 4) TO OUT (PIN 5 )) VOS Input offset voltage K2 Output buffer gain (3) 0V VCM VS 1.99 2 2.01 LMP8602, LMP8602-Q1 4.975 5 5.025 LMP8603, LMP8603-Q1 9.95 10 10.05 Over full temperature range VOL, RL = 100 k A2 output voltage swing (8) LMP8602, LMP8602-Q1 (9) LMP8603, LMP8603-Q1 VOH, RL = 100 k ISC (6) (7) (8) (9) (10) 6 2 2.5 LMP8601, LMP8601-Q1 LMP8601, LMP8601-Q1, A2 VOUT 0.5 -40 Input bias current of A2 (7), IB -2 Output short-circuit current (10) nA 4 Over full temperature range 20 10 Over full temperature range 40 mV 10 Over full temperature range 80 3.29 Sinking, VIN = GND, VOUT = VS V/V fA 20 Over full temperature range Sourcing, VIN = VS, VOUT = GND mV V 3.28 -25 -38 -60 30 46 65 mA AC common-mode signal is a 5-VPP sine-wave (0 V to 5 V) at the given frequency. Positive current corresponds to current flowing into the device. For this test input is driven from A1 stage. For VOL, RL is connected to VS and for VOH, RL is connected to GND. Short-Circuit test is a momentary test. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150C. Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 www.ti.com SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 6.7 Electrical Characteristics: VS = 5 V at TA = 25C, VS = 5 V, GND = 0 V, -22 V VCM 60 V, RL = , OFFSET (pin 7) is grounded, and 10 nF between VS and GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT OVERALL PERFORMANCE (FROM -IN (PIN 1) AND +IN (PIN 8) TO OUT (PIN 5) WITH PINS A1 (PIN 3) AND A2 (PIN 4) CONNECTED) IS Supply current AV Total gain (3) 1.1 Over full temperature range 19.9 20 20.1 LMP8602, LMP8602-Q1 49.75 50 50.25 LMP8603, LMP8603-Q1 99.5 100 100.5 -2.8 20 Gain drift -40C TA 125C Slew rate (4) VIN = 0.25 V BW Bandwidth VOS Input offset voltage TCVOS Input offset voltage drift (5) eN Input-referred voltage noise PSRR Power-supply rejection ratio (3) (4) (5) 0.6 0.83 50 60 mA V/V ppm/C V/s kHz 0.15 1 mV 2 10 V/C -40C TA 125C 0.1 Hz - 10 Hz, 6 sigma 17.5 VP-P Spectral density, 1 kHz 890 nV/Hz 90 4.5 V VS 5.5 V, DC Over full temperature range LMP8601, LMP8601-Q1 Input-referred LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 (1) (2) 1.5 LMP8601, LMP8601-Q1 SR Midscale offset scaling accuracy 0.7 dB 70 0.15% 0.5% 0.625 0.25% 1% 0.45% 1.5% Input-referred 0.50 Input-referred 0.375 mV mV mV Data sheet min and max limits are specified by test. Typical values represent the most likely parameter norms at TA = 25C, and at the Recommended Operation Conditions at the time of product characterization. Both the gain of preamplifier K1 and the gain of buffer amplifier K2 are measured individually. The overall gain of both amplifiers (AV) is also measured to assure the gain of all parts is always within the AV limits. Slew rate is the average of the rising and falling slew rates. Offset voltage drift determined by dividing the change in VOS at temperature extremes into the total temperature change. Copyright (c) 2008-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 7 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 www.ti.com Electrical Characteristics: VS = 5 V (continued) at TA = 25C, VS = 5 V, GND = 0 V, -22 V VCM 60 V, RL = , OFFSET (pin 7) is grounded, and 10 nF between VS and GND (unless otherwise noted) PARAMETER MIN (1) TEST CONDITIONS TYP (2) MAX (1) UNIT PREAMPLIFIER (FROM INPUT PINS -IN (PIN 1) AND +IN (PIN 8) TO A1 (PIN 3)) 0 V VCM 60 V RCM Input impedance, common mode -20 V VCM 0 V 0 V VCM 60 V RDM Input impedance, differential mode -20 V VCM 0 V VOS Input offset voltage 295 Over full temperature range 250 Over full temperature range 165 Over full temperature range 500 Over full temperature range 300 193 DC common-mode rejection ratio AC CMRR AC common-mode rejection ratio (6) CMVR Input common-mode voltage range K1 Preamplifier gain (3) RF-INT Output impedance filter resistor -20 V VCM 60 V 700 386 500 0.15 1 105 Over full temperature range f = 1 kHz 80 96 -22 9.95 60 10 k k k mV dB 83 Over full temperature range k dB 90 f = 10 kHz for 80-dB CMRR 250 590 VCM = VS / 2 DC CMRR 350 V 10.05 V/V k 100 TCRF-INT -40C TA 125C, 99 101 -40C TA 150C, LMP8601EDRQ1 only 97 103 Output impedance filter resistor drift 5 VOL, RL = A1 VOUT A1 output voltage swing VOH, RL = 50 2 Over full temperature range 10 4.985 Over full temperature range 4.95 Over full temperature range -2.5 ppm/C mV V OUTPUT BUFFER (FROM A2 (PIN 4) TO OUT (PIN 5)) VOS Input offset voltage K2 Output buffer gain (3) 0V VCM VS 1.99 2 2.01 LMP8602, LMP8602-Q1 4.975 5 5.025 LMP8603, LMP8603-Q1 9.95 10 10.05 Over full temperature range VOL, RL = A2 output voltage swing (8) LMP8602, LMP8602-Q1 (9) LMP8602, LMP8603-Q1 VOH, RL = ISC (6) (7) (8) (9) (10) 8 2 2.5 LMP8601, LMP8601-Q1 LMP8601, LMP8601-Q1, A2 VOUT 0.5 -40 Input bias current of A2 (7) IB -2 Output short-circuit current (10) nA 4 Over full temperature range 20 10 Over full temperature range 40 mV 10 Over full temperature range 80 4.99 Sinking, VIN = GND, VOUT = VS V/V fA 20 Over full temperature range Sourcing, VIN = VS, VOUT = GND mV V 4.98 -25 -42 -60 30 48 65 mA AC common-mode signal is a 5-VPP sine-wave (0 V to 5 V) at the given frequency. Positive current corresponds to current flowing into the device. For this test input is driven from A1 stage. For VOL, RL is connected to VS and for VOH, RL is connected to GND. Short-Circuit test is a momentary test. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150C. Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 www.ti.com SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 6.8 Typical Characteristics at TA = 25C, VS = 5 V, GND = 0 V, -22 VCM 60 V, RL = , OFFSET (pin 7) connected to VS, and 10 nF between VS and GND (unless otherwise noted) 1.0 1.0 0.8 0.8 0.6 125C 85C 0.6 VOFFSET (mV) VOFFSET (mV) 0.4 0.2 0 -0.2 25C -0.4 -0.6 0.4 0.2 0 -0.2 -0.4 -40C 25C -40C -0.6 -0.8 125C 85C -0.8 VS = 3.3V -1.0 VS = 5V -1.0 -4 0 4 8 12 16 20 24 28 30 -20 -10 0 VCM (V) 10 20 30 40 50 60 VCM (V) Figure 1. VOS vs VCM at VS = 3.3 V Figure 2. VOS vs VCM at VS = 5 V 100 200 75 150 25C 100 25C IBIAS (A) IBIAS (A) 50 25 125C 0 50 125C 0 -40C -25 -50 -40C -50 -10 0 10 20 -100 -30 30 -10 10 30 50 70 VCM (V) VCM (V) Figure 3. Input Bias Current Over Temperature (+IN and -IN pins) at VS = 3.3 V Figure 4. Input Bias Current Over Temperature (+IN and -IN pins) at VS = 5 V 100 200 -40C 0 100 IBIAS (fA) IBIAS (pA) 150 50 -100 25C 125C -200 0 -50 0 1 2 3 4 5 VCM (V) Figure 5. Input Bias Current Over Temperature (A2 pin) at VS = 5 V Copyright (c) 2008-2016, Texas Instruments Incorporated -300 0 1 2 3 4 5 VCM (V) Figure 6. Input Bias Current Over Temperature (A2 pin) at VS = 5 V Submit Documentation Feedback Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 9 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 www.ti.com Typical Characteristics (continued) at TA = 25C, VS = 5 V, GND = 0 V, -22 VCM 60 V, RL = , OFFSET (pin 7) connected to VS, and 10 nF between VS and GND (unless otherwise noted) 1.5 100 1.2 80 VS = 5V PSRR (dB) VOLTAGE NOISE (V/ Hz) VS = 5V 0.9 0.6 VS = 3.3V 0.3 VS = 3.3V 60 40 20 0 0.1 1 10 100 1k 10k 0 10 100k 100 FREQUENCY (Hz) 30 -40C 20 20 10 10 GAIN (dB) GAIN (dB) -40C 25C -10 85C -30 10k 0 25C -10 85C -20 -30 125C -40 VS = 3.3V VOUT = VS/2 -50 100 1k 100k 125C -40 VS = 5V VOUT = VS/2 -50 100 1k 1M 120 25C -40C 1M -40C 100 100 80 80 85C CMRR (dB) CMRR (dB) 100k Figure 10. Gain vs Frequency at VS = 5 V Figure 9. Gain vs Frequency at VS = 3.3 V 120 125C 60 40 0 100 125C 85C 60 40 20 20 10 10k FREQUENCY (Hz) FREQUENCY (Hz) 25C 100k Figure 8. PSRR vs Frequency 30 -20 10k FREQUENCY (Hz) Figure 7. Input-Referred Voltage Noise vs Frequency 0 1k VS = 3.3V 1k 10k 100k 0 100 VS = 5V 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 11. CMRR vs Frequency at VS = 3.3 V Figure 12. CMRR vs Frequency at VS = 5 V Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 www.ti.com SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 Typical Characteristics (continued) OUTPUT SIGNAL (1V/DIV) OUTPUT SIGNAL (1V/DIV) INPUT SIGNAL (100 mV/DIV) INPUT SIGNAL (200 mV/DIV) at TA = 25C, VS = 5 V, GND = 0 V, -22 VCM 60 V, RL = , OFFSET (pin 7) connected to VS, and 10 nF between VS and GND (unless otherwise noted) VS = 3.3V RL = 10 k VS = 5V RL = 10 k TIME (20 s/DIV) TIME (20 s/DIV) Figure 13. Step Response at VS = 3.3 V LMP8601 and LMP8601-Q1 INPUT SIGNAL (200 mV/DIV) OUTPUT SIGNAL (1V/DIV) INPUT SIGNAL (100 mV/DIV) OUTPUT SIGNAL (1V/DIV) Figure 14. Step Response at VS = 5 V LMP8601 and LMP8601-Q1 VS = 3.3V TIME (5 s/DIV) TIME (5 s/DIV) Figure 16. Settling Time (Falling Edge) at VS = 5 V LMP8601 and LMP8601-Q1 VS = 3.3V TIME (5 s/DIV) Figure 17. Settling Time (Rising Edge) at VS = 3.3 V LMP8601 and LMP8601-Q1 Copyright (c) 2008-2016, Texas Instruments Incorporated OUTPUT SIGNAL (1V/DIV) INPUT SIGNAL (100 mV/DIV) OUTPUT SIGNAL (200 mV/DIV) Figure 15. Settling Time (Falling Edge) at VS = 3.3 V LMP8601 and LMP8601-Q1 OUTPUT SIGNAL (1V/DIV) VS = 5V VS = 5V TIME (5 s/DIV) Figure 18. Settling Time (Rising Edge) at VS = 5 V LMP8601 and LMP8601-Q1 Submit Documentation Feedback Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 11 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 www.ti.com Typical Characteristics (continued) OUTPUT SIGNAL (1V/DIV) OUTPUT SIGNAL (1V/DIV) INPUT SIGNAL (50 mV/DIV) INPUT SIGNAL (50 mV/DIV) at TA = 25C, VS = 5 V, GND = 0 V, -22 VCM 60 V, RL = , OFFSET (pin 7) connected to VS, and 10 nF between VS and GND (unless otherwise noted) TIME (20 Ps/DIV) Figure 20. Step Response at VS = 5 V, RL = 10 k LMP8602 and LMP8602-Q1 OTPUT SIGNAL (1V/DIV) OUTPUT SIGNAL (1V/DIV) INPUT SIGNAL (50 mV/DIV) INPUT SIGNAL (50 mV/DIV) Figure 19. Step Response at VS = 3.3 V, RL = 10 k LMP8602 and LMP8602-Q1 TIME (20 Ps/DIV) TIME (5 Ps/DIV) OUTPUT SIGNAL (1V/DIV) OTPUT SIGNAL (1V/DIV) TIME (5 Ps/DIV) Figure 23. Settling Time (Rising Edge) at VS = 3.3 V LMP8602 and LMP8602-Q1 12 Figure 22. Settling Time (Falling Edge) at VS = 5 V LMP8602 and LMP8602-Q1 INPUT SIGNAL (50 mV/DIV) INPUT SIGNAL (50 mV/DIV) Figure 21. Settling Time (Falling Edge) at VS = 3.3 V LMP8602 and LMP8602-Q1 TIME (5 us/DIV) Submit Documentation Feedback TIME (5 us/DIV) Figure 24. Settling Time (Rising Edge) at VS = 5 V LMP8602 and LMP8602-Q1 Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 www.ti.com SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 Typical Characteristics (continued) at TA = 25C, VS = 5 V, GND = 0 V, -22 VCM 60 V, RL = , OFFSET (pin 7) connected to VS, and 10 nF between VS and GND (unless otherwise noted) VIN (20 mV/DIV) 8 7 6 5 7 6 5 4 4 3 3 VOUT (1V/DIV) VOUT (1V/DIV) VIN (20 mV/DIV) 8 2 1 0 2 1 0 TIME (20 us/DIV) TIME (20 us/DIV) INPUT SIGNAL (20 mV/DIV) Figure 26. Step Response at VS = 5 V, RL = 10 k LMP8603 and LMP8603-Q1 OUTPUT SIGNAL (1V/DIV) OUTPUT SIGNAL (1V/DIV) INPUT SIGNAL (20 mV/DIV) Figure 25. Step Response at VS = 3.3 V, RL = 10 k LMP8603 and LMP8603-Q1 TIME (5 us/DIV) INPUT SIGNAL (20 mV/DIV) Figure 28. Settling Time (Falling Edge) at VS = 5 V LMP8603 and LMP8603-Q1 OUTPUT SIGNAL (1V/DIV) OUTPUT SIGNAL (1V/DIV) INPUT SIGNAL (20 mV/DIV) Figure 27. Settling Time (Falling Edge) at VS = 3.3 V LMP8603 and LMP8603-Q1 TIME (5 us/DIV) TIME (5 us/DIV) Figure 29. Settling Time (Rising Edge) at VS = 3.3 V LMP8603 and LMP8603-Q1 Copyright (c) 2008-2016, Texas Instruments Incorporated TIME (5 us/DIV) Figure 30. Settling Time (Rising Edge) at VS = 5 V LMP8603 and LMP8603-Q1 Submit Documentation Feedback Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 13 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 www.ti.com Typical Characteristics (continued) at TA = 25C, VS = 5 V, GND = 0 V, -22 VCM 60 V, RL = , OFFSET (pin 7) connected to VS, and 10 nF between VS and GND (unless otherwise noted) 3.30 60 50 OUTPUT VOLTAGE (mV) 3.28 OUTPUT VOLTAGE (V) VS = 3.3V VIN = 0V VCM = VS/2 3.26 3.24 3.22 40 30 20 VS = 3.3V VIN = 165 mV VCM = VS/2 3.20 1k 10k 10 0 1k 100k 10k LOAD RESISTANCE () LOAD RESISTANCE () Figure 32. Negative Swing vs RLOAD at VS = 3.3 V 5.00 90 4.98 75 OUTPUT VOLTAGE (mV) OUTPUT VOLTAGE (V) Figure 31. Positive Swing vs RLOAD at VS = 3.3 V 4.96 4.94 4.92 4.90 10k VS = 5V VIN = 0V VCM = VS/2 60 45 30 15 VS = 5V VIN = 250 mV VCM = VS/2 4.88 1k 0 1k 100k 10k LOAD RESISTANCE () Figure 34. Negative Swing vs RLOAD at VS = 5 V 25C 30 25 20 -40C PERCENTAGE (%) PERCENTAGE (%) 30 35 VS = 3.3V 6000 parts 125C 15 10 5 0 -1.0 VS = 5V 6000 parts 25C 25 20 -40C 125C 15 10 5 -0.6 -0.2 0 0.2 0.6 1.0 VOS (mV) Figure 35. VOS Distribution at VS = 3.3 V 14 100k LOAD RESISTANCE () Figure 33. Positive Swing vs RLOAD VS = 5 V 35 100k Submit Documentation Feedback 0 -1.0 -0.6 -0.2 0 0.2 0.6 1.0 VOS (mV) Figure 36. VOS Distribution at VS = 5 V Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 www.ti.com SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 Typical Characteristics (continued) at TA = 25C, VS = 5 V, GND = 0 V, -22 VCM 60 V, RL = , OFFSET (pin 7) connected to VS, and 10 nF between VS and GND (unless otherwise noted) 30 30 1300 parts 1300 parts VS = 3.3V 25 25 PERCENTAGE (%) PERCENTAGE (%) VS = 5V 20 15 10 VS = 5V 20 15 VS = 3.3V 10 5 5 0 -10 -8 -6 -4 -2 0 2 4 6 8 0 -10 -8 10 -6 Figure 37. TCVOS Distribution VS = 3V3 20 VS = 5V 2 4 6 8 10 VS = 3.3V VS = 5V PERCENTAGE (%) PERCENTAGE (%) 0 Figure 38. Gain Drift Distribution, 1300 Parts LMP8601 and LMP8601-Q1 12 9 6 3 0 15 10 5 0 -10 -8 -6 -4 -2 0 2 4 6 8 10 -10 -8 GAIN DRIFT (ppm/C) -6 -4 -2 0 2 4 GAIN DRIFT (ppm/C) 6 8 10 Figure 39. Gain Drift Distribution, 5000 Parts LMP8602 and LMP8602-Q1 Figure 40. Gain Drift Distribution, 5000 Parts LMP8603 and LMP8603-Q1 20 20 VS = 3.3V VS = 5V 6000 parts 6000 parts -40C 15 10 PERCENTAGE (%) PERCENTAGE (%) -2 GAIN DRIFT (ppm/C) TCVOS (V/C) 15 -4 25C 125C 5 0 -0.50 -0.25 0.00 0.25 0.50 15 -40C 10 25C 125C 5 0 -0.50 -0.25 0.00 0.25 0.50 GAIN ERROR (%) GAIN ERROR (%) Figure 41. Gain Error Distribution at VS = 3.3 V LMP8601 and LMP8601-Q1 Figure 42. Gain Error Distribution at VS = 5 V LMP8601 and LMP8601-Q1 Copyright (c) 2008-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 15 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 www.ti.com Typical Characteristics (continued) at TA = 25C, VS = 5 V, GND = 0 V, -22 VCM 60 V, RL = , OFFSET (pin 7) connected to VS, and 10 nF between VS and GND (unless otherwise noted) 20 25C 15 25C 125C 15 PERCENTAGE (%) PERCENTAGE (%) 20 125C 10 -40C 5 0 -40C 10 5 0 -0.50 -0.25 0.00 0.25 0.50 -0.50 -0.25 Figure 43. Gain Error Distribution at VS = 3.3 V, 5000 Parts LMP8602 and LMP8602-Q1 20 VS = 3.3V VS = 3.3V 15 PERCENTAGE (%) PERCENTAGE (%) VS = 5V 10 5 0 15 10 5 0 -10 -8 -6 -4 -2 0 2 4 GAIN DRIFT (ppm/C) 6 8 10 -10 -8 Figure 45. Gain Error Distribution at VS = 3.3 V, 5000 Parts LMP8603 and LMP8603-Q1 -6 -4 -2 0 2 4 GAIN DRIFT (ppm/C) 6 8 10 Figure 46. Gain Error Distribution at VS = 5 V LMP8603 and LMP8603-Q1 30 30 25C -40C VS = 3.3V VS = 5V 6000 parts 6000 parts 25 125C PERCENTAGE (%) 25 PERCENTAGE (%) 0.50 Figure 44. Gain Error Distribution at VS = 5 V, 5000 Parts LMP8602 and LMP8602-Q1 VS = 5V 20 15 10 5 -40C 20 25C 15 125C 10 5 0 0 80 90 100 110 120 CMRR (dB) 130 140 Figure 47. CMRR Distribution at VS = 3.3 V 16 0.25 GAIN ERROR (%) GAIN ERROR (%) 20 0.00 Submit Documentation Feedback 80 90 100 110 120 CMRR (dB) 130 140 Figure 48. CMRR Distribution at VS = 5 V Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 www.ti.com SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 Typical Characteristics (continued) at TA = 25C, VS = 5 V, GND = 0 V, -22 VCM 60 V, RL = , OFFSET (pin 7) connected to VS, and 10 nF between VS and GND (unless otherwise noted) 5 60 VS = 5V, VCM = 0V VS = 5V, VCM = 0V 50 4 VOUT (mV) VOUT (V) 40 3 2 30 20 1 10 0 0 50 100 150 200 0 -2.5 250 -1.5 VIN (mV) -0.5 0.5 1.5 2.5 VIN (mV) C001 Figure 49. Output Voltage vs VIN C003 Figure 50. Output Voltage vs VIN (Enlarged Close to 0 V) 5 60 VS = 3.3V, VCM = 0V VS = 3.3V, VCM = 0V 50 4 VOUT (mV) VOUT (V) 40 3 2 30 20 1 10 0 0 50 100 150 200 250 VIN (mV) 0 -2.5 -1.5 -0.5 0.5 C002 Figure 51. Output Voltage vs VIN Copyright (c) 2008-2016, Texas Instruments Incorporated 1.5 2.5 VIN (mV) C004 Figure 52. Output Voltage vs VIN (Enlarged Close to 0 V) Submit Documentation Feedback Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 17 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 www.ti.com 7 Detailed Description 7.1 Overview The LMP860x and LMP860x-Q1 are fixed gain differential voltage precision amplifiers, with a -22-V to +60-V input common-mode voltage range when operating from a single 5-V supply, or a -4-V to +27-V input commonmode voltage range when operating from a single 3.3-V supply. The LMP8601 and LMP8601-Q1 have a gain of 20x, the LMP8602 and LMP8602-Q1 have a gain of 50x, and the LMP8603 and LMP8603-Q1 have a gain of 100x. The LMP860x and LMP860x-Q1 are members of the LMP family and are ideal parts for unidirectional and bidirectional current sensing applications. Because of the proprietary chopping level-shift input stage, the LMP860x and LMP860x-Q1 achieve very low offset, very low thermal offset drift, and very high CMRR. The LMP860x and LMP860x-Q1 amplify and filter small differential signals in the presence of high common-mode voltages. The LMP860x and LMP860x-Q1 use level shift resistors at the inputs. Because of these resistors, the LMP860x and LMP860x-Q1 can easily withstand very large differential input voltages that may exist in fault conditions where some other less protected high-performance current sense amplifiers might sustain permanent damage. 7.1.1 Theory of Operation The schematic shown in the Functional Block Diagram gives a basic representation of the internal operation of the LMP860x and LMP860x-Q1. The signal on the input pins is typically a small differential voltage developed across a current sensing shunt resistor. The input signal may also appear at a high common-mode voltage. The input signals are accessed through two input resistors that change the voltage into a current. The proprietary chopping level-shift current circuit pulls or pushes current through the input resistors to bring the common-mode voltage behind these resistors within the supply rails. Subsequently, the signal is gained up by a factor of 10 and brought out on the A1 pin through a trimmed 100-k resistor. In the application, additional gain adjustment or filtering components can be added between the A1 and A2 pins as explained in subsequent sections. The signal on the A2 pin is further amplified by a factor of 2 (LMP8601 and LMP8601-Q1), 5 (LMP8602, LMP8602-Q1), or 10 (LMP8603, LMP8603-Q1), and brought out on the OUT pin. 7.2 Functional Block Diagram OFFSET VS 7 6 +IN Level shift 8 + Preamplifier Gain = 10 -IN 1 Output Buffer Gain = K2 5 OUT - 100 k: 2 GND 3 4 A1 A2 NOTE: K2 = 2 for LMP8601, LMP8601-Q1; 5 for LMP8602, LMP8602-Q1; or 10 for LMP8603, LMP8603-Q1. 18 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 www.ti.com SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 7.3 Feature Description 7.3.1 Offset Input Pin The OFFSET pin allows the output signal to be level-shifted to enable bidirectional current sensing. The output signal is bidirectional and mid-rail referenced when the offset pin is connected to the positive supply rail. With the offset pin connected to ground, the output signal is unidirectional and ground-referenced. The signal on the A1 and OUT pins is ground-referenced when the offset pin is connected to ground. This means that the output signal can only represent positive values of the current through the shunt resistor, so only currents flowing in one direction can be measured. When the offset pin is tied to the positive supply rail, the signal on the A1 and OUT pins is referenced to a midrail voltage which allows bidirectional current sensing. The operation of the amplifier will be fully bidirectional and symmetrical around 0 V differential at the input pins. The signal at the output will follow this voltage difference multiplied by the gain and at an offset voltage at the output of half VS. When the offset pin is connected to an external voltage source, the output signal will be level shifted to that voltage divided by two. In principle, the output signal can be shifted to any voltage between 0 and VS / 2 by applying twice that voltage to the OFFSET pin. NOTE The OFFSET pin must be driven from a very low-impedance source (< 10 ). This low source impedance is required because the OFFSET pin internally connects directly to the resistive feedback networks of the two gain stages. When the OFFSET pin is driven from a relatively large impedance (for example, a resistive divider between the supply rails), accuracy decreases. Examples: * LMP8601, LMP8601-Q1: A 5-V supply, a gain of 20x, OFFSET pin tied to VS, and a differential input signal of 10 mV results in 2.7 V at the output pin. Similarly, -10 mV at the input results in 2.3 V at the output pin. * LMP8602, LMP8602-Q1: A 5-V supply, a gain of 50x, and a differential input signal of 10 mV results in 3.0 V at the output pin. Similarly, -10 mV at the input results in 2.0 V at the output pin. * LMP8603, LMP8603-Q1: A 5-V supply, a gain of 100x, and a differential input signal of 10 mV results in 3.5 V at the output pin. Similarly, -10 mV at the input results in 1.5 V at the output pin. (1) (1) (1) The OFFSET pin must be driven from a very low-impedance source (< 10 ) because the OFFSET pin internally connects directly to the resistive feedback networks of the two gain stages. When the OFFSET pin is driven from a relatively large impedance (for example, a resistive divider between the supply rails), accuracy decreases. Copyright (c) 2008-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 19 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 www.ti.com Feature Description (continued) 7.3.2 Additional Second-Order Low-Pass Filter The LMP86x1 and LMP86x1-Q1 have a third-order Butterworth lowpass characteristic with a typical bandwidth of 60 kHz integrated in the preamplifier stage. The bandwidth of the output buffer can be reduced by adding a capacitor on the A1 pin to create a first-order low-pass filter with a time constant determined by the 100-k internal resistor and the external filter capacitor. It is also possible to create an additional second-order, Sallen-Key, low-pass filter by adding external components R2, C1 and C2. Together with the internal 100-k resistor R1 as illustrated in Figure 53, this circuit creates a second-order, low-pass filter characteristic. OFFSET 7 +IN 8 -IN 1 + Level shift Output Buffer Gain = K2 Preamplifier Gain = K1 - 5 OUT Internal R1 100 k: 3 4 A1 A2 R2 C1 C2 NOTE: K1 = 10; K2 = 2 for LMP8601, LMP8601-Q1; 5 for LMP8602, LMP8602-Q1; or 10 for LMP8603, LMP8603-Q1. Figure 53. Second-Order Low-Pass Filter When the corner frequency of the additional filter is much lower than 60 kHz, the transfer function of the described amplifier can be written as: K1 * K2 H(s) = 2 s +s* 1 R1R2C1C2 (1 - K2) 1 1 1 + + + R 1C2 R 2C2 R2C1 R1R2C1C2 where * K1 equals the gain of the preamplifier and K2 that of the buffer amplifier. (1) Equation 1 can be written in the normalized frequency response for a second-order lowpass filter: G(jZ) = K1 * K2 2 jZ (jZ) +1 2 + QZo Zo (2) The cutoff frequency o in rad/sec (divide by 2 to get the cut-off frequency in Hz) is given by: Zo = 1 R 1 R 2C 1 C 2 20 Submit Documentation Feedback (3) Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 www.ti.com SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 Feature Description (continued) and the quality factor of the filter is given by: Q= R 1R2C1 C2 R1C1 + R2C1 + (1 - K2) * R1C2 (4) With K2 = 2x, Equation 4 transforms results in: R 1 R 2 C 1C 2 Q= R 1C 1 + R 2 C 1 - R1 C 2 (5) For any filter gain K > 1x, the design procedure can be very simple if the two capacitors are chosen to in a certain ratio. C2 = C1 K2 1 (6) Inserting this in Equation 4 for Q results in: R 1R 2 Q= C1 K2 2 1 (K2 R 1C1 + R 2C 1 1)R1C1 K2 1 (7) Which results in: 2 R 1R2 Q= C1 K2 1 C1R2 R1R 2 = K2 1 R2 (8) In this case, given the predetermined value of R1 = 100 k (the internal resistor), the quality factor is set solely by the value of the resistor R2. R2 can be calculated based on the desired value of Q as the first step of the design procedure with the following equation: R2 = R1 (K - 1) Q2 (9) For the gain of 2 for the LMP8601 and LMP8601-Q1, the result is: R2 = R1 2 Q (10) For the gain of 5 for the LMP8602 and LMP8602-Q1, the result is: R2 = R1 4Q2 (11) For the gain of 10 for the LMP8603 and LMP8603-Q1, the result is: R2 = R1 2 9Q (12) Copyright (c) 2008-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 21 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 www.ti.com Feature Description (continued) For instance, the value of Q can be set to 0.52 to create a Butterworth response, to 1/3 to create a Bessel response, or a 0.5 to create a critically damped response. After the value of R2 has been found, the second and last step of the design procedure is to calculate the required value of C to give the desired low-pass cut-off frequency using: C1 = 1)Q (K2 R1Z0 (13) For the gain = 2, the result is: Q R1Zo C= (14) The gain = 5 results in: C1 = 4Q R1Z0 (15) The gain = 10 gives: C1 = 9Q R1Z0 (16) For C2 the value is calculated with: C2 = C1 K2 1 (17) For a gain = 2: C2 = C1 (18) Or for a gain = 5: C2 = C1 4 (19) And for a gain = 10: C2 = C1 9 (20) Note that the frequency response achieved using this procedure is only accurate if the cut-off frequency of the second-order filter is much smaller than the intrinsic 60-kHz, low-pass filter. In other words, choose the frequency response of the LMP860x or LMP860x-Q1 circuit so that the internal poles do not affect the external secondorder filter. 7.4 Device Functional Modes 7.4.1 Gain Adjustment The gain of the LMP860x and LMP860x-Q1 is fixed; however, the overall gain may be adjusted as the signal path between the two internal amplifiers is available on the A1 and A2 pins. 22 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 www.ti.com SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 Device Functional Modes (continued) 7.4.1.1 Reducing Gain Figure 54 shows the configuration that can be used to reduce the gain of the LMP8601 and LMP8601-Q1. OFFSET 7 +IN 8 1 + Level shift -IN Output Buffer Gain = K2 Preamplifier Gain = 10 - 5 OUT Internal Resistor 100 k: 3 4 A2 A1 Rr NOTE: K2 = 2 for LMP8601, LMP8601-Q1; 5 for LMP8602, LMP8602-Q1; or 10 for LMP8603, LMP8603-Q1. Figure 54. Reduce Gain Rr creates a resistive divider together with the internal 100-k resistor such that the reduced gain Gr becomes: Gr = 20 Rr Rr + 100 k: (21) For the LMP8602 and LMP8602-Q1: Gr = 50 Rr Rr + 100 k: (22) And for the LMP8603 and LMP8603-Q1: Gr = 100 Rr Rr + 100 k: (23) Given a desired value of the reduced gain Gr, using this equation, the LMP8601 and LMP8601-Q1 required value for the Rr is calculated with: Rr = 100 k: X Gr 20 - Gr (24) For the LMP8602 and LMP8602-Q1: Rr = 100 k: X Gr 50 - Gr (25) And for the LMP8603 and LMP8603-Q1: Rr = 100 k: x Gr 100 - Gr (26) 7.4.1.2 Increasing Gain Figure 55 shows the configuration that can be used to increase the gain of the LMP8601 and LMP8601-Q1. Copyright (c) 2008-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 23 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 www.ti.com Device Functional Modes (continued) OFFSET 7 +IN 8 1 + Level shift -IN Output Buffer Gain = K2 Preamplifier Gain = 10 - 5 OUT Internal Resistor 100 k: 3 A1 4 A2 Ri NOTE: K2 = 2 for LMP8601, LMP8601-Q1; 5 for LMP8602, LMP8602-Q1; or 10 for LMP8603, LMP8603-Q1. Figure 55. Increase Gain Ri creates positive feedback from the output pin to the input of the buffer amplifier. The positive feedback increases the gain. The increased gain Gi for the LMP8601 and LMP8601-Q1 becomes: 20 Ri Gi = Ri - 100 k: (27) For the LMP8602 and LMP8602-Q1: Gi = 50 Ri Ri - 400 k: (28) And for the LMP8603 and LMP8603-Q1: Gi = 100 Ri Ri - 900 k: (29) From this equation, for a desired value of the gain, the LMP8601 and LMP8601-Q1 required value of Ri is calculated with: Gi Ri = 100 k: X Gi - 20 (30) For the LMP8602 and LMP8602-Q1: Gi Gi - 50 Ri = 400 k: X (31) And for the LMP8603 with: Ri = 900 k: x Gi Gi - 100 (32) Note that from the equation for the gain Gi, for large gains, Ri approaches 100 k. In this case, the denominator in the equation becomes close to zero. In practice, for large gains, the denominator is determined by tolerances in the value of the external resistor Ri and the internal 100-k resistor. In this case, the gain becomes very inaccurate. If the denominator becomes equal to zero, the system becomes unstable. TI recommends to limit the application of this technique to gain values of 50 or smaller. 24 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 www.ti.com SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 Device Functional Modes (continued) 7.4.2 Driving Switched Capacitive Loads Some ADCs load their signal source with a sample and hold capacitor. The capacitor may be discharged prior to being connected to the signal source. If the LMP860x and LMP860x-Q1 are driving such ADCs, the sudden current that should be delivered when the sampling occurs may disturb the output signal. This effect was simulated with the circuit shown in Figure 56 where the output is to a capacitor that is driven by a rail-to-rail square wave. VS LMP8601/ LMP8601Q 0V Figure 56. Driving Switched Capacitive Load This circuit simulates the switched connection of a discharged capacitor to the LMP860x and LMP860x-Q1 output. The resulting VOUT disturbance signals are shown in Figure 57 and Figure 58. 0.4 0.5 VS = 5V VS = 3.3V 0.4 0.2 0.3 0 10 pF 0.1 VOUT (V) VOUT (V) 0.2 0 -0.1 -0.2 -0.4 10 pF -0.2 -0.6 20 pF 20 pF -0.3 -0.8 -0.4 -0.5 -1.0 0 50 100 150 200 250 300 0 50 100 150 200 250 300 TIME (ns) TIME (ns) Figure 57. Capacitive Load Response at 3.3 V Figure 58. Capacitive Load Response at 5.0 V These figures can be used to estimate the disturbance that will be caused when driving a switched capacitive load. To minimize the error signal introduced by the sampling that occurs on the ADC input, place an additional RC filter between the LMP860x or LMP860x-Q1 and the ADC, as illustrated in Figure 59. Output Buffer ADC Figure 59. Reduce Error When Driving ADCs The external capacitor absorbs the charge that flows when the ADC sampling capacitor is connected. The external capacitor should be much larger than the sample-and-hold capacitor at the input of the ADC, and the RC time constant of the external filter should be such that the speed of the system is not affected. Copyright (c) 2008-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 25 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Specifying Performance To specify the high performance of the LMP860x and LMP860x-Q1, all minimum and maximum values shown in the parameter tables of this data sheet are 100% tested, and all over temperature limits are also 100% tested over temperature. 8.2 Typical Applications 8.2.1 High-Side, Current-Sensing Application Figure 60 illustrates the application of the LMP860x and LMP860x-Q1 in a high-side sensing application. This application is similar to the low-side sensing discussed below, except in this application the common-mode voltage on the shunt drops below ground when the driver is switched off. Because the common-mode voltage range of the LMP860x and LMP860x-Q1 extends below the negative rail, the LMP860x and LMP860x-Q1 are also very well suited for this application. POWER SWITCH OFFSET 7 INDUCTIVE LOAD +IN 8 + + 24V - RSENSE 1 -IN Level shift Output Buffer Gain = K2 Preamplifier Gain = 10 - 5 OUT Internal Resistor 100 k: 3 4 A2 A1 C1 NOTE: For this application example, K2 = 2. Figure 60. High-Side, Current-Sensing Application 26 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 www.ti.com SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 Typical Applications (continued) 8.2.1.1 Design Requirements Using the circuit in Figure 60, the requirement is to measure coil current up to 10 A and drive the ADC input to a maximum of 3.3 V. The OFFSET pin is grounded, so zero current will result in a zero volt output. 8.2.1.2 Detailed Design Procedure First, the value of RSENSE must be determined. RSENSE can be found by dividing the maximum desired output swing by the gain to determine the maximum input voltage. In this example, the LMP8601 is used, with a gain of 20 V/V, as shown in Equation 33: 3.3 V VOUTMAX = = 165 mV VINMAX = Gain 20 V/V (33) Knowing 165 mV must be generated, the ideal value of the sense resistor can be determined through simple ohms law: 165 mV VINMAX = = 16.5 PY RSENSE = 10A ILOADMAX (34) The ideal sense resistor value is 16.5 m. The closest standard value is 15 m, but this value may cause the output to slightly overrange at 10 V. It is recommended to reduce the expected maximum output by a few percent to allow for overloads and component tolerances. The next most popular values would be 10 m, 15 m, and 20 m. 10 m allows for a maximum output of 2 V at 10 A, but may be too low and not use the full output range. 20 m provides more sensitivity, but limits the maximum current to 8.25 A. 15 m is a good compromise at 11 A maximum, and allows for some component tolerance variation. If a suitable sense resistor value is not available, it is possible to adjust the gain as detailed in the Gain Adjustment section. The sense resistor does dissipates power, so the maximum wattage rating and appropriate power deratings must be observed. In the example above, the sense resistor dissipates 0.165 V x 10 A = 1.65 W, so a sense resistor of at least twice the maximum expected power should be used (greater than 4 W). 8.2.1.3 Application Curve Below is the expected output value using a 15-m sense resistor. 5.0 VS = 5V Output Voltage (V) 4.0 3.0 VS = 3.3V 2.0 1.0 RSENSE = 15mY 0.0 0 2 4 6 8 10 12 Load Current (A) 14 16 18 20 C001 Figure 61. Expected Output Voltage vs Load Current Using 15-m Sense Resistor Copyright (c) 2008-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 27 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 www.ti.com Typical Applications (continued) 8.2.2 Low-Side, Current-Sensing Application Figure 62 illustrates a low-side, current-sensing application with a low-side driver. The power transistor is pulse width modulated to control the average current flowing through the inductive load which is connected to a relatively high battery voltage. The current through the load is measured across a shunt resistor RSENSE in series with the load. When the power transistor is on, current flows from the battery through the inductive load, the shunt resistor and the power transistor to ground. In this case, the common-mode voltage on the shunt is close to ground. When the power transistor is off, current flows through the inductive load, through the shunt resistor and through the freewheeling diode. In this case the common-mode voltage on the shunt is at least one diode voltage drop above the battery voltage. Therefore, in this application the common-mode voltage on the shunt is varying between a large positive voltage and a relatively low voltage. Because the large common-mode voltage range of the LMP860x and LMP860x-Q1 and because of the high ac common-mode rejection ratio, the LMP860x and LMP860x-Q1 are very well suited for this application. OFFSET 7 INDUCTIVE LOAD +IN 8 RSENSE 1 -IN + 24V + Level shift Output Buffer Gain = K2 Preamplifier Gain = 10 - OUT - Internal Resistor 100 k: 3 POWER SWITCH 5 A1 4 A2 C1 RSENSE = 0.01 , K2 = 2, VOUT = 0.2 V/A Figure 62. Low-Side Current-Sensing Application For this application, the following example can be used for the calculation of the sense voltage (VSENSE): When using a sense resistor, RSENSE, of 0.01 and a current, ILOAD, of 1 A, the sense voltage at the input pins of the LMP860x and LMP860x-Q1 is: VSENSE = RSENSE x ILOAD = 0.01 x 1 A = 0.01 V (35) With the gain of 20 for the LMP8601, the result is an output of 0.2 V. Or in other words, VOUT = 0.2 V/A. The result is the same for the LMP8601-Q1. For the LMP8602 and LMP8602-Q1 with a gain of 50, the output is 0.5 V/A. For the LMP8603 and LMP8603-Q1 with a gain of 100, the output is 1 V/A. 28 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 www.ti.com SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 Typical Applications (continued) 8.2.3 Battery Current Monitor Application This application example shows how the LMP860x and LMP860x-Q1 can be used to monitor the current flowing in and out of a battery pack. The fact that the LMP860x and LMP860x-Q1 can measure small voltages at a high offset voltage outside the parts own supply range makes this part a very good choice for such applications. If the load current of the battery is higher then the charging current, the output voltage of the LMP860x and LMP860xQ1 will be above the half offset voltage for a net current flowing out of the battery. When the charging current is higher then the load current the output will be below this half offset voltage. ICharge ILoad LOAD Charger VS OFFSET ICharge - ILoad 7 +IN 8 RSENSE 1 -IN + Level shift Output Buffer Gain = K2 Preamplifier Gain = 10 - 5 OUT Internal Resistor 100 k: + 3 4 - A1 A2 C1 NOTE: K2 = 2 for LMP8601, LMP8601-Q1; 5 for LMP8602, LMP8602-Q1; or 10 for LMP8603, LMP8603-Q1. Figure 63. Battery Current Monitor Application Copyright (c) 2008-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 29 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 www.ti.com Typical Applications (continued) 8.2.4 Advanced Battery Charger Application Figure 63 can be used to realize an advanced battery charger that has the capability to monitor the exact net current that flows in and out the battery as show in Figure 64. The output signal of the LMP860x and LMP860xQ1 is digitized with the ADC and used as an input for the charge controller. The Charge controller can be used to regulate the charger circuit to deliver exactly the current that is required by the load, avoiding overcharging a fully loaded battery. ILoad LOAD VS ICharge - ILoad OFFSET 7 +IN 8 ICharge RSENSE 1 + Level shift - -IN OUT A/D Internal Resistor 100 k: + 12V 5 Output Buffer Gain = K2 Preamplifier Gain = 10 - 3 4 A2 A1 C1 Charge Controler Charger NOTE: K2 = 2 for LMP8601, LMP8601-Q1; 5 for LMP8602, LMP8602-Q1; or 10 for LMP8603, LMP8603-Q1. Figure 64. Advanced Battery Charger Application 8.2.5 Current Loop Receiver Application Many industrial applications use 4-mA to 20-mA transmitters to send an analog value of a sensor to a central control room. The LMP860x and LMP860x-Q1 can be used as a current loop receiver as shown in Figure 65. VS OFFSET 7 +IN 8 4 mA to 20 mA CURRENT LOOP RSENSE 1 -IN + Level shift Output Buffer Gain = K2 Preamplifier Gain = 10 - 5 OUT Internal Resistor 100 k: 3 4 A2 A1 C1 NOTE: K2 = 2 for LMP8601, LMP8601-Q1; 5 for LMP8602, LMP8602-Q1; or 10 for LMP8603, LMP8603-Q1. Figure 65. Current-Loop Receiver Application 30 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 www.ti.com SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 9 Power Supply Recommendations In order to decouple the LMP860x and LMP860x-Q1 from AC noise on the power supply, place a 0.1-F bypass capacitor between the VS and GND pins. Place this capacitor as close as possible to the supply pins. In some cases, an additional 10-F bypass capacitor may further reduce the supply noise. 10 Layout 10.1 Layout Guidelines The traces leading to and from the sense resistor can be significant error sources. With small value sense resistors (< 100 m), any trace resistance shared with the load current can cause significant errors. The amplifier inputs should be directly connected to the sense resistor pads using Kelvin or 4-wire connection techniques. The traces should be one continuous piece of copper from the sense resistor pad to the amplifier input pin pad, and ideally on the same copper layer with minimal vias or connectors. This can be important around the sense resistor if it is generating any significant heat gradients. To minimize noise pickup and thermal errors, the input traces should be treated as a differential signal pair and routed tightly together with a direct path to the input pins. The input traces should be run away from noise sources, such as digital lines, switching supplies or motor drive lines. Remember that these traces can contain high voltage, and should have the appropriate trace routing clearances. Since the sense traces only carry the amplifier bias current, the connecting input traces can be thinner, signal level traces. Excessive Resistance in the trace should also be avoided. The paths of the traces should be identical, including connectors and vias, so that any errors will be equal and cancel. The sense resistor will heat up as the load increases. As the resistor heats up, the resistance generally goes up, which will cause a change in the readings. The sense resistor should have as much heatsinking as possible to remove this heat through the use of heatsinks or large copper areas coupled to the resistor pads. A reading drifting over time after turnon can usually be traced back to sense resistor heating. 10.2 Layout Example Figure 66. Kelvin or 4-wire Connection to the Sense Resistor Copyright (c) 2008-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 31 LMP8601, LMP8601-Q1 LMP8602, LMP8602-Q1 LMP8603, LMP8603-Q1 SNOSAR2H - SEPTEMBER 2008 - REVISED APRIL 2016 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support LMP8601 TINA SPICE Model, SNOM084 TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti 11.2 Related Links Table 1 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LMP8601 Click here Click here Click here Click here Click here LMP8601-Q1 Click here Click here Click here Click here Click here LMP8602 Click here Click here Click here Click here Click here LMP8602-Q1 Click here Click here Click here Click here Click here LMP8603 Click here Click here Click here Click here Click here LMP8603-Q1 Click here Click here Click here Click here Click here 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 32 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP8601 LMP8601-Q1 LMP8602 LMP8602-Q1 LMP8603 LMP8603-Q1 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LMP8601EDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 150 LMP86 01EDQ1 LMP8601MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP86 01MA LMP8601MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP86 01MA LMP8601QMA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP86 01QMA LMP8601QMAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP86 01QMA LMP8602MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP86 02MA LMP8602MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP86 02MA LMP8602MM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AN3A LMP8602MME/NOPB ACTIVE VSSOP DGK 8 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AN3A LMP8602MMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AN3A LMP8602QMA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP86 02QMA LMP8602QMAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP86 02QMA LMP8602QMM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AF7A LMP8602QMME/NOPB ACTIVE VSSOP DGK 8 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AF7A LMP8602QMMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AF7A LMP8603MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP86 03MA LMP8603MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP86 03MA LMP8603MM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AP3A Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 10-Dec-2020 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LMP8603MME/NOPB ACTIVE VSSOP DGK 8 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AP3A LMP8603MMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AP3A LMP8603QMA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP86 03QMA LMP8603QMAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP86 03QMA LMP8603QMM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AH7A LMP8603QMME/NOPB ACTIVE VSSOP DGK 8 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AH7A LMP8603QMMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AH7A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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OTHER QUALIFIED VERSIONS OF LMP8601, LMP8601-Q1, LMP8602, LMP8602-Q1, LMP8603, LMP8603-Q1 : * Catalog: LMP8601, LMP8602, LMP8603 * Automotive: LMP8601-Q1, LMP8602-Q1, LMP8603-Q1 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2020 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMP8601EDRQ1 SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMP8601MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMP8601QMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMP8602MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMP8602MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8602MME/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8602MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8602QMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMP8602QMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8602QMME/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8602QMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8603MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMP8603MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8603MME/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8603MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8603QMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMP8603QMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8603QMME/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2020 Device LMP8603QMMX/NOPB Package Package Pins Type Drawing VSSOP DGK 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3500 330.0 12.4 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.0 Q1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMP8601EDRQ1 SOIC D 8 2500 367.0 367.0 35.0 LMP8601MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMP8601QMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMP8602MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMP8602MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMP8602MME/NOPB VSSOP DGK 8 250 210.0 185.0 35.0 LMP8602MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LMP8602QMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMP8602QMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMP8602QMME/NOPB VSSOP DGK 8 250 210.0 185.0 35.0 LMP8602QMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LMP8603MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMP8603MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMP8603MME/NOPB VSSOP DGK 8 250 210.0 185.0 35.0 LMP8603MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LMP8603QMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2020 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMP8603QMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMP8603QMME/NOPB VSSOP DGK 8 250 210.0 185.0 35.0 LMP8603QMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 3 PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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