US1010 1A LOW DROPOUT POSITIVE ADJUSTABLE REGULATOR DESCRIPTION FEATURES Guaranteed < 1.3V Dropout at Full Load Current Fast Transient Response 1% Voltage Reference Initial Accuracy Built-in Thermal Shutdown Available in SOT-223, D-PAK , Power Flex and 8 pin SOIC Surface Mount Packages APPLICATIONS VGA & Sound Card Applications Low Voltage High Speed Termination Applications Standard 3.3V Chip-Set and Logic Applications PRELIMINARY DATASHEET The US1010 is a low dropout three terminal adjustable regulator with minimum of 1A output current capability. This product is specifically designed to provide well regulated supply for low voltage IC applications such as high speed bus termination and low current 3.3V logic supply. The US1010 is also well suited for other applications such as VGA and sound cards. The US 1010 is guaranteed to have <1.3V drop out at full load current making it ideal to provide well regulated outputs of 2.5V to 3.6V with 4.75V to 7V input supply. TYPICAL APPLICATION D1 5V C1 10uF Vin 3 US1010 Vout 2 2.85V / 1A R1 121 Adj 1 R2 154 1010app1-1.4 C2 22uF Typical Application of US1010 in a 5V to 2.85V SCSI termination regulator . PACKAGE ORDER INFORMATION Tj (C) 0 TO 150 Rev. 1.3 10/30/00 2 PIN PLASTIC TO252 (D) US1010CD 3 PIN PLASTIC SOT223 (Y) US1010CY 2 PIN PLASTIC POWER FLEX (P) US1010CP 8 PIN PLASTIC SOIC (S) US1010CS 2-1 US1010 ABSOLUTE MAXIMUM RATINGS Input Voltage (Vin) .................................................................. 7V Power Dissipation ............................................ Internally Limited Storage Temperature Range .............................. -65C TO 150C Operating Junction Temperature Range .................. 0C TO 150C PACKAGE INFORMATION 2 PIN PLASTIC TO252 ( D ) 3 PIN PLASTIC SOT223 ( Y ) FRONT VIEW Vin 3 Tab is Vout 4 1 Vin 2 Vout 1 Adj Adj JA=70C/W for 0.5" Sq pad 8 PIN PLASTIC SOIC (S) FRONT VIEW TOP VIEW 3 Tab is Vout 2 PIN PLASTIC PFLEX ( P ) JA=90C/W for 0.4" Sq pad TOP VIEW 3 Tab is Vout Vin Vin NC NC Adj 4 1 Adj JA=70C/W for 0.5" Sq pad 1 8 2 7 3 6 4 5 Vout Vout Vout Vout JA=55C/W for 1" Sq pad ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over, Cin=1uF, Cout=10uF, and Tj=0 to 150C.Typical values refer to Tj=25C. PARAMETER Reference Voltage Line Regulation Load Regulation (note 1) Dropout Voltage (note 2) Current Limit Minimum Load Current (note 3) Thermal Regulation Ripple Rejection Adjust Pin Current Adjust Pin Current Change Temperature Stability Long Term Stability RMS Output Noise SYM VREF VO IADJ TEST CONDITION MIN TYP Io=10mA,Tj=25C,(Vin-Vo)=1.5V 1.243 1.250 Io=10mA, (Vin-Vo)=1.5V 1.237 1.250 Io=10mA,1.3V<(Vin-Vo)<7V Vin=3.3V,Vadj=0,10mA<Io<1A Note 2 , Io=1A Vin=3.3V,dVo=100mV Vin=3.3V,Vadj=0V 30 mS PULSE,Vin-Vo=3V,Io=1A f=120HZ ,Co=25uF Tan Io=0.5A,Vin-Vo=3V Io=10mA,Vin-Vo=1.5V,Tj=25 Io=10mA,Vin-Vo=1.5V Io=10mA,Vin-Vo=1.5V,Tj=25 Vin=3.3V,Vadj=0V,Io=10mA Tj=125C,1000 Hrs Tj=25C 10hz<f<10khz Note 1 : Low duty cycle pulse testing with Kelvin connections are required in order to maintain accurate data. Note 2 : Drop-out voltage is defined as the minimum differential voltage between Vin and Vout required to maintain regulation at Vout. It is measured when the output voltage drops 1% below its nominal value. 2-2 MAX 1.257 1.263 0.2 0.4 UNITS V 1.1 1.3 5 10 V A mA 0.01 0.02 %/W 1.1 60 70 55 0.2 0.5 0.3 0.003 % % dB 120 5 1 uA uA % % %Vo Note 3 : Minimum load current is defined as the minimum current required at the output in order for the output voltage to maintain regulation. Typically the resistor dividers are selected such that it automatically maintains this current. Rev. 1.3 10/30/00 US1010 PIN DESCRIPTIONS PIN # 1 2 PIN SYMBOL Adj Vout 3 Vin PIN DESCRIPTION A resistor divider from this pin to the Vout pin and ground sets the output voltage. The output of the regulator. A minimum of 10uF capacitor must be connected from this pin to ground to insure stability. The input pin of the regulator. Typically a large storage capacitor is connected from this pin to ground to insure that the input voltage does not sag below the minimum drop out voltage during the load transient response. This pin must always be 1.3V higher than Vout in order for the device to regulate properly. BLOCK DIAGRAM Vin 3 2 Vout + 1.25V + CURRENT LIMIT THERMAL SHUTDOWN 1 Adj 1010blk1-1.0 Figure 1 - Simplified block diagram of the US1010 APPLICATION INFORMATION Introduction The US1010 adjustable Low Dropout (LDO) regulator is a 3 terminal device which can easily be programmed with the addition of two external resistors to any voltages within the range of 1.25 to 5.5 V.This regulator unlike the first generation of the 3T regulators such as LM117 that required 3V differential between the input and the regulated output,only needs 1.3V differential to maintain output regulation. This is a key requirement for today'slow voltage IC applications that typically need 3.3V supply and are often generated from the 5V supply. Other applications such as high speed memory termination need to switch the load current from zero to full load in tens of nanoseconds at the their pins ,which Rev. 1.3 10/30/00 translates to an approximately 300 to 500 nS current step at the regulator . In addition, the output voltage tolerances are sometimes tight and they include the transient response as part of the specification. The US1010 is specifically designed to meet the fast current transient needs as well as providing an accurate initial voltage , reducing the overall system cost with the need for fewer output capacitors. 2-3 US1010 Output Voltage Setting The US1010 can be programmed to any voltages in the range of 1.25V to 5.5V with the addition of R1 and R2 external resistors according to the following formula: R2 VOUT = VREF 1 + + IADJ x R2 R1 Where : VREF = 125 . V Typically IADJ = 50 uA Typically R1 & R2 as shown in figure 2 Vin Vin PARASITIC LINE RESISTANCE Vout Vout Rp US1010 Adj regulation is achieved when the bottom side of R2 is connected to the load and the top side of R1 resistor is connected directly to the case or the Vout pin of the regulator and not to the load. In fact , if R1 is connected to the load side, the effective resistance between the regulator and the load is gained up by the factor of (1+R2/ R1) ,or the effective resistance will be ,Rp(eff)=Rp*(1+R2/ R1).It is important to note that for high current applications, this can represent a significant percentage of the overall load regulation and one must keep the path from the regulator to the load as short as possible to minimize this effect. Vin Vref IAdj = 50uA Vin Vout US1010 R1 Adj R2 1010app2-1.0 R2 Figure 2 - Typical application of the US1010 for programming the output voltage. The US1010 keeps a constant 1.25V between the output pin and the adjust pin. By placing a resistor R1 across these two pins a constant current flows through R1, adding to the Iadj current and into the R2 resistor producing a voltage equal to the (1.25/R1)*R2 + Iadj*R2 which will be added to the 1.25V to set the output voltage. This is summarized in the above equation. Since the minimum load current requirement of the US1010 is 10 mA , R1 is typically selected to be 121 resistor so that it automatically satisfies the minimum current requirement. Notice that since Iadj is typically in the range of 50uA it only adds a small error to the output voltage and should only be considered when a very precise output voltage setting is required. For example, in a typical 3.3V application where R1=121 and R2=200 the error due to Iadj is only 0.3% of the nominal set point. Load Regulation RL R1 1010app3-1.0 Figure 3 - Schematic showing connection for best load regulation Stability The US1010 requires the use of an output capacitor as part of the frequency compensation in order to make the regulator stable. Typical designs for microprocessor applications use standard electrolytic capacitors with a typical ESR in the range of 50 to 100 m and an output capacitance of 500 to 1000uF. Fortunately as the capacitance increases, the ESR decreases resulting in a fixed RC time constant. The US1010 takes advantage of this phenomena in making the overall regulator loop stable.For most applications a minimum of 100uF aluminum electrolytic capacitor such as Sanyo MVGX series ,Panasonic FA series as well as the Nichicon PL series insures both stability and good transient response. Since the US1010 is only a 3 terminal device , it is not possible to provide true remote sensing of the output voltage at the load.Figure 3 shows that the best load 2-4 Rev. 1.3 10/30/00 US1010 Thermal Design The US1010 incorporates an internal thermal shutdown that protects the device when the junction temperature exceeds the maximum allowable junction temperature. Although this device can operate with junction temperatures in the range of 150C ,it is recommended that the selected heat sink be chosen such that during maximum continuous load operation the junction temperature is kept below this number. The example below for a SCSI terminator application shows the steps in selecting the proper regulator in a surface mount package .(See US1015 for non surface mount packages) Assuming the following specifications : VIN = 5 V VF = 0.5 V VO = 2.85V IOUTMAX = 0.8 A To set the output DC voltage, we need to select R1 and R2 : 3) Assuming R1=121 , 1% VOUT 2.85 R2 = - 1 x 121 = - 1 x 121 = 154.8 VREF 125 . Select R2=154 ,1% D1 5V Vin C1 10uF 1) Calculate the maximum power dissipation using : PD = IOUT x ( VIN - VF - VOUT ) PD = 0.8 x (5 - 0.5 - 2.85) = 132 . W 2) Calculate the maximum JA allowed for our example: C2 22uF US1010 Adj TA = 35 C Where ; VF is the forward voltage drop of the D1diode as shown in figure 4. The steps for selecting the right package with proper board area for heatsinking to keep the junction temperature below 135C is given as : 2.85V Vout R1 121 1% R2 154 1% 1010app4-1.3 Figure 4 - Final Schematic for half of the GTL+ termination regulator. Layout Consideration The output capacitors must be located as close to the Vout terminal of the device as possible. It is recommended to use a section of a layer of the PC board as a plane to connect the Vout pin to the output capacitors to prevent any high frequency oscillation that may result due to excessive trace inductance. TJ - TA PD 135 - 35 JAMAX = = 75.6 C / W 132 . JAMAX = 2) Select a package from the datasheet with lower JA than the one calculated in the previous step. Selecting TO252 (D Pak) with at least 0.5" square of 0.062" FR4 board using 1OZ copper has 70C/W which is lower than the calculated number. Rev. 1.3 10/30/00 2-5