Pentium-Processor - Intel

Embedded Pentium

Processor

Datasheet 19

2.0 Embedded Pentium® Processor Electrical

Specifications

This section describes the DC and AC specifications for the embedded Pentium processor.

2.1 3.3 V Power Supply

The processor has all VCC 3.3-V inputs. The CLK and PICCLK in puts can tolerate a 5-V input

signal. This allows the processor to use 5-V or 3.3-V clock drivers.

2.2 3.3 V Inputs and Outputs

The inputs and outputs of the processor are 3.3 V JEDEC standard levels. Both inputs and outputs

are also TTL-compatible, althoug h the inputs cannot tolerate voltage swings above the 3.3 V VIN

max. The CLK and PICCLK inputs of the processor are 5 V tolerant. This allows a 5-V clock

driver to drive the processor. All other pins are 3.3 V only.

For processor outputs, if the system support components use TTL-compatible inputs, the

components will interface to the processor without extra logic. This is because the processor drives

according to the 5-V TTL specification (but not beyond 3.3 V).

For processor inputs, the voltage must not exceed the 3.3 V VIH3 maximum specification. System

support components can consist of 3.3 V devices or open-collector devices. In an open-collector

configuration, the external resistor can be biased with the processor’s VCC. As the processor’s VCC

changes from 5 V to 3.3 V, so does this signal’s maximum drive.

2.3 Absolute Maximum Ratings

Functional operating con ditions are given in the AC and DC specification tables. Functional

operation at t he maximu ms i s not imp lied or guaran tee d. Extend ed o peratio n beyon d t he maxi mum

ratings may affect device reliability. Furthermor e, altho ugh the Pentium processor con tains

protective circuitry to resist damage fr om static electric discharge, always take preca utions to avoid

high static voltages or electric fields.

Warning: St ressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.

These are stress ratings only.

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20 Datasheet
2.4 DC Specifications
Tables 16–18 list the DC specifications that apply to the Pentium processor. The Pentium processor 
is a 3.3 V part intern ally. The CLK and PIC CLK inputs may be 3.3 V or 5 V inputs. Sin ce the 3.3 V 
(5 V-safe) input levels defined in Table 16 are the same as the 5 V TTL levels, the CLK and 
PICCLK inputs are compatible with existing 5 V clock drivers. 
Table 15.  Absolute Maximum Ratings 
Param eter Maximum Rating
Case temperature under bias −65° C to 110° C
Storage temperature −65° C to 150° C
3 V Supply voltage with respect to VSS −0.5 V to +4.6 V
3 V Only Buffer DC Input Voltage −0.5 V to VCC + 0.5; not to exceed VCC3 max1
5 V Safe Buffer DC Input Voltage −0.5 V to 6.5 V2,3
NOTES:
1. Applies to all Pentium® processor inputs except CLK and PICCLK.
2. Applies to CLK and PICCLK.
3. See overshoot/undershoot transient specification.
Table 16.  3.3 V DC Specifications
TCASE = 0 to 70° C; 3.135 V < VCC < 3.6 V for 100 and 133 MHz devices
TCASE = 0 to 70° C; 3.4 V < VCC < 3.6 V for 166 MHz (VRE device)
Symbol Parameter Min Max Unit Notes
VIL3 Input Low Voltage –0.3 0.8 V TTL Level, Note 1
VIH3 Input High Voltage 2.0 VCC+0.3 V TTL Level, Note 1
VOL3 Output Low Voltage 0.4 V TTL Level, 
Note 2, Note 1
VOH3 Output High Voltage 2.4 V TTL Level,
Note 3, Note 1
ICC3 Power Supply Current 4250
3400
3250
mA
mA
mA
166 MHz, Note 4
133 MHz, Note 4
100 MHz, Note 4
NOTES:
1. 3.3 V TTL levels apply to all signals except CLK and PICCLK.
2. Parameter measured at 4 mA.
3. Parameter measured at 3 mA.
4. This value should be used for power supply design. It was determined using a worst-case instruction mix 
and VCC = 3.6 V. Power supply transient response and decoupling capacitors must be sufficient to handle 
the instantaneous current changes occurring during transitions from stop clock to full active modes. For 
more information, refer to “Decoupling Recommendations” on page 22.
Table 17.  3.3 V (5 V-Safe) DC Specifications
Symbol Parameter Min Max Unit Notes
VIL5 Input Low Voltage –0.3 0.8 V TTL Level†
VIH5 Input High Voltage 2.0 5.55 V TTL Level†
†Applies to CLK and PICCLK only.

Embedded Pentium

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Datasheet 21

2.5 A C Specifications

The AC specifications of the Pentium processor consist of setup times, hold times, and valid delays

at 0 pF.

2.5.1 Private Bus

When two Pentium processor are operating in dual processor mode, a “private bus” exists to

arbitrate for the processor bu s and maintain local cache coher ency. The private bus consists of two

pinout changes:

1. Five pins are added: PBREQ#, PBGNT#, PHIT#, PHITM#, D/P#.

2. Ten output pins become I/O pins: ADS#, D/C#, W/R#, M/IO#, CACHE#, LOCK#, HIT#,

HITM#, HLDA, SCYC.

The new pins are given AC specifications of valid delays at 0 pF, setup times, and hold times.

Simulate with these parameters and their respective I/O buffer models to guarantee that proper

timings are met.

The AC specification gives input setup and hold times for the ten signals that become I/O pins.

These setup and hold times must only be met when a dual processor is present in the system.

2.5.2 Power and Ground

For clean on-chip power distribution, the Pentium processor has 53 VCC (power) and 53 VSS

(ground) inputs. Power and ground connections must be made to all external VCC and VSS pins of

the processor. On the circuit board all VCC pins must be connected to a VCC plane. All VSS pins

must be connected to a VSS plane.

Table 18. Input and Output Characteristics

Symbol Parameter Min Max Unit Notes

CIN Input Capacitance 15 pF Guaranteed by design.

COOutput Capacitance 20 pF Guaranteed by design.

CI/O I/O Capacitance 25 pF Guaranteed by design.

CCLK CLK Input Capacitance 15 pF Guaranteed by design.

CTIN Test Input Capacitance 15 pF Guaranteed by design.

CTOUT Test Output Capacitance 20 pF Guaranteed by design.

CTCK Test Clock Capacitance 15 pF Guaranteed by design.

ILI Input Leakage Current 0 < VIN < VCC3, Th i s

parameter is for input

without pullup or pulldown.

ILO Output Leakage Current 0 < VIN < VCC3, Th i s

parameter is for input

without pullup or pulldown.

IIH Input Leakage Current 200 VIN = 2.4 V, This parameter

is for input with pulldown.

IIL Input Leakage Current –400 VIN = 0.4 V, This parameter

is for input with pullup.

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22 Datasheet

2.5.3 Decoupling Recommendations

Liberal decoupling capacitance should be placed near the processor. Transient power surges can

occur when the processor is driving its address and data buses at high frequencies. This is most

common when d ri ving large capacitive loads.

Low inductance capacitors and interconnects are recommended for best high frequency electrical

performance. Inductance can be reduced by minimizing the length of the circuit board traces

between the processor and the decoupling capacitors.

These capacitors should be evenly distributed around each component on the 3.3 V plane.

Capacitor values should b e cho sen to ensure that they eliminate bo th lo w and h igh freq uency no ise

components.

For the Pentium processor , the p ower consumption can transition fro m a low power level to a much

higher lev el (or high- to -low power ) very rapidl y. A typical example is when ente ring or exi ting the

Stop Grant state. Other examples are when executing a HALT instruction (cau sing the processor to

enter the Auto HALT Powerdown state) or when transitioning from HALT to the Normal state. All

these examples may cause abrupt changes in the power being co nsumed by the processor. Note that

the Auto HALT Powerdown feature is always enabled even when other power management

features are not implemented.

Bulk storage capacitors with a low ESR (Ef fective Series Resistance) in the 10 to 1 00 µF ran ge are

required to maintain a regulated supply voltage during the interval between the time the current

load changes and the point at which the regulated power supply outpu t reacts to the change in load .

In order to reduce the ESR, it may be necessary to place several bulk storage capacitors in parallel.

These capacitors should be placed near the processor (on the 3.3 V plane) to ensure that the supply

voltage stays within specified limits during changes in the supply current during operation.

2.5.4 Connection Specifications

All NC and INC pins must remain unconnected. For reliable operation, always connect unused

inputs to an appropriate signal level. Unused active low inputs should be connected to VCC.

Unused active high inputs should be connected to ground.

2.5.5 AC Timing Tables

The AC specifications given in Table 19 and Table 20 consist of output delays, input setup

requirements and input hold requirements for a 66-MHz external bus. All AC specifications (with

the exception of those for the TAP signals and APIC signals) are relative to the rising edge of the

CLK input.

All timings are referenced to 1.5 V for both “0” and “1” logic levels unless otherwise specified.

Within the sampling window, a synchronous input must be stable for correct processor operation.

Each valid delay is specified for a 0 pF load. The system designer should use I/O buffer models to

account for signal flight time delays.

The following applies to all standard TTL signals used with the Pentium processor family:

•TTL input test waveforms are assumed to be 0 to 3 V transitions with 1 V/ns rise and fall

times.

•0.3 V/ns ≤ input rise/fall time ≤ 5 V/ns.

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Datasheet 23
Table 19.  AC Specifications
TCASE = 0 to 70° C; 3.135 V < VCC < 3.6 V for 100 and 133 MHz devices, CL = 0 pF
TCASE = 0 to 70° C; 3.4 V < VCC < 3.6 V for 166 MHz (VRE device), CL = 0 pF
Symbol Parameter Min Max Unit Figure Notes
Frequency 33.33 66.6 MHz
t1a CLK Period 15.0 30.0 ns 5
t1b CLK Period Stability ps Adjacent Clocks, 
Notes 1, 21
t2CLK High Time 4.0 ns 5 2 V, Note 1
t3CLK Low Time 4.0 ns 5 0.8 V, Note 1
t4CLK Fall T ime 0.15 1.5 ns 6 2.0 V–0.8 V,
Note 1
t5CLK Rise Time 0.15 1.5 ns 5 0.8 V–2.0 V,
Note 1
t6a PWT, PCD, CACHE# Valid Delay 1.0 7.0 ns 6
t6b AP Valid Delay 1.0 8.5 ns 6
t6c BE7#–BE0#, LOCK# Valid Delay 0.9 7.0 ns 6
t6d ADS# Valid Delay 0.8 6.0 ns 6
t6e ADSC#, D/C#, W/R#, SCYC, Valid Delay 0.8 7.0 ns 6
t6f M/IO# Valid Delay 0.8 5.9 ns 6
t6g A16–A3 Valid Delay 0.5 6.3 ns 6
t6h A31–A17 Valid Delay 0.6 6.3 ns 6
t7ADS#, ADSC#, AP, A31–A3, PWT, PCD, 
BE7#–BE0#, M/IO#, D/C#, W/R#, 
CACHE#, SCYC, LOCK# Float Delay 10.0 ns 7 1
t8a APCHK#, IERR#, FERR# Va lid Delay 1.0 8.3 ns 6 3
t8b PCHK# Valid Delay 1.0 7.0 ns 6 3
t9a BREQ Valid Delay 1.0 8.0 ns 6 3
t9b SMIACT# Valid Delay 1.0 7.3 ns 6 3
t9c HLDA Valid Delay 1.0 6.8 ns 6
t10a HIT# Valid Delay 1.0 6.8 ns 6
t10b HITM# Valid Delay 0.7 6.0 ns 6
t11a PM1–PM0, BP3–BP0 Valid Delay 1.0 10.0 ns 6
t11b PRDY Valid Delay 1.0 8.0 ns 6
t12 D63–D0, DP7–DP0 Write Data Valid Delay 1.3 7.5 ns 6
t13 D63–D0, DP3–DP0 Write Data Float Delay 10.0 ns 7 1
t14 A31–A5 Setup Time 6.0 ns 8 22
t15 A31–A5 Hold Tim e 1.0 ns 8
t16a INV, AP Setup Time 5.0 ns 8
t16b EADS# Setup Time 5.0 ns 8
t17 EADS#, INV, AP Hold Time 1.0 ns 8
t18a KEN# Setup Time 5.0   ns 8
NOTE: See Table 21 for notes.

Embedded Pentium
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24 Datasheet
t18b NA#, WB/WT# Setup Time 4.5 ns 8
t19 KEN#, WB/WT#, NA# Hold Time 1.0 ns 8
t20 BRDY#, BRDYC# Setup Time 5.0 ns 8
t21 BRDY#, BRDYC# Hold Time 1.0 ns 8
t22 AHOLD, BOFF# Setup Time 5.5 ns 8
t23 AHOLD, BOFF# Hold Time 1.0 ns 8
t24a BUSCHK#, EWBE#, HOLD Setup Time 5.0 ns 8
t24b PEN# Setup Time 4.8 ns 8
t25a BUSCHK#, EWBE#, PEN# Hold Time 1.0 ns 8
t25b HOLD Hold Time 1.5 ns 8
t26 A20M#, INTR, STPCLK# Setup Time 5.0 ns 8 9, 12
t27 A20M#, INTR, STPCLK# Hold Time 1.0 ns 8 10
t28 INIT, FLUSH#, NMI, SMI#, IGNNE# Setup 
Time 5.0 ns 8 9, 12, 13
t29 INIT, FLUSH#, NMI, SMI#, IGNNE# Hold 
Time 1.0 ns 8 10
t30 INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse 
Width, Async 2.0 CLKs 11, 13
t31 R/S# Setup Time 5.0 ns 8 9, 12, 13
t32 R/S# Hold Time 1.0 ns 8 10
t33 R/S# Pulse Width, Async. 2.0 CLKs 11, 13
t34 D63–D0, DP7–DP0 Read Data Setup Time 2.8 ns 8
t35 D63–D0, DP7–DP0 Read Data Hold Tim e 1.5 ns 8
t36 RESET Setup Time 5.0 ns 9 8, 9, 12
t37 RESET Hold Time 1.0 ns 9 8, 10
t38 RESET Pulse Width, VCC & CLK Stable 15.0 CLKs 9 8, 13
t39 RESET Active After VCC & CLK Stable 1.0 ms 9 Power up
t40 Reset Configuration Signals (INIT, 
FLUSH#, FRCMC#) Setup Time 5.0 ns 9 9, 12, 13
t41 Reset Configuration Signals (INIT, 
FLUSH#, FRCMC#) Hold Time 1.0 ns 9 10
t42a Reset Configuration Signals (INIT, 
FLUSH#, FRCMC#) Setup Time, Async. 2.0 CLKs 9 To RESET falling 
edge, Note 12
t42b Reset Configuration Signals (INIT, 
FLUSH#, FRCMC#, BRDYC#, BUSCHK#) 
Hold Time, Asy nc. 2.0 CLKs 9 To RESET falling 
edge, Note 23
t42d Reset Configuration Signal BRDYC# Hold 
Time, RESET driven synchronously 1.0 ns To RESET falling 
edge, 1, 23
t43a BF, CPUTYP Setup Time 1.0 ms 9 To RESET falling 
edge, Note 18
Table 19.  AC Specifications
TCASE = 0 to 70° C; 3.135 V < VCC < 3.6 V for 100 and 133 MHz devices, CL = 0 pF
TCASE = 0 to 70° C; 3.4 V < VCC < 3.6 V for 166 MHz (VRE device), CL = 0 pF
Symbol Parameter Min Max Unit Figure Notes
NOTE: See Table 21 for notes.

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Datasheet 25
t43b BF, CPUTYP Hold Tim e 2.0 CLKs 9 To RESET falling 
edge, Note 18
t43c APICEN, BE4# Setup Time 2.0 CLKs 9 To RESET falling 
edge
t43d APICEN, BE4# Hold Time 2.0 CLKs 9 To RES ET falling 
edge
t44 TCK Frequency 16.0 MHz
t45 TCK Period 62.5 ns 5
t46 TCK High Time 25.0 ns 5 2 V, Note 1
t47 TCK Low Time 25.0 ns 5 0.8 V, Note 1
t48 TCK Fall Time 5.0 ns 5 2.0 V–0.8 V,
Notes 1,5,6
t49 TCK Rise Time 5.0 ns 5 0.8 V–2.0 V,
Notes 1,5,6
t50 TRST# Pulse Width 40.0 ns 11 Asynchronous, 
Note 1
t51 TDI, TMS Setup Time 5.0 ns 10 4
t52 TDI, TMS Hold Time 13.0 ns 10 4
t53 TDO Valid Delay 3.0 20.0 ns 10 5
t54 TDO Float Delay 25.0 ns 10 1, 5
t55 All Non-Test Outputs Valid Delay 3.0 20.0 ns 10 2, 5, 7
t56 All Non-Test Outputs Float Delay 25.0 ns 10 1, 2, 5, 7
t57 All Non-Tes t Inputs Setup Time 5.0 ns 10 2, 4, 7
t58 All Non-Test Inputs Hold Time 13.0 ns 10 2, 4, 7
APIC AC Specifications
t60a PICCLK Frequency 2.0 16.66 MHz
t60b PICCLK Period 60.0 500.0 ns 5
t60c PICCLK High Time 15.0 ns 5
t60d PICCLK Low Time 15.0 ns 5
t60e PICCLK Rise Time 0.15 2.5 ns 5
t60f PICCLK Fall Time 0.15 2.5 ns 5
t60g PICD1–PICD0 Setup Time 3.0 ns 8 To PICCLK
t60h PICD1–PICD0 Hold Time 2.5 ns 8 To PICCLK
t60i PICD1–PICD0 Valid Delay (LtoH) 4.0 38.0 ns 6 From PICCLK, 
Notes 24, 25
t60j PICD1–PICD0 Valid Delay (HtoL) 4.0 22.0 ns 6 From PICCLK, 
Notes 24, 25
t61 PICCLK Setup Time 5.0 ns To CLK, Note 26
t62 PICCLK Hold Time 2.0 ns To CLK, Note 26
t63 PICCLK Ratio (CLK/PICCLK) 4 27
Table 19.  AC Specifications
TCASE = 0 to 70° C; 3.135 V < VCC < 3.6 V for 100 and 133 MHz devices, CL = 0 pF
TCASE = 0 to 70° C; 3.4 V < VCC < 3.6 V for 166 MHz (VRE device), CL = 0 pF
Symbol Parameter Min Max Unit Figure Notes
NOTE: See Table 21 for notes.

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26 Datasheet
Table 20.  Dual Processor Mode AC Specifications
TCASE = 0 to 70° C; 3.135 V < VCC < 3.6 V for 100 and 133 MHz devices, CL = 0 pF
TCASE = 0 to 70° C; 3.4 V < VCC < 3.6 V for 166 MHz (VRE device), CL = 0 pF
Symbol Parameter Min Max Unit Figure Notes
t80a PBREQ#, PBGNT#, PHIT# Flight Time 0 2.0 ns 20, 25
t80b PHITM# Flight Time 0 1.8 ns 20, 25
t83a A31–A5 Setup Time 3.7 ns 8 14, 17, 22
t83b D/C#, W/R#, CACHE#, LOCK#, SCYC 
Setup Time
t83c ADS#, M/IO# Setup Time  5.8 ns 8 1 4, 17
t83d HIT#, HITM# Setup Time 6.0 ns 8 14, 17
t83e HLDA Setup Time 6.0 ns 8 14, 17
t84 ADS#, D/C#, W/R#, M/IO#, CACHE#, 
LOCK#, A31–A5, HLDA, HIT#, HITM#, 
SCYC Hold Time 1.0 ns 8 14, 17
t85 DPEN# Valid Time 10.0 CLKs 14, 15, 19
t86 DPEN# Hold Time 2.0 CLKs 14, 16, 19
t87 APIC ID (BE3#–BE0#) Setup Time 2.0 CLKs 9 To RESET falling 
edge, Note 19
t88 APIC ID (BE3#–BE0#) Hold Time 2.0 CLK s 9 From RESET 
falling edge, 
Note 19
t89 D/P# Valid Delay 1.0 8.0 ns 6 Primary 
Processor Only
NOTE: See Table 21 for table notes.

Embedded Pentium

Processor

Datasheet 27

Table 21. Notes for Tables 19 and 20

1. Not 100% tested. Guaranteed by design/characterization.

2. Non-test outputs and inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and

TMS). These timings correspond to the response of these signals due to boundary scan operations.

3. APCHK#, FERR#, HLDA, IERR#, LOCK#, and PCHK# are glitch-free outputs. Glitch-free signals

monotonically transition without false transitions.

4. Referenced to TCK rising edge.

5. Referenced to TCK falling edge.

6. 1 ns can be added to the maximum TCK rise and fall times for every 10 MHz of frequency below 33 MHz.

7. During probe mode operation, do not use the boundary scan timings (t 55-58).

8. FRCMC# should be tied to VCC (high) to ensure proper operation of the Pentium processor as a primary

processor.

9. Setup time is required to guarantee recognition on a specific clock. The Pentium processor must meet t his

specification for dual processor operation for the FLUSH# and RESET signals.

10.H old time is required to guarantee recognition on a specific clock. The Pentium processor must meet this

specification for dual processor operation for the FLUSH# and RESET signals.

11.To guarantee proper asynchronous recognition, the signal must have been deasserted (inactive) for a

minimum of two clocks before being returned active and must meet the minimum pulse width.

12.This input may be driven asynchronously. Howeve r, when operating two processors in dual processing

mode, FLUSH# and RESET must be asserted synchronously to both processors.

13.When driven asynchronous ly, RESET, NMI, FLUSH#, R/S#, INIT, and SMI# must be deasserted (inactive)

for a minimum of two clocks before being returned active.

14.Timings are valid only when dual processor is present.

15.Maximum time DPEN# is valid from rising edge of RESET.

16.Minimum time DPEN# is valid after falling edge of RESET.

17.The D/C#, M/IO#, W/R#, CACHE#, and A31–A5 signals are sampled only on the CLK during which ADS#

is active.

18.BF and CPUTYP should be strapped to VCC or VSS.

19.R ESE T is synchronous in dual processing mode and functional redundancy checking mode. All signals

that have a setup or hold time with respect to a falling or rising edge of RESET in UP mode should be

measured with respect to the first processor clock edge in which RESET is sampled either active or

inactive in dual processing and functional redundancy checking modes.

20.The PHIT# and PHITM# signals operate at the core frequency.

21.These signals are measured on the rising edge of adjacent CLKs at 1.5 V. To ensure a 1:1 relationship

between the amplitude of the input jitter and the internal and external clocks, the jitter frequency spectrum

should not have any power spectrum peaking between 500 KHz and 1/3 of the CLK operating frequency.

The amount of jitter present must be accounted for as a component of CLK skew between devices.

22.In dual processing mode, timing t14 is replaced by t83a. Timing t14 is required for external snooping (e.g.,

address setup to the CLK in which EADS# is sampled active) in both uniprocessor and dual processor

modes.

23.BRDYC# and BUSCHK# are used as reset configuration signals to select buffer size.

24.This assumes an external pullup resistor to VCC and a lumped capacitive load. The pullup resi stor must be

between 300 Ohms and 1 KOhms, the capacitance must be between 20 pF and 120 pF, and the RC

product must be between 3 ns and 36 ns. VOL for PICD1–PICD0 is 0.55 V.

25.This is a flight time specification that includes both flight time and clock skew. The flight time is the time

from when the unloaded driver crosses 1.5 V (50% of min. VCC), to when the receiver crosses the 1.5 V

level (50% of mi n. VCC). See Figure 12.

26.This is for the lock-step operation of the component only. This guarantees that APIC interrupts will be

recognized on specific clocks to support two processors running in a lock step fashion, including FRC

mode. FRC on the APIC pins is not supported but mismatches on these pins will result in a mismatch on

other pins of the CPU.

27.The CLK to PICCLK ratio for lock-step operation must be an integer and t he ratio (CLK/PICCLK) cannot be

smaller than 4:1.

Embedded Pentium

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28 Datasheet

Figure 5. Clock Waveform

Figure 6. Valid Delay Timings

Figure 7. Float Delay Timings

Signal VALID

1.5V

T max.

xT min.

Tx= t6, t8, t9, t10, t11, t12, t60i, t80a, t89

Embedded Pentium

Processor

Datasheet 29

Figure 8. Setup and Hold Ti mings

Figure 9. Reset and Configuration Timings

Embedded Pentium

Process or

30 Datasheet

Figure 10. Test Timings

Figure 11. Test Reset Timings

Embedded Pentium

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Datasheet 31

Figure 12. 50% VCC Measurement of Flight Time

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32 Datasheet