CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CMX867
Low Power
V.22 Modem
2004 Consumer Microcircuits Limited
D/867/5 March 2004 Provisional Issue
Features Applications
V.22, Bell 212A 1200/1200 or 600/600 bps DPSK Telephone Telemetry Systems
V.23 1200/75, 1200/1200, 75, 1200 bps FSK Remote Utility Meter Reading
Bell 202 1200/150, 1200/1200, 150, 1200 bps FSK Security Systems
V.21 or Bell 103 300/300 bps FSK Industrial Control Systems
DTMF/Tones Transmit and Receive Electronic Cash Terminals
‘Powersave’ Standby Mode Pay-Phones
Software and Hardware Compatible with CMX868 Cable TV Set-Top Boxes
1.1 Brief Description
The CMX867 is a multi-standard modem for use in telephone based information and telemetry systems.
Control of the device is via a simple high speed serial bus, compatible with most types of µC serial
interface. The data transmitted and received by the modem is also transferred over the same serial bus.
On-chip programmable Tx and Rx USARTs meeting the requirements of V.14 are provided for use with
asynchronous data and allow unformatted synchronous data to be received or transmitted as 8-bit words.
It can transmit and detect standard DTMF and modem calling and answer signals or user-specific
programmed single or dual tone signals. A general purpose Call Progress signal detector is also included.
Flexible line driver and receive hybrid circuits are integrated on chip, requiring only passive external
components to build a 2 or 4-wire line interface.
The device also features a Hook Switch Relay Drive output and a Ring Detector circuit which continues
to function when the device is in the Powersave mode, providing an interrupt which can be used to wake
up the host µController when line voltage reversal or ringing is detected.
The CMX867 operates from a single 2.7 to 5.5V supply over a temperature range of -40°C to +85°C and
is available in 24-pin TSSOP, SOIC and DIP packages.
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CONTENTS
Section Page
1.1 Brief Description..................................................................................1
1.2 Block Diagram .....................................................................................3
1.3 Signal List............................................................................................4
1.4 External Components..........................................................................5
1.4.1 Ring Detector Interface...........................................................6
1.4.2 Line Interface...........................................................................7
1.5 General Description...........................................................................10
1.5.1 Tx USART..............................................................................11
1.5.2 FSK and DPSK Modulators ..................................................12
1.5.3 Tx Filter and Equaliser..........................................................13
1.5.4 DTMF/Tone Generator..........................................................13
1.5.5 Tx Level Control and Output Buffer.....................................13
1.5.6 Rx DTMF/Tones Detectors....................................................14
1.5.7 Rx Modem Filterering and Demodulation............................15
1.5.8 Rx Modem Pattern Detectors and Descrambler ..................16
1.5.9 Rx Data Register and USART ...............................................16
1.5.10 C-BUS Interface.....................................................................18
1.5.10.1 General Reset Command..............................18
1.5.10.2 General Control Register..............................20
1.5.10.3 Transmit Mode Register ...............................22
1.5.10.4 Receive Mode Register.................................26
1.5.10.5 Tx Data Register............................................28
1.5.10.6 Rx Data Register ...........................................28
1.5.10.7 Status Register..............................................29
1.5.10.8 Programming Register..................................32
1.6 Application Notes..............................................................................36
1.6.1 V.22 Calling Modem Application..........................................36
1.6.2 V.22 Answering Modem Application....................................37
1.6.3 Reference Diagrams..............................................................37
1.7 Performance Specification................................................................38
1.7.1 Electrical Performance..........................................................38
1.7.1.1 Absolute Maximum Ratings.....................................38
1.7.1.2 Operating Limits.......................................................38
1.7.1.3 Operating Characteristics........................................39
1.7.2 Packaging..............................................................................46
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1.2 Block Diagram
Figure 1 Block Diagram
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1.3 Signal List
CMX867
D2/E2/P4 Signal Description
Pin No. Name Type
1 XTALN O/P The output of the on-chip Xtal oscillator inverter.
2 XTAL/CLOCK I/P The input to the oscillator inverter from the Xtal
circuit or external clock source.
3 RDRVN O/P Relay drive output, low resistance pull down to
VSS when active and medium resistance pull up
to VDD when inactive.
4, 8, 12, 17, 21 VSS Power The negative supply rail (ground).
5 RD I/P Schmitt trigger input to the Ring signal detector.
Connect to VSS if Ring Detector not used.
6 RT BI Open drain output and Schmitt trigger input
forming part of the Ring signal detector.
Connect to VDD if Ring Detector not used.
7, 16, 24 VDD Power The positive supply rail. Levels and thresholds
within the device are proportional to this
voltage.
9 RXAFB O/P The output of the Rx Input Amplifier.
10 RXAN I/P The inverting input to the Rx Input Amplifier
11 RXA I/P The non-inverting input to the Rx Input Amplifier
13 VBIAS O/P Internally generated bias voltage of
approximately VDD /2, except when the device
is in ‘Powersave’ mode when VBIAS will
discharge to VSS. Should be decoupled to VSS
by a capacitor mounted close to the device pins.
14 TXAN O/P The inverted output of the Tx Output Buffer.
15 TXA O/P The non-inverted output of the Tx Output Buffer.
18 CSN I/P The C-BUS chip select input from the µC.
19 COMMAND
DATA I/P The C-BUS serial data input from the µC.
20 SERIAL
CLOCK I/P The C-BUS serial clock input from the µC.
22 REPLY DATA T/S A 3-state C-BUS serial data output to the µC.
This output is high impedance when not sending
data to the µC.
23 IRQN O/P A ‘wire-ORable’ output for connection to a µC
Interrupt Request input. This output is pulled
down to VSS when active and is high impedance
when inactive. An external pullup resistor is
required ie R1 of Figure 2.
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Notes:
I/P = Input
O/P = Output
BI = Bidirectional
T/S = 3-state Output
NC = No Connection
1.4 External Components
R1 100k C1, C2 22pF
X1 11.0592MHz C3, C4 100nF
or 12.288MHz C5 10uF
Resistors ±5%, capacitors ±20% unless otherwise stated.
Figure 2 Recommended External Components for Typical Application
This device is capable of detecting and decoding small amplitude signals. To achieve this VDD and
VBIAS should be decoupled and the receive path protected from extraneous in-band signals. It is
recommended that the printed circuit board is laid out with a VSS ground plane in the CMX867 area to
provide a low impedance connection between the VSS pins and the VDD and VBIAS decoupling capacitors.
The V
SS connections to the Xtal oscillator capacitors C1 and C2 should also be low impedance and
preferably be part of the VSS ground plane to ensure reliable start up of the oscillator.
For best results, an Xtal oscillator design should drive the clock inverter input with signal levels of at least
40% of VDD peak-to-peak. Tuning-fork Xtals generally cannot meet this requirement. To obtain Xtal
oscillator design assistance, please consult your Xtal manufacturer.
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1.4.1 Ring Detector Interface
Figure 3 shows how the CMX867 may be used to detect the large amplitude Ringing signal voltage
present on the 2-wire line at the start of an incoming telephone call.
The ring signal is usually applied at the subscriber's exchange as an ac voltage inserted in series with
one of the telephone wires and will pass through either C20 and R20 or C21 and R21 to appear at the top
end of R22 (point X in Figure 3) in a rectified and attenuated form.
The signal at point X is further attenuated by the potential divider formed by R22 and R23 before being
applied to the CMX867 RD input. If the amplitude of the signal appearing at RD is greater than the input
threshold (Vthi) of Schmitt trigger 'A' then the N transistor connected to RT will be turned on, pulling the
voltage at RT to VSS by discharging the external capacitor C22. The output of the Schmitt trigger 'B' will
then go high, setting bit 14 (Ring Detect) of the Status Register.
The minimum amplitude ringing signal that is certain to be detected is:
( 0.7 + Vthi x [R20 + R22 + R23] / R23 ) x 0.707 Vrms
where Vthi is the high-going threshold voltage of the Schmitt trigger A (see section 1.7.1).
With R20-22 all 470k as Figure 3, then setting R23 to 68k will guarantee detection of ringing signals
of 40Vrms and above for VDD over the range 3 to 5V.
R20, 21, 22 470k C20, 21 0.1µF
R23 See text C22 0.33µF
R24 470k D1-4 1N4004
Resistors ±5%, capacitors ±20%
Figure 3 Ring Signal Detector Interface Circuit
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If the time constant of R24 and C22 is large enough then the voltage on RT will remain below the
threshold of the 'B' Schmitt trigger for the duration of a ring cycle.
The time for the voltage on RT to charge from VSS towards VDD can be derived from the formula
VRT = VDD x [1 - exp(-t/(R24 x C22)) ]
As the Schmitt trigger high-going input threshold voltage (Vthi) has a minimum value of 0.56 x VDD, then
the Schmitt trigger B output will remain high for a time of at least 0.821 x R24 x C22 following a pulse at
RD.
The values of R24 and C22 given in Figure 3 (470k and 0.33µF) give a minimum RT charge time of
100 msec, which is adequate for ring frequencies of 10Hz or above.
Note that the circuit will also respond to a telephone line voltage reversal. If necessary the µC can
distinguish between a Ring signal and a line voltage reversal by measuring the time that bit 14 of the
Status Register (Ring Detect) is high.
If the Ring detect function is not used then pin RD should be connected to VSS and RT to VDD.
1.4.2 Line Interface
A line interface circuit is needed to provide dc isolation and to terminate the line. Typical interface circuits
are described below.
2-Wire Line Interface
Figure 4a shows a simplified interface for use with a 600 2-wire line. The complex line termination is
provided by R13 and C10, high frequency noise is attenuated by C10 and C11, while R11 and R12 set
the receive signal level into the modem. For clarity the 2-wire line protection circuits have not been
shown.
R11 See text C3 See Figure 2
R12 100k C10 33nF
R13 600 C11 100pF
Resistors ±5%, capacitors ±20%
Figure 4a 2-Wire Line Interface Circuit
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Resistor R13 is used to match the AC impedance of the interface to the line. With an ideal transformer
this resistor would be equal to the desired impedance (e.g. 600); however in practice with a real
transformer, R13 should be set such that the interface as a whole presents the desired impedance. Line
transformer manufacturers normally provide guidance in this regard.
The transmit line signal level is determined by the voltage swing between the TXA and TXAN pins, less
6dB due to the line termination, and less the loss in the line coupling transformer.
Allowing for 1dB loss in the transformer, then with the Tx Mode Register set for a Tx Level Control gain
of 0dB the nominal transmit line levels will be:
VDD = 3.0V VDD = 5.0V
QAM, DPSK and FSK Tx modes (no guard tone) -10dBm -5.5dBm
Single tone transmit mode -10dBm -5.5dBm
DTMF transmit mode -6 and -8 dBm -1.5 and -3.5 dBm
For a line impedance of 600, 0dBm = 775mVrms. See also section 1.7.1.3
In the receive direction, the signal detection thresholds within the CMX868 are proportional to VDD and
are affected by the Rx Gain Control gain setting in the Rx Mode Register. The signal level into the
CMX868 is affected by the line coupling transformer loss and the values of R11 and R12 of Figure 4a.
Assuming 1dB transformer loss, the Rx Gain Control programmed to 0dB and R12 = 100k, then for
correct operation (see section 1.7.1.3) the value of R11 should be equal to 500 / VDD k i.e. 160k at
3.0V, falling to 100k at 5.0V.
For best Rx performance it is recommended that the transformer coupling arrangement should provide at
least 7dB trans-hybrid loss. This is achieved by minimising the amount of the transmitted signal
presented to the receiver at RXAFB. A mis-match between the transformer impedance and R13 will
result in a proportion of the transmitted signal being fed to the receiver op-amp circuit via R11. The effect
of this can be significantly nulled by careful selection of the potential divider components R14 and R15 to
provide a cancellation signal at RXA. (Note: with an ideal transformer, R13 would be set equal to the line
impedance, and R14 would be set equal to R15.
Further details of line interfacing can be found in the EV8680 and DE8681 User Manuals, available from
the CML website.
As an example, the following component values are appropriate for use with the MIDCOM 82111 line
transformer:
R11 See text C10 33nF
R12 100k C11 100pF
R13 392 C12 0.1µF
R14 120k C13 47pF
R15 180k
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4-Wire Line Interface
Figure 4b shows a simplified interface for use with a 600 4-wire line. The line terminations are provided
by R10 and R13, the values of which are dependent on the choice of transformer: see notes above. High
frequency noise is attenuated by C11 while R11 and R12 set the receive signal level into the modem.
Transmit and receive line level settings and the value of R11 are as for the 2-wire circuit.
R10, 13 See text C3 See Figure 2
R11 See text C11 100pF
R12 100k C12 33nF
Resistors ±5%, capacitors ±20%
Figure 4b 4-Wire Line Interface Circuit
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1.5 General Description
The CMX867 transmit and receive operating modes are independently programmable.
The transmit mode can be set to any one of the following:
V.22 and Bell 212A modem. 1200 or 600 bps DPSK (Differential Phase Shift Keying).
V.21 modem. 300bps FSK (Frequency Shift Keying).
Bell 103 modem. 300bps FSK.
V.23 modem. 1200 or 75 bps FSK.
Bell 202 modem. 1200 or 150 bps FSK.
DTMF transmit.
Single tone transmit (from a range of modem calling, answer and other tone frequencies)
User programmed tone or tone pair transmit (programmable frequencies and levels)
Disabled.
The receive mode can be set to any one of the following:
V.22 and Bell 212A modem. 1200 or 600 bps DPSK.
V.21 modem. 300bps FSK.
Bell 103 modem. 300 bps FSK.
V.23 modem. 1200 or 75 bps FSK.
Bell 202 modem. 1200 or 150 bps FSK.
DTMF detect.
2100Hz and 2225Hz answer tone detect.
Call progress signal detect.
User programmed tone or tone pair detect.
Disabled.
The CMX867 may also be set into a Powersave mode which disables all circuitry except for the C-BUS
interface and the Ring Detector.
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1.5.1 Tx USART
A flexible Tx USART is provided for all modem modes, meeting the requirements of V.14 for DPSK
modems.
It can be programmed to transmit continuous patterns, Start-Stop characters or Synchronous Data.
In both Synchronous Data and Start-Stop modes the data to be transmitted is written by the µC into the
8-bit C-BUS Tx Data Register from which it is transferred to the Tx Data Buffer.
If Synchronous Data mode has been selected the 8 data bits in the Tx Data Buffer are transmitted
serially, b0 being sent first.
In Start-Stop mode a single Start bit is transmitted, followed by 5, 6, 7 or 8 data bits from the Tx Data
Buffer - b0 first - followed by an optional Parity bit then - normally - one or two Stop bits. The Start, Parity
and Stop bits are generated by the USART as determined by the Tx Mode Register settings and are not
taken from the Tx Data Register.
Figure 5a Tx USART
Every time the contents of the C-BUS Tx Data Register are transferred to the Tx Data Buffer the Tx Data
Ready flag bit of the Status Register is set to 1 to indicate that a new value should be loaded into the C-
BUS Tx Data Register. This flag bit is cleared to 0 when a new value is loaded into the Tx Data Register.
Figure 5b Tx USART Function (Start-Stop mode, 8 Data Bits + Parity)
If a new value is not loaded into the Tx Data Register in time for the next Tx Data Register to Tx Data
Buffer transfer then the Status Register Tx Data Underflow bit will be set to 1. In this event the contents
of the Tx Data Buffer will be re-transmitted if Synchronous Data mode has been selected, or if the Tx
modem is in Start-Stop mode then a continuous Stop signal (1) will be transmitted until a new value is
loaded into the Tx Data Register.
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In all modes the transmitted bit and baud rates are the nominal rates for the selected modem type, with
an accuracy determined by the XTAL frequency accuracy, however for DPSK modes V.14 requires that
Start-Stop characters can be transmitted at up to 1% overspeed (basic signalling rate range) or 2.3%
overspeed (extended signalling rate range) by deleting a Stop bit from no more than one out of every 8
(basic range) or 4 (extended range) consecutive transmitted characters.
To accommodate the V.14 requirement the Tx Data Register has been given two C-BUS addresses, $E3
and $E4. Data should normally be written to $E3.
In DPSK Start-Stop modes if data is written to $E4 then the programmed number of Stop bits will be
reduced by one for that character. In this way the µC can delete transmitted Stop bits as needed.
In FSK Start-Stop modes, data written to $E4 will be transmitted with a 12.5% reduction in the length of
the Stop bit at the end of that character.
In all Synchronous Data modes data written to $E4 will be treated as though it had been written to $E3.
The underspeed transmission requirement of V.14 is automatically met by the CMX867 as in Start-Stop
mode it automatically inserts extra Stop bit(s) if it has to wait for new data to be loaded into the C-BUS
Tx Data Register.
The optional V.22 compatible data scrambler can be programmed to invert the next input bit in the event
of 64 consecutive ones appearing at its input. It uses the generating polynomial:
1 + x-14 + x-17
1.5.2 FSK and DPSK Modulators
Serial data from the USART is fed via the optional scrambler to the FSK modulator if V.21, V.23, Bell
103 or Bell 202 mode has been selected or to the DPSK modulator for V.22 and Bell 212A modes.
The FSK modulator generates one of two frequencies according to the transmit mode and the value of
current transmit data bit.
The DPSK modulator generates a carrier of 1200Hz (Low Band, Calling modem) or 2400Hz (High Band,
Answering modem) which is modulated at 600 symbols/sec as described below:
600bps V.22 signals are transmitted as a +90° carrier phase change for a ‘0’ bit, +270° for ‘1’.
For V.22 and Bell 212A 1200bps DPSK the transmit data stream is divided into groups of two
consecutive bits (dibits) which are encoded as a carrier phase change:
Dibit
(left-hand bit is the
first of the pair)
Phase change
00 +90°
01 0°
11 +270°
10 +180°
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1.5.3 Tx Filter and Equaliser
The FSK or DPSK modulator output signal is fed through the Transmit Filter and Equaliser block which
limits the out-of-band signal energy to acceptable limits. In 600 and 1200 bps FSK and DPSK modes this
block includes a fixed compromise line equaliser which is automatically set for the particular modulation
type and frequency band being employed. This fixed compromise line equaliser may be enabled or
disabled by bit 10 of the General Control Register. The amount of Tx equalisation provided compensates
for one quarter of the relative amplitude and delay distortion of ETS Test Line 1 over the frequency band
used.
1.5.4 DTMF/Tone Generator
In DTMF/Tones mode this block generates DTMF signals or single or dual frequency tones. In DPSK
modem modes it is used to generate the optional 550 or 1800Hz guard tone.
1.5.5 Tx Level Control and Output Buffer
The outputs (if present) of the Transmit Filter and DTMF/Tone Generator are summed then passed
through the programmable Tx Level Control and Tx Output Buffer to the pins TXA and TXAN. The Tx
Output Buffer has symmetrical outputs to provide sufficient line voltage swing at low values of VDD and
to reduce harmonic distortion of the signal.
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1.5.6 Rx DTMF/Tones Detectors
In Rx Tones Detect mode the received signal, after passing through the Rx Gain Control block, is fed to
the DTMF / Tones / Call Progress / Answer Tone detector. The user may select any of four separate
detectors:
The DTMF detector detects standard DTMF signals. A valid DTMF signal will set bit 5 of the Status
Register to 1 for as long as the signal is detected.
The programmable tone pair detector includes two separate tone detectors (see Figure 11). The first
detector will set bit 6 of the Status Register for as long as a valid signal is detected, the second detector
sets bit 7, and bit 10 of the Status Register will be set when both tones are detected.
The Call Progress detector measures the amplitude of the signal at the output of a 275 - 665 Hz
bandpass filter and sets bit 10 of the Status Register to 1 when the signal level exceeds the
measurement threshold.
-60
-50
-40
-30
-20
-10
0
10
00.5 11.5 22.5 33.5 4
kHz
dB
Figure 6a Response of Call Progress Filter
The Answer Tone detector measures both amplitude and frequency of the received signal and sets bit 6
or bit 7 of the Status Register when a valid 2225Hz or 2100Hz signal is received.
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1.5.7 Rx Modem Filterering and Demodulation
When the receive part of the CMX867 is operating as a modem, the received signal is fed to a bandpass
filter to attenuate unwanted signals and to provide fixed compromise line equalisation for 600 and
1200bps FSK and DPSK modes. The characteristics of the bandpass filter and equaliser are determined
by the chosen receive modem type and frequency band. The line equaliser may be enabled or disabled
by bit 10 of the General Control Register and compensates for one quarter of the relative amplitude and
delay distortion of ETS Test Line 1.
The responses of these filters, including the line equaliser and the effect of external components used in
Figures 4a and 4b, are shown in Figures 6b-e:
-60
-50
-40
-30
-20
-10
0
10
00.5 11.5 22.5 33.5 4
kHz
dB
-60
-50
-40
-30
-20
-10
0
10
00.5 11.5 22.5 33.5 4
kHz
dB
Figure 6b DPSK Rx Filters Figure 6c V.21 Rx Filters
-60
-50
-40
-30
-20
-10
0
10
00.5 11.5 22.5 33.5 4
kHz
dB
-60
-50
-40
-30
-20
-10
0
10
00.5 11.5 22.5 33.5 4
kHz
dB
Figure 6d Bell 103 Rx Filters Figure 6e V.23/Bell 202 Rx Filters
The signal level at the output of the Receive Modem Filter and Equaliser is measured in the Modem
Energy Detector block, compared to a threshold value, and the result controls bit 10 of the Status
Register.
The output of the Receive Modem Filter and Equaliser is also fed to the FSK or DPSK demodulator
depending on the selected modem type.
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The FSK demodulator recognises individual frequencies as representing received ‘1’ or ‘0’ data bits:
The DPSK demodulator decodes DPSK modulation of a 1200Hz or 2400Hz carrier and is used for V.22
and Bell 212A modes. It includes an adaptive receive signal equaliser (auto-equaliser) that will
automatically compensate for a wide range of line conditions in DPSK modes. The auto-equaliser can
provide a useful improvement in performance in 600 or 1200bps DPSK modes, so although it must be
disabled at the start of a handshake sequence, it can be enabled as soon as scrambled 1200bps 1s have
been detected.
Both FSK and DPSK demodulators produce a serial data bit stream which is fed to the Rx pattern
detector, descrambler and USART block, see Figure 7a. The demodulator input is also monitored for
continuous dibits '00,11' in 1200bps DPSK mode and continuous alternating 1s and 0s in all other modes.
The DPSK demodulator also estimates the received bit error rate by comparing the actual received signal
against an ideal waveform. This estimate is placed in bits 2-0 of the Status Register, see Figure 10.
1.5.8 Rx Modem Pattern Detectors and Descrambler
See Figure 7a.
The 1010.. pattern detector operates only in FSK modes and will set bit 9 of the Status Register when 32
bits of alternating 1’s and 0’s have been received.
The ‘Continuous Unscrambled 1’s’ detector operates in all modem modes and sets bits 8 and 7 of the
Status Register to ‘01’ when 32 consecutive 1’s have been received.
The descrambler operates only in DPSK modes and is enabled by setting bit 7 of the Rx Mode Register.
The ‘Continuous Scrambled 1’s’ detector operates only in DPSK modes when the descrambler is enabled
and sets bits 8 and 7 of the Status Register to ‘11’ when 32 consecutive 1’s appear at the output of the
descrambler. To avoid possible ambiguity, the ‘Scrambled 1’s’ detector is disabled when continuous
unscrambled 1’s are detected.
The ‘Continuous 0’s’ detector sets bits 8 and 7 of the Status Register to ‘10’ when NX consecutive 0’s
have been received, NX being 32 except when DPSK Start-Stop mode has been selected, in which case
NX = 2N + 4 where N is the number of bits per character including the Start, Stop and any Parity bits.
All of these pattern detectors will hold the ‘detect’ output for 12 bit times after the end of the detected
pattern unless the received bit rate or operating mode is changed, in which case the detectors are reset
within 2 msec.
1.5.9 Rx Data Register and USART
A flexible Rx USART is provided for all modem modes, meeting the requirements of V.14 for DPSK
modems. It can be programmed to treat the received data bit stream as Synchronous data or as Start-
Stop characters.
In Synchronous mode the received data bits are all fed into the Rx Data Buffer which is copied into the
C-BUS Rx Data Register after every 8 bits.
In Start-Stop mode the USART Control logic looks for the start of each character, then feeds only the
required number of data bits (not parity) into the Rx Data Buffer. The parity bit (if used) and the presence
of a Stop bit are then checked and the data bits in the Rx Data Buffer copied to the C-BUS Rx Data
Register.
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Figure 7a Rx Modem Data Paths
Whenever a new character is copied into the C-BUS Rx Data Register, the Rx Data Ready flag bit of the
Status Register is set to ‘1’ to prompt the µC to read the new data and, in Start-Stop mode, the Even Rx
Parity flag bit of the Status Register is updated.
In Start-Stop mode, if the Stop bit is missing (received as a ‘0’ instead of a ‘1’) the received character will
still be placed into the Rx Data Register and the Rx Data Ready flag bit set, but, unless allowed by the
V.14 overspeed option described below, the Status Register Rx Framing Error bit will also be set to ‘1’
and the USART will re-synchronise onto the next ‘1’ ‘0’ (Stop Start) transition. The Rx Framing Error
bit will remain set until the next character has been received.
Figure 7b Rx USART Function (Start-Stop mode, 8 Data Bits + Parity)
If the µC has not read the previous data from the Rx Data Register by the time that new data is copied to
it from the Rx Data Buffer then the Rx Data Overflow flag bit of the Status Register will be set to 1.
The Rx Data Ready flag and Rx Data Overflow bits are cleared to 0 when the Rx Data Register is read
by the µC.
For DPSK Start-Stop modes, V.14 requires that the receive USART be able to cope with missing Stop
bits; up to 1 missing Stop bit in every 8 consecutive received characters being allowed for the +1%
overspeed (basic signalling rate) V.14 mode and 1 in 4 for the +2.3% overspeed (extended signalling
rate) mode.
To accommodate the requirements of V.14, the CMX867 Rx Mode Register can be set for 0, +1% or
+2.3% overspeed operation in DPSK Start-Stop modes. Missing Stop bits beyond those allowed by the
selected overspeed option will set the Rx Framing Error flag bit of the Status Register.
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In order that received Break signals can be handled correctly in V.14 Rx overspeed mode, a received
character which has all bits ‘0’, including the Stop and any Parity bits, will always cause the Rx Framing
Error bit to be set and the USART to re-synchronise onto the next ‘1’ ‘0’ transition. Additionally the
received Continuous 0s detector will respond when more than 2M + 3 consecutive ‘0’s are received,
where ‘M’ is the selected total number of bits per character including Stop and any Parity bits.
1.5.10 C-BUS Interface
This block provides for the transfer of data and control or status information between the CMX867’s
internal registers and the µC over the C-BUS serial bus. Each transaction consists of a single Register
Address byte sent from the µC which may be followed by a one or more data byte(s) sent from the µC to
be written into one of the CMX867’s Write Only Registers, or a one or more byte(s) of data read out from
one of the CMX867’s Read Only Registers, as illustrated in Figure 8.
Data sent from the µC on the Command Data line is clocked into the CMX867 on the rising edge of the
Serial Clock input. Reply Data sent from the CMX867 to the µC is valid when the Serial Clock is high.
The CSN line must be held low during a data transfer and kept high between transfers. The C-BUS
interface is compatible with most common µC serial interfaces and may also be easily implemented with
general purpose µC I/O pins controlled by a simple software routine. Figure 14 gives detailed C-BUS
timing requirements.
The following C-BUS addresses and registers are used by the CMX867:
General Reset Command (address only, no data). Address $01
General Control Register, 16-bit write only. Address $E0
Transmit Mode Register, 16-bit write-only. Address $E1
Receive Mode Register, 16-bit write-only. Address $E2
Transmit Data Register, 8-bit write only. Addresses $E3 and $E4
Receive Data Register, 8-bit read-only. Address $E5
Status Register, 16-bit read-only. Address $E6
Programming Register, 16-bit write-only. Address $E8
Note: The C-BUS addresses $E9, $EA and $EB are allocated for production testing and should not be
accessed in normal operation.
1.5.10.1 General Reset Command
General Reset Command (no data) C-BUS address $01
This command resets the device and clears all bits of the General Control , Transmit Mode and Receive
Mode Registers and bits 15 and 13-0 of the Status Register.
Whenever power is applied to the CMX867 a General Reset command should be sent to the device, after
which the General Control Register should be set as required.
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Figure 8 C-BUS Transactions
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1.5.10.2 General Control Register
General Control Register: 16-bit write-only. C-BUS address $E0
This register controls general features of the CMX867 such as the Powersave and Loopback modes, the
IRQ mask bits and the Relay Drive output. It also allows the fixed compromise equalisers in the Tx and
Rx signal paths to be disabled if desired, and sets the internal clock dividers to use either a 11.0592 or a
12.288 MHz XTAL frequency.
All bits of this register are cleared to 0 by a General Reset command.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 Xtal
freq LB Equ Rly
drv Pwr Rst Irqn
en IRQ Mask Bits
General Control Register b15-13: Reserved, set to 000
General Control Register b12: Xtal frequency
This bit should be set according to the Xtal frequency.
b12 = 1 11.0592MHz
b12 = 0 12.2880MHz
General Control Register b11: Analogue Loopback test mode
This bit controls the analogue loopback test mode. Note that in loopback test mode both
Transmit and Receive Mode Registers should be set to the same modem type and band or bit
rate.
b11 = 1 Local analogue loopback mode enabled
b11 = 0 No loopback (normal modem operation)
General Control Register b10: Tx and Rx Fixed Compromise Equalisers
This bit allows the Tx and Rx fixed compromise equalisers in the modem transmit and receive
filter blocks to be disabled.
b10 = 1 Disable equalisers
b10 = 0 Enable equalisers (600 or 1200bps modem modes)
General Control Register b9: Relay Drive
This bit directly controls the RDRVN output pin.
b9 = 1 RDRVN output pin pulled to VSS
b9 = 0 RDRVN output pin pulled to VDD
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General Control Register b8: Powerup
This bit controls the internal power supply to most of the internal circuits, including the Xtal
oscillator and VBIAS supply. Note that the General Reset command clears this bit, putting the
device into Powersave mode.
b8 = 1 Device powered up normally
b8 = 0 Powersave mode (all circuits except Ring Detect, RDRVN and C-BUS
interface disabled)
When the power is first applied to the device, the following powerup procedure should be
followed to ensure correct operation.
i. (Power is applied to the device)
ii. Issue a General Reset command
iii. Write to the General Control Register (address $E0) setting both the Powerup bit
(b8) and the Reset bit (b7) to 1 leave in this state for a minimum of about 20ms
it is required that the crystal initially runs for this time in order to clock the internal
logic into a defined state. The device is now powered up, with the crystal and VBIAS
supply operating, but is otherwise not running any transmit or receive functions.
iv. The device is now ready to be programmed as and when required. Examples:
A General Reset command could be issued to clear all the registers and
therefore powersave the device.
The Reset bit in the General Control Register could be set to 0 as part of a
routine to program all the relevant registers for setting up a particular operating
mode.
When the device is switched from Powersave mode to normal operation by setting the
Powerup bit to 1, the Reset bit should also be set to 1 and should be held at 1 for about 20ms
while the internal circuits, Xtal oscillator and VBIAS stabilise before starting to use the transmitter
or receiver.
General Control Register b7: Reset
Setting this bit to 1 resets the CMX867’s internal circuitry, clearing all bits of the Transmit and
Receive Mode Registers and b13-0 of the Status Register.
b7 = 1 Internal circuitry in a reset condition.
b7 = 0 Normal operation
General Control Register b6: IRQNEN (IRQN O/P Enable)
Setting this bit to 1 enables the IRQN output pin.
b6 = 1 IRQN pin driven low (to VSS) if the IRQ bit of the Status Register = 1
b6 = 0 IRQN pin disabled (high impedance)
General Control Register b5-0: IRQ Mask bits
These bits affect the operation of the IRQ bit of the Status Register as described in section
1.5.10.7
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1.5.10.3 Transmit Mode Register
Transmit Mode Register: 16-bit write-only. C-BUS address $E1
This register controls the CMX867 transmit signal type and level. All bits of this register are cleared to 0
by a General Reset command, or when b7 (Reset) of the General Control Register is 1.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Tx mode = modem Tx level Guard tone Scrambler Start-stop /
synch data # data bits /
synch data source
Tx mode = DTMF/Tones Tx level DTMF Twist DTMF or Tone select
Tx mode = Disabled Set to 0000 0000 0000
Tx Mode Register b15-12: Tx mode
These 4 bits select the transmit operating mode.
b15 b14 b13 b12
1 1 1 1 Transmitter disabled (Reserved for future use)
1 1 1 0 Transmitter disabled (Reserved for future use)
1 1 0 1 V.22/Bell 212A 1200 bps DPSK High band (Answering modem)
1 1 0 0 Low band (Calling modem)
1 0 1 1 V.22 600 bps DPSK High band (Answering modem)
1 0 1 0 Low band (Calling modem)
1 0 0 1 V.21 300 bps FSK High band (Answering modem)
1 0 0 0 Low band (Calling modem)
0 1 1 1 Bell 103 300 bps FSK High band (Answering modem)
0 1 1 0 Low band (Calling modem)
0 1 0 1 V.23 FSK 1200 bps
0 1 0 0 75 bps
0 0 1 1 Bell 202 FSK 1200 bps
0 0 1 0 150 bps
0 0 0 1 DTMF / Tones
0 0 0 0 Transmitter disabled
Tx Mode Register b11-9: Tx level
These 3 bits set the gain of the Tx Level Control block.
b11 b10 b9
1 1 1 0dB
1 1 0 -1.5dB
1 0 1 -3.0dB
1 0 0 -4.5dB
0 1 1 -6.0dB
0 1 0 -7.5dB
0 0 1 -9.0dB
0 0 0 -10.5dB
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Tx Mode Register b7-5: DTMF Twist (DTMF mode)
These 3 bits allow for adjustment of the DTMF twist to compensate for the frequency
response of different external circuits. Set b8 to 0. The device varies the twist by making
changes to the upper tone group levels. Note that the twist cannot be adjusted mid-tone.
b7 b6 b5
0 0 0 +2.0dB twist (normal setting when external response is flat)
0 0 1 +1.0dB twist
0 1 0 +1.5dB twist
0 1 1 +2.5dB twist
1 0 0 +3.0dB twist
1 0 1 +3.5dB twist
1 1 0 +4.0dB twist
1 1 1 +4.5dB twist (do not use in conjunction with the 0dB tx level
setting).
Tx Mode Register b6-5: Tx Scrambler (DPSK modes)
These 2 bits control the operation of the Tx scrambler used in DPSK modes. Set both
bits to 0 in FSK modes.
b6 b5
1 1 Scrambler enabled, 64 ones detect circuit enabled (normal use)
1 0 Scrambler enabled, 64 ones detect circuit disabled
0 x Scrambler disabled
Tx Mode Register b4-3: Tx Data Format (DPSK and FSK modes)
These two bits select Synchronous or Start-stop mode and the addition of a parity bit to
transmitted characters in Start-stop mode.
b4 b3
1 1 Synchronous mode
1 0 Start-stop mode, no parity
0 1 Start-stop mode, even parity bit added to data bits
0 0 Start-stop mode, odd parity bit added to data bits
Tx Mode Register b2-0: Tx Data and Stop bits (DPSK and FSK: Start-Stop modes)
In Start-stop mode these three bits select the number of Tx data and stop bits.
b2 b1 b0
1 1 1 8 data bits, 2 stop bits
1 1 0 8 data bits, 1 stop bit
1 0 1 7 data bits, 2 stop bits
1 0 0 7 data bits, 1 stop bit
0 1 1 6 data bits, 2 stop bits
0 1 0 6 data bits, 1 stop bit
0 0 1 5 data bits, 2 stop bits
0 0 0 5 data bits, 1 stop bit
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Tx Mode Register b2-0: Tx Data source (DPSK and FSK: Synchronous mode)
In Synchronous mode (b4-3 = 11) these three bits select the source of the data fed to the Tx
FSK or DPSK scrambler and modulator.
b2 b1 b0
1 x x Data bytes from Tx Data Buffer
0 1 1 Continuous 1s
0 1 0 Continuous 0s
0 0 x Continuous dibits ’00,11’ in 1200bps DPSK mode, continuous
alternating 1s and 0s in all other modes.