Ultra Fast FET-Input
Operational Amplifier
LH0032 / LH0032C
FEATURES
••500V/µs Slew R a te
••70M Hz Bandw idt h
••1012Ω Input Impe dance
••As Low as 2mV Max Input Offset Voltage
••FE T Input
••Of f set Null wi t h Singl e Pot
••No Co mp ensation fo r Gains Above 50
••Pea k O utput Curr ent t o 100m A
LLC
CALOGIC LLC, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076 DS047 REV A
OUT
NC
NC
NC
V-
V+
H12A
Top View
4
789
10
11
12
123
-
+
NC
NON-INV
INPUT
INV
INPUT
OUTPUT
COMPENSATION
BALANCE/
COMPENSATION
5
6
GENERAL DESCRIPTIO N
The LH0032 is a FET input, high sl ew rate amplifier capable
of driv ing up t o 100mA cu rren t.
With wide bandwidth, high slew rate, high input impedance
and high current drive capability , LH0032 is an ideal choice for
many applications that includes high speed integrator, video
amplif ie r, sum m in g am p l ifier, h ig h spee d D/A converters, et c.
ORDERING INFORMATION
Part Package Temperature Range
LH0032G H12A (TO8-12 Lead ) -55oC to +125oC
LH0032CG H12A (TO8-1 2 Lead ) -25oC to +85oC
CONNECTION DIAGRAMS
ABSOLUTE M AXIM UM R A T INGS
Supply Voltage, VS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V
Input Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Diff erent ial In put V o ltag e . . . . . . . . . . . . . . . . . . ±30V or± 2VS
Power Dissipation, PD
T
A = 2 5oC. . . . . . . . . . . . . 1.5W, derate 100oC/ W to 125oC
T
C = 25 oC. . . . . . . . . . . . . 2.2W , derate 70oC/W to 125oC
Oper at ing Temper atur e Ra nge, T A
LH0032G . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125 oC
LH0032CG. . . . . . . . . . . . . . . . . . . . . . . . . -25oC to +85oC
Oper at ing J unct ion Temper atur e, T J. . . . . . . . . . . . . . 175oC
Stor age Temper atur e Ra nge . . . . . . . . . . . . -65oC to +150oC
Lead Temp. ( Soldering, 10 s econds). . . . . . . . . . . . . . 300 oC
LLC
CALOGIC LLC, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076 DS047 REV A
DC ELECTRICA L CHARACT ERISTICS VS = ±15V, TMIN ≤ T A ≤ TMAX unle ss ot her wise note d (Note 1 ) (TA = Tj)
SYMBOL PARAMETER LH0032 LH0032C UNITS TEST CONDITIONS
MIN TYP MAX MIN TYP MAX
VOS Input Offset Voltage 25
10 215
20 mV
VIN = 0
TA = TJ = 25oC (Note 3)
∆VOS/∆T Average Offset Voltage Drift 15 50 15 50 µV/oC (Note 4)
IOS Input Offset Current 25
250
25
50
500
5
pA
pA
nA
TJ = 25oC (Note 2)
TA = 25oC (Note 3)
IBInput Bias Current 100
1
50
500
5
15
pA
nA
nA
TJ = 25oC (Note 2)
TA = 25oC (Note 3)
VINCM Input Voltage Range ±10 ±12 ±10 ±12 V Note 6
CMRR Co mmon Mode Rejection
Ratio 50 60 50 60 dB ∆VIN = ±10V
AVOL Open-Loop Voltage Gain
60 70 60 70 dB VO = ±10V,
f = 1kHz
RL = 1kΩ
(Note 7)
TJ = 25oC
57 57
VOOu tp ut Voltag e S win g ±10 ±13.5 ±10 ±13 V RL = 1kΩ
ISPower Supply Current 18 20 20 22 mA TA = 25oC,
IO = 0 (Note 3)
PSRR Power Supply Rejection
Ratio 50 60 50 60 dB ∆VS = 10V
(±5 to ±15V)
LH0032 / LH0032C
LLC
CALOGIC LLC, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076 DS047 REV A
AC ELECTRICA L CHARACT ERISTICS VS = ±15V, RL = 1k Ω, TJ = 2 5oC (Note 5 )
SYMBOL PARAMETER MIN TYP MAX UNITS CONDITIONS
SRSlew Rate 350 500 V/µsA
V = +1
∆VIN = 20V
tsSettling Time to 1% of Final Value 100 AV = -1
tsSettling Time to 0.1% of Final Value 300 ns
tRSma ll Sign al Rise Tim e 8 2 0 AV = +1, ∆VIN = 1V
tDSma ll Sign al Delay Time 10 25
Note 1. LH00 32 G/CG are 100% production teste d a s specifie d at 25oC, Specifications at temperature extremes are verified by testing, periodic
cha racteri zation, or correlatio n.
Note 2. Specification is at 25oC junction temperature due to requirements of high-speed automatic testing. Actual values at operating
tem pe ratu re will e x ceed th e value at TJ = 25oC. When supply voltages are ±15V, no -load op era ting jun cti on temp era tu re ma y rise 40-60 oC above
amb ient, and more unde r lo ad condition s. Accordingly, VOS ma y change one to several mV, and IB and IOS will change significantly during
warm-up. Refer to IB and IOS vs. te m pe rature gra ph for expect ed value s.
Note 3. Measured in still air 7 minutes after application of power. Guaranteed thru correlated automatic pulse test ing.
Note 4. ∆VOS/∆T is the average value calculated from measurements at 25oC and TMAX, specifications at temperature are verified by testing,
periodic characterization, or correlation.
Note 5. Not 100% production tested; verified by testing, periodic characterization, or correlation.
Note 6. Guaranteed by CMRR test condition.
Note 7. Guaranteed thru correlated pulse testing at Tj = 25oC.
11
3
4
12
6
OUTPUT
V+
5
V-
-
+
LH0032
10k
10
INPUTS
11
2
12
6
5
V-
-
+
LH0032
10
V+
62Ω
LM113
Out put Shor t Circ uit Prot ecti on
AUXILIARY CIRCUITS
Offset Null
LH0032 / LH0032C
LLC
CALOGIC LLC, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076 DS047 REV A
FREQUENCY (Hz)
VOLTAGE GAIN (dB)
80
10k
BODE PLOT (UNITY GAIN
COMPENSATED)
60
0100M
40
20
10M1M100k
45
135
0
90
PHASE (DEGREES)
PHASE
GAIN
V
S
= ±15V
TEMPERATURE (˚C)
POWER DISSIPATION (W)
0.5
0
7525 50
MAXIMUM POWER
DISSIPATION
0100 125 150
2.0
1.5
1.0
2.5
JC
θ= 70˚C/W
NO HEAT SINK
JA
θ= 100˚C/W
INFINITE HEAT SINK
SUPPLY VOLTAGE (±V)
010
INPUT VOLTAGE RANGE AND OUTPUT
VOLTAGE vs. SUPPLY VOLTAGE
15
20
15
10
5
0520
V(±V)
INCM
, V
OUT
T
C
= 25˚C
R
L
= 1k
V
OUT
V
IN
FREQUENCY (Hz)
VOLTAGE GAIN (dB)
26
10
LARGE SIGNAL
FREQUENCY RESPONSE
6100M10M1M100
24
22
20
18
16
14
12
10
8
A
V
= +10
A
V
= +1
T
C
= +25˚C
R
L
= 1k
V
S
= ±15V
SUPPLY VOLTAGE (±V)
SUPPLY CURRENT (mA)
510
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
15 20
24
22
20
18
16
14
12
10
T
C
= 25˚C
T = +125˚C
A
T = -55˚C
A
FREQUENCY (Hz)
VOLTAGE GAIN (dB)
80
10k
BODE PLOT
(UNCOMPENSATED)
60
0100M
40
20
10M1M100k
45
135
225
90
0
180
270
PHASE (DEGREES)
PHASE
GAIN
V
S
= ±15V
TYPICAL PERFO RM ANCE CHARACTERI STICS
LH0032 / LH0032C
LLC
CALOGIC LLC, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076 DS047 REV A
TIME FROM POWER TURN-ON (MINUTES)
CURRENT – NORMALIZED
TO CURRENT AT TIME = 0
100
0624
NORMALIZED INPUT BIAS
CURRENT DURING WARM-UP
1810
10
T
A
V
S
= ±15V
= 25˚C
FREQUENCY (Hz)
COMMON-MODE REJECTION RATIO (dB)
90
10k
COMMON MODE REJECTION
RATIO vs. FREQUENCY
100M10M1M100k
80
70
60
50
40
30
20
10
0
R
L
= 1k
V
S
= ±15V
TIME (ns)
OUTPUT VOLTAGE (V)
LARGE SIGNAL
PULSE RESPONSE
10
5
0
-5
-10
0 100 200 300 400 500
V
S
= ±15V
A
V
= +10
R
L
= 1k
TIME (ns)
OUTPUT VOLTAGE (V)
LARGE SIGNAL
PULSE RESPONSE
+10
+5
0
-5
-10
0 100 200 300 400 500
V
S
= ±15V
A
V
= +1
R
L
= 1k
JUNCTION TEMPERATURE (˚C)
25 8545 65
NORMALIZED INPUT BIAS AND OFFSET
CURRENT vs. JUNCTION TEMPERATURE
105 125 165145
CURRENT – NORMALIZED
J
= 25˚CTO CURRENT AT T
10
0
10
1
10
2
10
3
10
4
TYPICAL PERFO RM ANCE CHARACTERI STICS (Continued)
LH0032 / LH0032C
LLC
CALOGIC LLC, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076 DS047 REV A
TYPIC AL APPLI CA T IONS
Unity Gain Amplifier
INPUT
11
6
5
10 100pF
100
V-8pF - 10pF
OUTPUT
V-
2k 12 23
4
-
+
LH0032
10X Buf fer Am pl ifier
V-
10
INPUT
11
6
V-5pF
OUTPUT
12 23
-
+
LH0032
5
1k
9k
100X Buffe r Amplif ier
V-
10
INPUT
11
612
-
+
LH0032
5
100
10k
V+
Non-Compensat ed Unity Gain Inverter
INPUT
11
6
5
10
+
+
V+
OUTPUT
270
10k
10k
12
LH0032
+
-
0.01
V-
High Speed Sample and Hold
*Use polystyrene dielectric for minimum drift
V-
V+
LOGIC
CONTROL
LH0032
-
+
1/2 DH0034
V
+
1N914
V
IN
2N4391
100
Ω
2N2222
2N3907
S
C
= 1000pF
V
OUT
100
Ω
10k
V-
1k
LH0032 / LH0032C
APPLICAT ION INFORMATION:
Power Supply Decoupling
The LH0032, like most high speed circuits, is sensitive to
layout and stray capacitance. Power supplies should be
bypassed as near to pins 10 and 12 as practicable with low
inductance capacitors such as 0.01µF disc ceramics.
Compensation components should also be located close to
the appro pr iate pins to minimize st ray reac tances .
Input Cur rent
Because the input devices are FETs, the input bias current
may be expected to double for each 11oC junction
temperature rise. This characteristic is plotted in the typical
performance characteristics graphs. The device will self-heat
due to internal power dissipation after application of power
thus raising the FET junction temperature 40-60oC above
free-air ambient temperature when supplies are ±15V. The
device temperature will stabilize within 5-10 minutes after
appl ication of power, and the i nput bias currents measured at
that time will be indicative of normal operating currents. An
additional rise would occur as power is delivered to a load due
to additional int er nal power dissipation .
There is an additional eff ect on input bias current as the i nput
voltage is changed. The effect, common to all FETs, is an
avalanche-like increase in gate current as the FET
gate-to-drain voltage is increased above a critical value
depending on FET geometry and doping levels. This effect
will be noted as the input voltage of the LH0032 is taken
below ground potential when the supplies are ±1 5 V. All of the
effects described here may be minimized by operating the
devic e with VS ≤ ±15V.
The se eff ec ts are indicat ed in the ty pical per for mance cur ves.
Input Capa cita nce
The input capacitance to the LH0032/LH0032C is typically
5pF and thus may form a significant time constant with high
value resistors. For optimum performance, the input
LLC
CALOGIC LLC, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076 DS047 REV A
TYPIC AL APPLICATIONS (Continued)
High S pe ed Cu r ren t Mod e MU X
AM9710
LH0032
-
+
V
OUT
R1
R2
R3
R4
A3
A4
A1
A2
2
6
9
13
G1
G2
G3
G4
11 5
6
11
V-
10
45R5
3.8pF
6
3
5
10
12
1
7
8
14
12
23
18µF
V-
5.1k
5.1k
5.1k
5.1k
LH0032 / LH0032C
capacitance to the inverting input should be compensated by
a small capacitor across the feedback resistor. The value is
strongly dependent on layout and closed loop gain, but will
typically be in the neigh bor hoo d of sever al picof arad s.
In the non-inverting configuration, it may be advantageous to
bootstrap the case and/or a guard conductor to the inverting
input. This serves both to divert leakage currents away from
the non-inverting input and to reduce the effective input
capacitance. A unity gain follower so treated will have an
input capacitance under a picofarad.
Compensation
Two compensation schemes may be used, depending on the
desig ner’s spe cific ne eds.
The first technique is shown in
Figure 1.
It offers the best
0.1% settling time for a ±10V square wave input. The
compensation capacitors CC and CA should be selected from
Figure 2
for various closed-loop gains.
Figure 3
shows how
the LH0032 frequency response is modified for different value
compensation capacitors.
CALOGIC LLC, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076 DS047 REV A
LLC
Figur e 1. LH0 032 Fr equ ency Comp ensatio n Cir cui t
0.01
µ
F
R2
R1
INPUT
R3
5
6
10
3
4
11
12
-15V
+15V
C
2
C
C
A
LH0032
+
_
OUTPUT
0.01
µ
F
CLOSED LOOP GAIN
1 100010 100
0
5
10 100
COMPENSATION CAPACITANCE C (pF)
C
COMPENSATION CAPACITANCE C (pF)
A
75
50
25
0
C
A
C
C
FREQUENCY (Hz)
VOLTAGE GAIN (dB)
80
10k
60
0
100M
40
20
10M1M100k
-45
-135
-90
0
-180
PHASE SHIFT (DEGREES)
-20
C
C
= 0pF
C
C
= 1pF
C
C
= 5pF
C
C = 10pF
C
C
= 5pF
C
C
= 10pFPHASE
C
C
C
= 1pF
C
= 0pF
V
S
= ±15V
T
A
= 25˚C
R
L
= 1k
A
VOL
Fi gure 3. T h e Eff e c t of Vario u s Co m pe n sa t i on
Capacitor s on LH0 032 Ope n Loop Frequenc y
Response
Figur e 2. Recom mended V a lue of Comp ensation
Capacitor vs Closed -Loop G ain for Op tim um
Settl ing T i me
10V
10V 100nS
Figur e 4. LH0 032 Uni ty Gai n Non-I nve rting Lar g e
Signal Pul se Resp onse:
TA = 2 5oC, CC = 10pF, CA = 100pF
LH0032 / LH0032C
Although this approach offers the shortest settling time, the
falling edge exhibits overshoot up to 30% lasting 200 to
300ns.
Figure 4
shows the typical pulse response.
If obtai ning minimum ringing at the fall ing edge is the prima ry
objective, a slight modification to the above is recommended.
It is based on t he sa me circ uit as t ha t of
Figure 1.
The values of the unity gain compensation capacitors CC and
CA should be modified to 5pF and 1000pF, respectively.
Figure 5
shows the suitable capacitance to use for various
closed-loop gains. The resulting unity gain pulse response
waveform is shown in
Figure 6.
The s ettlin g ti me to 1 % final
val ue is actually superior to the firs t method of compensa tion.
How ever, the LH0032 suffers slow settling thereafter to 0.1%
accuracy at t he falling edge, and near ly four times as much at
the rising edge, compared to the previous scheme. Note,
however , t hat the falling edge ringing is c onside rably r educ ed.
Furthermore, the slew rate is consistentl y superior using this
compensation because of the smaller value of Miller
capacitance CC requ ired .
The second compensation scheme works well with both
inverting or non-inverting modes.
Figure 7
shows the circuit
schem atic, in wh ich a 270ohm resist or an d a 0.0 1 µF capacit or
are shunted across the inputs of the device. This lag
compensation introduces a zero in the loop modifying the
response such that adequate phase margin is preserved at
unity gain crossover frequency. Note that the circuit requires
no addition al com pen sation.
Heat Sinking
While the LH0032 is specified for operation without any
explicit heat sink, internal power dissipation does cause a
significant temperature rise. Improved bias current
perf orm ance can thus be obtained by l imiting this t em p er at ur e
rise with a sm a ll heat sink such as the Ther m alloy No. 2241 or
equivalent. The case of the device has no internal
connection, so it may be electrically connected to the sink if
this is advantageous. However, that this will affect the stray
capacitance to all pins and may thus require adjustment of
circuit compensation values.
CALOGIC LLC, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076 DS047 REV A
LLC
CLOSED LOOP GAIN
1 100010 100
0
2
41000
COMPENSATION CAPACITANCE C (pF)
C
COMPENSATION CAPACITANCE C (pF)
A
500
0
5
3
1C
A
C
C
Figur e 7. LH0 032 No n-Co mp ensa te d Unity Ga in
Compensation
0.01
µ
F
1k
INPUT
1k
5
6
11
-15V
+15V
0.01
µ
F
OUTPUT
1k
0.01
µ
F
10
12
LH0032
+
_
270
Figur e 5. Recom mended V a lue of Comp ensation
Capacitor vs Closed -L oop Gai n for Op tim um Slew Rate
10V
10V 50nS
Figur e 6. LH0 032 Uni ty Gai n Non-I nve rting Lar g e
Signal Pulse Response : CC = 5pF, CA = 100 0pF
LH0032 / LH0032C
