IP4778CZ38,118 - NXP SEMICONDUCTORS

1. General description

The IP4778CZ38 is designed for HDMI receiver host interface protection.

The IP4778CZ38 includes DDC buffering, slew rate acceleration and decoupling, hot plug

control, backdrive protection, CEC slew rate control, optional multiplexing of DDC signals,

and high-level ESD protection diodes for all HDMI signals.

The DDC lines are buffered using a ne w buffering concept which deco uples the internal

capacitive load from the external cap acitive load. This allows higher PCB design flexibility

for the DDC lines with respect to a maximu m load of 50 p F. This buf f ering a lso boo sts the

DDC signals, allowing the use of longer HDMI cables having a higher capacitive load than

700 pF. The CEC slew rate limiter prevents ringing on the CEC line and greatly reduces

the number of discrete components needed by the CEC application. HDMI receiver and

system GPIO applications are simplified by an internal hot plug driver module and ho t plug

control.

The DDC, hot plug and CEC line s ar e ba ckd riv e pr ot ected to guarant ee HD MI inte rfa ce

signals are not pulled down if the system is powered down or enters Standby mode.

All TMDS intra-pairs are protected by a special diode configuration offering a low line

capacitance of 0.7 pF only (to ground) and 0.05 pF between the TMDS pairs. These

diodes provide protection to components downstream from ESD voltages of up to ±8kV

contact in accordance with the IEC 61000-4-2, level 4 standard.

2. Features and benefits

Pb-free and RoHS compliant

Robust ESD protection without degradation after several ESD strikes

Low leakage even after several hundred ESD discharges

Very high diode switching speed (ns) and low line cap acitanc e of 0.7 pF to ground and

0.05 pF between channels ensures signal integrity

DDC capacitive decoupling between system side and HDMI connector side and drive

cable buffering with capacitive load (> 700 pF)

Hot plug control for direct connection to system GPIO

CEC ringing prevention by slew rate limiter

DDC and hot plug enable signal for multiplexing and backdrive protection

All TMDS lines with integrated rail-to-rail clamping diodes with downstream

ESD protection of ±8 kV in accordance with IEC 61000-4-2, level 4

Matched 0.5 mm trace spacing

Component count reduction of HDMI receiver application

IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

Rev. 3 — 31 March 2011 Product data sheet

Product data sheet Rev. 3 — 3 1 March 2011 2 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

Highest integration in a small footprint, PCB level, optimized RF routing, 38-pin

TSSOP lead-free package

Choice of system compatible or RF routing optimized pinning variants

3. Applications

The IP4778CZ38 can be used for a wide r ange of HDMI sink devices e.g.:

TV

Projectors

PC monitors

HDMI buffer modules (extensions of HDMI cable length)

HDMI picture performance quality enhancer modules

4. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

IP4778CZ38 TSSOP38 plastic thin shrink small outline package; 38 leads;

body width 4.4 mm; lead pitch 0.5 mm SOT510-1

IP4778CZ38/V

Product data sheet Rev. 3 — 3 1 March 2011 3 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

5. Functional diagram

Fig 1. Functional di agram

TMDS_D2+ TMDS_D1+ TMDS_D0+TMDS_BIAS

TMDS_GND

TMDS_CLK+

TMDS_CLK−TMDS_D0−TMDS_D1−TMDS_D2−

5V0

10 μA

HOT_PLUG_DET_INHOT_PLUG_DET_OUT

VCC(5V0) VCC(3V3)

TMDS_BIAS

SLEW

RATE

LIMITER

VCC(3V3)

TMDS_BIAS

CEC_OUT CEC_IN

001aae86

SLEW

RATE

ACCELERATOR

ENABLE

DDC_DAT_IN

TMDS_BIAS VCC(5V0)

DDC_DAT_OUT

SLEW

RATE

ACCELERATOR

ENABLE

DDC_CLK_IN

TMDS_BIAS VCC(5V0)

DDC_CLK_OUT

Product data sheet Rev. 3 — 3 1 March 2011 4 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

6. Pinning information

6.1 Pinning

Fig 2. Pin configuration of IP47 78 C Z3 8

Fig 3. Pin configuration of IP47 78 C Z3 8 /V

IP4778CZ38

VCC(5V0) TMDS_BIAS

ENABLE VCC(3V3)

GND GND

TMDS_D2+ n.c.

n.c. TMDS_D2−

TMDS_GND TMDS_GND

TMDS_D1+ n.c.

n.c. TMDS_D1−

TMDS_GND TMDS_GND

TMDS_D0+ n.c.

n.c. TMDS_D0−

TMDS_GND TMDS_GND

TMDS_CLK+ n.c.

n.c. TMDS_CLK−

TMDS_GND TMDS_GND

CEC_IN CEC_OUT

DDC_CLK_IN DDC_CLK_OUT

DDC_DAT_IN DDC_DAT_OUT

HOT_PLUG_DET_IN HOT_PLUG_DET_OUT

001aag032

IP4778CZ38/V

VCC(5V0) TMDS_BIAS

ENABLE VCC(3V3)

GND GND

TMDS_D2+ n.c.

TMDS_GND TMDS_GND

n.c. TMDS_D2−

TMDS_D1+ n.c.

TMDS_GND TMDS_GND

n.c. TMDS_D1−

TMDS_D0+ n.c.

TMDS_GND TMDS_GND

n.c. TMDS_D0−

TMDS_CLK+ n.c.

TMDS_GND TMDS_GND

n.c. TMDS_CLK−

CEC_IN CEC_OUT

DDC_CLK_IN DDC_CLK_OUT

DDC_DAT_IN DDC_DAT_OUT

HOT_PLUG_DET_IN HOT_PLUG_DET_OUT

001aag031

Product data sheet Rev. 3 — 3 1 March 2011 5 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

6.2 Pin description

Table 2. Pin description

Symbol Pin Description

IP4778CZ38 IP4778CZ38/V

VCC(5V0) 1 1 supply voltage for DDC and hot plug

circuits

ENABLE 2 2 enable for DDC and hot plug circuits

GND 3 3 ground for DDC, hot plug and CEC

circuits[1]

TMDS_D2+ 4 4 ESD protection TMDS channel D2+[2]

TMDS_GND 6 5 ground for TMDS channel[1]

n.c. 5 6 not connected[2]

TMDS_D1+ 7 7 ESD protection TMDS channel D1+[2]

TMDS_GND 9 8 ground for TMDS channel[1]

n.c. 8 9 not connected[2]

TMDS_D0+ 10 10 ESD protection TMDS channel D0+[2]

TMDS_GND 12 11 ground for TMDS channel[1]

n.c. 11 12 not connected[2]

TMDS_CLK+ 13 13 ESD protection TMDS channel

CLK+[2]

TMDS_GND 15 14 ground for TMDS channel[1]

n.c. 14 15 not connected[2]

CEC_IN 16 16 CEC signal input to system

controller[3]

DDC_CLK_IN 17 17 DDC clock input to system

controller[3]

DDC_DAT_IN 18 18 DDC data input to system controller[3]

HOT_PLUG_DET_IN 19 19 hot plug Detect input from system

GPIO[3]

HOT_PLUG_DET_OUT 20 20 hot plug Detect output to HDMI

connector[4]

DDC_DAT_OUT 21 21 DDC data output to HDMI connector[4]

DDC_CLK_OUT 22 22 DDC clock output to HDMI

connector[4]

CEC_OUT 23 23 CEC signal output to HDMI

connector[3]

TMDS_CLK−25 24 ESD protection TMDS channel

CLK−[2]

TMDS_GND 24 25 ground for TMDS channel[1]

n.c. 26 26 not connected[2]

TMDS_D0−28 27 ESD protection TMDS channel D0−[2]

TMDS_GND 27 28 ground for TMDS channel[1]

n.c. 29 29 not connected[2]

TMDS_D1−31 30 ESD protection TMDS channel D1−[2]

TMDS_GND 30 31 ground for TMDS channel[1]

Product data sheet Rev. 3 — 3 1 March 2011 6 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

[1] Pins GND and TMDS_GND are internally connected.

[2] This pin must always be connected to the IC pin located opposite via a PCB track to guarantee correct

functionality; see Figure 15.

[3] VCC(3V3) referenced logic level in.

[4] VCC(5V0) referenced logic level out.

7. Limiting values

[1] Connector side pins:

TMDS_D2+, TMDS_D2−, TMDS_D1+, TMDS_D1−, TMDS_D0+, TMDS_D0−,

TMDS_CLK+, TMDS_CLK−,

CEC_OUT,

DDC_DAT_OUT and DDC_CLK_OUT,

HOT_PLUG_DET_OUT.

[2] Board side pins:

CEC_IN,

DDC_DAT_IN and DDC_CLK_IN,

HOT_PLUG_DET_IN,

ENABLE.

n.c. 32 32 not connected[2]

TMDS_D2−34 33 ESD protection TMDS channel D2−[2]

TMDS_GND 33 34 ground for TMDS channel[1]

n.c. 35 35 not connected[2]

GND 36 36 ground for DDC, hot plug and CEC

circuits[1]

VCC(3V3) 37 37 supply voltage for CEC circuit

TMDS_BIAS 38 38 bias input for TMDS ESD protection.

This pin must be connected to a

0.1 μF capacitor.

Table 2. Pin description …continued

Symbol Pin Description

IP4778CZ38 IP4778CZ38/V

Table 3. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage GND − 0.5 5.5 V

VIinput voltage at input pi ns GND − 0.5 5.5 V

VESD electrostatic discharge

voltage connector side pins (to ground);

IEC 61000-4-2, level 4 [1]

contact −8+8kV

board side pins; IEC 61000-4-2, level 1 [2]

contact −2+2kV

Ptot total power dissipation DDC operating at 100 kHz - 8 mW

Tstg storage temperature −55 +125 °C

Product data sheet Rev. 3 — 3 1 March 2011 7 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

8. Static characteristics

[1] This measurement is performed with a 0.1 μF external capacitor on pin TMDS_BIAS.

[2] This parameter is guaranteed by design.

Table 4. TMDS protection circuit

Tamb =25

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Zener diode

VBRzd Zener diode breakdown

voltage I=1mA 6 - 9 V

Rdyn dynamic resistance I = 1 A; IEC 61000-4-5/9

positive transient - 2.4 - Ω

negative transient - 1.3 - Ω

Protection diode

Ibck back current from pins TMDS_x to pin TMDS_BIAS;

VCC(5V0) =0V; V

CC(3V3) =0V -0.15μA

IL(r) reverse leakage current VI=3.0V - 1 - μA

VFforward voltage - 0.7 - V

VCL(ch)trt(pos) positive transient channel

clamping voltage VESD = 8 kV per IEC 61000-4-2; voltage

30 ns af te r tr i gg e r [1] -8-V

TMDS channel: pins TMDS_x

Cch(TMDS) TMDS channel capacitance VCC(5V0) = 5 V; f = 1 MHz; Vbias =2.5V [2] -0.7-pF

ΔCch(TMDS) TMDS channel capacitance

difference VCC(5V0) = 5 V; f = 1 MHz; Vbias =2.5V [2] -0.05-pF

Cch(mutual) mutual channel capacitance between signal pin TMDS_x and

pin n.c.; VCC(5V0) = 0 V; f = 1 MHz;

Vbias =2.5V

[2] -0.07-pF

Table 5. DDC circuit

VCC(3V3) = 2.7 V to 5.5 V; VCC(5V0) = 4.5 V to 5.5 V; GND = 0 V; Tamb =25

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Supplies: pins VCC(5V0) and VCC(3V3)

VCC(5V0) supply voltage (5.0 V) 4.5 5.0 5.5 V

VCC(3V3) supply voltage (3.3 V) 2.7 3.3 5.5 V

ICC(5V0) supply current (5.0 V) VCC(5V0) =5.5V;

both channels HIGH:

DDC_DAT_OUT = VCC(5V0);

DDC_CLK_OUT = VCC(5V0)

-0.51.0mA

VCC(5V0) = 5.5 V;

both channels LOW:

DDC_DAT_IN = GND;

DDC_CLK_IN = GND;

DDC_DAT_OUT = open;

DDC_CLK_OUT = open

-0.51.0mA

ICC(3V3) supply current (3.3 V) no pull-up resistor

connected to VCC(3V3)

--0.1μA

Product data sheet Rev. 3 — 3 1 March 2011 8 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

Board side: pins DDC_CLK_OUT and DDC_DAT_OUT

Used as input

VIH HIGH-level input voltage 0.7 × VCC(3V3) -5.5 V

VIL LOW-level input voltage −0.5 - 0.3 × VCC(3V3) V

IIL LOW-level input current VI=0.2V - - 1 μA

VIK input clamping voltage Ii=−18 mA - - −1.2 V

ILI input leakage curren t VI=3.6V - - ±1μA

Ciinput capacitance VI=3V or 0V

VCC(3V3) =3.3V - 8 10 pF

VCC(3V3) =3.0V - 8 10 pF

Used as output

VOL LOW-level output voltage IOL = 100 μA or 6 mA - 200 - mV

IOH HIGH-level output current VO=3.6V - - 1 μA

Cooutput capacitance VI=3V or 0V

VCC(3V3) =3.3V - 8 10 pF

VCC(3V3) =3.0V - 8 10 pF

Connector side: pins DDC_CLK_IN and DDC_DAT_IN

Used as input

VIH HIGH-level input voltage - 410 - mV

VIL LOW-level input voltage - 400 - mV

IIL LOW-level input current DDC_DAT_OUT,

DDC_CLK_OUT, VI=0.2V --10μA

VIK input clamping voltage II=−18 mA - - −1.2 V

ILI input leakage curren t VI=3.6V - - ±1μA

Ciinput capacitance VI=3V or 0V

VCC(3V3) =3.3V - 7 9 pF

VCC(3V3) =3.0V - 7 9 pF

Used as output

VOL LOW-level output voltage IOL = 100 μA or 3 mA - 700 - mV

IOH HIGH-level output current VO=3.6V - - 1 μA

Cooutput capacitance VI=3V or 0V

VCC(3V3) =3.3V - 8 10 pF

VCC(3V3) =3.0V - 8 10 pF

Table 5. DDC circuit …continued

VCC(3V3) = 2.7 V to 5.5 V; VCC(5V0) = 4.5 V to 5.5 V; GND = 0 V; Tamb =25

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 3 — 3 1 March 2011 9 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

[1] This parameter is guaranteed by design.

[2] For level shifting N-FET.

[3] This measurement is performed with a 0.1 μF external capacitor on pin TMDS_BIAS.

[1] The ENABLE pin has to be connected permanently to VCC(3V3) if no enable control is needed.

Table 6. CEC circuit

VCC(3V3) = 2.7 V to 5.5 V; GND = 0 V; Tamb =25

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Board side: input pin CEC_IN

CI(ch-GND)(levsh) level shifting input capacitance

from channel to ground VCC(3V3) = 0 V; f = 1 MHz;

Vbias =2.5V [1] -1216pF

SRrrising slew rate VI>1.8V - 10 - mV/μs

N-FET

ΔVon on-state voltage drop N-FET state = on;

VCC(3V3) = 2.5 V; VS= GND;

IDS =3mA

[2] - 125 140 mV

Connector side: output pin CEC_OUT

ILI input leakage current −1+0.1+1μA

Rdyn dynamic resistance I = 1 A; IEC 61000-4-5/9

positive transient - 2.4 - Ω

negative transient - 1.3 - Ω

VCL(ch)trt(pos) positive transient channel

clamping voltage VESD = 8 kV per IEC 61000-4-2;

voltage 30 ns after trigge r;

Tamb =25°C

[3] -8-V

Table 7. Enable circuit

VCC(3V3) = 2.7 V to 5.5 V; GND = 0 V; Tamb =25

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Board side: input pin ENABLE[1]

VIH HIGH-level input voltage HIGH = enable 0.7 × VCC(3V3) -V

CC(5V0) + 0.5 V

VIL LOW-level input voltage LOW = disable −0.5 - 0.3 × VCC(3V3) V

IIL LOW-level input current VI=0.2V;

VCC(3V3) =5.5V -10-μA

ILI input leakage current −1+0.1+1μA

Ciinput capacitance VI=3V or 0V - 3 7 pF

Product data sheet Rev. 3 — 3 1 March 2011 10 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

9. Dynamic characteristics

[1] Typical values were measured with VCC(3V3) = 3.3 V; VCC(5V0) =5.0V.

[2] Pin ENABLE should only change state when the DDC bus is in an idle state.

Table 8. hot plug control circuit

VCC(5V0) = 4.5 V to 5.5 V; VCC(3V3) = 2.7 V to 5.5 V; GND = 0 V; Tamb =25

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Board side: input pin HOT_PLUG_DET _IN

VIH HIGH-level input voltage HIGH = hot plug off 0.7 × VCC(3V3) -V

CC(5V0) + 0.5 V

VIL LOW-level input voltage LOW = hot plug on −0.5 - 0.3 × VCC(3V3) V

IIL LOW-level input current VI=2.0V; V

CC(3V3) =5.5V - 10 - μA

ILI input leakage curren t −1+0.1+1μA

Ciinput capacitance VI=3V or 0V - 4 7 pF

Connector side: output pin HOT_PLUG_DET_OUT

ILI input leakage curren t −1+0.1+1μA

Ciinput capacitance VI=3V or 0V - 6 7 pF

Von on-state voltage II= 5 mA - 400 - mV

Table 9. DDC circuits

VCC(3V3) = 2.7 V to 5.5 V; VCC(5V0) = 4.5 V to 5.5 V; GND = 0 V; Tamb =25

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Board side to connector side; see Figure 4

Pins DDC_CLK_IN to DDC_CLK_OUT and DDC_DAT_IN to DDC_DAT_OUT

tPLH LOW to HIGH propagation delay [1] 150 270 300 ns

tPHL HIGH to LOW propagation delay [1] 125 210 225 ns

Pins DDC_CLK_OUT and DDC_DAT_OUT

tTLH LOW to HIGH transition time RL=1.35kΩ; CL= 50 pF 90 110 130 ns

tTHL HIGH to LOW transition time [1] 235ns

Connector side to board side; see Figure 5

Pins DDC_CLK_OUT to DDC_CLK_ IN and DDC_DAT_OUT to DDC_DAT_IN

tPLH LOW to HIGH propagation delay 90 110 130 ns

tPHL HIGH to LOW propagation delay [1] 20 30 40 ns

Pins DDC_CLK_IN and DDC_DAT_IN

tTLH LOW to HIGH transition time 100 120 140 ns

tTHL HIGH to LOW transition time [1] 235ns

Enable: pin ENABLE

tsu set-up time pin ENABLE = HIGH before start

condition [2] 100 - - ns

thhold time pin ENABLE = HIGH after stop

condition [2] 100 - - ns

Product data sheet Rev. 3 — 3 1 March 2011 11 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

9.1 AC Waveforms

a. Propagation delay tPLH

(1) Dotted line indicates effect without slew rate accelerator.

b. Propagation delay tPHL and transition time

Fig 4. Board side to connector side operation

001aag03

1.5 V

tPLH

0.7 V

input: board side

3.3 V

5.0 V

output: connector side

001aag03

2.5 V

0.1 V

(1)

5.0 V

3.3 V

20 %

VOL

80 %

1.65 V

input: board side

output: connector side

0.3VCC(5V0)

tTHL tTLH

tPHL tPLH

Product data sheet Rev. 3 — 3 1 March 2011 12 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

10. Application information

10.1 TMDS

To protect the TMDS lines and also to comply with the impedance requirements of the

HDMI specification, the IP4778CZ38 provides ESD protection with a low capacitive load.

The dominant value for the TMDS line impedance is the cap acitive load to ground. The

IP4778CZ38 has a cap acitive load of only 0.7 pF.

Propagation delay output to input and transition time input

Fig 5. Connecto r side to board side operation

001aag03

1.65 V

VOL

3.3 V

5.0 V

20 %

VIL

80 %

0.3VCC(5V0)

output: connector side

input: board side

tTHL tTLH

tPLH

tPHL

Fig 6. ESD prot ection of TMDS lines

001aag03

TMDS_D2+ TMDS_D1+ TMDS_D0+TMDS_BIAS

TMDS_GND

TMDS_CLK+

TMDS_CLK−TMDS_D0−TMDS_D1−TMDS_D2−

CC(5V0)

Product data sheet Rev. 3 — 3 1 March 2011 13 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

10.2 DDC circuit

The DDC-bus circuit conta ins full capa citive decoupling between the HDM I connector and

the DDC-bus lines on the PCB. The capacitive decoupling ensures that the maximum

capacitive load is within the 50 pF maximum of the HDMI specification.

The slew rate accelerator supp orts high capacitive load on the HDMI cable side. Various

HDMI cable suppliers produce low-cost and long (typically 25 m) HDMI cables with a

capacitive load of up to 6 nF.

The slew rate accelerator boosts the DDC signal independent of which side of the bus is

releasing the signal. The DDC module provides a level shifting and a multiplex option

which is enabled by the ENABLE si gn al.

a. DDC clock b. DDC data

Fig 7. DDC circuit

001aag040

SLEW

RATE

ACCELERATOR

ENABLE

DDC_CLK_IN

TMDS_BIAS VCC(5V0)

DDC_CLK_OUT

001aag041

SLEW

RATE

ACCELERATOR

ENABLE

DDC_DAT_IN

TMDS_BIAS V

CC(5V0)

DDC_DAT_OUT

(1) Dotted line indicates effect without slew rate accelerator.

Fig 8. DDC output waveform

001aag04

(1) (1)

0.3VCC(5V0)

5.0 V

Product data sheet Rev. 3 — 3 1 March 2011 14 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

10.3 Hot plug driver circuit

The IP4778CZ38 includes a ho t plug driver circuit that simplifies the hot plug application.

The circuit can be connected directly to GPIO pins.

The hot plug control input is actively pulled LOW to ensure that at system standby or

start-up, the hot plug signal is HIGH even if a GPIO pin is in a 3-state condition.

For correct CEC handling, it is essential that the hot plug signa l is at HIGH - lev el in

Standby mode. The HDMI source requires a hot plug signal so that it can read out the

EDID information to initiate a proper start-up CEC sequence.

Fig 9. Hot plug driver circuit

001aag043

10 μA

HOT_PLUG_DET_INHOT_PLUG_DET_OUT

VCC(5V0) VCC(3V3)

TMDS_BIAS

Product data sheet Rev. 3 — 3 1 March 2011 15 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

10.4 CEC

The CEC signal can generate distor tions caused b y signal ringing in a 1 kHz domain. The

CEC slew rate limiter ensures that a signal does n ot ri ng independently of the CEC slave

that is releasing th e signa l .

A MOSFET transistor implements the backdrive protection which blocks signals during a

power-down state.

The slew rate of the CEC bus is controlled by a slew rate that is defined independently of

the load (ohmic and capacitive) at the CEC bus.

Fig 10. CEC module

SLEW

RATE

LIMITER

001aag044

VCC(3V3)

TMDS_BIAS

CEC_OUT CEC_IN

(1) Dotted line indicates effect without slew rate limiter.

Fig 11. CEC output waveform

001aag04

(1)

0.8 V

(1)

Product data sheet Rev. 3 — 3 1 March 2011 16 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

10.5 Multiplexing

Up to four HDMI interface ports can exist on an HDMI receiver. The DDC and hot plug

signals are both needed to support vario us HDMI co nnectors, multiplexing and switching

of the TMDS lines. The CEC bus has to remain functional in order to detect activity such

as a brake in support.

The combination of a TMDS switch and the IP4778CZ38 is a cost-effective way to attain

various HDMI ports by using a single input HDMI receiver device. The ENABLE signal

activates the HDMI DDC and hot plug lines at the port that is selected by the system

controller.

Fig 12. Example of multiplexing both DDC and hot plug

001aag04

ENABLE

DDC_CLK_IN

DDC_DAT_IN

HOT_PLUG_DET_IN

ENABLE

DDC_CLK_IN

DDC_DAT_IN

HOT_PLUG_DET_IN

ENABLE

DDC_CLK_IN

DDC_DAT_IN

HOT_PLUG_DET_IN

DDC_CLK_IN

DDC_DAT_IN

HOT_PLUG_DET_IN

input 1

input 2

input 3

Product data sheet Rev. 3 — 3 1 March 2011 17 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

10.6 Backdrive protection

The HDMI contains various signals which can partly supply current into an HDMI device

that is powered do wn.

Typic ally, the DDC lines and the CEC signals can force 5 V into the switched-off device.

The IP4778CZ38 ensures that at power-down, the critical signals are blocked to prevent

any damage to the HDMI sink and HDMI source.

Fig 13. Backdrive protection

001aag04

HDMI ASIC

HDMI source

supply off 5 V

backdrive current

I2C-bus ASIC

HDMI sink

Product data sheet Rev. 3 — 3 1 March 2011 18 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

10.7 Application schematic

Figure 14 shows a typical application where the IP4778CZ38 provides a simplified

interface to an HDMI port. This application requires only a few external components to

adapt the HDMI port to the parameters of the HDMI receiver device or HDMI multiplexer.

Fig 14. Schematic of IP4778CZ 38 application

001aah83

1.5

kΩ

1.5

kΩ

100

kΩ

100 Ω

kΩ

1 μF

1 kΩ

kΩ

BAV40

ENABLE

u/c: >3V3 = enabled

0V = disabled

TMDS_D2+

TMDS_D2−

7TMDS_D1+

8TMDS_D1−

10IP4778CZ38

EDID

TMDS_D0+

TMDS_D0−

13TMDS_CLK+

14TMDS_CLK−

CEC_IN

DDC_CLK_IN

DDC_DAT_IN

HDMI

CONNECTOR

VCC(5V0) VCC(3V3)

3, 6, 9, 12, 15,

24, 27, 30, 33, 36

TMDS_D2+

TMDS_D2−

TMDS_D1+

TMDS_D1−

TMDS_D0+

TMDS_D0−

TMDS_CLK+

TMDS_CLK−

CEC

DDC_CLK

DDC_DAT

HOTPLUG_DET

+5 V

7, 8

51, 2, 3, 4

HOT_PLUG_DET_IN

Product data sheet Rev. 3 — 3 1 March 2011 19 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

10.8 Typical application

This application ensures that the EDID (stored in the EEPROM) can be read out in

S t andby mode, e ven if long cables are used, to guarantee correct CEC wake-up handling.

To wake up the system from Standby to normal operation, the HDMI source has to first

read the EDID in order to hand ove r the port ID via the CEC protocol. This ensures that

the HDMI starts up and switches to the correct HDMI port to display the HDMI source

which initiates the CEC wake-up sequence.

The CEC bus is enabled by ac tiva tin g th e VCC(3V3) standby supply.

The RF routing optimized pin position variant allows optimum design layout of the RF

routing microstrip s to ensure that the impedance of the TMDS lines remain within the

specification limits. Part of the microstrip s comprise a solid ground plane which is located

beneath the device.

Fig 15. Applica tion showing opti mize d PCB mic ro s trip lines

8765

1234

EDID

001aag049

IP4778CZ38

HDMI

connector

TMDS_D2+

TMDS_D2−

TMDS_D1+

TMDS_D1−

TMDS_D0+

TMDS_D0−

TMDS_CLK+

TMDS_CLK−

CEC_IN

DDC_CLK_IN

DDC_DAT_IN

HOT_PLUG_DET_IN

+3.3 V

Rdata

1.5 kΩ

Rclock

1.5 kΩ

RCEC

100 kΩ

RCEC

27 kΩ

Rdata

47 kΩ

Rclock

47 kΩ

ENABLE

VCC(5V0)

VCC(3V3) stand by

TMDS_D2+

TMDS_GND

TMDS_D2−

TMDS_D1+

TMDS_GND

TMDS_D1−

TMDS_D0+

TMDS_GND

TMDS_D0−

TMDS_CLK+

TMDS_GND

TMDS_CLK−

CEC

n.c.

DDC_CLK

DDC_DAT

GND

+5 V

HOTPLUG_DET

RDDC

100 Ω

RHP

1 kΩ

+5.0 V

Product data sheet Rev. 3 — 3 1 March 2011 20 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

11. Test information

See Table 10 for test data.

Rterm = termination resistance should be equal to output impedance Zo of the pulse generator.

RL = load resistance.

CL = load capacitance.

Fig 16. Test circuit for DDC and CEC lines

Table 10. Test data

Test RLCLVCC

DDC lines 1.35 kΩ50 pF VCC(5V0)

CEC line 27 kΩ50 pF VCC(3V3)

001aah46

DUT

Rterm

VCC

VCC(3V3)

VCC(5V0)

Product data sheet Rev. 3 — 3 1 March 2011 21 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

12. Package outline

Fig 17. Package outline SOT510-1 (TSSOP38)

UNIT A1A2A3bpcD

(1) E(2) eH

ELL

pZ(1)

ywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05

0.08

DIMENSIONS (mm are the original dimensions).

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

SOT510-1 03-02-18

05-11-02

detail X

(A )

0.25

119

38 20

0.95

0.85

0.27

0.17

0.20

0.09

9.8

9.6

4.5

4.3 0.5 1 0.2

6.4 0.49

0.21

0.08

0.7

0.5

EvMA

SSOP38: plastic thin shrink small outline package; 38 leads; body width 4.4 mm;

ead pitch 0.5 mm SOT510

-1

max.

1.1

2.5

5 mm

scale

pin 1 index

MO-153

Product data sheet Rev. 3 — 3 1 March 2011 22 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-h ole and

Surface Mount Devices (SMDs) are mixed on on e printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reflow soldering

W ave soldering is a joining te chnology in which the joints are m ade by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solde r lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads ha ving a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solde rable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering ve rsus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 3 — 3 1 March 2011 23 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

13.4 Reflow soldering

Key characteristics in reflow soldering are :

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 18) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) an d cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on p ackage thickness and volume and is classified in accordance with

Table 11 an d 12

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 18.

Table 11. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 12. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 3 — 3 1 March 2011 24 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

For further informa tion on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

14. Abbreviations

15. Glossary

HDMI sink — Device which receives HDMI signals e.g. a TV set.

HDMI source — Device which transm it H DM I sign al e. g. a DVD playe r.

MSL: Moisture Sensitivity Level

Fig 18. Temperature profiles for large and small components

001aac84

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 13. Abbreviations

Acronym Description

CEC Consumer Electronics Control

DDC Data Display Channel

DVD Digital Video Disk

DVI Digital Video Interface

EDID Extended Display Identification Data

EEPROM Electrically Erasable Programmable Read-Only Memory

ESD ElectroStatic Discharge

FET Field-Effect Transistor

GPIO General Purpose Input/Output

HDMI High-Definition Multimedia Interface

MOSFET Metal Oxide Semiconductor Field Effect Transistor

RoHS Restriction of Hazardous Substances

TMDS Transition Minimized Differential Signaling

Product data sheet Rev. 3 — 3 1 March 2011 25 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

16. Revision history

Table 14. Revision history

Document ID Release date Data sheet status Change notice Supersedes

IP4778CZ38 v.3 20110331 Product data sheet - IP4778CZ38 v.2

Modifications: •Section 1 “General description”: updated.

•Section 2 “Features and benefits”: updated.

•Section 14 “Abbreviations”: updated.

•Section 17 “Legal information”: updated.

IP4778CZ38 v.2 20090212 Product data sheet - IP4778CZ38 v.1

IP4778CZ38 v.1 20080410 Objective data sheet - -

Product data sheet Rev. 3 — 3 1 March 2011 26 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

17.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

17.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability t owards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descripti ons, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suit able for use in life support, life-crit ical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expect ed

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or application s and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associate d with t heir

applications and products.

NXP Semiconductors does not accept any liabil i ty related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the appl ication or use by customer’s

third party custo m er(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property right s.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contain s data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 3 — 3 1 March 2011 27 of 28

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors prod uct is automotive qualified,

the product is not suitable for automo tive use. It i s neit her qua lif ied nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifi cations, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting f rom customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specif ications.

17.4 Licenses

17.5 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Purchase of NXP ICs with HDMI technology

Use of an NXP IC with HDMI technology in equipment that co mplies with

the HDMI standard requires a license from HDMI Licensing LLC, 1060 E.

Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail:

admin@hdmi.org.

NXP Semiconductors IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 31 March 2011

Document identifier: IP4778CZ38

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

19. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6

8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7

9 Dynamic characteristics . . . . . . . . . . . . . . . . . 10

9.1 AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 11

10 Application information. . . . . . . . . . . . . . . . . . 12

10.1 TMDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

10.2 DDC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

10.3 Hot plug driver circuit . . . . . . . . . . . . . . . . . . . 14

10.4 CEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

10.5 Multiplexing. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

10.6 Backdrive protection. . . . . . . . . . . . . . . . . . . . 17

10.7 Application schematic. . . . . . . . . . . . . . . . . . . 18

10.8 Typical application . . . . . . . . . . . . . . . . . . . . . 19

11 Test information. . . . . . . . . . . . . . . . . . . . . . . . 20

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21

13 Soldering of SMD packages . . . . . . . . . . . . . . 22

13.1 Introduction to soldering . . . . . . . . . . . . . . . . . 22

13.2 Wave and reflow soldering . . . . . . . . . . . . . . . 22

13.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 22

13.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 23

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 24

15 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 25

17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 26

17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26

17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 26

17.4 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

17.5 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27

18 Contact information. . . . . . . . . . . . . . . . . . . . . 27

19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28