1. Product profile
1.1 General description
180 W LDMOS power transistor for various applications such as ISM and industrial
heating at freque n c ies fro m 24 00 MHz to 2500 M Hz.
1.2 Features and benefits
Easy power control
Integrated ESD protection
High efficiency
Excellent thermal stability
Designed for broadband operation (2400 MHz to 2500 MHz)
Internally matched for ease of use
Compliant to Directive 2002/95/EC, rega rd in g Re stri ctio n of Hazard ou s Sub stances
(RoHS)
1.3 Applications
RF power amplifiers for CW applications in the 2400 MHz to 2500 MHz frequency
range such as ISM and industrial heating.
BLF2425M6L180P;
BLF2425M6LS180P
Power LDMOS transistor
Rev. 3 — 12 July 2013 Product data sheet
Table 1. Typical performance
RF performance at Tcase = 25
C in a common source class-AB production test circuit.
Test signal f IDq VDS PL(AV) GpD
(MHz) (mA) (V) (W) (dB) (%)
CW 2450 10 28 180 13.3 53.5
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Product data sheet Rev. 3 — 12 July 2013 2 of 12
NXP Semiconductors BLF2425M6L(S)180P
Power LDMOS transistor
2. Pinning information
[1] Connected to flange.
3. Ordering information
4. Limiting values
Table 2. Pinning
Pin Description Simplified outline Graphic symbol
BLF2425M6L180P (SOT539A)
1drain1
2drain2
3gate1
4gate2
5source [1]
BLF2425M6LS180P (SOT539B)
1drain1
2drain2
3gate1
4gate2
5source [1]
5
12
43
4
35
1
2sym117
5
12
43
4
35
1
2sym117
Tabl e 3. Ordering information
Type number Package
Name Description Version
BLF2425M6L180P - flanged balanced ceramic package; 2 mounting holes;
4 leads SOT539A
BLF2425M6LS180P - earless flanged balanced ceramic package; 4 leads SOT539B
Table 4. Limitin g values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage - 65 V
VGS gate-source voltage 0.5 +13 V
Tstg storage temperature 65 +150 C
Tjjunction temperature - 225 C
BLF2425M6L180P_25M6LS180P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 12 July 2013 3 of 12
NXP Semiconductors BLF2425M6L(S)180P
Power LDMOS transistor
5. Thermal characteristics
6. Characteristics
7. Test information
7.1 Ruggedness in class-AB operation
The BLF2425M6L180P and BLF2425M6LS180P are capable of withstanding a load
mismatch corresponding to VSWR = 5 : 1 through all phases under the following
conditions: VDS =28V; I
Dq =10mA; P
L = 180 W (CW); f = 2450 MHz.
Table 5. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-case) thermal resistance from junction to case Tcase =80C; PL= 180 W 0.38 K/W
Table 6. DC ch aracteristics
Tj = 25
C per section; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V(BR)DSS drain-source breakdown
voltage VGS =0V; I
D=1.44mA65--V
VGS(th) gate-source threshold voltage VDS =10 V; I
D= 144 mA 1.4 1.8 2.4 V
IDSS drain leakage current VGS =0V
VDS =28V --3A
VDS =65V --5A
IDSX drain cut-off current VGS =V
GS(th) +3.75 V;
VDS =10V -24-A
IGSS gate leakage current VGS =11 V; V
DS = 0 V - - 300 nA
gfs forward transcondu ctance VDS =10V; I
D=7.2A - 10 - S
RDS(on) drain-source on-state
resistance VGS =V
GS(th) + 3.75 V;
ID=5A -0.1-
Table 7. RF characteristics
Test signal: CW; f = 2450 MHz; VDS = 28 V; IDq = 10 mA; Tcase = 25
C unless otherwise specified in
a class-AB production test circuit.
Symbol Parameter Conditions Min Typ Max Unit
Gppower gain PL= 180 W 11.0 13.3 - dB
Ddrain efficiency PL= 180 W 50 53.5 - %
RLin input return loss PL=180 W - 15 9dB
BLF2425M6L180P_25M6LS180P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 12 July 2013 4 of 12
NXP Semiconductors BLF2425M6L(S)180P
Power LDMOS transistor
7.2 Impedance information
Table 8. Typical impedance
Measured load-pull data. Typical values per section.
ZS and ZL defined in Figure 1.
f ZSZL
(MHz) () ()
2400 5.9 j8.0 2.8 j3.1
2450 8.4 j7.6 2.5 j3.1
2500 10.6 j5.8 2.3 j3.0
Fig 1. Definition of transis tor imp e danc e
001aaf059
drain
Z
L
Z
S
gate
BLF2425M6L180P_25M6LS180P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 12 July 2013 5 of 12
NXP Semiconductors BLF2425M6L(S)180P
Power LDMOS transistor
7.3 Test circuit
[1] American technical ceramics type 100A or capacitor of same quality.
[2] American technical ceramics type 800B or capacitor of same quality.
[3] American technical ceramics type 100B or capacitor of same quality.
Striplines are on a double copper-clad Rogers R04350 Printed-Circuit Board (PCB) with r = 3.5
and thickness = 0.508 mm.
See Table 9 for list of components.
Fig 2. Component layou t for test circuit
Table 9. List of components
For test circuit, see Figure 2.
Component Description Value Remarks
C1, C2, C3 multilayer ceramic chip capacitor 15 pF [1]
C4, C5, C10, C11 multilayer ceramic chip capacitor 220 nF SMD 1206
C6, C12, C13 multilayer ceramic chip capacitor 4.7 F
C7 multilayer ceramic chip capacitor 39 pF [2]
C8, C9 multilayer ceramic chip capacitor 6.8 pF [3]
C14 electrolytic capacitor 220 F, 63 V
R1, R2 chip resistor 6.2 SMD 1206
aaa-002274
C3
C1
C6
C13C11
C9
C12
C14
C10
C8
C5
R1
C4
R2
C7
C2
BLF2425M6L180P_25M6LS180P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 12 July 2013 6 of 12
NXP Semiconductors BLF2425M6L(S)180P
Power LDMOS transistor
7.4 Graphical data
VDS = 28 V; IDq = 10 mA.
(1) f = 2400 MHz
(2) f = 2450 MHz
(3) f = 2500 MHz
VDS = 28 V; IDq = 10 mA.
(1) f = 2400 MHz
(2) f = 2450 MHz
(3) f = 2500 MHz
Fig 3. Power gain and drain efficiency as function of
load power; typical values Fig 4. Power gain and drain efficiency as function of
load power; typical values
DDD
       

 

 
 
 
 
3/:
*S
*S
G%G%G%
Ș'
Ș'







*S
*SȘ'
Ș'
DDD
      

 

 
 
 
 
3/G%P
*S
*S
G%G%G%
Ș'
Ș'







*S
*S
Ș'
Ș'
BLF2425M6L180P_25M6LS180P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 12 July 2013 7 of 12
NXP Semiconductors BLF2425M6L(S)180P
Power LDMOS transistor
8. Package outline
Fig 5. Package outline SOT539A
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
SOT539A 12-05-02
10-02-02
0 5 10 mm
scale
p
AF
b
e
D
U2
L
H
Q
c
5
12
43
D1
E
A
w1AB
M M M
q
U1
H1
C
B
M M
w2C
E1
M
w3
UNIT A
mm
Db
11.81
11.56 0.18
0.10 31.55
30.94 13.72 9.53
9.27 17.12
16.10 10.29
10.03
4.7
4.2
ce U2
0.250.25 0.51
w3
35.56
qw
2
w1
F
1.75
1.50
U1
41.28
41.02
H1
25.53
25.27
p
3.30
3.05
Q
2.26
2.01
EE
1
9.50
9.30
inches 0.465
0.455 0.007
0.004 1.242
1.218
D1
31.52
30.96
1.241
1.219 0.540 0.375
0.365 0.674
0.634 0.405
0.395
0.185
0.165 0.0100.010 0.0201.400
0.069
0.059 1.625
1.615
1.005
0.995 0.130
0.120 0.089
0.079
0.374
0.366
H
3.48
2.97
0.137
0.117
L
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
Flanged balanced ceramic package; 2 mounting holes; 4 leads SOT539A
Note
1. millimeter dimensions are derived from the original inch dimensions.
2. recommended screw pitch dimension of 1.52 inch (38.6 mm) based on M3 screw.
BLF2425M6L180P_25M6LS180P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 12 July 2013 8 of 12
NXP Semiconductors BLF2425M6L(S)180P
Power LDMOS transistor
Fig 6. Package outline SOT539B
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT539B
sot539b_po
12-05-02
13-05-24
Unit(1)
mm max
nom
min
4.7
4.2
11.81
11.56
31.55
30.94
31.52
30.96
9.5
9.3
9.53
9.27
1.75
1.50
17.12
16.10
3.48
2.97
10.29
10.03 0.25
A
Dimensions
Earless flanged balanced ceramic package; 4 leads SOT539B
bc
0.18
0.10
DD
1EE
1e
13.72
FHH
1
25.53
25.27
LQ
2.26
2.01
U1
32.39
32.13
U2w2
0.25
inches max
nom
min
0.185
0.165
0.465
0.455
1.242
1.218
1.241
1.219
0.374
0.366
0.375
0.365
0.069
0.059
0.674
0.634
0.137
0.117
0.405
0.395 0.01
0.007
0.004 0.54 1.005
0.995
0.089
0.079
1.275
1.265 0.01
w3
0 5 10 mm
scale
c
E
Q
E1
e
H
L
b
H1
U1
U2
Dw2
w3
1 2
3 4
D
D
AF
D1
5
Note
1. millimeter dimensions are derived from the original inch dimensions.
BLF2425M6L180P_25M6LS180P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 12 July 2013 9 of 12
NXP Semiconductors BLF2425M6L(S)180P
Power LDMOS transistor
9. Handling information
10. Abbreviations
11. Revision history
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
Table 10. Abbreviations
Acronym Description
CW Continuous Wave
ESD ElectroStatic Discharge
ISM Industrial, Scientific and Medical
LDMOS Laterally Diffused Metal-Oxide Semiconductor
SMD Surface Mounted Device
VSWR Voltage Standing-Wave Ratio
Table 11. Revision history
Document ID Release
date Data sheet status Change
notice Supersedes
BLF2425M6L180P_25M6LS180P v.3 20130712 Product data sheet - BLF2425M6L180P_25 M6LS180P v.2
Modifications: The package outline Figure 6 is updated.
BLF2425M6L180P_25M6LS180P v.2 20120920 Product data sheet - BLF2425M6L180P_25 M6LS180P v.1
Modifications: The status of this document has been changed to Product data sheet.
Table 1 on page 1: several changes have been made.
Section 1.2 on page 1: several changes have been ma de.
Table 4 on page 2: an item has been removed.
Table 6 on page 3: several changes have been made.
Table 7 on page 3: several changes have been made.
Section 7.1 on page 3: a value has been added.
Section 7.4 on page 6: this section has been added.
BLF2425M6L180P_25M6LS180P v.1 20120207 Objective data sheet - -
BLF2425M6L180P_25M6LS180P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 12 July 2013 10 of 12
NXP Semiconductors BLF2425M6L(S)180P
Power LDMOS transistor
12. Legal information
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[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
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the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
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Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contain s data from the preliminary specification.
Product [short] dat a sheet Production This document contain s the product specification.
BLF2425M6L180P_25M6LS180P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 12 July 2013 11 of 12
NXP Semiconductors BLF2425M6L(S)180P
Power LDMOS transistor
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13. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors BLF2425M6L(S)180P
Power LDMOS transistor
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12 July 2013
Document identifier: BLF 2425M6L180P_25M6LS180P
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
14. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Thermal characteristics . . . . . . . . . . . . . . . . . . 3
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 3
7.1 Ruggedness in class-AB operation . . . . . . . . . 3
7.2 Impedance information. . . . . . . . . . . . . . . . . . . 4
7.3 Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
7.4 Graphical data . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
9 Handling information. . . . . . . . . . . . . . . . . . . . . 9
10 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . 9
11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 9
12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10
12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10
12.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
12.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
12.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
13 Contact information. . . . . . . . . . . . . . . . . . . . . 11
14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12