VND7004AY Double channel high-side driver with MultiSense analog feedback for automotive applications Datasheet - production data Configurable latch-off on overtemperature or power limitation with dedicated fault reset pin Loss of ground and loss of VCC Reverse battery with self switch of the PowerMOS Electrostatic discharge protection Applications Features Specially intended for Automotive smart power distribution, glow plugs, heating systems, DC motors, relay replacement and high power resistive and inductive actuators. Max transient supply voltage VCC 40 V Operating voltage range VCC 4 to 28 V Typ. on-state resistance (per Ch) RON 4 m Description Current limitation (typ) ILIMH 100 A Standby current (max) ISTBY 0.5 A The device is a double channel high-side driver manufactured using ST proprietary VIPower(R) M0 7 technology and housed in PowerSSO-36 package. The device is designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOS-compatible interface, providing protection and diagnostics. AEC-Q100 qualified General Double channel smart high-side driver with MultiSense analog feedback Very low standby current Compatible with 3 V and 5 V CMOS outputs MultiSense diagnostic functions Multiplexed analog feedback of: load current with high precision proportional current mirror, VCC supply voltage and TCHIP device temperature Overload and short to ground (power limitation) indication Thermal shutdown indication OFF-state open-load detection Output short to VCC detection Sense enable/disable Protections Undervoltage shutdown Overvoltage clamp Load current limitation Self limiting of fast thermal transients June 2017 The device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off. A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality. A dedicated multifunction multiplexed analog output pin delivers sophisticated diagnostic functions including high precision proportional load current sense, supply voltage feedback and chip temperature sense, in addition to the detection of overload and short circuit to ground, short to VCC and OFF-state open-load. A sense enable pin allows OFF-state diagnosis to be disabled during the module low-power mode as well as external sense resistor sharing among similar devices. DocID027772 Rev 11 This is information on a product in full production. 1/47 www.st.com Contents VND7004AY Contents 1 Block diagram and pin description ................................................ 5 2 Electrical specification .................................................................... 7 3 4 5 2.1 Absolute maximum ratings ................................................................ 7 2.2 Thermal data ..................................................................................... 8 2.3 Main electrical characteristics ........................................................... 8 2.4 Waveforms ...................................................................................... 20 2.5 Electrical characteristics curves ...................................................... 22 Protections..................................................................................... 26 3.1 Power limitation ............................................................................... 26 3.2 Thermal shutdown ........................................................................... 26 3.3 Current limitation ............................................................................. 26 3.4 Negative voltage clamp ................................................................... 26 Application information ................................................................ 27 4.1 GND protection network against reverse battery............................. 27 4.2 Immunity against transient electrical disturbances .......................... 28 4.3 MCU I/Os protection ........................................................................ 28 4.4 Multisense - analog current sense .................................................. 29 4.4.1 Principle of Multisense signal generation ......................................... 30 4.4.2 TCASE and VCC monitor ................................................................. 32 4.4.3 Short to VCC and OFF-state open-load detection ........................... 33 Package and PCB thermal data .................................................... 34 5.1 PowerSSO-36 thermal data ............................................................ 34 6 Maximum demagnetization energy (VCC = 16 V) ........................ 38 7 Package information ..................................................................... 39 8 9 2/47 7.1 PowerSSO-36 package information ................................................ 39 7.2 PowerSSO-36 packing information ................................................. 41 7.3 PowerSSO-36 marking information ................................................. 43 Order codes ................................................................................... 44 Revision history ............................................................................ 45 DocID027772 Rev 11 VND7004AY List of tables List of tables Table 1: Pin functions ................................................................................................................................. 5 Table 2: Suggested connections for unused and not connected pins ........................................................ 6 Table 3: Absolute maximum ratings ........................................................................................................... 7 Table 4: Thermal data ................................................................................................................................. 8 Table 5: Power section ............................................................................................................................... 8 Table 6: Switching..................................................................................................................................... 10 Table 7: Logic inputs ................................................................................................................................. 10 Table 8: Protections .................................................................................................................................. 11 Table 9: MultiSense .................................................................................................................................. 12 Table 10: Truth table ................................................................................................................................. 19 Table 11: MultiSense multiplexer addressing ........................................................................................... 19 Table 12: ISO 7637-2 - electrical transient conduction along supply line ................................................. 28 Table 13: MultiSense pin levels in off-state .............................................................................................. 32 Table 14: PCB properties ......................................................................................................................... 35 Table 15: Thermal parameters ................................................................................................................. 37 Table 16: PowerSSO-36 mechanical data................................................................................................ 39 Table 17: Reel dimensions ....................................................................................................................... 41 Table 18: PowerSSO-36 carrier tape dimensions .................................................................................... 42 Table 19: Device summary ....................................................................................................................... 44 Table 20: Document revision history ........................................................................................................ 45 DocID027772 Rev 11 3/47 List of figures VND7004AY List of figures Figure 1: Block diagram .............................................................................................................................. 5 Figure 2: Configuration diagram (top view)................................................................................................. 6 Figure 3: Current and voltage conventions ................................................................................................. 7 Figure 4: Switching time and Pulse skew ................................................................................................. 17 Figure 5: MultiSense timings (current sense mode) ................................................................................. 17 Figure 6: Multisense timings (chip temperature and VCC sense mode) .................................................. 18 Figure 7: TDSTKON.................................................................................................................................. 18 Figure 8: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) ........................ 20 Figure 9: Latch functionality - behavior in hard short circuit condition ...................................................... 20 Figure 10: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) .... 21 Figure 11: Standby mode activation ......................................................................................................... 21 Figure 12: Standby state diagram ............................................................................................................. 22 Figure 13: OFF-state output current ......................................................................................................... 22 Figure 14: Standby current ....................................................................................................................... 22 Figure 15: IGND(ON) vs. Iout ................................................................................................................... 22 Figure 16: Logic Input high level voltage .................................................................................................. 22 Figure 17: Logic Input low level voltage.................................................................................................... 23 Figure 18: High level logic input current ................................................................................................... 23 Figure 19: Low level logic input current .................................................................................................... 23 Figure 20: Logic Input hysteresis voltage ................................................................................................. 23 Figure 21: FaultRST Input clamp voltage ................................................................................................. 23 Figure 22: Undervoltage shutdown ........................................................................................................... 23 Figure 23: On-state resistance vs. Tcase ................................................................................................. 24 Figure 24: On-state resistance vs. VCC ................................................................................................... 24 Figure 25: Turn-on voltage slope .............................................................................................................. 24 Figure 26: Turn-off voltage slope .............................................................................................................. 24 Figure 27: Won vs. Tcase ......................................................................................................................... 24 Figure 28: Woff vs. Tcase ......................................................................................................................... 24 Figure 29: OFF-state open-load voltage detection threshold ................................................................... 25 Figure 30: Vsense clamp vs. Tcase.......................................................................................................... 25 Figure 31: Vsenseh vs. Tcase .................................................................................................................. 25 Figure 32: Application diagram ................................................................................................................. 27 Figure 33: Simplified internal structure ..................................................................................................... 27 Figure 34: MultiSense and diagnostic - block diagram ............................................................................ 29 Figure 35: MultiSense block diagram ....................................................................................................... 30 Figure 36: Analogue HSD - open-load detection in off-state ................................................................... 31 Figure 37: Open-load / short to VCC condition ......................................................................................... 32 Figure 38: GND voltage shift .................................................................................................................... 33 Figure 39: PowerSSO-36 PC board ......................................................................................................... 34 Figure 40: Rthj-amb vs PCB copper area in open box free air conditions ............................................... 35 Figure 41: PowerSSO-36 thermal impedance junction ambient single pulse .......................................... 36 Figure 42: Thermal fitting model for PowerSSO-36 .................................................................................. 36 Figure 43: Maximum turn off current versus inductance .......................................................................... 38 Figure 44: PowerSSO-36 package outline ............................................................................................... 39 Figure 45: PowerSSO-36 reel 13" ............................................................................................................ 41 Figure 46: PowerSSO-36 carrier tape ...................................................................................................... 42 Figure 47: PowerSSO-36 schematic drawing of leader and trailer tape .................................................. 43 Figure 48: PowerSSO-36 marking information ......................................................................................... 43 4/47 DocID027772 Rev 11 VND7004AY Block diagram and pin description Figure 1: Block diagram V CC Internal supply VCC - GND Clamp Undervoltage shut-down CH1 Channe l 1 Control & Di agno stic Channe l 0 VCC - OUT Clamp FaultRST CH0 INPUT 1 Gate Driver INPUT 0 SE L 1 T V CC OUTPUT 1 SE L 0 Current Limitation SE n Multisense MUX 1 Block diagram and pin description Power Limitation Overtemperature T Short to VCC Open-Loadin OFF Current Sense 0 GND Fault V SENSEH OUTPUT 0 Table 1: Pin functions Name VCC OUTPUT0,1 GND INPUT0,1 Function Battery connection. Power output. Ground connection. Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs. They control output switch state. MultiSense Multiplexed analog sense output pin; it delivers a current proportional to the selected diagnostic: load current, supply voltage or chip temperature. SEn Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the MultiSense diagnostic pin. SEL0,1 FaultRST Active high compatible with 3 V and 5 V CMOS outputs pin; they address the MultiSense multiplexer. Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in case of fault; If kept low, sets the outputs in auto-restart mode DocID027772 Rev 11 5/47 Block diagram and pin description VND7004AY Figure 2: Configuration diagram (top view) OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 N.C. N.C. N.C. SEn N.C. SEL1 SEL0 N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 TAB/Vcc 17 18 20 19 OUTPUT0 OUTPUT0 OUTPUT0 OUTPUT0 OUTPUT0 OUTPUT0 OUTPUT0 OUTPUT0 OUTPUT0 OUTPUT0 N.C. N.C. N.C. INPUT1 INPUT0 MultiSense GND FaultRST PowerSSO-36 Table 2: Suggested connections for unused and not connected pins SEn, SELx, Connection / pin MultiSense N.C. Floating Not allowed X (1) X X X To ground Through 1 k resistor X Not allowed Through 10 k resistor Through 10 k resistor Output Notes: (1)X: 6/47 do not care. DocID027772 Rev 11 Input FaultRST VND7004AY 2 Electrical specification Electrical specification Figure 3: Current and voltage conventions IS VCC FaultRST ISEn IOUT OUTPUT0,1 ISEL MultiSense VSEn SEL0,1 VSEL VOUT ISENSE SEn VFR VCC VFn IFR VSENSE IIN VIN INPUT0,1 IGND GAPGCFT00315 VF = VOUT - VCC when VOUT > VCC and INPUT = LOW. 2.1 Absolute maximum ratings Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Table 3: Absolute maximum ratings Symbol Parameter Value Unit VCC DC supply voltage 38 -VCC Reverse DC supply voltage 16 VCCPK Maximum transient supply voltage (ISO 7637-2:2004 Pulse 5b level IV clamped to 40 V; RL = 4 ) 40 V VCCJS Maximum jump start voltage for single pulse short circuit protection 28 V -IGND DC reverse ground pin current 200 mA IOUT OUTPUT0,1 DC output current Internally limited A -IOUT Reverse DC output current IIN INPUT0,1 DC input current ISEn SEn DC input current ISEL SEL0,1 DC input current IFR FaultRST DC input current VFR FaultRST DC input voltage DocID027772 Rev 11 V 65 -1 to 10 mA 7.5 V 7/47 Electrical specification VND7004AY Symbol Parameter Unit MultiSense pin DC output current (VGND = VCC and VSENSE < 0 V) 10 MultiSense pin DC output current in reverse (VCC < 0 V) -20 EMAX Maximum switching energy (single pulse) (TDEMAG = 0.4 ms; Tjstart = 150 C) 103 mJ VESD Electrostatic discharge (JEDEC 22A-114F) INPUT0,1 MultiSense SEn, SEL0,1, FaultRST OUTPUT0,1 VCC 4000 2000 4000 4000 4000 V V V V V VESD Charge device model (CDM-AEC-Q100-011) 750 V ISENSE Tj Tstg 2.2 Value mA Junction operating temperature -40 to 150 Storage temperature -55 to 150 C Thermal data Table 4: Thermal data Symbol Parameter Thermal resistance junction-board Rthj-board Rthj-amb Rthj-amb Typ. value (1) Unit 3.4 Thermal resistance junction-ambient (JEDEC JESD 51-5)(1)(2) 50.6 Thermal resistance junction-ambient (JEDEC JESD 51-7)(1)(3) 15.8 C/W Notes: (1)One 2.3 channel ON. (2)Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace (3)Device mounted on four-layers 2s2p PCB Main electrical characteristics 7 V < VCC < 28 V; -40C < Tj < 150C, unless otherwise specified. All typical values refer to VCC = 13 V; Tj = 25C, unless otherwise specified. Table 5: Power section Symbol Test conditions Min. Typ. Max. Unit 4 13 28 V VCC Operating supply voltage VUSD Undervoltage shutdown 4 V VUSDReset Undervoltage shutdown reset 5 V VUSDhyst Undervoltage shutdown hysteresis RON 8/47 Parameter On-state IOUT = 15 A; Tj = 25C DocID027772 Rev 11 0.3 V 4 m VND7004AY Electrical specification Symbol Parameter resistance(1) RON_REV Vclamp ISTBY tD_STBY IS(ON) IGND(ON) IL(off) VF Test conditions IOUT = 15 A; VCC = 4 V; Tj = 25C 6 Clamp voltage IS = 20 mA; 25C < Tj < 150C 41 46 52 0.5 VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1 = 0 V; Tj = 85C (3) 1.9 VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1 = 0 V; Tj = 125C 15 VCC = 13 V; VIN = VOUT = VFR = VSEL0,1 = 0 V; VSEn = 5 V to 0 V Supply current VCC = 13 V; VSEn = VFR = VSEL0,1 = 0 V; VIN0 = 5 V; VIN1 = 5 V; IOUT0 = 0 A; IOUT1 = 0 A Control stage current consumption in ON state. All channels active. VCC = 13 V; VSEn = 5 V; VFR = VSEL0,1 = 0 V; VIN0 = 5 V; VIN1 = 5 V; IOUT0,1 = 15 A 60 VIN = VOUT = 0 V; VCC = 13 V; Tj = 25C 0 VIN = VOUT = 0 V; VCC = 13 V; Tj = 125C 0 IOUT = -15 A; Tj = 150C Unit m 4 VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1 = 0 V; Tj = 25C Standby mode blanking time Output - VCC diode voltage Max. 8 IOUT = -15 A; VCC = -13 V; Tj = 25C Off-state output current (2) Typ. IOUT = 15 A; Tj = 150C On-state resistance in reverse battery Supply current in standby at VCC = 13 V (2) Min. V A 300 550 s 6 12 mA 12 mA 0.01 0.5 A 7.5 0.7 V Notes: (1)For each channel (2)PowerMOS (3)Parameter leakage included. specified by design; not subjected to production test. DocID027772 Rev 11 9/47 Electrical specification VND7004AY Table 6: Switching VCC = 13 V; -40C < Tj < 150C, unless otherwise specified Symbol Test conditions Parameter td(on)(1) Turn-on delay time td(off)(1) Turn-off delay time (dVOUT/dt)on(1) Turn-on voltage slope (dVOUT/dt)off(1) Turn-off voltage slope RL = 0.87 RL = 0.87 Min. Typ. Max. 60 110 195 50 100 160 0.05 0.21 0.35 0.05 0.21 0.35 Unit s V/s WON Switching energy losses at turn-on (twon) RL = 0.87 -- 2.3 3.7(2) mJ WOFF Switching energy losses at turn-off (twoff) RL = 0.87 -- 2.5 4.5(2) mJ tSKEW (1) Differential pulse skew (tPHL - tPLH) RL = 0.87 -65 0 65 s Notes: (1)See Figure 4: "Switching time and Pulse skew". (2)Parameter guaranteed by design and characterization; not subjected to production test. Table 7: Logic inputs 7 V < VCC < 28 V; -40C < Tj < 150C Symbol Parameter Test conditions Min. Typ. Max. Unit 0.9 V INPUT0,1 characteristics VIL Input low level voltage IIL Low level input current VIH Input high level voltage IIH High level input current VI(hyst) Input hysteresis voltage VICL Input clamp voltage VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA V 5.3 IIN = -1 mA A 7.2 -0.7 V FaultRST characteristics VFRL Input low level voltage IFRL Low level input current VFRH Input high level voltage IFRH High level input current VFR(hyst) Input hysteresis voltage VFRCL Input clamp voltage 0.9 VIN = 0.9 V A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA V 1 V 5.3 IIN = -1 mA A 7.5 -0.7 V SEL0,1 characteristics (7 V < VCC < 18 V) 10/47 VSELL Input low level voltage ISELL Low level input current VSELH Input high level voltage ISELH High level input current 0.9 VIN = 0.9 V VIN = 2.1 V DocID027772 Rev 11 V 1 A 2.1 V 10 A VND7004AY Electrical specification 7 V < VCC < 28 V; -40C < Tj < 150C Symbol VSEL(hyst) VSELCL Parameter Test conditions Input hysteresis voltage Min. Typ. Max. 0.2 IIN = 1 mA Input clamp voltage V 5.3 IIN = -1 mA Unit 7.2 -0.7 V SEn characteristics (7 V < VCC < 18 V) VSEnL Input low level voltage ISEnL Low level input current VSEnH Input high level voltage ISEnH High level input current VSEn(hyst) Input hysteresis voltage VSEnCL 0.9 VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Input clamp voltage V V 5.3 IIN = -1 mA A 7.2 -0.7 V Table 8: Protections 7 V < VCC < 18 V; -40C < Tj < 150C Symbol Parameter Test conditions ILIMH DC short circuit current VCC = 13 V ILIML Short circuit current during thermal cycling VCC = 13 V; TR < Tj < TTSD TTSD Shutdown temperature 4 V < VCC < 18 TR Reset temperature(1) TRS Thermal reset of fault diagnostic indication VFR = 0 V; VSEn = 5 V Thermal hysteresis (TTSD - TR)(1) TJ_SD Dynamic temperature Tj = -40C; VCC = 13 V Fault reset time for output unlatch VFR = 5 V to 0 V; VSEn = 5 V; VIN = 5 V; VSEL0,1 = 0 V VDEMAG Turn-off output voltage clamp Typ. 70 100 V(1) THYST tLATCH_RST Min. Max. Unit 140 A 33 150 175 TRS + 1 TRS + 7 200 C 135 7 60 3 IOUT = 2 A; L = 6 mH; Tj = 40C VCC 38 IOUT = 2 A; L = 6 mH; Tj = 25C to 150C VCC 41 10 K 20 s V VCC 46 VCC 52 V Notes: (1)Parameter guaranteed by design and characterization; not subjected to production test. DocID027772 Rev 11 11/47 Electrical specification VND7004AY Table 9: MultiSense 7 V < VCC < 18 V; -40C < Tj < 150C Symbol Parameter VSENSE_CL MultiSense clamp voltage Test conditions Min. VSEn = 0 V; ISENSE = 1 mA -17 Typ. Max. Unit -12 V VSEn = 0 V; ISENSE = -1 mA 7 Current sense characteristics K1 dK1/K1(1)(2) KGP dKGP/KGP(1)(2) K2 dK2/K2(1)(2) K3 dK3/K3(1)(2) ISENSE0 12/47 IOUT/ISENSE IOUT = 3.5 A; VSENSE = 4 V; VSEn = 5 V 5000 Current sense ratio drift IOUT = 3.5 A; VSENSE = 4 V; VSEn = 5 V -30 IOUT/ISENSE IOUT = 10 A; VSENSE = 4 V; VSEn = 5 V 7990 Current sense ratio drift IOUT = 10 A; VSENSE = 4 V; VSEn = 5 V -10 IOUT/ISENSE IOUT = 15 A; VSENSE = 4 V; VSEn = 5 V 9580 Current sense ratio drift IOUT = 15 A; VSENSE = 4 V; VSEn = 5 V -7 IOUT/ISENSE IOUT = 45 A; VSENSE = 4 V; VSEn = 5 V 11470 Current sense ratio drift IOUT = 45 A; VSENSE = 4 V; VSEn = 5 V -5 5 MultiSense disabled: VSEn = 0 V 0 0.5 MultiSense disabled: -1 V < VSENSE < 5 V(1) -0.5 0.5 MultiSense enabled: VSEn = 5 V; All channels ON; IOUTX = 0 A; ChX diagnostic selected; E.g. Ch0: VIN0 = 5 V; VIN1 = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT0 = 0 A; IOUT1 = 15 A 0 120 MultiSense enabled: VSEn = 5 V; ChX OFF; ChX diagnostic selected: E.g. Ch0: VIN0 = 0 V; VIN1 = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT1 = 15 A 0 MultiSense leakage current DocID027772 Rev 11 14200 31500 30 13900 21050 10 13850 % 19020 7 13800 % % 15840 % A 2 VND7004AY Electrical specification 7 V < VCC < 18 V; -40C < Tj < 150C Symbol Parameter Test conditions Min. Typ. Max. Unit Output Voltage for MultiSense shutdown VSEn = 5 V; RSENSE = 2.7 k; E.g. Ch0: VIN0 = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT0 = 15 A VSENSE_SAT Multisense saturation voltage VCC = 7 V; RSENSE = 2.7 k; VSEn = 5 V; VIN0 = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT0 = 45 A; Tj = 150C 5 V ISENSE_SAT(1) CS saturation current VCC = 7 V; VSENSE = 4 V; VIN0 = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; Tj = 150C 4 mA Output saturation current VCC = 7 V; VSENSE = 4 V; VIN0 = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; Tj = 150C 65 A VOL OFF-state openload voltage detection threshold VSEn = 5 V; ChX OFF; ChX diagnostic selected E.g: Ch0 VIN0 = 0 V; VSEL0 = 0 V; VSEL1 = 0 V 2 IL(off2) OFF-state output sink current VIN = 0 V; VOUT = VOL; Tj = -40C to 125C -100 tDSTKON OFF-state diagnostic delay time from falling edge of INPUT (see Figure 7: "TDSTKON") VSEn = 5 V; ChX ON to OFF transition; ChX diagnostic selected E.g: Ch0 VIN0 = 5 V to 0 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT0 = 0 A; VOUT = 4 V 100 tD_OL_V Settling time for valid OFF-state open load diagnostic indication from rising edge of SEn VIN0 = 0 V; VIN1 = 0 V; VFR = 0 V; VSEL0 = 0 V; VSEL1 = 0 V; VOUT0 = 4 V; VSEn = 0 V to 5 V VOUT_MSD(1) IOUT_SAT (1) 5 V OFF-state diagnostic DocID027772 Rev 11 3 350 4 V -15 A 700 s 60 s 13/47 Electrical specification VND7004AY 7 V < VCC < 18 V; -40C < Tj < 150C Symbol tD_VOL Parameter OFF-state diagnostic delay time from rising edge of VOUT Test conditions Min. VSEn = 5 V; ChX OFF; ChX diagnostic selected E.g: Ch0 VIN0 = 0 V; VSEL0 = 0 V; VSEL1 = 0 V; VOUT = 0 V to 4 V Typ. Max. Unit 5 30 s Chip temperature analog feedback VSENSE_TC dVSENSE_TC/dT(1) MultiSense output voltage proportional to chip temperature Temperature coefficient VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN0,1 = 0 V; RSENSE = 1 k; Tj = -40C 2.325 2.41 2.495 V VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN0,1 = 0 V; RSENSE = 1 k; Tj = 25C 1.985 2.07 2.155 V VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN0,1 = 0 V; RSENSE = 1 k; Tj = 125C 1.435 1.52 1.605 V Tj = -40C to 150C Transfer function -5.5 mV/K VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0) VCC supply voltage analog feedback VSENSE_VCC MultiSense output voltage proportional to VCC supply voltage Transfer function (3) VCC = 13 V; VSEn = 5 V; VSEL0 = 5 V; VSEL1 = 5 V; VIN0,1 = 0 V; RSENSE = 1 k 3.16 3.23 3.3 V 6.6 V 30 mA VSENSE_VCC = VCC / 4 Fault diagnostic feedback (see Table 10: "Truth table") VSENSEH MultiSense output voltage in fault condition VCC = 13 V; RSENSE = 1 k; E.g: Ch0 in open load VIN0 = 0 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT0 = 0 A; VOUT = 4 V ISENSEH MultiSense output current in fault condition VCC = 13 V; VSENSE = 5 V 5 7 20 MultiSense timings (current sense mode - see Figure 5: "MultiSense timings (current sense mode)")(4) tDSENSE1H 14/47 Current sense settling time from rising edge of SEn VIN = 5 V; VSEn = 0 V to 5 V; RSENSE = 1 k; RL = 0.87 DocID027772 Rev 11 60 s VND7004AY Electrical specification 7 V < VCC < 18 V; -40C < Tj < 150C Symbol Parameter Test conditions tDSENSE1L Current sense disable delay time from falling edge of SEn VIN = 5 V; VSEn = 5 V to 0 V; RSENSE = 1 k; RL = 0.87 tDSENSE2H Current sense settling time from rising edge of INPUT VIN = 0 V to 5 V; VSEn = 5 V; RSENSE = 1 k; RL = 0.87 tDSENSE2H Current sense settling time from rising edge of IOUT (dynamic response to a step change of IOUT) VIN = 5 V; VSEn = 5 V; RSENSE = 1 k; ISENSE = 90 % of ISENSEMAX; RL = 0.87 tDSENSE2L Current sense turn-off delay time from falling edge of INPUT VIN = 5 V to 0 V; VSEn = 5 V; RSENSE = 1 k; RL = 0.87 Min. Typ. Max. Unit 5 20 s 170 400 s 200 s 250 s 50 MultiSense timings (chip temperature sense mode - see Figure 6: "Multisense timings (chip temperature and VCC sense mode)")(4) tDSENSE3H VSENSE_TC settling time from rising edge of SEn VSEn = 0 V to 5 V; VSEL0 = 0 V; VSEL1 = 5 V; RSENSE = 1 k 60 s tDSENSE3L VSENSE_TC disable delay time from falling edge of SEn VSEn = 5 V to 0 V; VSEL0 = 0 V; VSEL1 = 5 V; RSENSE = 1 k 20 s MultiSense timings (VCC voltage sense mode - see Figure 6: "Multisense timings (chip temperature and VCC sense mode)")(4) tDSENSE4H VSENSE_VCC settling time from rising edge of SEn VSEn = 0 V to 5 V; VSEL0 = 5 V; VSEL1 = 5 V; RSENSE = 1 k 60 s tDSENSE4L VSENSE_VCC disable delay time from falling edge of SEn VSEn = 5 V to 0 V; VSEL0 = 5 V; VSEL1 = 5 V; RSENSE = 1 k 20 s MultiSense timings (Multiplexer transition times)(4) tD_XtoY tD_CStoTC MultiSense transition delay from ChX to ChY VIN0 = 5 V; VIN1 = 5 V; VSEn = 5 V; VSEL1 = 0 V; VSEL0 = 0 V to 5 V; IOUT0 = 0 A; IOUT1 = 15 A; RSENSE = 1 k 20 s MultiSense transition delay from current sense to TC sense VIN0 = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V to 5 V; IOUT0 = 1.5 A; RSENSE = 1 k 60 s DocID027772 Rev 11 15/47 Electrical specification VND7004AY 7 V < VCC < 18 V; -40C < Tj < 150C Symbol Parameter Test conditions Min. Typ. Unit tD_TCtoCS MultiSense transition delay from TC sense to current sense VIN0 = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V to 0 V; IOUT0 = 1.5 A; RSENSE = 1 k 20 s tD_CStoVCC MultiSense transition delay from current sense to VCC sense VIN1 = 5 V; VSEn = 5 V; VSEL0 = 5 V; VSEL1 = 0 V to 5 V; IOUT1 = 15A; RSENSE = 1 k 60 s tD_VCCtoCS MultiSense transition delay from VCC sense to current sense VIN1 = 5 V; VSEn = 5 V; VSEL0 = 5 V; VSEL1 = 5 V to 0 V; IOUT1 = 15 A; RSENSE = 1 k 20 s tD_TCtoVCC MultiSense transition delay from TC sense to VCC sense VCC = 13 V; Tj = 125C; VSEn = 5 V; VSEL0 = 0 V to 5 V; VSEL1 = 5 V; RSENSE = 1 k 20 s tD_VCCtoTC MultiSense transition delay from VCC sense to TC sense VCC = 13 V; Tj = 125C; VSEn = 5 V; VSEL0 = 5 V to 0 V; VSEL1 = 5 V; RSENSE = 1 k 20 s tD_CStoVSENSEH MultiSense transition delay from stable current sense on ChX to VSENSEH on ChY VIN0 = 5 V; VIN1 = 0 V; VSEn = 5 V; VSEL1 = 0 V; VSEL0 = 0 V to 5 V; IOUT0 = 3 A; VOUT1 = 15 V; RSENSE = 1 k 20 s Notes: (1)Parameter (2)All (3)V guaranteed by design and characterization; not subjected to production test. values refer to VCC = 13 V; Tj = 25 C, unless otherwise specified. CC sensing and TC sensing are referred to GND potential. (4)Transition 16/47 Max. delay are measured up to +/- 10% of final conditions. DocID027772 Rev 11 VND7004AY Electrical specification Figure 4: Switching time and Pulse skew twon VOUT twoff Vcc 80% Vcc ON dV OUT OFF /dt dV /dt OUT 20% Vcc t INPUT td(off) td(on) tpLH tpHL t Figure 5: MultiSense timings (current sense mode) IN1 High SEn Low High SEL0 Low High SEL1 Low IOUT1 CURRENT SENSE tDSENSE2H tDSENSE1L DocID027772 Rev 11 tDSENSE1H tDSENSE2L 17/47 Electrical specification VND7004AY Figure 6: Multisense timings (chip temperature and VCC sense mode) High SEn Low High SEL0 Low High SEL1 Low V CC V SENSE = VSENSE_VCC V SENSE = V SENSE_TC SENSE tDSENSE4H t DSENSE4L VCC VOLTAGE SENSE MODE t DSENSE3H tDSENSE3L CHIP TEMPERATUR E SENSE MODE GAPGCFT00319 Figure 7: TDSTKON VINPU T VOU T VOU T > VOL MultiSense TDSTKON GAPG2609141140CFT 18/47 DocID027772 Rev 11 VND7004AY Electrical specification Table 10: Truth table Mode Standby Conditions INX FR SEn SELX OUTX MultiSense All logic inputs low L L L L L Hi-Z L X L See (1) H L H See (1) Outputs configured for auto-restart Outputs configured for Latch-off Nominal load connected; Tj < 150 C Normal H H H See (1) L X L See (1) H See (1) L See (1) Output latchesoff L L Hi-Z Hi-Z Re-start when VCC > VUSD + VUSDhyst (rising) H See (1) H See (1) <0V See (1) H L H H VCC < VUSD (falling) X X OFF-state diagnostics Short to VCC L X Open-load L X Negative output voltage Inductive loads turn-off L X Undervoltage Low quiescent current consumption See (1) Overload or short to GND causing: Tj > TTSD or Tj > Tj_SD Overload Comments See (1) X X See (1) See (1) Output cycles with temperature hysteresis External pull-up Notes: (1)Refer to Table 11: "MultiSense multiplexer addressing" Table 11: MultiSense multiplexer addressing MultiSense output SEn SEL1 SEL0 MUX channel Normal mode Overload OFF-state diag. (1) Negative output L X X Hi-Z H L L Channel 0 diagnostic ISENSE = 1/K * IOUT0 VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z H L H Channel 1 diagnostic ISENSE = 1/K * IOUT1 VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z H H L TCHIP Sense VSENSE = VSENSE_TC H H H VCC Sense VSENSE = VSENSE_VCC Notes: (1)In case the output channel corresponding to the selected MUX channel is latched off while the relevant input is low, Multisense pin delivers feedback according to OFF-State diagnostic. Example 1: FR = 1; IN0 = 0; OUT0 = L (latched); MUX channel = channel 0 diagnostic; Mutisense = 0. Example 2: FR = 1; IN0 = 0; OUT0 = latched, VOUT0 > VOL; MUX channel = channel 0 diagnostic; Mutisense = VSENSEH DocID027772 Rev 11 19/47 Electrical specification 2.4 VND7004AY Waveforms Figure 8: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) Figure 9: Latch functionality - behavior in hard short circuit condition 20/47 DocID027772 Rev 11 VND7004AY Electrical specification Figure 10: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) Figure 11: Standby mode activation DocID027772 Rev 11 21/47 Electrical specification VND7004AY Figure 12: Standby state diagram Normal Operation t > t D_STBY INx = Low AND FaultRST = Low AND SEn = Low AND SELx = Low INx = High OR FaultRST = High OR SEn = High OR SELx = High Stand-by Mode GAPGCFT00598 2.5 22/47 Electrical characteristics curves Figure 13: OFF-state output current Figure 14: Standby current Figure 15: IGND(ON) vs. Iout Figure 16: Logic Input high level voltage DocID027772 Rev 11 VND7004AY Electrical specification Figure 17: Logic Input low level voltage Figure 18: High level logic input current Figure 19: Low level logic input current Figure 20: Logic Input hysteresis voltage Figure 21: FaultRST Input clamp voltage Figure 22: Undervoltage shutdown DocID027772 Rev 11 23/47 Electrical specification 24/47 VND7004AY Figure 23: On-state resistance vs. Tcase Figure 24: On-state resistance vs. VCC Figure 25: Turn-on voltage slope Figure 26: Turn-off voltage slope Figure 27: Won vs. Tcase Figure 28: Woff vs. Tcase DocID027772 Rev 11 VND7004AY Electrical specification Figure 29: OFF-state open-load voltage detection threshold Figure 30: Vsense clamp vs. Tcase Figure 31: Vsenseh vs. Tcase DocID027772 Rev 11 25/47 Protections VND7004AY 3 Protections 3.1 Power limitation The basic working principle of this protection consists of an indirect measurement of the junction temperature swing Tj through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output MOSFET as soon as Tj exceeds the safety level of 60 K. According to the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off (FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermo-mechanical fatigue. 3.2 Thermal shutdown In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175C), it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the FaultRST pin, the device switches on again as soon as its junction temperature drops to TRS (FaultRST = Low) or remains off (FaultRST = High). 3.3 Current limitation The device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, ILIMH, by operating the output power MOSFET in the active region. 3.4 Negative voltage clamp In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the device. 26/47 DocID027772 Rev 11 VND7004AY 4 Application information Application information Figure 32: Application diagram 4.1 GND protection network against reverse battery Figure 33: Simplified internal structure Vcc 5V Rprot INPUT Rprot SEn Rprot FaultRST MCU Dld OUTPUT Rprot Multisense GND Rsense GND The device does not need any external components to protect the internal logic in case of a reverse battery condition. The protection is provided by internal structures. DocID027772 Rev 11 27/47 Application information VND7004AY In addition, due to the fact that the output MOSFET turns on even in reverse battery mode, thus providing the same low ohmic path as in regular operating conditions, no additional power dissipation has to be considered. 4.2 Immunity against transient electrical disturbances The immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010. The related function performance status classification is shown in Table 12: "ISO 7637-2 electrical transient conduction along supply line". Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device only, without components and accessed through VCC and GND terminals. Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: "The function does not perform as designed during the test but returns automatically to normal operation after the test". Table 12: ISO 7637-2 - electrical transient conduction along supply line Test Pulse 2011(E) Test pulse severity level with Status II functional performance status Minimum number of pulses or test time Burst cycle / pulse repetition time Pulse duration and pulse generator internal impedance Level US(1) 1 III -112 V 500 pulses 0.5 s 2a(3) III +55 V 500 pulses 0.2 s 5s 50 s, 2 3a IV -220 V 1h 90 ms 100 ms 0.1 s, 50 3b IV +150 V 1h 90 ms 100 ms 0.1 s, 50 4 (2) IV -7 V 1 pulse min max 2 ms, 10 100 ms, 0.01 Load dump according to ISO 16750-2:2010 Test B(3) 40 V 5 pulse 1 min 400 ms, 2 Notes: (1)U S 4.3 is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6. (2)Test pulse from ISO 7637-2:2004(E). (3)With 40 V external suppressor referred to ground (-40C < Tj < 150 C). MCU I/Os protection If a ground protection network is used and negative transients are present on the V CC line, the control pins will be pulled negative. ST suggests to insert a resistor (R prot) in line both to prevent the microcontroller I/O pins from latching-up and to protect the HSD inputs. The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os. 28/47 DocID027772 Rev 11 VND7004AY Application information Equation VCCpeak/Ilatchup Rprot (VOHC - VIH - VGND) / IIHmax Calculation example: For VCCpeak = -150 V; Ilatchup 20 mA; VOHC 4.5 V 7.5 k Rprot 140 k. Recommended values: Rprot = 15 k 4.4 Multisense - analog current sense Diagnostic information on device and load status are provided by an analog output pin (MultiSense) delivering the following signals: Current monitor: current mirror of channel output current VCC monitor: voltage propotional to VCC TCASE: voltage propotional to chip temperature Those signals are routed through an analog multiplexer which is configured and controlled by means of SELx and SEn pins, according to the address map in MultiSense multiplexer addressing Table. Figure 34: MultiSense and diagnostic - block diagram DocID027772 Rev 11 29/47 Application information 4.4.1 VND7004AY Principle of Multisense signal generation Figure 35: MultiSense block diagram Current monitor When current mode is selected via MultiSense, this output is capable of providing: Current mirror proportional to the load current in normal operation, delivering current proportional to the load according to a known ratio named K Diagnostics flag in fault conditions delivering fixed voltage V SENSEH The current delivered by the current sense circuit, ISENSE, can be easily converted to a voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load monitoring and abnormal condition detection. Normal operation (channel ON, no fault, SEn active) While device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using simple equations Current provided by MultiSense output: ISENSE = IOUT/K Voltage on RSENSE: VSENSE = RSENSE * ISENSE = RSENSE * IOUT/K 30/47 DocID027772 Rev 11 VND7004AY Where: Application information VSENSE is the voltage measurable on RSENSE resistor ISENSE is the current provided from MultiSense pin in current output mode IOUT is the current flowing through output K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of overall circuitry specifying the ratio between IOUT and ISENSE. Failure flag indication In case of power limitation/overtemperature, the fault is indicated by the MultiSense pin which is switched to a "current limited" voltage source, VSENSEH. In any case, the current sourced by the MultiSense in this condition is limited to I SENSEH. The typical behavior in case of overload or hard short circuit is shown in Waveforms section. Figure 36: Analogue HSD - open-load detection in off-state DocID027772 Rev 11 31/47 Application information VND7004AY Figure 37: Open-load / short to VCC condition VIN VSENSE Pull-up connected VSENSEH Open-load VSENSE = 0 VSENSE Pull-up disconnected tDSTKON Short to VCC VSENSEH Table 13: MultiSense pin levels in off-state Condition Output VOUT > VOL Open-load VOUT < VOL 4.4.2 Short to VCC VOUT > VOL Nominal VOUT < VOL MultiSense SEn Hi-Z L VSENSEH H Hi-Z L 0 H Hi-Z L VSENSEH H Hi-Z L 0 H TCASE and VCC monitor In this case, MultiSense output operates in voltage mode and output level is referred to device GND. Care must be taken in case a GND network protection is used, because a voltage shift is generated between the device GND and the microcontroller input GND reference. Figure 38: "GND voltage shift" shows the link between VMEASURED and the real VSENSE signal. 32/47 DocID027772 Rev 11 VND7004AY Application information Figure 38: GND voltage shift VCC monitor Battery monitoring channel provides VSENSE = VCC / 8. Case temperature monitor Case temperature monitor is capable of providing information about the actual device temperature. Since a diode is used for temperature sensing, the following equation describes the link between temperature and output VSENSE level: VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0) where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40 C to 150 C)). 4.4.3 Short to VCC and OFF-state open-load detection Short to VCC A short circuit between VCC and output is indicated by the relevant current sense pin set to VSENSEH during the device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature of the short circuit. OFF-state open-load with external circuitry Detection of an open-load in off mode requires an external pull-up resistor RPU connecting the output to a positive supply voltage VPU. It is preferable that VPU is switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected. RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following equation: Equation DocID027772 Rev 11 33/47 Package and PCB thermal data VND7004AY 5 Package and PCB thermal data 5.1 PowerSSO-36 thermal data Figure 39: PowerSSO-36 PC board 34/47 DocID027772 Rev 11 VND7004AY Package and PCB thermal data Table 14: PCB properties Dimension Value Board finish thickness 1.6 mm +/- 10% Board dimension 129 mm x 60 mm Board Material FR4 Copper thickness (top and bottom layers) 0.070 mm Copper thickness (inner layers) 0.035 mm Thermal vias separation 1.2 mm Thermal via diameter 0.3 mm +/- 0.08 mm Copper thickness on vias 0.025 mm Footprint dimension (top layer) 4.1 mm x 6.5 mm Footprint, 2 cm2 or 8 cm2 Heatsink copper area dimension (bottom layer) Figure 40: Rthj-amb vs PCB copper area in open box free air conditions RTHjamb 65 RTHjamb 60 55 50 45 40 35 30 0 2 4 DocID027772 Rev 11 6 8 10 35/47 Package and PCB thermal data VND7004AY Figure 41: PowerSSO-36 thermal impedance junction ambient single pulse ZTH (C/W) 100 Cu=8 cm2 Cu=2 cm2 Cu=foot print 4Layer 10 1 0.1 0.0001 0.001 0.01 0.1 1 10 100 1000 Time (s) Equation: pulse calculation formula ZTH = RTH * + ZTHtp (1 - ) where = tP/T Figure 42: Thermal fitting model for PowerSSO-36 The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. 36/47 DocID027772 Rev 11 VND7004AY Package and PCB thermal data Table 15: Thermal parameters Area/island (cm2) FP 2 8 4L R1 = R7 (C/W) 0.01 R2 = R8 (C/W) 1.2 R3 (C/W) 3.4 3.4 3.4 2.6 R4 (C/W) 6 6 6 3 R5 (C/W) 18 14 10 2 R6 (C/W) 30 26 15 7 C1 = C7 (W*s/C) 0.0005 C2 = C8 (W*s/C) 0.001 C3 (W*s/C) 0.1 C4 (W*s/C) 0.5 0.8 0.8 1 C5 (W*s/C) 1 2 3 10 C6 (W*s/C) 3 5 9 18 DocID027772 Rev 11 37/47 Maximum demagnetization energy (VCC = 16 V) 6 VND7004AY Maximum demagnetization energy (VCC = 16 V) Figure 43: Maximum turn off current versus inductance 100 I (A) 10 1 VND7004AY - Single Pulse Repetitive pulse Tjstart=100C Repetitive pulse Tjstart=125C 0.1 0.1 1 10 L (mH) 100 1000 Values are generated with RL = 0 . In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. 38/47 DocID027772 Rev 11 VND7004AY 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK (R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 7.1 PowerSSO-36 package information Figure 44: PowerSSO-36 package outline BOTTOM VIEW TOP VIEW SECTION A-A SECTION B-B GAPG2508150825CF T Table 16: PowerSSO-36 mechanical data Dimensions Ref. Millimeters Min. Typ. Max. 0 8 1 5 10 2 0 A 2.15 2.45 A1 0.00 0.10 DocID027772 Rev 11 39/47 Package information VND7004AY Dimensions Ref. Millimeters Min. A2 2.15 b 0.18 b1 0.13 c 0.23 c1 0.20 D D1 Typ. 2.35 0.32 0.25 0.20 0.30 10.30 BSC 6.90 7.50 3.65 D3 4.30 e 0.50 BSC E 10.30 BSC E1 7.50 BSC 4.30 5.20 E3 2.30 E4 2.90 G1 1.20 G2 1.00 G3 0.80 h 0.30 L 0.55 0.40 0.70 L1 1.40 REF L2 0.25 BSC N 36 R 0.30 R1 0.20 S 0.25 Tolerance of form and position 40/47 0.30 0.32 D2 E2 Max. aaa 0.20 bbb 0.20 ccc 0.10 ddd 0.20 eee 0.10 fff 0.20 ggg 0.15 DocID027772 Rev 11 0.85 VND7004AY 7.2 Package information PowerSSO-36 packing information Figure 45: PowerSSO-36 reel 13" Table 17: Reel dimensions Description Value(1) Base quantity 1000 Bulk quantity 1000 A (max) 330 B (min) 1.5 C ( 0.2) 13 F 20.2 G (+2 / -0) 24.4 N (min) 100 T (max) 30.4 Notes: (1)All dimensions are in mm. DocID027772 Rev 11 41/47 Package information VND7004AY Figure 46: PowerSSO-36 carrier tape Table 18: PowerSSO-36 carrier tape dimensions Description Value(1) A0 10.90 0.10 B0 10.80 0.10 K0 2.75 0.10 K1 2.45 0.10 D0 1.50 (+0.10 / -0) D1 1.60 0.10 P0 4.00 0.10 P1 12.00 0.10 P2 2.00 0.10 P10 40.00 0.20 E 1.75 0.10 F 11.50 0.10 W 24.00 0.30 T 0.30 0.05 Notes: (1)All 42/47 dimensions are in mm. DocID027772 Rev 11 VND7004AY Package information Figure 47: PowerSSO-36 schematic drawing of leader and trailer tape 7.3 PowerSSO-36 marking information Figure 48: PowerSSO-36 marking information Engineering Samples: Parts marked as "&" are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. Commercial Samples: fully qualified parts from ST standard production with no usage restrictions. DocID027772 Rev 11 43/47 Order codes 8 VND7004AY Order codes Table 19: Device summary Order codes Package Tape and reel PowerSSO-36 44/47 VND7004AYTR DocID027772 Rev 11 VND7004AY 9 Revision history Revision history Table 20: Document revision history Date Revision 23-Apr-2015 1 Changes Initial release. Table 3: "Absolute maximum ratings": -IOUT: updated value Updated Table 4: "Thermal data" and Table 6: "Switching" Table 8: "Protections": 20-Jul-2015 2 TR, THYST: added note Table 9: "MultiSense": K0, dK0/K0: removed rows Kx, dKx/Kx, IOUT_SAT: updated values Added Section 5: "Package and PCB thermal data" Updated Figure 1: "Block diagram" Updated Table 1: "Pin functions" Table 3: "Absolute maximum ratings": ISENSE: updated parameter and value EMAX: updated parameter Table 5: "Power section": 30-Jul-2015 3 RON_REV: updated value Table 9: "MultiSense": VSENSE_CL, VSENSE_TC, VSENSE_VCC: updated test conditions Removed following tables: Table: Electrical transient requirements (part 1) Table: Electrical transient requirements (part 2) Table: Electrical transient requirements (part 3) Added Section 4: "Application information" Table 5: "Power section": 02-Dec-2015 4 ISTBY, IL(off): updated values Updated Table 6: "Switching" Table 9: "MultiSense": Kx, tDSENSE2H: updated values Added Section 2.5: "Electrical characteristics curves" Table 9: "MultiSense": 27-Jan-2016 5 ISENSE0: updated value DocID027772 Rev 11 45/47 Revision history Date VND7004AY Revision Changes Updated Features list Table 3: "Absolute maximum ratings": 20-Apr-2016 6 EMAX: updated value Table 9: "MultiSense": dKx/Kx, ISENSE_SAT, IOUT_SAT: added note Added Section 6: "Maximum demagnetization energy (VCC = 16 V)" 46/47 26-Apr-2016 7 Updated Figure 1: "Block diagram" and Figure 34: "MultiSense and diagnostic - block diagram" 15-Jul-2016 8 Updated Figure 45: "PowerSSO-36 reel 13""and Table 17: "Reel dimensions" 02-Nov-2016 9 Updated Applications section 16-Dec-2016 10 in Table 6: "Switching" - updated tSKEW Min. Typ. and Max. values 22-Jun-2017 11 Changed the K1 minimum value in Table 9: "MultiSense". DocID027772 Rev 11 VND7004AY IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2017 STMicroelectronics - All rights reserved DocID027772 Rev 11 47/47