June 2017
DocID027772 Rev 11
1/47
This is information on a product in full production.
www.st.com
VND7004AY
Double channel high-side driver with MultiSense analog
feedback for automotive applications
Datasheet - production data
Features
Max transient supply voltage
40 V
Operating voltage range
4 to 28 V
Typ. on-state resistance (per Ch)
4 mΩ
Current limitation (typ)
100 A
Standby current (max)
0.5 µA
AEC-Q100 qualified
General
Double channel smart high-side driver
with MultiSense analog feedback
Very low standby current
Compatible with 3 V and 5 V CMOS
outputs
MultiSense diagnostic functions
Multiplexed analog feedback of: load
current with high precision proportional
current mirror, VCC supply voltage and
TCHIP device temperature
Overload and short to ground (power
limitation) indication
Thermal shutdown indication
OFF-state open-load detection
Output short to VCC detection
Sense enable/disable
Protections
Undervoltage shutdown
Overvoltage clamp
Load current limitation
Self limiting of fast thermal transients
Configurable latch-off on
overtemperature or power limitation
with dedicated fault reset pin
Loss of ground and loss of VCC
Reverse battery with self switch of the
PowerMOS
Electrostatic discharge protection
Applications
Specially intended for Automotive smart power
distribution, glow plugs, heating systems, DC
motors, relay replacement and high power
resistive and inductive actuators.
Description
The device is a double channel high-side driver
manufactured using ST proprietary VIPower®
M0‑7 technology and housed in PowerSSO-36
package. The device is designed to drive 12 V
automotive grounded loads through a 3 V and
5 V CMOS-compatible interface, providing
protection and diagnostics.
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown with configurable
latch-off.
A FaultRST pin unlatches the output in case of
fault or disables the latch-off functionality.
A dedicated multifunction multiplexed analog
output pin delivers sophisticated diagnostic
functions including high precision proportional
load current sense, supply voltage feedback and
chip temperature sense, in addition to the
detection of overload and short circuit to ground,
short to VCC and OFF-state open-load.
A sense enable pin allows OFF-state diagnosis to
be disabled during the module low-power mode
as well as external sense resistor sharing among
similar devices.
Contents
VND7004AY
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DocID027772 Rev 11
Contents
1 Block diagram and pin description ................................................ 5
2 Electrical specification .................................................................... 7
2.1 Absolute maximum ratings ................................................................ 7
2.2 Thermal data ..................................................................................... 8
2.3 Main electrical characteristics ........................................................... 8
2.4 Waveforms ...................................................................................... 20
2.5 Electrical characteristics curves ...................................................... 22
3 Protections..................................................................................... 26
3.1 Power limitation ............................................................................... 26
3.2 Thermal shutdown ........................................................................... 26
3.3 Current limitation ............................................................................. 26
3.4 Negative voltage clamp ................................................................... 26
4 Application information ................................................................ 27
4.1 GND protection network against reverse battery ............................. 27
4.2 Immunity against transient electrical disturbances .......................... 28
4.3 MCU I/Os protection ........................................................................ 28
4.4 Multisense - analog current sense .................................................. 29
4.4.1 Principle of Multisense signal generation ......................................... 30
4.4.2 TCASE and VCC monitor ................................................................. 32
4.4.3 Short to VCC and OFF-state open-load detection ........................... 33
5 Package and PCB thermal data .................................................... 34
5.1 PowerSSO-36 thermal data ............................................................ 34
6 Maximum demagnetization energy (VCC = 16 V) ........................ 38
7 Package information ..................................................................... 39
7.1 PowerSSO-36 package information ................................................ 39
7.2 PowerSSO-36 packing information ................................................. 41
7.3 PowerSSO-36 marking information ................................................. 43
8 Order codes ................................................................................... 44
9 Revision history ............................................................................ 45
VND7004AY
List of tables
DocID027772 Rev 11
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List of tables
Table 1: Pin functions ................................................................................................................................. 5
Table 2: Suggested connections for unused and not connected pins ........................................................ 6
Table 3: Absolute maximum ratings ........................................................................................................... 7
Table 4: Thermal data ................................................................................................................................. 8
Table 5: Power section ............................................................................................................................... 8
Table 6: Switching ..................................................................................................................................... 10
Table 7: Logic inputs ................................................................................................................................. 10
Table 8: Protections .................................................................................................................................. 11
Table 9: MultiSense .................................................................................................................................. 12
Table 10: Truth table ................................................................................................................................. 19
Table 11: MultiSense multiplexer addressing ........................................................................................... 19
Table 12: ISO 7637-2 - electrical transient conduction along supply line ................................................. 28
Table 13: MultiSense pin levels in off-state .............................................................................................. 32
Table 14: PCB properties ......................................................................................................................... 35
Table 15: Thermal parameters ................................................................................................................. 37
Table 16: PowerSSO-36 mechanical data................................................................................................ 39
Table 17: Reel dimensions ....................................................................................................................... 41
Table 18: PowerSSO-36 carrier tape dimensions .................................................................................... 42
Table 19: Device summary ....................................................................................................................... 44
Table 20: Document revision history ........................................................................................................ 45
List of figures
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DocID027772 Rev 11
List of figures
Figure 1: Block diagram .............................................................................................................................. 5
Figure 2: Configuration diagram (top view)................................................................................................. 6
Figure 3: Current and voltage conventions ................................................................................................. 7
Figure 4: Switching time and Pulse skew ................................................................................................. 17
Figure 5: MultiSense timings (current sense mode) ................................................................................. 17
Figure 6: Multisense timings (chip temperature and VCC sense mode) .................................................. 18
Figure 7: TDSTKON .................................................................................................................................. 18
Figure 8: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) ........................ 20
Figure 9: Latch functionality - behavior in hard short circuit condition ...................................................... 20
Figure 10: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) .... 21
Figure 11: Standby mode activation ......................................................................................................... 21
Figure 12: Standby state diagram ............................................................................................................. 22
Figure 13: OFF-state output current ......................................................................................................... 22
Figure 14: Standby current ....................................................................................................................... 22
Figure 15: IGND(ON) vs. Iout ................................................................................................................... 22
Figure 16: Logic Input high level voltage .................................................................................................. 22
Figure 17: Logic Input low level voltage.................................................................................................... 23
Figure 18: High level logic input current ................................................................................................... 23
Figure 19: Low level logic input current .................................................................................................... 23
Figure 20: Logic Input hysteresis voltage ................................................................................................. 23
Figure 21: FaultRST Input clamp voltage ................................................................................................. 23
Figure 22: Undervoltage shutdown ........................................................................................................... 23
Figure 23: On-state resistance vs. Tcase ................................................................................................. 24
Figure 24: On-state resistance vs. VCC ................................................................................................... 24
Figure 25: Turn-on voltage slope .............................................................................................................. 24
Figure 26: Turn-off voltage slope .............................................................................................................. 24
Figure 27: Won vs. Tcase ......................................................................................................................... 24
Figure 28: Woff vs. Tcase ......................................................................................................................... 24
Figure 29: OFF-state open-load voltage detection threshold ................................................................... 25
Figure 30: Vsense clamp vs. Tcase .......................................................................................................... 25
Figure 31: Vsenseh vs. Tcase .................................................................................................................. 25
Figure 32: Application diagram ................................................................................................................. 27
Figure 33: Simplified internal structure ..................................................................................................... 27
Figure 34: MultiSense and diagnostic – block diagram ............................................................................ 29
Figure 35: MultiSense block diagram ....................................................................................................... 30
Figure 36: Analogue HSD – open-load detection in off-state ................................................................... 31
Figure 37: Open-load / short to VCC condition ......................................................................................... 32
Figure 38: GND voltage shift .................................................................................................................... 33
Figure 39: PowerSSO-36 PC board ......................................................................................................... 34
Figure 40: Rthj-amb vs PCB copper area in open box free air conditions ............................................... 35
Figure 41: PowerSSO-36 thermal impedance junction ambient single pulse .......................................... 36
Figure 42: Thermal fitting model for PowerSSO-36 .................................................................................. 36
Figure 43: Maximum turn off current versus inductance .......................................................................... 38
Figure 44: PowerSSO-36 package outline ............................................................................................... 39
Figure 45: PowerSSO-36 reel 13" ............................................................................................................ 41
Figure 46: PowerSSO-36 carrier tape ...................................................................................................... 42
Figure 47: PowerSSO-36 schematic drawing of leader and trailer tape .................................................. 43
Figure 48: PowerSSO-36 marking information ......................................................................................... 43
VND7004AY
Block diagram and pin description
DocID027772 Rev 11
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1 Block diagram and pin description
Figure 1: Block diagram
Table 1: Pin functions
Name
Function
VCC
Battery connection.
OUTPUT0,1
Power output.
GND
Ground connection.
INPUT0,1
Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS
outputs. They control output switch state.
MultiSense
Multiplexed analog sense output pin; it delivers a current proportional to the selected
diagnostic: load current, supply voltage or chip temperature.
SEn
Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the MultiSense
diagnostic pin.
SEL0,1
Active high compatible with 3 V and 5 V CMOS outputs pin; they address the
MultiSense multiplexer.
FaultRST
Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in
case of fault; If kept low, sets the outputs in auto-restart mode
Channe l 1
Control & Diagnostic
Channe l 0
VCC
Current
Limitation
VCC–OUT
Clamp
Internal supply
CH1
OUTPUT0
CH0
MUX
Current
Sense
0
GND
Undervoltage
shut-down
VCC–GND
Clamp
Fault
T
Short to VCC
Open-LoadinOFF
Overtemperature
Power Limitation
T
VSENSEH
INPUT0
SEL0
SEL1
SEn
Multisense
FaultRST
INPUT1
OUTPUT1
VCC
GateDriver
Block diagram and pin description
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DocID027772 Rev 11
Figure 2: Configuration diagram (top view)
Table 2: Suggested connections for unused and not connected pins
Connection /
pin
MultiSense
N.C.
Output
Input
SEn, SELx,
FaultRST
Floating
Not allowed
X (1)
X
X
X
To ground
Through 1 kΩ
resistor
X
Not
allowed
Through 10 kΩ
resistor
Through 10 kΩ
resistor
Notes:
(1)X: do not care.
11
10
9
8
7
6
5
4
3
2
1
PowerSSO-36
12
13
14
15
16
17
18
26
27
28
29
30
31
32
33
34
35
36
25
24
23
22
21
20
19
SEL1
SEL0
N.C.
MultiSense
GND
FaultRST
N.C.
INPUT1
TAB/Vcc
SEn
N.C.
N.C.
N.C. N.C.
N.C.
OUTPUT0
OUTPUT0
OUTPUT0
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT0
OUTPUT0
OUTPUT0
OUTPUT0
OUTPUT0
OUTPUT0
OUTPUT0
INPUT0
N.C.
VND7004AY
Electrical specification
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2 Electrical specification
Figure 3: Current and voltage conventions
VF = VOUT - VCC when VOUT > VCC and INPUT = LOW.
2.1 Absolute maximum ratings
Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability.
Table 3: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
DC supply voltage
38
V
-VCC
Reverse DC supply voltage
16
VCCPK
Maximum transient supply voltage (ISO 7637-2:2004 Pulse 5b
level IV clamped to 40 V; RL = 4 Ω)
40
V
VCCJS
Maximum jump start voltage for single pulse short circuit protection
28
V
-IGND
DC reverse ground pin current
200
mA
IOUT
OUTPUT0,1 DC output current
Internally
limited
A
-IOUT
Reverse DC output current
65
IIN
INPUT0,1 DC input current
-1 to 10
mA
ISEn
SEn DC input current
ISEL
SEL0,1 DC input current
IFR
FaultRST DC input current
VFR
FaultRST DC input voltage
7.5
V
VIN
OUTPUT0,1
MultiSense
FaultRST
SEn
SEL0,1
INPUT0,1
IIN
ISEL
ISEn
IFR
IGND
VSENSE
VOUT
VCC
VFn
IS
IOUT
ISENSE
VCC
VSEL
VSEn
VFR
GAPGCFT00315
Electrical specification
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DocID027772 Rev 11
Symbol
Parameter
Value
Unit
ISENSE
MultiSense pin DC output current (VGND = VCC and VSENSE < 0 V)
10
mA
MultiSense pin DC output current in reverse (VCC < 0 V)
-20
EMAX
Maximum switching energy (single pulse) (TDEMAG = 0.4 ms;
Tjstart = 150 °C)
103
mJ
VESD
Electrostatic discharge (JEDEC 22A-114F)
INPUT0,1
MultiSense
SEn, SEL0,1, FaultRST
OUTPUT0,1
VCC
4000
2000
4000
4000
4000
V
V
V
V
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Tj
Junction operating temperature
-40 to 150
°C
Tstg
Storage temperature
-55 to 150
2.2 Thermal data
Table 4: Thermal data
Symbol
Parameter
Typ. value
Unit
Rthj-board
Thermal resistance junction-board (1)
3.4
°C/W
Rthj-amb
Thermal resistance junction-ambient (JEDEC JESD 51-5)(1)(2)
50.6
Rthj-amb
Thermal resistance junction-ambient (JEDEC JESD 51-7)(1)(3)
15.8
Notes:
(1)One channel ON.
(2)Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace
(3)Device mounted on four-layers 2s2p PCB
2.3 Main electrical characteristics
7 V < VCC < 28 V; -40°C < Tj < 150°C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
Table 5: Power section
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VCC
Operating supply
voltage
4
13
28
V
VUSD
Undervoltage
shutdown
4
V
VUSDReset
Undervoltage
shutdown reset
5
V
VUSDhyst
Undervoltage
shutdown
hysteresis
0.3
V
RON
On-state
IOUT = 15 A; Tj = 25°C
4
mΩ
VND7004AY
Electrical specification
DocID027772 Rev 11
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Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
resistance(1)
IOUT = 15 A; Tj = 150°C
8
IOUT = 15 A; VCC = 4 V; Tj = 25°C
6
RON_REV
On-state resistance
in reverse battery
IOUT = -15 A; VCC = -13 V; Tj = 25°C
4
mΩ
Vclamp
Clamp voltage
IS = 20 mA; 25°C < Tj < 150°C
41
46
52
V
ISTBY
Supply current in
standby at
VCC = 13 V (2)
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 25°C
0.5
µA
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 85°C (3)
1.9
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 125°C
15
tD_STBY
Standby mode
blanking time
VCC = 13 V;
VIN = VOUT = VFR = VSEL0,1 = 0 V;
VSEn = 5 V to 0 V
60
300
550
µs
IS(ON)
Supply current
VCC = 13 V;
VSEn = VFR = VSEL0,1 = 0 V; VIN0 = 5 V;
VIN1 = 5 V;
IOUT0 = 0 A; IOUT1 = 0 A
6
12
mA
IGND(ON)
Control stage
current
consumption in ON
state. All channels
active.
VCC = 13 V; VSEn = 5 V;
VFR = VSEL0,1 = 0 V; VIN0 = 5 V;
VIN1 = 5 V; IOUT0,1 = 15 A
12
mA
IL(off)
Off-state output
current (2)
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25°C
0
0.01
0.5
µA
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125°C
0
7.5
VF
Output - VCC diode
voltage
IOUT = -15 A; Tj = 150°C
0.7
V
Notes:
(1)For each channel
(2)PowerMOS leakage included.
(3)Parameter specified by design; not subjected to production test.
Electrical specification
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DocID027772 Rev 11
Table 6: Switching
VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified
Symbol
Parameter
Test
conditions
Min.
Typ.
Max.
Unit
td(on)(1)
Turn-on delay time
RL = 0.87 Ω
60
110
195
µs
td(off)(1)
Turn-off delay time
50
100
160
(dVOUT/dt)on(1)
Turn-on voltage slope
RL = 0.87 Ω
0.05
0.21
0.35
V/µs
(dVOUT/dt)off(1)
Turn-off voltage slope
0.05
0.21
0.35
WON
Switching energy losses at turn-on
(twon)
RL = 0.87 Ω
—
2.3
3.7(2)
mJ
WOFF
Switching energy losses at turn-off
(twoff)
RL = 0.87 Ω
—
2.5
4.5(2)
mJ
tSKEW(1)
Differential pulse skew (tPHL - tPLH)
RL = 0.87 Ω
-65
0
65
µs
Notes:
(1)See Figure 4: "Switching time and Pulse skew".
(2)Parameter guaranteed by design and characterization; not subjected to production test.
Table 7: Logic inputs
7 V < VCC < 28 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
INPUT0,1 characteristics
VIL
Input low level voltage
0.9
V
IIL
Low level input current
VIN = 0.9 V
1
µA
VIH
Input high level voltage
2.1
V
IIH
High level input current
VIN = 2.1 V
10
µA
VI(hyst)
Input hysteresis voltage
0.2
V
VICL
Input clamp voltage
IIN = 1 mA
5.3
7.2
V
IIN = -1 mA
-0.7
FaultRST characteristics
VFRL
Input low level voltage
0.9
V
IFRL
Low level input current
VIN = 0.9 V
1
µA
VFRH
Input high level voltage
2.1
V
IFRH
High level input current
VIN = 2.1 V
10
µA
VFR(hyst)
Input hysteresis voltage
0.2
V
VFRCL
Input clamp voltage
IIN = 1 mA
5.3
7.5
V
IIN = -1 mA
-0.7
SEL0,1 characteristics (7 V < VCC < 18 V)
VSELL
Input low level voltage
0.9
V
ISELL
Low level input current
VIN = 0.9 V
1
µA
VSELH
Input high level voltage
2.1
V
ISELH
High level input current
VIN = 2.1 V
10
µA
VND7004AY
Electrical specification
DocID027772 Rev 11
11/47
7 V < VCC < 28 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VSEL(hyst)
Input hysteresis voltage
0.2
V
VSELCL
Input clamp voltage
IIN = 1 mA
5.3
7.2
V
IIN = -1 mA
-0.7
SEn characteristics (7 V < VCC < 18 V)
VSEnL
Input low level voltage
0.9
V
ISEnL
Low level input current
VIN = 0.9 V
1
µA
VSEnH
Input high level voltage
2.1
V
ISEnH
High level input current
VIN = 2.1 V
10
µA
VSEn(hyst)
Input hysteresis voltage
0.2
V
VSEnCL
Input clamp voltage
IIN = 1 mA
5.3
7.2
V
IIN = -1 mA
-0.7
Table 8: Protections
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
ILIMH
DC short circuit
current
VCC = 13 V
70
100
140
A
4 V < VCC < 18 V(1)
ILIML
Short circuit current
during thermal cycling
VCC = 13 V;
TR < Tj < TTSD
33
TTSD
Shutdown
temperature
150
175
200
°C
TR
Reset temperature(1)
TRS + 1
TRS + 7
TRS
Thermal reset of fault
diagnostic indication
VFR = 0 V; VSEn = 5 V
135
THYST
Thermal hysteresis
(TTSD - TR)(1)
7
ΔTJ_SD
Dynamic temperature
Tj = -40°C; VCC = 13 V
60
K
tLATCH_RST
Fault reset time for
output unlatch
VFR = 5 V to 0 V;
VSEn = 5 V; VIN = 5 V;
VSEL0,1 = 0 V
3
10
20
µs
VDEMAG
Turn-off output
voltage clamp
IOUT = 2 A; L = 6 mH; Tj = -
40°C
VCC -
38
V
IOUT = 2 A; L = 6 mH;
Tj = 25°C to 150°C
VCC -
41
VCC -
46
VCC -
52
V
Notes:
(1)Parameter guaranteed by design and characterization; not subjected to production test.
Electrical specification
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DocID027772 Rev 11
Table 9: MultiSense
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VSENSE_CL
MultiSense clamp
voltage
VSEn = 0 V; ISENSE = 1 mA
-17
-12
V
VSEn = 0 V; ISENSE = -1 mA
7
Current sense characteristics
K1
IOUT/ISENSE
IOUT = 3.5 A; VSENSE = 4 V;
VSEn = 5 V
5000
14200
31500
dK1/K1(1)(2)
Current sense
ratio drift
IOUT = 3.5 A; VSENSE = 4 V;
VSEn = 5 V
-30
30
%
KGP
IOUT/ISENSE
IOUT = 10 A; VSENSE = 4 V;
VSEn = 5 V
7990
13900
21050
dKGP/KGP(1)(2)
Current sense
ratio drift
IOUT = 10 A; VSENSE = 4 V;
VSEn = 5 V
-10
10
%
K2
IOUT/ISENSE
IOUT = 15 A; VSENSE = 4 V;
VSEn = 5 V
9580
13850
19020
dK2/K2(1)(2)
Current sense
ratio drift
IOUT = 15 A; VSENSE = 4 V;
VSEn = 5 V
-7
7
%
K3
IOUT/ISENSE
IOUT = 45 A; VSENSE = 4 V;
VSEn = 5 V
11470
13800
15840
dK3/K3(1)(2)
Current sense
ratio drift
IOUT = 45 A; VSENSE = 4 V;
VSEn = 5 V
-5
5
%
ISENSE0
MultiSense
leakage current
MultiSense disabled:
VSEn = 0 V
0
0.5
µA
MultiSense disabled:
-1 V < VSENSE < 5 V(1)
-0.5
0.5
MultiSense enabled:
VSEn = 5 V; All channels
ON; IOUTX = 0 A; ChX
diagnostic selected;
E.g. Ch0:
VIN0 = 5 V;
VIN1 = 5 V;
VSEL0 = 0 V;
VSEL1 = 0 V;
IOUT0 = 0 A;
IOUT1 = 15 A
0
120
MultiSense enabled:
VSEn = 5 V; ChX OFF; ChX
diagnostic selected:
E.g. Ch0:
VIN0 = 0 V;
VIN1 = 5 V;
VSEL0 = 0 V;
VSEL1 = 0 V;
IOUT1 = 15 A
0
2
VND7004AY
Electrical specification
DocID027772 Rev 11
13/47
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VOUT_MSD(1)
Output Voltage for
MultiSense
shutdown
VSEn = 5 V;
RSENSE = 2.7 kΩ;
E.g. Ch0:
VIN0 = 5 V;
VSEL0 = 0 V;
VSEL1 = 0 V;
IOUT0 = 15 A
5
V
VSENSE_SAT
Multisense
saturation voltage
VCC = 7 V;
RSENSE = 2.7 kΩ;
VSEn = 5 V; VIN0 = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
IOUT0 = 45 A; Tj = 150°C
5
V
ISENSE_SAT(1)
CS saturation
current
VCC = 7 V; VSENSE = 4 V;
VIN0 = 5 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
Tj = 150°C
4
mA
IOUT_SAT(1)
Output saturation
current
VCC = 7 V; VSENSE = 4 V;
VIN0 = 5 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
Tj = 150°C
65
A
OFF-state diagnostic
VOL
OFF-state open-
load voltage
detection
threshold
VSEn = 5 V; ChX OFF;
ChX diagnostic selected
E.g: Ch0
VIN0 = 0 V;
VSEL0 = 0 V;
VSEL1 = 0 V
2
3
4
V
IL(off2)
OFF-state output
sink current
VIN = 0 V; VOUT = VOL;
Tj = -40°C to 125°C
-100
-15
µA
tDSTKON
OFF-state
diagnostic delay
time from falling
edge of INPUT
(see Figure 7:
"TDSTKON")
VSEn = 5 V; ChX ON to
OFF transition;
ChX diagnostic selected
E.g: Ch0
VIN0 = 5 V to 0 V;
VSEL0 = 0 V;
VSEL1 = 0 V;
IOUT0 = 0 A;
VOUT = 4 V
100
350
700
µs
tD_OL_V
Settling time for
valid OFF-state
open load
diagnostic
indication from
rising edge of SEn
VIN0 = 0 V; VIN1 = 0 V;
VFR = 0 V; VSEL0 = 0 V;
VSEL1 = 0 V; VOUT0 = 4 V;
VSEn = 0 V to 5 V
60
µs
Electrical specification
VND7004AY
14/47
DocID027772 Rev 11
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
tD_VOL
OFF-state
diagnostic delay
time from rising
edge of VOUT
VSEn = 5 V; ChX OFF;
ChX diagnostic selected
E.g: Ch0
VIN0 = 0 V;
VSEL0 = 0 V;
VSEL1 = 0 V;
VOUT = 0 V to 4 V
5
30
µs
Chip temperature analog feedback
VSENSE_TC
MultiSense output
voltage
proportional to
chip temperature
VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; VIN0,1 = 0 V;
RSENSE = 1 kΩ; Tj = -40°C
2.325
2.41
2.495
V
VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; VIN0,1 = 0 V;
RSENSE = 1 kΩ; Tj = 25°C
1.985
2.07
2.155
V
VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; VIN0,1 = 0 V;
RSENSE = 1 kΩ; Tj = 125°C
1.435
1.52
1.605
V
dVSENSE_TC/dT(1)
Temperature
coefficient
Tj = -40°C to 150°C
-5.5
mV/K
Transfer function
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
VCC supply voltage analog feedback
VSENSE_VCC
MultiSense output
voltage
proportional to VCC
supply voltage
VCC = 13 V; VSEn = 5 V;
VSEL0 = 5 V; VSEL1 = 5 V;
VIN0,1 = 0 V;
RSENSE = 1 kΩ
3.16
3.23
3.3
V
Transfer function (3)
VSENSE_VCC = VCC / 4
Fault diagnostic feedback (see Table 10: "Truth table")
VSENSEH
MultiSense output
voltage in fault
condition
VCC = 13 V;
RSENSE = 1 kΩ;
E.g: Ch0 in open
load VIN0 = 0 V;
VSEn = 5 V;
VSEL0 = 0 V;
VSEL1 = 0 V;
IOUT0 = 0 A;
VOUT = 4 V
5
6.6
V
ISENSEH
MultiSense output
current in fault
condition
VCC = 13 V; VSENSE = 5 V
7
20
30
mA
MultiSense timings (current sense mode - see Figure 5: "MultiSense timings (current sense
mode)")(4)
tDSENSE1H
Current sense
settling time from
rising edge of SEn
VIN = 5 V; VSEn = 0 V to
5 V; RSENSE = 1 kΩ;
RL = 0.87 Ω
60
µs
VND7004AY
Electrical specification
DocID027772 Rev 11
15/47
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
tDSENSE1L
Current sense
disable delay time
from falling edge
of SEn
VIN = 5 V; VSEn = 5 V to
0 V; RSENSE = 1 kΩ;
RL = 0.87 Ω
5
20
µs
tDSENSE2H
Current sense
settling time from
rising edge of
INPUT
VIN = 0 V to 5 V;
VSEn = 5 V;
RSENSE = 1 kΩ;
RL = 0.87 Ω
170
400
µs
ΔtDSENSE2H
Current sense
settling time from
rising edge of IOUT
(dynamic
response to a step
change of IOUT)
VIN = 5 V; VSEn = 5 V;
RSENSE = 1 kΩ; ISENSE
= 90 % of ISENSEMAX;
RL = 0.87 Ω
200
µs
tDSENSE2L
Current sense
turn-off delay time
from falling edge
of INPUT
VIN = 5 V to 0 V;
VSEn = 5 V;
RSENSE = 1 kΩ;
RL = 0.87 Ω
50
250
µs
MultiSense timings (chip temperature sense mode - see Figure 6: "Multisense timings (chip
temperature and VCC sense mode)")(4)
tDSENSE3H
VSENSE_TC settling
time from rising
edge of SEn
VSEn = 0 V to 5 V;
VSEL0 = 0 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
60
µs
tDSENSE3L
VSENSE_TC disable
delay time from
falling edge of
SEn
VSEn = 5 V to 0 V;
VSEL0 = 0 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
20
µs
MultiSense timings (VCC voltage sense mode - see Figure 6: "Multisense timings (chip
temperature and VCC sense mode)")(4)
tDSENSE4H
VSENSE_VCC settling
time from rising
edge of SEn
VSEn = 0 V to 5 V;
VSEL0 = 5 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
60
µs
tDSENSE4L
VSENSE_VCC disable
delay time from
falling edge of
SEn
VSEn = 5 V to 0 V;
VSEL0 = 5 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
20
µs
MultiSense timings (Multiplexer transition times)(4)
tD_XtoY
MultiSense
transition delay
from ChX to ChY
VIN0 = 5 V; VIN1 = 5 V;
VSEn = 5 V; VSEL1 = 0 V;
VSEL0 = 0 V to 5 V;
IOUT0 = 0 A; IOUT1 = 15 A;
RSENSE = 1 kΩ
20
µs
tD_CStoTC
MultiSense
transition delay
from current
sense to TC sense
VIN0 = 5 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V to
5 V; IOUT0 = 1.5 A;
RSENSE = 1 kΩ
60
µs
Electrical specification
VND7004AY
16/47
DocID027772 Rev 11
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
tD_TCtoCS
MultiSense
transition delay
from TC sense to
current sense
VIN0 = 5 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 5 V to
0 V; IOUT0 = 1.5 A;
RSENSE = 1 kΩ
20
µs
tD_CStoVCC
MultiSense
transition delay
from current
sense to VCC
sense
VIN1 = 5 V; VSEn = 5 V;
VSEL0 = 5 V; VSEL1 = 0 V to
5 V; IOUT1 = 15A;
RSENSE = 1 kΩ
60
µs
tD_VCCtoCS
MultiSense
transition delay
from VCC sense to
current sense
VIN1 = 5 V; VSEn = 5 V;
VSEL0 = 5 V; VSEL1 = 5 V to
0 V; IOUT1 = 15 A;
RSENSE = 1 kΩ
20
µs
tD_TCtoVCC
MultiSense
transition delay
from TC sense to
VCC sense
VCC = 13 V; Tj = 125°C;
VSEn = 5 V; VSEL0 = 0 V to
5 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
20
µs
tD_VCCtoTC
MultiSense
transition delay
from VCC sense to
TC sense
VCC = 13 V; Tj = 125°C;
VSEn = 5 V; VSEL0 = 5 V to
0 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
20
µs
tD_CStoVSENSEH
MultiSense
transition delay
from stable
current sense on
ChX to VSENSEH on
ChY
VIN0 = 5 V; VIN1 = 0 V;
VSEn = 5 V; VSEL1 = 0 V;
VSEL0 = 0 V to 5 V;
IOUT0 = 3 A; VOUT1 = 15 V;
RSENSE = 1 kΩ
20
µs
Notes:
(1)Parameter guaranteed by design and characterization; not subjected to production test.
(2)All values refer to VCC = 13 V; Tj = 25 °C, unless otherwise specified.
(3)VCC sensing and TC sensing are referred to GND potential.
(4)Transition delay are measured up to +/- 10% of final conditions.
VND7004AY
Electrical specification
DocID027772 Rev 11
17/47
Figure 4: Switching time and Pulse skew
Figure 5: MultiSense timings (current sense mode)
VOUT
t
Vcc
twon
80% Vcc
20% Vcc
twoff
INPUT
td(on)
tpLH tpHL
td(off)
t
dVOUT/dt
ON OFF
dVOUT/dt
CURRENT SENSE
IN1
SEn
IOUT1
tDSENSE2H tDSENSE1L tDSENSE2L
tDSENSE1H
SEL0
SEL1 Low
High
Low
High
Low
High
Electrical specification
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DocID027772 Rev 11
Figure 6: Multisense timings (chip temperature and VCC sense mode)
Figure 7: TDSTKON
SENSE
SEn
VCC
tDSENSE4H tDSENSE4L tDSENSE3L
tDSENSE3H
SEL0
SEL1 Low
High
Low
High
Low
High
VSENSE = VSENSE_VCCVSENSE = VSENSE_TC
VCC VOLTAGE SENSE MODE CHIP TEMPERATURE SENSE MODE
GAPGCFT00319
TDSTKON
VINPU T
VOUT
MultiSense
VOUT> VOL
GAPG2609141140CFT
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Electrical specification
DocID027772 Rev 11
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Table 10: Truth table
Mode
Conditions
INX
FR
SEn
SELX
OUTX
MultiSense
Comments
Standby
All logic inputs
low
L
L
L
L
L
Hi-Z
Low quiescent
current
consumption
Normal
Nominal load
connected;
Tj < 150 °C
L
X
See (1)
L
See (1)
H
L
H
See (1)
Outputs
configured for
auto-restart
H
H
H
See (1)
Outputs
configured for
Latch-off
Overload
Overload or
short to GND
causing:
Tj > TTSD or
ΔTj > ΔTj_SD
L
X
See (1)
L
See (1)
H
L
H
See (1)
Output cycles
with
temperature
hysteresis
H
H
L
See (1)
Output latches-
off
Undervoltage
VCC < VUSD
(falling)
X
X
X
X
L
L
Hi-Z
Hi-Z
Re-start when
VCC > VUSD +
VUSDhyst (rising)
OFF-state
diagnostics
Short to VCC
L
X
See (1)
H
See (1)
Open-load
L
X
H
See (1)
External pull-up
Negative
output voltage
Inductive
loads turn-off
L
X
See (1)
< 0 V
See (1)
Notes:
(1)Refer to Table 11: "MultiSense multiplexer addressing"
Table 11: MultiSense multiplexer addressing
SEn
SEL1
SEL0
MUX channel
MultiSense output
Normal
mode
Overload
OFF-state
diag. (1)
Negative
output
L
X
X
Hi-Z
H
L
L
Channel 0
diagnostic
ISENSE =
1/K * IOUT0
VSENSE =
VSENSEH
VSENSE =
VSENSEH
Hi-Z
H
L
H
Channel 1
diagnostic
ISENSE =
1/K * IOUT1
VSENSE =
VSENSEH
VSENSE =
VSENSEH
Hi-Z
H
H
L
TCHIP Sense
VSENSE = VSENSE_TC
H
H
H
VCC Sense
VSENSE = VSENSE_VCC
Notes:
(1)In case the output channel corresponding to the selected MUX channel is latched off while the
relevant input is low, Multisense pin delivers feedback according to OFF-State diagnostic.
Example 1: FR = 1; IN0 = 0; OUT0 = L (latched); MUX channel = channel 0 diagnostic; Mutisense = 0.
Example 2: FR = 1; IN0 = 0; OUT0 = latched, VOUT0 > VOL; MUX channel = channel 0 diagnostic;
Mutisense = VSENSEH
Electrical specification
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DocID027772 Rev 11
2.4 Waveforms
Figure 8: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD)
Figure 9: Latch functionality - behavior in hard short circuit condition
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Electrical specification
DocID027772 Rev 11
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Figure 10: Latch functionality - behavior in hard short circuit condition (autorestart mode +
latch off)
Figure 11: Standby mode activation
Electrical specification
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DocID027772 Rev 11
Figure 12: Standby state diagram
2.5 Electrical characteristics curves
Figure 13: OFF-state output current
Figure 14: Standby current
Figure 15: IGND(ON) vs. Iout
Figure 16: Logic Input high level voltage
GAPGCFT00598
Normal Operation
Stand-by Mode
t > tD_STBY
INx = Low
AND
FaultRST = Low
AND
SEn = Low
AND
SELx = Low
INx = High
OR
FaultRST = High
OR
SEn = High
OR
SELx = High
VND7004AY
Electrical specification
DocID027772 Rev 11
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Figure 17: Logic Input low level voltage
Figure 18: High level logic input current
Figure 19: Low level logic input current
Figure 20: Logic Input hysteresis voltage
Figure 21: FaultRST Input clamp voltage
Figure 22: Undervoltage shutdown
Electrical specification
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Figure 23: On-state resistance vs. Tcase
Figure 24: On-state resistance vs. VCC
Figure 25: Turn-on voltage slope
Figure 26: Turn-off voltage slope
Figure 27: Won vs. Tcase
Figure 28: Woff vs. Tcase
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Electrical specification
DocID027772 Rev 11
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Figure 29: OFF-state open-load voltage
detection threshold
Figure 30: Vsense clamp vs. Tcase
Figure 31: Vsenseh vs. Tcase
Protections
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3 Protections
3.1 Power limitation
The basic working principle of this protection consists of an indirect measurement of the
junction temperature swing ΔTj through the direct measurement of the spatial temperature
gradient on the device surface in order to automatically shut off the output MOSFET as
soon as ΔTj exceeds the safety level of 60 K. According to the voltage level on the
FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis
according to the maximum instantaneous power which can be handled (FaultRST = Low)
or remains off (FaultRST = High). The protection prevents fast thermal transient effects
and, consequently, reduces thermo-mechanical fatigue.
3.2 Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold
(typically 175°C), it automatically switches off and the diagnostic indication is triggered.
According to the voltage level on the FaultRST pin, the device switches on again as soon
as its junction temperature drops to TRS (FaultRST = Low) or remains off
(FaultRST = High).
3.3 Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well
as the other components of the system (e.g. bonding wires, wiring harness, connectors,
loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or
during load power-up, the output current is clamped to a safety level, ILIMH, by operating the
output power MOSFET in the active region.
3.4 Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during
turn off. A negative voltage clamp structure limits the maximum negative voltage to a
certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the
device.
VND7004AY
Application information
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4 Application information
Figure 32: Application diagram
4.1 GND protection network against reverse battery
Figure 33: Simplified internal structure
The device does not need any external components to protect the internal logic in case of a
reverse battery condition. The protection is provided by internal structures.
MCU
INPUT
SEn
Multisense
FaultRST
Vcc
OUTPUT
GND
Rprot
Rprot
Rprot
Rprot
Dld
Rsense
5V
GND
Application information
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In addition, due to the fact that the output MOSFET turns on even in reverse battery mode,
thus providing the same low ohmic path as in regular operating conditions, no additional
power dissipation has to be considered.
4.2 Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 12: "ISO 7637-2 -
electrical transient conduction along supply line".
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present
device only, without components and accessed through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns
automatically to normal operation after the test”.
Table 12: ISO 7637-2 - electrical transient conduction along supply line
Test
Pulse
2011(E)
Test pulse severity
level with Status II
functional performance
status
Minimum
number of
pulses or test
time
Burst cycle /
pulse
repetition time
Pulse duration and
pulse generator
internal impedance
Level
US(1)
min
max
1
III
-112 V
500 pulses
0.5 s
2 ms, 10 Ω
2a(3)
III
+55 V
500 pulses
0.2 s
5 s
50 µs, 2 Ω
3a
IV
-220 V
1h
90 ms
100
ms
0.1 µs, 50 Ω
3b
IV
+150 V
1h
90 ms
100
ms
0.1 µs, 50 Ω
4 (2)
IV
-7 V
1 pulse
100 ms, 0.01 Ω
Load dump according to ISO 16750-2:2010
Test B(3)
40 V
5 pulse
1 min
400 ms, 2 Ω
Notes:
(1)US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
(2)Test pulse from ISO 7637-2:2004(E).
(3)With 40 V external suppressor referred to ground (-40°C < Tj < 150 °C).
4.3 MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to
prevent the microcontroller I/O pins from latching-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of
microcontroller and the current required by the HSD I/Os (Input levels compatibility) with
the latch-up limit of microcontroller I/Os.
VND7004AY
Application information
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Equation
VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax
Calculation example:
For VCCpeak = -150 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V
7.5 kΩ ≤ Rprot ≤ 140 kΩ.
Recommended values: Rprot = 15 kΩ
4.4 Multisense - analog current sense
Diagnostic information on device and load status are provided by an analog output pin
(MultiSense) delivering the following signals:
Current monitor: current mirror of channel output current
VCC monitor: voltage propotional to VCC
TCASE: voltage propotional to chip temperature
Those signals are routed through an analog multiplexer which is configured and controlled
by means of SELx and SEn pins, according to the address map in MultiSense multiplexer
addressing Table.
Figure 34: MultiSense and diagnostic – block diagram
Application information
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4.4.1 Principle of Multisense signal generation
Figure 35: MultiSense block diagram
Current monitor
When current mode is selected via MultiSense, this output is capable of providing:
Current mirror proportional to the load current in normal operation, delivering current
proportional to the load according to a known ratio named K
Diagnostics flag in fault conditions delivering fixed voltage VSENSEH
The current delivered by the current sense circuit, ISENSE, can be easily converted to a
voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load
monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), VSENSE calculation can
be done using simple equations
Current provided by MultiSense output: ISENSE = IOUT/K
Voltage on RSENSE: VSENSE = RSENSE · ISENSE = RSENSE · IOUT/K
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Application information
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Where:
VSENSE is the voltage measurable on RSENSE resistor
ISENSE is the current provided from MultiSense pin in current output mode
IOUT is the current flowing through output
K factor represents the ratio between PowerMOS cells and SenseMOS cells; its
spread includes geometric factor spread, current sense amplifier offset and process
parameters spread of overall circuitry specifying the ratio between IOUT and ISENSE.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the MultiSense pin
which is switched to a “current limited” voltage source, VSENSEH.
In any case, the current sourced by the MultiSense in this condition is limited to ISENSEH.
The typical behavior in case of overload or hard short circuit is shown in Waveforms
section.
Figure 36: Analogue HSD – open-load detection in off-state
Application information
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Figure 37: Open-load / short to VCC condition
Table 13: MultiSense pin levels in off-state
Condition
Output
MultiSense
SEn
Open-load
VOUT > VOL
Hi-Z
L
VSENSEH
H
VOUT < VOL
Hi-Z
L
0
H
Short to VCC
VOUT > VOL
Hi-Z
L
VSENSEH
H
Nominal
VOUT < VOL
Hi-Z
L
0
H
4.4.2 TCASE and VCC monitor
In this case, MultiSense output operates in voltage mode and output level is referred to
device GND. Care must be taken in case a GND network protection is used, because a
voltage shift is generated between the device GND and the microcontroller input GND
reference.
Figure 38: "GND voltage shift" shows the link between VMEASURED and the real VSENSE
signal.
VSENSEH
VSENSE = 0
VSENSEH
tDSTKON
VSENSE
VSENSE
VIN
Pull-up connected
Pull-up
disconnected
Open-load
Short to VCC
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Figure 38: GND voltage shift
VCC monitor
Battery monitoring channel provides VSENSE = VCC / 8.
Case temperature monitor
Case temperature monitor is capable of providing information about the actual device
temperature. Since a diode is used for temperature sensing, the following equation
describes the link between temperature and output VSENSE level:
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40 °C to 150 °C)).
4.4.3 Short to VCC and OFF-state open-load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device off-state. Small or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
It is preferable that VPU is switched off during the module standby mode in order to avoid
the overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following
equation:
Equation
Package and PCB thermal data
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5 Package and PCB thermal data
5.1 PowerSSO-36 thermal data
Figure 39: PowerSSO-36 PC board
VND7004AY
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Table 14: PCB properties
Dimension
Value
Board finish thickness
1.6 mm +/- 10%
Board dimension
129 mm x 60 mm
Board Material
FR4
Copper thickness (top and bottom layers)
0.070 mm
Copper thickness (inner layers)
0.035 mm
Thermal vias separation
1.2 mm
Thermal via diameter
0.3 mm +/- 0.08 mm
Copper thickness on vias
0.025 mm
Footprint dimension (top layer)
4.1 mm x 6.5 mm
Heatsink copper area dimension (bottom layer)
Footprint, 2 cm2 or 8 cm2
Figure 40: Rthj-amb vs PCB copper area in open box free air conditions
30
35
40
45
50
55
60
65
0 2 4 6 8 10
RTHjamb
RTHjamb
Package and PCB thermal data
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Figure 41: PowerSSO-36 thermal impedance junction ambient single pulse
Equation: pulse calculation formula
ZTHδ = RTH · δ + ZTHtp (1 - δ)
where δ = tP/T
Figure 42: Thermal fitting model for PowerSSO-36
The fitting model is a simplified thermal tool and is valid for transient evolutions
where the embedded protections (power limitation or thermal cycling during
thermal shutdown) are not triggered.
0.1
1
10
100
0.0001 0.001 0.01 0.1 1 10 1001000
ZTH (°C/W)
Time (s)
Cu=8 cm2
Cu=2 cm2
Cu=foot print
4Layer
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Table 15: Thermal parameters
Area/island (cm2)
FP
2
8
4L
R1 = R7 (°C/W)
0.01
R2 = R8 (°C/W)
1.2
R3 (°C/W)
3.4
3.4
3.4
2.6
R4 (°C/W)
6
6
6
3
R5 (°C/W)
18
14
10
2
R6 (°C/W)
30
26
15
7
C1 = C7 (W·s/°C)
0.0005
C2 = C8 (W·s/°C)
0.001
C3 (W·s/°C)
0.1
C4 (W·s/°C)
0.5
0.8
0.8
1
C5 (W·s/°C)
1
2
3
10
C6 (W·s/°C)
3
5
9
18
Maximum demagnetization energy (VCC = 16 V)
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6 Maximum demagnetization energy (VCC = 16 V)
Figure 43: Maximum turn off current versus inductance
Values are generated with RL = 0 Ω.
In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of
every pulse must not exceed the temperature specified above for curves A and B.
0.1
1
10
100
0.1 1 10 100 1000
I (A)
L (mH)
VND7004AY - Single Pulse
Repetitive pulse Tjstart=100°C
Repetitive pulse Tjstart=125°C
VND7004AY
Package information
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7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1 PowerSSO-36 package information
Figure 44: PowerSSO-36 package outline
Table 16: PowerSSO-36 mechanical data
Ref.
Dimensions
Millimeters
Min.
Typ.
Max.
Θ
0°
8°
Θ1
5°
10°
Θ2
0°
A
2.15
2.45
A1
0.00
0.10
BOTTOM VIEW TOP VIEW
SECTION A-A SECTION B-B
GAPG2508150825CFT
Package information
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Ref.
Dimensions
Millimeters
Min.
Typ.
Max.
A2
2.15
2.35
b
0.18
0.32
b1
0.13
0.25
0.30
c
0.23
0.32
c1
0.20
0.20
0.30
D
10.30 BSC
D1
6.90
7.50
D2
3.65
D3
4.30
e
0.50 BSC
E
10.30 BSC
E1
7.50 BSC
E2
4.30
5.20
E3
2.30
E4
2.90
G1
1.20
G2
1.00
G3
0.80
h
0.30
0.40
L
0.55
0.70
0.85
L1
1.40 REF
L2
0.25 BSC
N
36
R
0.30
R1
0.20
S
0.25
Tolerance of form and position
aaa
0.20
bbb
0.20
ccc
0.10
ddd
0.20
eee
0.10
fff
0.20
ggg
0.15
VND7004AY
Package information
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7.2 PowerSSO-36 packing information
Figure 45: PowerSSO-36 reel 13"
Table 17: Reel dimensions
Description
Value(1)
Base quantity
1000
Bulk quantity
1000
A (max)
330
B (min)
1.5
C (± 0.2)
13
F
20.2
G (+2 / -0)
24.4
N (min)
100
T (max)
30.4
Notes:
(1)All dimensions are in mm.
Package information
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Figure 46: PowerSSO-36 carrier tape
Table 18: PowerSSO-36 carrier tape dimensions
Description
Value(1)
A0
10.90 ± 0.10
B0
10.80 ± 0.10
K0
2.75 ± 0.10
K1
2.45 ± 0.10
D0
1.50 (+0.10 / -0)
D1
1.60 ± 0.10
P0
4.00 ± 0.10
P1
12.00 ± 0.10
P2
2.00 ± 0.10
P10
40.00 ± 0.20
E
1.75 ± 0.10
F
11.50 ± 0.10
W
24.00 ± 0.30
T
0.30 ± 0.05
Notes:
(1)All dimensions are in mm.
VND7004AY
Package information
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Figure 47: PowerSSO-36 schematic drawing of leader and trailer tape
7.3 PowerSSO-36 marking information
Figure 48: PowerSSO-36 marking information
Engineering Samples: Parts marked as “&” are not yet qualified and therefore not
approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of
these engineering samples in production. ST’s Quality department must be
contacted prior to any decision to use these engineering samples to run a
qualification activity.
Commercial Samples: fully qualified parts from ST standard production with no
usage restrictions.
Order codes
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8 Order codes
Table 19: Device summary
Package
Order codes
Tape and reel
PowerSSO-36
VND7004AYTR
VND7004AY
Revision history
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9 Revision history
Table 20: Document revision history
Date
Revision
Changes
23-Apr-2015
1
Initial release.
20-Jul-2015
2
Table 3: "Absolute maximum ratings":
-IOUT: updated value
Updated Table 4: "Thermal data" and Table 6: "Switching"
Table 8: "Protections":
TR, THYST: added note
Table 9: "MultiSense":
K0, dK0/K0: removed rows
Kx, dKx/Kx, IOUT_SAT: updated values
Added Section 5: "Package and PCB thermal data"
30-Jul-2015
3
Updated Figure 1: "Block diagram"
Updated Table 1: "Pin functions"
Table 3: "Absolute maximum ratings":
ISENSE: updated parameter and value
EMAX: updated parameter
Table 5: "Power section":
RON_REV: updated value
Table 9: "MultiSense":
VSENSE_CL, VSENSE_TC, VSENSE_VCC: updated test conditions
Removed following tables:
Table: Electrical transient requirements (part 1)
Table: Electrical transient requirements (part 2)
Table: Electrical transient requirements (part 3)
Added Section 4: "Application information"
02-Dec-2015
4
Table 5: "Power section":
ISTBY, IL(off): updated values
Updated Table 6: "Switching"
Table 9: "MultiSense":
Kx, tDSENSE2H: updated values
Added Section 2.5: "Electrical characteristics curves"
27-Jan-2016
5
Table 9: "MultiSense":
ISENSE0: updated value
Revision history
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Date
Revision
Changes
20-Apr-2016
6
Updated Features list
Table 3: "Absolute maximum ratings":
EMAX: updated value
Table 9: "MultiSense":
dKx/Kx, ISENSE_SAT, IOUT_SAT: added note
Added Section 6: "Maximum demagnetization energy (VCC = 16 V)"
26-Apr-2016
7
Updated Figure 1: "Block diagram" and Figure 34: "MultiSense and
diagnostic – block diagram"
15-Jul-2016
8
Updated Figure 45: "PowerSSO-36 reel 13""and Table 17: "Reel
dimensions"
02-Nov-2016
9
Updated Applications section
16-Dec-2016
10
in Table 6: "Switching"
- updated tSKEW Min. Typ. and Max. values
22-Jun-2017
11
Changed the K1 minimum value in Table 9: "MultiSense".
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