========================================================

| MPC555.C 03J12F Modules |

========================================================

| Current Module Revision |

========================================================

| BBC.CDR1UBUS_01_0 |

| CMF.192KB_CDR1UBUS_01_1 |

| CMF.256KA_CDR1UBUS_01_1 |

| DPTRAM.6K_CDR1IMB3_01_0 |

| JTAG.CDR1_01_0 |

| QADC64.CDR1IMB3_01_0 |

| QSMCM.CDR1IMB3_01_0 |

| TOUCAN.CDR1IMB3_03_0A |

| TPU3.CDR1IMB3_01_0 |

| UIMB.CDR1UBUSIMB3_01_0 |

| USIU.CDR1UBUS_01_0 |

========================================================

ERRATA AND INFORMATION SUMMARY

AR_252 Censorship has been disabled within the CMF

AR_226 Part number in IMMR is 0x04, and will change to 0x30. Mask number is 0.

AR_636 CMF: Program at reduced temperature and voltage ranges

AR_249 Do not use reset configuration word from the internal flash

AR_250 Ensure multiple pulses in program/erase sequence

AR_279 CMFCTL register field, CLKPE, definition is changing

AR_101 Be cautious when terminating flash programming early -- follow users manual

AR_102 Avoid margin read of flash at wrong time -- follow users manual

AR_105 Avoid margin read of flash at wrong time -- follow users manual

AR_268 Do not access any DPTRAM control registers in TPU emulation mode

AR_485 Disable of TPU emulation mode while MISC enabled corrupts data in RAM

AR_15 Only enter low power mode following a SYNC

AR_296 Do not use the value in the MIOS DASM B register when in input capture mode

AR_443 MIOS: Do not write data into the MDASMBR when in an input mode.

AR_444 MIOS: Warning in MDASM OPWM mode when MDASMAR = MDASMBR.

AR_446 MIOS: Avoid 100% pulse in MDASM OPWM mode.

AR_452 MIOS: "non-reset" registers are undefined after reset.

AR_351 Hreset and Sreset falsely change during poreset and powerdown

AR_182 Minimize resistance between CLKOUT and any loads

AR_298 Latch address during address phase of write cycle

AR_127 Ignore data obtained from JTAG for IRQ6 pin

AR_128 Configure MIOS/VF/VFLS pins as all MIOS or all VF/VFLS

AR_209 Hysteresis is unavailable on MIOS pins

AR_349 Drive 3V inputs to the rail

AR_454 Use external resistors/drivers when using external reset configuration word

AR_680 CLKOUT and ENGCLK drive strengths will change

AR_154 0 in the PDMCR sets pads to slow slew rate -- see later versions of users manua

AR_292 QADC64 Pins have active pull-ups

AR_219 Avoid (or fix output from) compilers which generate specific branch sequence

AR_754 QADC64:Do not use queue1 in external gated mode with queue2 in continuous mode.

AR_89 Mask off address field data during QADC port register reads in external mux mod

AR_143 Use software to disable QADC external gated single scan mode at end of queue

AR_144 In external gated continuous scan mode of the QADC, avoid use of CCW-EOQ

AR_145 Do not program QADC64 QACR2 BQ2 field to a value greater than 63

AR_307 Program the QADC64 end of Q2 in software cont mode with CCW-EOQ

AR_421 QADC64: Don’t switch to software triggered continuous scan after completing Q1.

AR_422 QADC64: Do not rely on set of TOR1 in external gated continuous scan mode

AR_419 QADC64: False trigger upon configuration (Does NOT apply to ALL parts)

AR_420 QADC64: Don’t change BQ2 with a set of SSE2 without a mode change.

AR_435 QADC64: TOR1 flag operates in both single and continuous external gated modes.

AR_577 TPU3 - TCR2PSCK2 bit does not give TCR2 divide ratios specified.

AR_498 UIMB: Read failures occur for IMB accesses when IMB clock is half speed

AR_90 Poll TPU3 development status register to determine if TPU breakpoint occurs

AR_92 Avoid instruction accesses from IMB regions

AR_231 Avoid external master accesses to internal resources which result in data error

AR_232 Do not configure IRQ1 and IRQ4 pins as AT2, RSV, or GPIO

AR_235 Do not activate data show cycles when external master may access internal space

AR_236 In slave mode, do not access another MPC55X

AR_239 Reprogram RTCAL register for accurate real time clock interrupts

AR_241 External write data may be corrupted during reset (SRESET or HRESET)

AR_224 Run external bus in full frequency mode (not half frequency)

AR_234 Program must not change locked bits in the SIUMCR register

AR_237 Read the USIU GPIO data register immediately after every data direction change

AR_240 External master should not request burst from the MPC555

AR_242 Avoid 2 accesses in a row to non-existent external addresses

AR_304 Factory test mode required to use TPU debug features

AR_380 Assert PORESET until all 3V supplies are in regulation

AR_610 Additional current on KAPWR when power is not applied

AR_227 Use MIOS PWM channel instead of ENGCLK to generate 1MHz clock

AR_238 Avoid byte writes to PDMCR

AR_270 Write either all 0s or all 1s to the reserved bits of SGPIOCR[8:15]

AR_287 Set the TBS bit in SCCR register when MODCK(1) = 0

AR_288 Avoid unnecessary MF changes

AR_289 HRESET may be shorter than 70ns during SWT reset

AR_379 Don’t set MLRC=11 in multiple master configurations

AR_483 USIU: BDIP may not assert for non-MEMC mapped accesses

AR_222 Program the memory controller base registers prior to enabling it

AR_269 Load address signal is not provided when external master initiates cycles

DETAILED ERRATA DESCRIPTIONS

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CDR_AR_252 Customer Erratum MPC555.C

Censorship has been disabled within the CMF

DESCRIPTION:

The censorship mode for the CMF modules has been disabled. The value of the CMF

Censor bits will not provide any protection of the contents of the CMF memory

array.

Part number in IMMR is 0x04, and will change to 0x30. Mask number is 0.

DESCRIPTION:

Part Number in IMMR is incorrectly 0x04 and will be changed in a future revision

to 0x30. The mask number for this revision is 0.

WORKAROUND:

Write software so that both part number values are identified as the MPC555 device.

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CDR_AR_382 Customer Information MPC555.C

7ns). AC specifications: 8, 8a, 8b, 11 are 15ns (were 13ns). AC specification 15

is 10ns (was 9.75ns). AC specification 19 max is 15ns (was 14ns). AC specification

20 max is 9ns (was 8ns). AC specification 22 is 9ns (was 8ns). AC specifications

28, 29 are 14ns (were 7ns). AC specification 23 is 1ns minimum (was 2ns).

WORKAROUND:

Ensure external devices are matched to these specifications.

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CDR_AR_441 Customer Information MPC555.C

Updated Operating Current Projections

DESCRIPTION:

The operating current specification is listed as TBD in version 2.1 of the

electrical specification. The estimated currents in Addendum 2 are outdated. The

currents listed below are the design targets, and will be updated and become part

of the specification when final silicon is fully characterized.

consumed via VDDI, causing IDDI to be larger than the above projection. NOTE: As

shown in the above numbers, VDDSRAM should be capable of supplying operating

current -- a suggested connection is shown in Figure 8-11 External Power Supply

Scheme of the MPC555 User’s Manual.

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CDR_AR_212 Customer Erratum BBC.CDR1UBUS_01_0

Do not assert SRESET pin without asserting HRESET first

DESCRIPTION:

BBC samples reset configuration using SRESET. If only SRESET is asserted, reset

configuration bits in BBC may be corrupted. Reset configuration bits in BBC include

CDR_AR_213 Customer Erratum BBC.CDR1UBUS_01_0

Ignore redundant instruction show cycles

DESCRIPTION:

Instruction Show cycle may be repeated several times.

WORKAROUND:

Ignore the extra show cycles. This is a rare situation.

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will be determined as if address[7:9] were replaced by IMMR[ISB]. It is not

possible to alter protection attributes (User/supervisor, access, and guarded)

where address[7:9] is not the same as IMMR[ISB]. When accessing external address to

MPC555 space region then the protection attributes are matched as if the address

was in the internal range.

WORKAROUND:

Use the same IMPU protection for all address spaces.

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CDR_AR_261 Customer Erratum CMF.192KB_CDR1UBUS_01_1

Boot from internal flash at low frequency (˜ 10 MHz or less)

DESCRIPTION:

The CMF does not negate the data error signal quickly enough. As a result, the CMF

may inadvertently data error accesses. This makes it difficult to boot from flash

except at low frequencies. In addition, access to the CMF immediately following

data errored accesses may result in a data error. When the error occurs, the core

frequency and booting from the CMF module.

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CDR_AR_636 Customer Erratum CMF.192KB_CDR1UBUS_01_1

CMF: Program at reduced temperature and voltage ranges

DESCRIPTION:

There may be insufficient program margin to be able to correctly read all bits of

the array at cold with 3.0Vdd if the part was programmed at hot.

WORKAROUND:

Workarounds in order of effectiveness: First, reduce temperature while programming.

temperature range.

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CDR_AR_249 Customer Erratum CMF.192KB_CDR1UBUS_01_1

Do not use reset configuration word from the internal flash

DESCRIPTION:

The device cannot boot using the reset configuration word from the internal flash

register (CMFCFIG). If the internal value is used, the device will be unable to

boot, and will be unable to accessed via the development port.

word; note that this prevents booting from CMF.

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CDR_AR_250 Customer Erratum CMF.192KB_CDR1UBUS_01_1

Ensure multiple pulses in program/erase sequence

DESCRIPTION:

On the 1st program/erase pulse, HVS may not set.

WORKAROUND:

Follow the specified program/erase sequence in the user manual. This will result in

DESCRIPTION:

The CLKPE field in the CMFCTL register now has a new definition for PE=0 beginning

with CMF_02_0_MODULES revision of the CMF module:CLKPE[0:1]=00 Exponent = 5,

CLKPE[0:1]=01 Exponent = 6,CLKPE[0:1]=10 Exponent = 7, CLKPE[0:1]=11 Exponent =

8

WORKAROUND:

Software requires update for the new CLKPE definition.

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CDR_AR_101 Customer Information CMF.256KA_CDR1UBUS_01_1

Be cautious when terminating flash programming early -- follow users manual

Don’t terminate the program or erase cycle early and then immediately read the

array. No problem will occur if program/erase sequence as defined in the spec is

followed.

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CDR_AR_102 Customer Information CMF.192KB_CDR1UBUS_01_1

Avoid margin read of flash at wrong time -- follow users manual

DESCRIPTION:

If the first array interlock write is followed on the next clock by an array margin

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CDR_AR_105 Customer Information CMF.192KB_CDR1UBUS_01_1

Avoid margin read of flash at wrong time -- follow users manual

DESCRIPTION:

If margin reads are done in between writes to the same page before a programming,

only the first read will return the correct value. The data to be programmed is

correct.

DESCRIPTION:

When the DPTRAM is in TPU emulation mode, the DPTRAM spuriously asserts the TEA

signal if HOST tries to access any of its control registers.

WORKAROUND:

Set up all DPTRAM control registers before putting the device in emulation mode. Do

not access them upon entering the emulation mode.

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CDR_AR_485 Customer Information DPTRAM.6K_CDR1IMB3_01_0

Disable of TPU emulation mode while MISC enabled corrupts data in RAM

In test mode / TPU development mode, disable the MISCEN (DPTMCR) before negation of

TPEMEM in the TCR. In normal mode, disable MISCEN prior to performing a soft reset

of the TPU (TPUMCR2).

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CDR_AR_15 Customer Erratum L2U.CDR1LBUSUBUS_01_0

Only enter low power mode following a SYNC

DESCRIPTION:

During entry into low power mode, the device can be stalled in a deadlock

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CDR_AR_142 Customer Erratum L2U.CDR1LBUSUBUS_01_0

Leave L-bus show cycles disabled

DESCRIPTION:

A data showcycle may be missed or the data from previous showcycle may be corrupted

for U-bus pipelined showcycles. This may cause the device to hang. Instruction

showcycle is not affected by this errata. Data showcycle cannot be done through L-

bus. However, data showcycle through U-bus is not affected.

Insert additional machine check handler at h1400

DESCRIPTION:

The 10K RAM issues the wrong exception request for accesses which cause an

exception. The processor will execute a dsi exception (vector to h1400) instead of

a machine check exception (vector to h0200).

WORKAROUND:

Make sure that the code at vector h1400 will handle the exception.

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CDR_AR_93 Customer Erratum LRAM.10KA_CDR1LBUS_01_0

development hardware.

WORKAROUND:

None.

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CDR_AR_445 Customer Erratum MIOS1.CDR1IMB3_01_0

Potential trap state in MIOS MDASM in OPWM mode.

DESCRIPTION:

WORKAROUND:

Ensure that the software never writes MDASMBR (in OPWM mode) to a value which is

less than the MCSMMOD value.

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CDR_AR_211 Customer Information RCPU.CDR1LBUSIBUS_11_1

Do not break point mtspr ICTRL instruction

DESCRIPTION:

When a break point is set on mtspr ICTRL Rx instruction and value of bit 28 (IFM)

is 1, the result will be unpredictable. Break Point can be taken or not on the

instruction and value of the IFM bit can be either 0 or 1.

Only negate interrupts while the EE bit (MSR) disables interrupts

DESCRIPTION:

An IRQ to the core, which is negated before the core services it, may cause the

core to stop fetching until reset.

WORKAROUND:

Interrupt request to the core should only be negated while interrupts are disabled

by the EE bit in the MSR. Software should disable interrupts in the CPU core prior

to masking or disabling any interrupt which might be currently pending at the CPU

core. For external interrupts, it is recommended to use the edge triggered

interrupt scheme. After disabling an interrupt, sufficient time should be allowed

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CDR_AR_563 Customer Erratum QADC64.CDR1IMB3_01_0

QSM/QSMCM/QADC64 corrupts data after an IACK cycle in CISC parts.

DESCRIPTION:

This problem does not affect parts that do not run IACK cycles (i.e. RISC CPUs).

The Common BIU state machine, used by the QSM/QSMCM/QADC64, mis-tracks an IACK

cycle if an interrupt is issued while an IACK cycle for the same level is in

progress. In this case, the next access on the IMB3 will be corrupted by the

(handler address) causes the processor to jump to an incorrect location or to

produce an address error.

WORKAROUND:

Workarounds exist for both CPU32 and CPU32X based parts. On CPU32 based parts the

first access after an IACK cycles is the stacking of the vector offset The risk to

the system by corrupting this stacked value is very low, it is not used by the

processor. On CPU32X based parts which have the stack located in the FASRAM the

first IMB3 access is the fetch from the vector table. Corruption of this value

(handler address) causes the processor to jump to an incorrect location or to

produce an address error. The suggested workarounds for the QSM/QSMCM/QADC64 are

listed below. For CPU32 based parts: - assign the QSM/QSMCM/QADC64 it’s own

Loss of Accuracy upon current injection to analog pins

DESCRIPTION:

QADC64 conversion results are affected when the immediately following channel

undergoes a current injection condition. When a channel being converted experiences

current injection, the prior conversion will be affected (regardless of which

channel was the prior conversion). Up to 7 counts of deviation are seen at 1 ma of

injection. At ˜20 ua of current injection, there is a one count deviation.

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CDR_AR_754 Customer Erratum QADC64.CDR1IMB3_01_0

QADC64:Do not use queue1 in external gated mode with queue2 in continuous mode.

DESCRIPTION:

When the gate for queue1 opens when queue2 is converting the last word in its

queue, queue1 completion flag will immediately set and no conversions will occur.

Queue1 will remain in a hung state for the duration of the gate (no conversions

will occur regardless of how long the gate is open). This failure will only occur

is still in result space 0, then the failure has occured.

WORKAROUND:

There are 2 workarounds: 1) Do not use queue 2 if queue1 is set for external gated

mode. Or, 2) If queue2 is used and queue1 is in external gated mode, set queue2 to

single scan mode.

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CDR_AR_89 Customer Erratum QADC64.CDR1IMB3_01_0

Mask off address field data during QADC port register reads in external mux mode

DESCRIPTION:

WORKAROUND:

This minor problem can be avoided by the customer by masking off the address field

data during the port register reads. To determine the current mux address, read the

CCW.

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CDR_AR_143 Customer Erratum QADC64.CDR1IMB3_01_0

Use software to disable QADC external gated single scan mode at end of queue

DESCRIPTION:

closure.

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CDR_AR_144 Customer Erratum QADC64.CDR1IMB3_01_0

In external gated continuous scan mode of the QADC, avoid use of CCW-EOQ

DESCRIPTION:

In the QADC64, CCW-EOQ is not recognized in external gated continuous scan mode.

The other 2 EOQ conditions, BQ2 encountered, and end of physical queue, operate

correctly.

DESCRIPTION:

Programming BQ2 pointer in QACR2 outside the implmented CCW table memory and

starting Q2 results in a Q2 false start. It goes active and does not correctly

process. It should not go active.

WORKAROUND:

Do not program BQ2 outside the implemented CCW table memory and start the Q2.

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CDR_AR_307 Customer Erratum QADC64.CDR1IMB3_01_0

Program the QADC64 end of Q2 in software cont mode with CCW-EOQ

Program Q2 for software continuous mode using a CCW-EOQ condition to end the queue.

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CDR_AR_421 Customer Erratum QADC64.CDR1IMB3_01_0

QADC64: Don’t switch to software triggered continuous scan after completing Q1.

DESCRIPTION:

In the case when application software switches Q1 to software triggered continuous

scan mode after Q1 completes a single scan where BQ2 provides the end of queue, an

indeterminate response results.

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CDR_AR_422 Customer Erratum QADC64.CDR1IMB3_01_0

QADC64: Do not rely on set of TOR1 in external gated continuous scan mode

DESCRIPTION:

In External Gated Continuous Scan mode: If the external gate is negated during the

last conversion (after the ccw has started, but before the result is converted) the

TOR1 flag will not set.

QADC64: False trigger upon configuration (Does NOT apply to ALL parts)

DESCRIPTION:

In some implementations, the QADC64 may have a false trigger upon entering an

external trigger mode. The potential for a false trigger only exists on QADC64’s

which are implemented with trigger pin(s) muxed through PortA[3 or 4]. If the

triggers have dedicated pins, then no difference exists between the value on the

pin and the value between the pad and the module.The false trigger can result when

an edge triggered mode is enabled and the logic value at the pin and the previously

latched value in the pad are not equal.

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CDR_AR_420 Customer Information QADC64.CDR1IMB3_01_0

QADC64: Don’t change BQ2 with a set of SSE2 without a mode change.

DESCRIPTION:

Changing BQ2 and setting SSE2 with no mode change will cause Q2 to begin but not

recognize the change in BQ2. Further, changes of BQ2 after SSE2 is set, but before

Q2 is triggered are also not recognized. All other sequences involving a change in

BQ2 are recognized.

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CDR_AR_435 Customer Information QADC64.CDR1IMB3_01_0

QADC64: TOR1 flag operates in both single and continuous external gated modes.

DESCRIPTION:

TOR1 response was added to QADC64 to provide an indication of more than 1 pass

through queue1. It was described in the specification as a continuous mode only

flag. The flag is however, operating in both single and continuous modes.

QSMCM Errata ONLY if QSMCM used on a CPU16/32/32X MCU

DESCRIPTION:

Wrong QSMCM interrupt source for IACK cycle may be returned on MODULAR parts. Bit 0

of the vector number is erroneously returned as a 1 for an SCI interrupt. It should

be 0. (Same as CDR_AR:205)

WORKAROUND:

Interrupt handlers for QSMCM could poll status registers to determine actual source

of the interrupt.

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CDR_AR_294 Customer Erratum QSMCM.CDR1IMB3_01_0

the RXTX queue being written.

WORKAROUND:

Do not use the SCI queue for SCI transmission or reception. Alternatively, ensure

that no IMB writes occur to locations $XXXXX02C:XXXXX06A, $XXXXX22C:XXXXX26A,

$XXXXX42C:XXXXX46A, $XXXXX62C:XXXXX66A, $XXXXX82C:XXXXX86A, $XXXXXA2C:XXXXXA6A,

$XXXXXC2C:XXXXXC6A, $XXXXXE2C:XXXXXE6A while the SCI1 RX or TX queue is in use.

Refer to the full chip memory map to determine which IMB registers reside in the

conflicting ranges.

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CDR_AR_563 Customer Erratum QSMCM.CDR1IMB3_01_0

QSM/QSMCM/QADC64 corrupts data after an IACK cycle in CISC parts.

DESCRIPTION:

This problem does not affect parts that do not run IACK cycles (i.e. RISC CPUs).

The Common BIU state machine, used by the QSM/QSMCM/QADC64, mis-tracks an IACK

cycle if an interrupt is issued while an IACK cycle for the same level is in

progress. In this case, the next access on the IMB3 will be corrupted by the

(handler address) causes the processor to jump to an incorrect location or to

produce an address error.

WORKAROUND:

Workarounds exist for both CPU32 and CPU32X based parts. On CPU32 based parts the

first access after an IACK cycles is the stacking of the vector offset The risk to

the system by corrupting this stacked value is very low, it is not used by the

processor. On CPU32X based parts which have the stack located in the FASRAM the

first IMB3 access is the fetch from the vector table. Corruption of this value

(handler address) causes the processor to jump to an incorrect location or to

produce an address error. The suggested workarounds for the QSM/QSMCM/QADC64 are

listed below. For CPU32 based parts: - assign the QSM/QSMCM/QADC64 it’s own

QSMCM: Do not use link baud and ECK modes

DESCRIPTION:

Reads of the SCI control and status registers do not read correctly when using the

link baud or the external clock source feature of the QSMCM. These modes are

enabled by the SCCxR0 control register bits 0 and 1 (OTHR and LNKBD). These modes

are not fully operational.

WORKAROUND:

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CDR_AR_16 Customer Information TOUCAN.CDR1IMB3_03_0A

Loop feature in the TOUCAN is not supported

DESCRIPTION:

Previous documentation indicated the capability in the TOUCAN to transmit back-to-

back frames. A problem exists where a second frame in a sequence of two may be

transmitted with its first IDENTIFIER bit corrupted. This function was enabled when

the LOOP bit in CTRL1 was = 1.

CDR_AR_627 Customer Information TPU3.CDR1IMB3_01_0

TPU: (Microcode) Add neg_mrl with write_mer and end_of_phase

DESCRIPTION:

Wrong generation of 50% d.c. caused when we have the command combination

"write_mer, end." If the write_mer is the last instruction together with the end,

this may create an additional match using the old content of the match register

(which is in the past now and therefore handled as an immediate match)

WORKAROUND:

Add neg_mrl together with the last write_mer and with end-of-phase. The negation of

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CDR_AR_577 Customer Information TPU3.CDR1IMB3_01_0

TPU3 - TCR2PSCK2 bit does not give TCR2 divide ratios specified.

DESCRIPTION:

The TCR2PSCK2 bit was originally specified to cause the TCR2 timebase to be divided

by 2. Actually, it causes the TCR2 timebase to be divided as follows: The /16 of

external clock and /128 of internal clock are eliminated and /3, /7, /15 of the

external clock and /24, /56, /120 of the internal clock are added.

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CDR_AR_498 Customer Erratum UIMB.CDR1UBUSIMB3_01_0

UIMB: Read failures occur for IMB accesses when IMB clock is half speed

DESCRIPTION:

When the imb clock is at half speed, a speed path occurs which prevents the proper

data in the uimb internal data latches from being observed by the user. Data is

transferred from the latches before the latches are updated with data for the

current cycle. This failure occurs when the part is heated (80-100C) and the

be disregarded when in half speed mode. (2). When running half speed on the imb,

keep the part as close to room temp. (25C) as possible. or (3). Only use full speed

imb mode. This workaround only applies to RevC or later.

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CDR_AR_90 Customer Erratum UIMB.CDR1UBUSIMB3_01_0

Poll TPU3 development status register to determine if TPU breakpoint occurs

DESCRIPTION:

A breakpoint requested by the TPU3 may not be recognized; hence, the FREEZE

indication may not be asserted by the development port. The TPU3 will still halt.

The device may draw up to 10mA more current when the breakpoint is requested by the

consumption.

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CDR_AR_92 Customer Erratum UIMB.CDR1UBUSIMB3_01_0

Avoid instruction accesses from IMB regions

DESCRIPTION:

The uimb ignores aborts (for example, on cache hit or branch) for instruction

accesses. This is applicable only when instructions are placed in the RAM of UIMB

modules.

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CDR_AR_231 Customer Erratum USIU.CDR1UBUS_01_0

Avoid external master accesses to internal resources which result in data error

DESCRIPTION:

When an external master accesses the device and the access has a data error, the

USIU asserts TEA externally but never releases bus request signals internally.

WORKAROUND:

DESCRIPTION:

IRQ1/RSV/SGPIOC[1] and IRQ4/AT[2]/SGPIOC[4] function as IRQ inputs only.

WORKAROUND:

Do not use these pins as GPIO/AT/RSV

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CDR_AR_235 Customer Erratum USIU.CDR1UBUS_01_0

Do not activate data show cycles when external master may access internal space

DESCRIPTION:

In slave mode, do not access another MPC55X

DESCRIPTION:

When the device is in SLAVE mode then the KR/RETRY pin is always an output.

WORKAROUND:

When the device is in SLAVE mode, do not access another MPC555.

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CDR_AR_239 Customer Erratum USIU.CDR1UBUS_01_0

WORKAROUND:

For alarm interrupt required every XXX seconds RTCAL register should be programmed

as follows: XXX / 2.6777 [20 MHz crystal] XXX / 9.3886 [4 MHz crystal].

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CDR_AR_222 Customer Information USIU.CDR1UBUS_01_0

Program the memory controller base registers prior to enabling it

DESCRIPTION:

Memory controller base registers 1, 2, 3 reset value is the same as the reset value

for base register 0.

WORKAROUND:

DESCRIPTION:

When External master utilizes Memory Controller services to access external memory

the CS will assert only at the 3rd clock of the access when TS is already negated.

WORKAROUND:

Do not use the MEMC to access external memory by external master if the memory uses

TS to latch/load the address.

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CDR_AR_228 Customer Information USIU.CDR1UBUS_01_0

In the USIU RSR, if both EHRS and ESRS are set, the reset source is internal.

If both internal and external (EHRS/ESRS) indicator bits are set, then the reset

source is internal. If only external (EHRS/ESRS) indicator bits are set, then the

reset source is external.

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CDR_AR_389 Customer Information USIU.CDR1UBUS_01_0

Little Endian modes are not supported

DESCRIPTION:

The little Endian modes are not functional.

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CDR_AR_442 Customer Information USIU.CDR1UBUS_01_0

Avoid loss of clock during HRESET

DESCRIPTION:

The chip may fail to switch to backup clock. This mode may occur if the input

reference clock fails to toggle during hreset while switching from normal clock to

backup clock. This condition may occur while switching from backup clock to normal

clock (during hreset) if the PLL is not locked and there is no reference clock. In

is enabled, instead enable an change of lock interrupt by setting the COLIE bit

(COLIR).

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CDR_AR_594 Customer Information USIU.CDR1UBUS_01_0

USIU: Changing PLL MF to 1:1 mode can have 180 degree phase shift

DESCRIPTION:

After software changes MF from >1 to MF = 1, a 180 degree skew between EXTCLK and

CLKOUT could occur.

WORKAROUND:

DESCRIPTION:

Future revisions of the PDMCR will have additional bits to control enabling and

disabling of pad pull-up / pull-down resistors. Software should be written so that

it is compatible with these changes. In this revision, PDMCR[8] (TPRDS) does not

change the function of the TPU T2CLK pull-up resistors -- the pull-ups remain

enabled.

WORKAROUND:

To ensure identical control in future revisions, when programming the PDMCR.

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CDR_AR_598 Customer Information USIU.CDR1UBUS_01_0

USIU: Ensure proper configuration for proper startup

DESCRIPTION:

In some systems, the PLL does not lock on power-up, or the system does not properly

execute software out of reset. This issue occurs on some board designs, and not on

others. Locking may be improved by board design and component selection, and can

be resolved by paying attention to the design and setup, and ensuring that the PLL

the XFC capacitor is connected to VDDSYN. Validate that the TRST_L pin is asserted

upon power-up. Do not connect TRST_L to HRESET_L or SRESET_L. Validate that all

power supplies are stable and all MODCK pins are at the correct levels in time for

the PLL and Oscillator to be stable prior to PORESET_L rising above VIL. Verify

that the proper reset configuration word is used. Validate the reset and post reset

pin state for each pin controlled by the reset configuration word, and ensure there

is not a conflict with an external driver. Preferably use the internal reset

configuration word. If using an external reset configuration word, do not rely on

the internal pull-downs to operate (refer to CDR_AR_454) and ensure that RSTCONF is

asserted until SRESET is negated. After the part exits reset with the system

running via the backup clock, validate the clock control registers settings and the

PLL status. If the PLL is slow on locking, or the register settings indicate the