IN2IN1
NC NC
GND V+ Substrate
NC NC
S2
D1
D2
S1
V– NC
Dual-In-Line
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Top View
Metal Can
NC
Top View
D1
V–
S1
IN1
V+ (Substrate and Case)
IN2
GND
S2D2
1
2
3
456
7
8
9
10
DG200A_MIL
Vishay Siliconix
Document Number: 70035
S-02314—Rev. E, 05-Oct-00 www.vishay.com
4-1
Monolithic Dual SPST CMOS Analog Switch
FEATURES BENEFITS APPLICATIONS
D"15 V Input Signal Range
D44-V Maximum Supply Ranges
DOn-Resistance: 45 W
DTTL and CMOS Compatibility
DWide Dynamic Range
DSimple Interfacing
DReduced External Component
Count
DServo Control Switching
DProgrammable Gain Amplifiers
DAudio Switching
DProgrammable Filters
DESCRIPTION
The DG200A_MIL is a dual, single-pole, single-throw analog
switch designed to provide general purpose switching of
analog signals. This device is ideally suited for designs
requiring a wide analog voltage range coupled with low
on-resistance.
The DG200A_MIL is designed on Vishay Siliconix’ improved
PLUS-40 CMOS process. An epitaxial layer prevents latchup.
Each switch conducts equally well in both directions when on,
and blocks up to 30 V peak-to-peak when off. In the on
condition, this bi-directional switch introduces no offset
voltage of its own.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
TRUTH TABLE
Logic Switch
0 ON
1 OFF
Logic “0” v 0.8 VLogic “0”
v
0.8 V
Logic “1” w 2.4 V
DG200A_MIL
Vishay Siliconix
www.vishay.com
4-2 Document Number: 70035
S-02314—Rev. E, 05-Oct-00
ORDERING INFORMATION
Temp Range Package Part Number
DG200AAK
14-Pin CerDIP DG200AAK/883, JM38510/12301BCA,
5962-9562901QCA
–55 to 125_CDG200AAA
10-Pin Metal Can DG200AAA/883, JM38510/12301BIC
14-Pin Sidebraze JM38510/12301BCC
ABSOLUTE MAXIMUM RATINGS
V+ to V–44 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GND to V–25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Inputsa, VS, VD(V–) –2 V to (V+) +2 V or. . . . . . . . . . . . . . . . . . . . . . . .
30 mA, whichever occurs first
Current (Any Terminal) Continuous 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current S or D
(Pulsed at 1 ms, 10% Duty Cycle Max) 100 mA. . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature –65 to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation (Package)b
10-Pin Metal Canc450 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14-Pin CerDIPd825 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes:
a. Signals on SX, DX, or INX exceeding V+ or V– will be clamped by internal
diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC Board.
c. Derate 6 mW/_C above 75_C
d. Derate 11 mW/_C above 75_C
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
FIGURE 1.
V+
INX
V–
GND
–
+
S
D
V–
V+
DG200A_MIL
Vishay Siliconix
Document Number: 70035
S-02314—Rev. E, 05-Oct-00 www.vishay.com
4-3
SPECIFICATIONSa
Test Conditions
Unless Otherwise Specified Limits
–55 to 125_C
Parameter Symbol V+ = 15 V, V– = –15 V
VIN = 2.4 V, 0.8 VfTempbMincTypdMaxcUnit
Analog Switch
Analog Signal RangeeVANALOG Full –15 15 V
Drain-Source
On-Resistance rDS(on) VD = "10 V, IS = –1 mA Room
Full 45 70
100 W
Source Off
Leakage Current IS(off) VS = "14 V, VD = #14 V Room
Full –2
–100 "0.01 2
100
Drain Off
Leakage Current ID(off) VD = "14 V, VS = #14 V Room
Full –2
–100 "0.01 2
100 nA
Channel On
Leakage CurrentfID(on) VS = VD = "14 V Room
Full –2
–200 "0.1 2
200
Digital Control
Input Current with VIN = 2.4 V Room
Full –0.5
–10.0009
Input Current with
Input Voltage High IINH VIN = 15 V Room
Full 0.005 0.5
1mA
Input Current with
Input Voltage Low IINL VIN = 0 V Room
Full –0.5
–1–0.0015
Dynamic Characteristics
Turn-On Time tON Room 440 1000
Turn-Off Time tOFF See Switching T ime Test Circuit Room 340 425 ns
Charge Injection QCL = 1000 pF, Vg = 0 V
Rg = 0 WRoom –10 pC
Source-Off Capacitance CS(off) f = 140 kHz VS = 0 V Room 9
Drain-Off Capacitance CD(off)
f = 140 kHz
VIN = 5 V VD = 0 V Room 9 pF
Channel-On Capacitance CD(on) +
CS(On) VD = VS = 0 V, VIN = 0 V Room 25
pF
Off Isolation OIRR
W
Room 75
Crosstalk
(Channel-to-Channel) XTALK
VIN = 5 V, RL = 75 W
VS = 2 V, f = 1 MHz Room 90 dB
Power Supplies
Positive Supply Current I+ Both Channels On or Off Room 0.8 2
Negative Supply Current I–Both Channels On or Off
VIN = 0 V and 2.4 V Room –1–0.23 mA
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. The algebraic convention whereby the most negative value is aminimum and the most positive a maximum, is used in this data sheet.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
DG200A_MIL
Vishay Siliconix
www.vishay.com
4-4 Document Number: 70035
S-02314—Rev. E, 05-Oct-00
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Leakage Currents vs. Analog VoltagerDS(on) vs. VD and Power Supply Voltage
rDS(on) ()W
(pA)I , I
SD
VD – Drain Voltage (V) VANALOG – Analog Voltage (V)
120
–15
D
C
+6
–15
E
015
100
80
60
40
20 015
0
–6
–12
–18
–24
ID(off) or IS(off)
ID(on)
TA = 25_C
A: "5 V
B: "10 V
C: "12 V
D: "15 V
E: "20 V
–12 –661293–3–9–12 –9–6–336912
B
A
Supply Currents vs. Toggle FrequencyInput Switching Threshold vs. V+ and V– Supply Voltages
V+, V– Positive and Negative Supplies (V) Toggle Frequency (Hz)
(V)
T
V
I+, I– (mA)
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
6
2.5
0
2.0
1.5
1.0
0.5
0
5
4
3
2
1
0
"5"10 "15 "20
I+
I–
V+ = 15 V
V– = –15 V
Both logic inputs
toggled simutaneously
1 k 10 k 100 k 1 M
DG200A_MIL
Vishay Siliconix
Document Number: 70035
S-02314—Rev. E, 05-Oct-00 www.vishay.com
4-5
TEST CIRCUITS
FIGURE 2. Switching Time
FIGURE 3. Charge Injection
CL
1000 p F
Vg3 V
D
V+
V–
Rg
–15 V
GND
IN
SVO
+15 V
VO
DVO
INXON ONOFF
DVO = measured voltage error due to charge injection
The charge injection in coulombs is DQ = CL x DVO
VO is the steady state output with switch on. Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform.
50%
0 V
3 V
tOFF
tON
VO
VS
tr <20 ns
tf <20 ns
Logic
Input
Switch
Input
Switch
Output
90%
CL
35 pF
RL
1 kW
VO = VSRL + rDS(on)
RL
VS = +5 V VO
V–
V+
IN
SD
3 V
–15 V
GND
+15 V
FIGURE 4. Off Isolation
S
IN RL
D
Rg = 50 W
VSVO
5 V
Off Isolation = 20 log VS
VO
V+
–15 V
GND V–C
C
+15 V
IN1
0V
VO
+15 V
–15 V
GND
RL
V+
V–
NC
XTALK = 20 log
C
VS
C
VO
0V
50 W
VSS1
IN2
S2
Rg = 50 W
D1
D2
C = RF bypass
FIGURE 5. Channel-to-Channel Crosstalk
