© 2009 Microchip Technology Inc. DS39894B
PIC18F8723 Family
Data Sheet
64/80-Pin, 1-Mbit,
Enhanced Flash Microcontrollers
with 12-Bit A/D and nanoWatt Technology
DS39894B-page 2 © 2009 Microchip Technology Inc.
Information contained in this publication regarding device
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and may be superseded by updates. It is your responsibility to
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
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Solutions Company are registered trademarks of Microchip
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Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
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Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
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are trademarks of Microchip Technology Incorporated in the
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SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2009 Microchip Technology Inc. DS39894B-page 3
PIC18F8723 FAMILY
Peripheral Highlights:
12-Bit, Up to 16-Channel Analog-to-Digital
Converter module (A/D):
- Auto-acquisition capability
- Conversion available during Sleep
Two Master Synchronous Serial Port (MSSP)
modules supporting 2/3/4-Wire SPI (all four
modes) and I2C™ Master and Slave modes
Two Capture/Compare/PWM (CCP) modules
Three Enhanced Capture/Compare/PWM (ECCP)
modules:
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-shutdown and auto-restart
Two Enhanced Addressable USART modules:
- Supports RS-485, RS-232 and LIN 1.2
- Auto-wake-up on Start bit
- Auto-Baud Detect
Dual Analog Comparators with Input Multiplexing
High-Current Sink/Source 25 mA/25 mA
Four Programmable External Interrupts
Four Input Change Interrupts
External Memory Interface:
Address Capability of Up to 2 Mbytes
8-Bit or 16-Bit Interface
8, 12, 16 and 20-Bit Address modes
Power-Managed Modes:
Run: CPU on, Peripherals on
Idle: CPU off, Peripherals on
Sleep: CPU off, Peripherals off
Idle mode Currents Down to 15 μA Typical
Sleep Current Down to 0.2 μA Typical
Timer1 Oscillator: 1.8 μA, 32 kHz, 2V
Watchdog Timer: 2.1 μA
Special Microcontroller Features:
C Compiler Optimized Architecture:
- Optional extended instruction set designed to
optimize re-entrant code
100,000 Erase/Write Cycle Enhanced Flash
Program Memory Typical
1,000,000 Erase/Write Cycle Data EEPROM
Memory Typical
Flash/Data EEPROM Retention: 100 Years Typical
Self-Programmable under Software Control
Priority Levels for Interrupts
8 x 8 Single-Cycle Hardware Multiplier
Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
Single-Supply In-Circuit Serial Programming™
(ICSP™) via Two Pins
In-Circuit Debug (ICD) via Two Pins
Wide Operating Voltage Range: 2.0V to 5.5V
Fail-Safe Clock Monitor
Two-Speed Oscillator Start-up
nanoWatt Technology
Note: This document is supplemented by the
“PIC18F8722 Family Data Sheet”
(DS39646). See Section 1.0 “Device
Overview”.
Device
Program Memory Data Memory
I/O 12-Bit
A/D (ch)
CCP/
ECCP
(PWM)
MSSP
EUSART
Comparators
Timers
8/16-Bit
External
Bus
Flash
(bytes)
# Single-Word
Instructions
SRAM
(bytes)
EEPROM
(bytes) SPI Master
I2C™
PIC18F6628 96K 49152 3936 1024 54 12 2/3 2 Y Y 2 2 2/3 N
PIC18F6723 128K 65536 3936 1024 54 12 2/3 2 Y Y 2 2 2/3 N
PIC18F8628 96K 49152 3936 1024 70 16 2/3 2 Y Y 2 2 2/3 Y
PIC18F8723 128K 65536 3936 1024 70 16 2/3 2 Y Y 2 2 2/3 Y
64/80-Pin, 1-Mbit, Enhanced Flash Microcontrollers
with 12-Bit A/D and nanoWatt Technology
PIC18F8723
DS39894B-page 4 © 2009 Microchip Technology Inc.
Pin Diagrams
Note 1: The ECCP2/P2A pin placement is determined by the CCP2MX Configuration bit.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
38
37
36
35
34
33
50 49
17 18 19 20 21 22 23 24 25 26
RE2/CS/P2B
RE3/P3C
RE4/P3B
RE5/P1C
RE6/P1B
RE7/ECCP2(1)/P2A(1)
RD0/PSP0
VDD
VSS
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4/SDO2
RD5/PSP5/SDI2/SDA2
RD6/PSP6/SCK2/SCL2
RD7/PSP7/SS2
RE1/WR/P2C
RE0/RD/P2D
RG0/ECCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
RG5/MCLR/VPP
RG4/CCP5/P1D
VSS
VDD
RF7/SS1
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
RB7/KBI3/PGD
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
RF0/AN5
RF1/AN6/C2OUT
AVDD
AVSS
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
VSS
VDD
RA4/T0CKI
RA5/AN4/HLVDIN
RC1/T1OSI/ECCP2(1)/P2A(1)
RC0/T1OSO/T13CKI
RC7/RX1/DT1
RC6/TX1/CK1
RC5/SDO1
15
16
31
40
39
27 28 29 30 32
48
47
46
45
44
43
42
41
54 53 52 5158 57 56 5560 5964 63 62 61
64-Pin TQFP
PIC18F6628
PIC18F6723
© 2009 Microchip Technology Inc. DS39894B-page 5
PIC18F8723
Pin Diagrams (Continued)
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
64 63 62 61
21 22 23 24 25 26 27 28 29 30 31 32
RE2/AD10/CS/P2B
RE3/AD11/P3C(2)
RE4/AD12/P3B(2)
RE5/AD13/P1C(2)
RE6/AD14/P1B(2)
RE7/AD15/ECCP2(1)/P2A(1)
RD0/AD0/PSP0
VDD
VSS
RD1/AD1/PSP1
RD2/AD2/PSP2
RD3/AD3/PSP3
RD4/AD4/PSP4/SDO2
RD5/AD5/PSP5/SDI2/SDA2
RD6/AD6/PSP6/SCK2/SCL2
RD7/AD7/PSP7/SS2
RE1/AD9/WR/P2C
RE0/AD8/RD/P2D
RG0/ECCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
RG5/MCLR/VPP
RG4/CCP5/P1D
VSS
VDD
RF7/SS1
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3/ECCP2(1)/P2A(1)
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
RB7/KBI3/PGD
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
RF0/AN5
RF1/AN6/C2OUT
AVDD
AVSS
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
VSS
VDD
RA4/T0CKI
RA5/AN4/HLVDIN
RC1/T1OSI/ECCP2(1)/P2A(1)
RC0/T1OSO/T13CKI
RC7/RX1/DT1
RC6/TX1/CK1
RC5/SDO1
RJ0/ALE
RJ1/OE
RH1/A17
RH0/A16
1
2
RH2/A18
RH3/A19
17
18
RH7/AN15/P1B(2)
RH6/AN14/P1C(2)
RH5/AN13/P3B(2)
RH4/AN12/P3C(2)
RJ5/CE
RJ4/BA0
37
RJ7/UB
RJ6/LB
50
49
RJ2/WRL
RJ3/WRH
19
20
33 34 35 36 38
58
57
56
55
54
53
52
51
60
59
68 67 66 6572 71 70 6974 7378 77 76 757980
80-Pin TQFP
Note 1: The ECCP2/P2A pin placement is determined by the CCP2MX Configuration bit and Processor mode settings.
2: P1B, P1C, P3B and P3C pin placement is determined by the ECCPMX Configuration bit.
RF5/AN10/CVREF
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
RF6/AN11
PIC18F8628
PIC18F8723
PIC18F8723
DS39894B-page 6 © 2009 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 31
3.0 Special Features of the CPU...................................................................................................................................................... 41
4.0 Electrical Characteristics ........................................................................................................................................................... 43
5.0 Packaging Information................................................................................................................................................................ 49
Appendix A: Revision History............................................................................................................................................................... 51
Appendix B: Device Differences........................................................................................................................................................... 51
Appendix C: Conversion Considerations ............................................................................................................................................. 52
Appendix D: Migration From Baseline to Enhanced Devices............................................................................................................... 52
Appendix E: Migration From Mid-Range to Enhanced Devices ........................................................................................................... 53
Appendix F: Migration From High-End to Enhanced Devices.............................................................................................................. 53
Index .................................................................................................................................................................................................... 55
The Microchip Web Site....................................................................................................................................................................... 57
Customer Change Notification Service ................................................................................................................................................ 57
Customer Support ................................................................................................................................................................................ 57
Reader Response ................................................................................................................................................................................ 58
PIC18F8723 family Product Identification System ............................................................................................................................... 59
© 2009 Microchip Technology Inc. DS39894B-page 7
PIC18F8723
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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PIC18F8723
DS39894B-page 8 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS39894B-page 9
PIC18F8723 FAMILY
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
The PIC18F8723 family of devices offers the
advantages of all PIC18 microcontrollers – namely, high
computational performance at an economical price
with the addition of high-endurance, Enhanced Flash
program memory. In addition to these features, the
PIC18F8723 introduces design enhancements that
make these microcontrollers a logical choice for many
high-performance, power-sensitive applications.
1.1 Special Features
12-Bit A/D Converter: The PIC18F8723 family
implements a 12-bit A/D Converter. A/D Converters
in both families incorporate programmable acquisi-
tion time. This allows for a channel to be selected
and a conversion to be initiated, without waiting for
a sampling period and thus, reducing code
overhead.
1.2 Details on Individual Family
Members
Devices in the PIC18F8723 family are available in
64-pin and 80-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.
The devices are differentiated from each other in the
following ways:
Flash program memory (96 Kbytes for
PIC18FX628 devices and 128 Kbytes for
PIC18FX723).
A/D channels (12 for PIC18F6628/6723 devices
and 16 for PIC18F8628/8723 devices).
I/O ports (seven bidirectional ports on
PIC18F6628/6723 devices and nine bidirectional
ports on PIC18F8628/8723 devices).
External Memory Bus, configurable for 8 and
16-bit operation
All other features for devices in this family are identical.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
Like all Microchip PIC18 devices, members of the
PIC18F8723 family are available as both standard and
low-voltage devices. Standard devices with Enhanced
Flash memory, designated with an “F” in the part
number (such as PIC18F6628), accommodate an
operating VDD range of 4.2V to 5.5V. Low-voltage
parts, designated by “LF” (such as PIC18LF6628),
function over an extended VDD range of 2.0V to 5.5V.
PIC18F6628 PIC18LF6628
PIC18F6723 PIC18LF6723
PIC18F8628 PIC18LF8628
PIC18F8723 PIC18LF8723
Note: This data sheet documents only the devices
features and specifications that are in addition
to the features and specifications of the
PIC18F8722 family devices. For information
on the features and specifications shared by
the PIC18F8723 family and PIC18F8722 fam-
ily devices, see the “PIC18F8722 Family Data
Sheet” (DS39646).
PIC18F8723 FAMILY
DS39894B-page 10 © 2009 Microchip Technology Inc.
TABLE 1-1: DEVICE FEATURES
Features PIC18F6628 PIC18F6723 PIC18F8628 PIC18F8723
Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz
Program Memory (Bytes) 96K 128K 96K 128K
Program Memory (Instructions) 49152 65536 49152 65536
Data Memory (Bytes) 3936 3936 3936 3936
Data EEPROM Memory (Bytes) 1024 1024 1024 1024
Interrupt Sources 28282929
I/O Ports Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G Ports A, B, C, D, E,
F, G, H, J
Ports A, B, C, D, E,
F, G, H, J
Timers 5 5 5 5
Capture/Compare/PWM
Modules
2222
Enhanced Capture/Compare/
PWM Modules
3333
Enhanced USART 2 2 2 2
Serial Communications MSSP,
Enhanced USART
MSSP,
Enhanced USART
MSSP,
Enhanced USART
MSSP,
Enhanced USART
Parallel Communications (PSP) Yes Yes Yes Yes
12-Bit Analog-to-Digital Module 12 Input Channels 12 Input Channels 16 Input Channels 16 Input Channels
Resets (and Delays) POR, BOR,
RESET Instruction,
Stack Full, Stack
Underflow (PWRT, OST),
MCLR (optional), WDT
POR, BOR,
RESET Instruction,
Stack Full, Stack
Underflow (PWRT, OST),
MCLR (optional), WDT
POR, BOR,
RESET Instruction,
Stack Full, Stack
Underflow (PWRT, OST),
MCLR (optional), WDT
POR, BOR,
RESET Instruction,
Stack Full, Stack
Underflow (PWRT, OST),
MCLR (optional), WDT
Programmable
High/Low-Voltage Detect
Yes Yes Yes Ye s
Programmable Brown-out
Reset
Yes Yes Yes Ye s
Instruction Set 75 Instructions;
83 with Extended
Instruction Set Enabled
75 Instructions;
83 with Extended
Instruction Set Enabled
75 Instructions;
83 with Extended
Instruction Set Enabled
75 Instructions;
83 with Extended
Instruction Set Enabled
Packages 64-Pin TQFP 64-Pin TQFP 80-Pin TQFP 80-Pin TQFP
© 2009 Microchip Technology Inc. DS39894B-page 11
PIC18F8723 FAMILY
FIGURE 1-1: PIC18F6628/6723 (64-PIN) BLOCK DIAGRAM
Instruction
Decode and
Control
PORTA
Data Latch
Data Memory
(3.9 Kbytes)
Address Latch
Data Address<12>
12
Access
BSR FSR0
FSR1
FSR2
inc/dec
logic
Address
412 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
(48/64/96/128
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
PCLATU
PCU
Note 1: See Table 1-2 for I/O port pin descriptions.
2: RG5 is only available when MCLR functionality is disabled.
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as
digital I/O. For additional information, refer to Section 2.0 “Oscillator Configurations” of the “PIC18F8722 Family
Data Sheet” (DS39646).
EUSART1
Comparators
MSSP1
Timer2Timer1 Timer3Timer0
HLVD
ECCP1
BOR ADC
12-Bit
W
Instruction Bus <16>
STKPTR Bank
8
State Machine
Control Signals
Decode
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1(3)
OSC2(3)
VDD,
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Precision
Reference
Band Gap
VSS
MCLR(2)
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSI
T1OSO
EUSART2
ECCP2
ROM Latch
ECCP3 MSSP2CCP4 CCP5
PORTC
PORTD
PORTE
PORTF
PORTG
RA0:RA7(1)
RC0:RC7(1)
RD0:RD7(1)
RE0:RE7(1)
RF0:RF7(1)
RG0:RG5
(1,2)
PORTB
RB0:RB7(1)
Timer4
Kbytes)
PIC18F8723 FAMILY
DS39894B-page 12 © 2009 Microchip Technology Inc.
FIGURE 1-2: PIC18F8628/8723 (80-PIN) BLOCK DIAGRAM
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
8
8
3
W8
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1(3)
OSC2(3)
VDD,
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Precision
Reference
Band Gap
VSS
MCLR(2)
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSI
T1OSO
Instruction
Decode &
Control
Data Latch
Data Memory
(3.9 Kbytes)
Address Latch
Data Address<12>
12
Access
BSR FSR0
FSR1
FSR2
inc/dec
logic
Address
4124
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
Address Latch
Program Memory
(48/64/96/128
Data Latch
20
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
ROM Latch
PCLATU
PCU
Instruction Bus <16>
STKPTR Bank
State Machine
Control Signals
Decode
System Bus Interface
AD15:AD0, A19:A16
(Multiplexed with PORTD,
PORTE and PORTH)
PORTA
PORTC
PORTD
PORTE
PORTF
PORTG
RA0:RA7(1)
RC0:RC7(1)
RD0:RD7(1)
RE0:RE7(1)
RF0:RF7(1)
RG0:RG5
(1,2)
PORTB
RB0:RB7(1)
PORTH
RH0:RH7(1)
PORTJ
RJ0:RJ7(1)
EUSART1
Comparators
MSSP1
Timer2Timer1 Timer3Timer0
HLVD
ECCP1
BOR ADC
12-bit
EUSART2
ECCP2 ECCP3 MSSP2CCP4 CCP5
Timer4
Note 1: See Table 1-3 for I/O port pin descriptions.
2: RG5 is only available when MCLR functionality is disabled.
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as
digital I/O. For additional information, refer to Section 2.0 “Oscillator Configurations” of the “PIC18F8722 Family Data
Sheet (DS39646).
Kbytes)
© 2009 Microchip Technology Inc. DS39894B-page 13
PIC18F8723 FAMILY
TABLE 1-2: PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
RG5/MCLR/VPP
RG5
MCLR
VPP
7
I
I
P
ST
ST
Master Clear (input) or programming voltage (input).
Digital input.
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
OSC1/CLKI/RA7
OSC1
CLKI
RA7
39
I
I
I/O
ST
CMOS
TTL
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS
otherwise.
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
40
O
O
I/O
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power I
2C™ = I2C/SMBus input buffer
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
PIC18F8723 FAMILY
DS39894B-page 14 © 2009 Microchip Technology Inc.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
24
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
23
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
RA2/AN2/VREF-
RA2
AN2
VREF-
22
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
AN3
VREF+
21
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI
RA4
T0CKI
28
I/O
I
ST
ST
Digital I/O.
Timer0 external clock input.
RA5/AN4/HLVDIN
RA5
AN4
HLVDIN
27
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 4.
High/Low-Voltage Detect input.
RA6 See the OSC2/CLKO/RA6 pin.
RA7 See the OSC1/CLKI/RA7 pin.
TABLE 1-2: PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power I
2C™ = I2C/SMBus input buffer
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc. DS39894B-page 15
PIC18F8723 FAMILY
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/FLT0
RB0
INT0
FLT0
48
I/O
I
I
TTL
ST
ST
Digital I/O.
External interrupt 0.
PWM Fault input for ECCPx.
RB1/INT1
RB1
INT1
47
I/O
I
TTL
ST
Digital I/O.
External interrupt 1.
RB2/INT2
RB2
INT2
46
I/O
I
TTL
ST
Digital I/O.
External interrupt 2.
RB3/INT3
RB3
INT3
45
I/O
I
TTL
ST
Digital I/O.
External interrupt 3.
RB4/KBI0
RB4
KBI0
44
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
RB5/KBI1/PGM
RB5
KBI1
PGM
43
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
42
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
37
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-2: PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power I
2C™ = I2C/SMBus input buffer
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
PIC18F8723 FAMILY
DS39894B-page 16 © 2009 Microchip Technology Inc.
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
30
I/O
O
I
ST
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/ECCP2/
P2A
RC1
T1OSI
ECCP2(1)
P2A(1)
29
I/O
I
I/O
O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Enhanced Capture 2 input/Compare 2 output/
PWM2 output.
ECCP2 PWM output A.
RC2/ECCP1/P1A
RC2
ECCP1
P1A
33
I/O
I/O
O
ST
ST
Digital I/O.
Enhanced Capture 1 input/Compare 1 output/
PWM1 output.
ECCP1 PWM output A.
RC3/SCK1/SCL1
RC3
SCK1
SCL1
34
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI1/SDA1
RC4
SDI1
SDA1
35
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
RC5/SDO1
RC5
SDO1
36
I/O
O
ST
Digital I/O.
SPI data out.
RC6/TX1/CK1
RC6
TX1
CK1
31
I/O
O
I/O
ST
ST
Digital I/O.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1).
RC7/RX1/DT1
RC7
RX1
DT1
32
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1).
TABLE 1-2: PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power I
2C™ = I2C/SMBus input buffer
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc. DS39894B-page 17
PIC18F8723 FAMILY
PORTD is a bidirectional I/O port.
RD0/PSP0
RD0
PSP0
58
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
RD1/PSP1
RD1
PSP1
55
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
RD2/PSP2
RD2
PSP2
54
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
RD3/PSP3
RD3
PSP3
53
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
RD4/PSP4/SDO2
RD4
PSP4
SDO2
52
I/O
I/O
O
ST
TTL
Digital I/O.
Parallel Slave Port data.
SPI data out.
RD5/PSP5/SDI2/
SDA2
RD5
PSP5
SDI2
SDA2
51
I/O
I/O
I
I/O
ST
TTL
ST
I2C/SMB
Digital I/O.
Parallel Slave Port data.
SPI data in.
I2C™ data I/O.
RD6/PSP6/SCK2/
SCL2
RD6
PSP6
SCK2
SCL2
50
I/O
I/O
I/O
I/O
ST
TTL
ST
I2C/SMB
Digital I/O.
Parallel Slave Port data.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
RD7/PSP7/SS2
RD7
PSP7
SS2
49
I/O
I/O
I
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
SPI slave select input.
TABLE 1-2: PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power I
2C™ = I2C/SMBus input buffer
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
PIC18F8723 FAMILY
DS39894B-page 18 © 2009 Microchip Technology Inc.
PORTE is a bidirectional I/O port.
RE0/RD/P2D
RE0
RD
P2D
2
I/O
I
O
ST
TTL
Digital I/O.
Read control for Parallel Slave Port.
ECCP2 PWM output D.
RE1/WR/P2C
RE1
WR
P2C
1
I/O
I
O
ST
TTL
Digital I/O.
Write control for Parallel Slave Port.
ECCP2 PWM output C.
RE2/CS/P2B
RE2
CS
P2B
64
I/O
I
O
ST
TTL
Digital I/O.
Chip select control for Parallel Slave Port.
ECCP2 PWM output B.
RE3/P3C
RE3
P3C
63
I/O
O
ST
Digital I/O.
ECCP3 PWM output C.
RE4/P3B
RE4
P3B
62
I/O
O
ST
Digital I/O.
ECCP3 PWM output B.
RE5/P1C
RE5
P1C
61
I/O
O
ST
Digital I/O.
ECCP1 PWM output C.
RE6/P1B
RE6
P1B
60
I/O
O
ST
Digital I/O.
ECCP1 PWM output B.
RE7/ECCP2/P2A
RE7
ECCP2(2)
P2A(2)
59
I/O
I/O
O
ST
ST
Digital I/O.
Enhanced Capture 2 input/Compare 2 output/
PWM2 output.
ECCP2 PWM output A.
TABLE 1-2: PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power I
2C™ = I2C/SMBus input buffer
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc. DS39894B-page 19
PIC18F8723 FAMILY
PORTF is a bidirectional I/O port.
RF0/AN5
RF0
AN5
18
I/O
I
ST
Analog
Digital I/O.
Analog input 5.
RF1/AN6/C2OUT
RF1
AN6
C2OUT
17
I/O
I
O
ST
Analog
Digital I/O.
Analog input 6.
Comparator 2 output.
RF2/AN7/C1OUT
RF2
AN7
C1OUT
16
I/O
I
O
ST
Analog
Digital I/O.
Analog input 7.
Comparator 1 output.
RF3/AN8
RF3
AN8
15
I/O
I
ST
Analog
Digital I/O.
Analog input 8.
RF4/AN9
RF4
AN9
14
I/O
I
ST
Analog
Digital I/O.
Analog input 9.
RF5/AN10/CVREF
RF5
AN10
CVREF
13
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 10.
Comparator reference voltage output.
RF6/AN11
RF6
AN11
12
I/O
I
ST
Analog
Digital I/O.
Analog input 11.
RF7/SS1
RF7
SS1
11
I/O
I
ST
TTL
Digital I/O.
SPI slave select input.
TABLE 1-2: PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power I
2C™ = I2C/SMBus input buffer
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
PIC18F8723 FAMILY
DS39894B-page 20 © 2009 Microchip Technology Inc.
PORTG is a bidirectional I/O port.
RG0/ECCP3/P3A
RG0
ECCP3
P3A
3
I/O
I/O
O
ST
ST
Digital I/O.
Enhanced Capture 3 input/Compare 3 output/
PWM3 output.
ECCP3 PWM output A.
RG1/TX2/CK2
RG1
TX2
CK2
4
I/O
O
I/O
ST
ST
Digital I/O.
EUSART2 asynchronous transmit.
EUSART2 synchronous clock (see related RX2/DT2).
RG2/RX2/DT2
RG2
RX2
DT2
5
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART2 asynchronous receive.
EUSART2 synchronous data (see related TX2/CK2).
RG3/CCP4/P3D
RG3
CCP4
P3D
6
I/O
I/O
O
ST
ST
Digital I/O.
Capture 4 input/Compare 4 output/PWM4 output.
ECCP3 PWM output D.
RG4/CCP5/P1D
RG4
CCP5
P1D
8
I/O
I/O
O
ST
ST
Digital I/O.
Capture 5 input/Compare 5 output/PWM5 output.
ECCP1 PWM output D.
RG5 See RG5/MCLR/VPP pin.
VSS 9, 25, 41, 56 P Ground reference for logic and I/O pins.
VDD 10, 26, 38, 57 P Positive supply for logic and I/O pins.
AVSS 20 P Ground reference for analog modules.
AVDD 19 P Positive supply for analog modules.
TABLE 1-2: PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power I
2C™ = I2C/SMBus input buffer
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc. DS39894B-page 21
PIC18F8723 FAMILY
TABLE 1-3: PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
RG5/MCLR/VPP
RG5
MCLR
VPP
9
I
I
P
ST
ST
Master Clear (input) or programming voltage (input).
Digital input.
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
OSC1/CLKI/RA7
OSC1
CLKI
RA7
49
I
I
I/O
ST
CMOS
TTL
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS
otherwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
50
O
O
I/O
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which has 1/4 the
frequency of OSC1 and denotes the
instruction cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power I
2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
PIC18F8723 FAMILY
DS39894B-page 22 © 2009 Microchip Technology Inc.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
30
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
29
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
RA2/AN2/VREF-
RA2
AN2
VREF-
28
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
AN3
VREF+
27
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI
RA4
T0CKI
34
I/O
I
ST
ST
Digital I/O.
Timer0 external clock input.
RA5/AN4/HLVDIN
RA5
AN4
HLVDIN
33
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 4.
High/Low-Voltage Detect input.
RA6 See the OSC2/CLKO/RA6 pin.
RA7 See the OSC1/CLKI/RA7 pin.
TABLE 1-3: PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power I
2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
© 2009 Microchip Technology Inc. DS39894B-page 23
PIC18F8723 FAMILY
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/FLT0
RB0
INT0
FLT0
58
I/O
I
I
TTL
ST
ST
Digital I/O.
External interrupt 0.
PWM Fault input for ECCPx.
RB1/INT1
RB1
INT1
57
I/O
I
TTL
ST
Digital I/O.
External interrupt 1.
RB2/INT2
RB2
INT2
56
I/O
I
TTL
ST
Digital I/O.
External interrupt 2.
RB3/INT3/ECCP2/P2A
RB3
INT3
ECCP2(1)
P2A(1)
55
I/O
I
O
O
TTL
ST
Digital I/O.
External interrupt 3.
Enhanced Capture 2 input/Compare 2 output/
PWM2 output.
ECCP2 PWM output A.
RB4/KBI0
RB4
KBI0
54
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
RB5/KBI1/PGM
RB5
KBI1
PGM
53
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
52
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
47
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-3: PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power I
2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
PIC18F8723 FAMILY
DS39894B-page 24 © 2009 Microchip Technology Inc.
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
36
I/O
O
I
ST
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/ECCP2/
P2A
RC1
T1OSI
ECCP2(2)
P2A(2)
35
I/O
I
I/O
O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Enhanced Capture 2 input/Compare 2 output/
PWM2 output.
ECCP2 PWM output A.
RC2/ECCP1/P1A
RC2
ECCP1
P1A
43
I/O
I/O
O
ST
ST
Digital I/O.
Enhanced Capture 1 input/Compare 1 output/
PWM1 output.
ECCP1 PWM output A.
RC3/SCK1/SCL1
RC3
SCK1
SCL1
44
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI1/SDA1
RC4
SDI1
SDA1
45
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
RC5/SDO1
RC5
SDO1
46
I/O
O
ST
Digital I/O.
SPI data out.
RC6/TX1/CK1
RC6
TX1
CK1
37
I/O
O
I/O
ST
ST
Digital I/O.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1).
RC7/RX1/DT1
RC7
RX1
DT1
38
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1).
TABLE 1-3: PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power I
2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
© 2009 Microchip Technology Inc. DS39894B-page 25
PIC18F8723 FAMILY
PORTD is a bidirectional I/O port.
RD0/AD0/PSP0
RD0
AD0
PSP0
72
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 0.
Parallel Slave Port data.
RD1/AD1/PSP1
RD1
AD1
PSP1
69
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 1.
Parallel Slave Port data.
RD2/AD2/PSP2
RD2
AD2
PSP2
68
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 2.
Parallel Slave Port data.
RD3/AD3/PSP3
RD3
AD3
PSP3
67
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 3.
Parallel Slave Port data.
RD4/AD4/PSP4/SDO2
RD4
AD4
PSP4
SDO2
66
I/O
I/O
I/O
O
ST
TTL
TTL
Digital I/O.
External memory address/data 4.
Parallel Slave Port data.
SPI data out.
RD5/AD5/PSP5/
SDI2/SDA2
RD5
AD5
PSP5
SDI2
SDA2
65
I/O
I/O
I/O
I
I/O
ST
TTL
TTL
ST
I2C/SMB
Digital I/O.
External memory address/data 5.
Parallel Slave Port data.
SPI data in.
I2C™ data I/O.
RD6/AD6/PSP6/
SCK2/SCL2
RD6
AD6
PSP6
SCK2
SCL2
64
I/O
I/O
I/O
I/O
I/O
ST
TTL
TTL
ST
I2C/SMB
Digital I/O.
External memory address/data 6.
Parallel Slave Port data.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
RD7/AD7/PSP7/SS2
RD7
AD7
PSP7
SS2
63
I/O
I/O
I/O
I
ST
TTL
TTL
TTL
Digital I/O.
External memory address/data 7.
Parallel Slave Port data.
SPI slave select input.
TABLE 1-3: PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power I
2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
PIC18F8723 FAMILY
DS39894B-page 26 © 2009 Microchip Technology Inc.
PORTE is a bidirectional I/O port.
RE0/AD8/RD/P2D
RE0
AD8
RD
P2D
4
I/O
I/O
I
O
ST
TTL
TTL
Digital I/O.
External memory address/data 8.
Read control for Parallel Slave Port.
ECCP2 PWM output D.
RE1/AD9/WR/P2C
RE1
AD9
WR
P2C
3
I/O
I/O
I
O
ST
TTL
TTL
Digital I/O.
External memory address/data 9.
Write control for Parallel Slave Port.
ECCP2 PWM output C.
RE2/AD10/CS/P2B
RE2
AD10
CS
P2B
78
I/O
I/O
I
O
ST
TTL
TTL
Digital I/O.
External memory address/data 10.
Chip select control for Parallel Slave Port.
ECCP2 PWM output B.
RE3/AD11/P3C
RE3
AD11
P3C(4)
77
I/O
I/O
O
ST
TTL
Digital I/O.
External memory address/data 11.
ECCP3 PWM output C.
RE4/AD12/P3B
RE4
AD12
P3B(4)
76
I/O
I/O
O
ST
TTL
Digital I/O.
External memory address/data 12.
ECCP3 PWM output B.
RE5/AD13/P1C
RE5
AD13
P1C(4)
75
I/O
I/O
O
ST
TTL
Digital I/O.
External memory address/data 13.
ECCP1 PWM output C.
RE6/AD14/P1B
RE6
AD14
P1B(4)
74
I/O
I/O
O
ST
TTL
Digital I/O.
External memory address/data 14.
ECCP1 PWM output B.
RE7/AD15/ECCP2/
P2A
RE7
AD15
ECCP2(3)
P2A(3)
73
I/O
I/O
I/O
O
ST
TTL
ST
Digital I/O.
External memory address/data 15.
Enhanced Capture 2 input/Compare 2 output/
PWM2 output.
ECCP2 PWM output A.
TABLE 1-3: PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power I
2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
© 2009 Microchip Technology Inc. DS39894B-page 27
PIC18F8723 FAMILY
PORTF is a bidirectional I/O port.
RF0/AN5
RF0
AN5
24
I/O
I
ST
Analog
Digital I/O.
Analog input 5.
RF1/AN6/C2OUT
RF1
AN6
C2OUT
23
I/O
I
O
ST
Analog
Digital I/O.
Analog input 6.
Comparator 2 output.
RF2/AN7/C1OUT
RF2
AN7
C1OUT
18
I/O
I
O
ST
Analog
Digital I/O.
Analog input 7.
Comparator 1 output.
RF3/AN8
RF3
AN8
17
I/O
I
ST
Analog
Digital I/O.
Analog input 8.
RF4/AN9
RF4
AN9
16
I/O
I
ST
Analog
Digital I/O.
Analog input 9.
RF5/AN10/CVREF
RF5
AN10
CVREF
15
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 10.
Comparator reference voltage output.
RF6/AN11
RF6
AN11
14
I/O
I
ST
Analog
Digital I/O.
Analog input 11.
RF7/SS1
RF7
SS1
13
I/O
I
ST
TTL
Digital I/O.
SPI slave select input.
TABLE 1-3: PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power I
2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
PIC18F8723 FAMILY
DS39894B-page 28 © 2009 Microchip Technology Inc.
PORTG is a bidirectional I/O port.
RG0/ECCP3/P3A
RG0
ECCP3
P3A
5
I/O
I/O
O
ST
ST
Digital I/O.
Enhanced Capture 3 input/Compare 3 output/
PWM3 output.
ECCP3 PWM output A.
RG1/TX2/CK2
RG1
TX2
CK2
6
I/O
O
I/O
ST
ST
Digital I/O.
EUSART2 asynchronous transmit.
EUSART2 synchronous clock (see related RX2/DT2).
RG2/RX2/DT2
RG2
RX2
DT2
7
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART2 asynchronous receive.
EUSART2 synchronous data (see related TX2/CK2).
RG3/CCP4/P3D
RG3
CCP4
P3D
8
I/O
I/O
O
ST
ST
Digital I/O.
Capture 4 input/Compare 4 output/PWM4 output.
ECCP3 PWM output D.
RG4/CCP5/P1D
RG4
CCP5
P1D
10
I/O
I/O
O
ST
ST
Digital I/O.
Capture 5 input/Compare 5 output/PWM5 output.
ECCP1 PWM output D.
RG5 See RG5/MCLR/VPP pin.
TABLE 1-3: PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power I
2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
© 2009 Microchip Technology Inc. DS39894B-page 29
PIC18F8723 FAMILY
PORTH is a bidirectional I/O port.
RH0/A16
RH0
A16
79
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 16.
RH1/A17
RH1
A17
80
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 17.
RH2/A18
RH2
A18
1
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 18.
RH3/A19
RH3
A19
2
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 19.
RH4/AN12/P3C
RH4
AN12
P3C(5)
22
I/O
I
O
ST
Analog
Digital I/O.
Analog input 12.
ECCP3 PWM output C.
RH5/AN13/P3B
RH5
AN13
P3B(5)
21
I/O
I
O
ST
Analog
Digital I/O.
Analog input 13.
ECCP3 PWM output B.
RH6/AN14/P1C
RH6
AN14
P1C(5)
20
I/O
I
O
ST
Analog
Digital I/O.
Analog input 14.
ECCP1 PWM output C.
RH7/AN15/P1B
RH7
AN15
P1B(5)
19
I/O
I
O
ST
Analog
Digital I/O.
Analog input 15.
ECCP1 PWM output B.
TABLE 1-3: PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power I
2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
PIC18F8723 FAMILY
DS39894B-page 30 © 2009 Microchip Technology Inc.
PORTJ is a bidirectional I/O port.
RJ0/ALE
RJ0
ALE
62
I/O
O
ST
Digital I/O.
External memory address latch enable.
RJ1/OE
RJ1
OE
61
I/O
O
ST
Digital I/O.
External memory output enable.
RJ2/WRL
RJ2
WRL
60
I/O
O
ST
Digital I/O.
External memory write low control.
RJ3/WRH
RJ3
WRH
59
I/O
O
ST
Digital I/O.
External memory write high control.
RJ4/BA0
RJ4
BA0
39
I/O
O
ST
Digital I/O.
External memory byte address 0 control.
RJ5/CE
RJ4
CE
40
I/O
O
ST
Digital I/O
External memory chip enable control.
RJ6/LB
RJ6
LB
41
I/O
O
ST
Digital I/O.
External memory low byte control.
RJ7/UB
RJ7
UB
42
I/O
O
ST
Digital I/O.
External memory high byte control.
VSS 11, 31, 51, 70 P Ground reference for logic and I/O pins.
VDD 12, 32, 48, 71 P Positive supply for logic and I/O pins.
AVSS 26 P Ground reference for analog modules.
AVDD 25 P Positive supply for analog modules.
TABLE 1-3: PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power I
2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
© 2009 Microchip Technology Inc. DS39894B-page 31
PIC18F8723 FAMILY
2.0 12-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module has
12 inputs for the 64-pin devices (PIC18F6628/6723) and
16 for the 80-pin devices (PIC18F8628/8723). This
module allows conversion of an analog input signal to a
corresponding 12-bit digital number.
The module has five registers:
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register 0 (ADCON0)
A/D Control Register 1 (ADCON1)
A/D Control Register 2 (ADCON2)
The ADCON0 register, shown in Register 2-1, controls
the operation of the A/D module. The ADCON1
register, shown in Register 2-2, configures the
functions of the port pins. The ADCON2 register,
shown in Register 2-3, configures the A/D clock
source, programmed acquisition time and justification.
REGISTER 2-1: ADCON0: A/D CONTROL REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0
bit 5-2 CHS3:CHS0: Analog Channel Select bits
0000 = Channel 0 (AN0)
0001 = Channel 1 (AN1)
0010 = Channel 2 (AN2)
0011 = Channel 3 (AN3)
0100 = Channel 4 (AN4)
0101 = Channel 5 (AN5)
0110 = Channel 6 (AN6)
0111 = Channel 7 (AN7)
1000 = Channel 8 (AN8)
1001 = Channel 9 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
1100 = Channel 12 (AN12)(1,2)
1101 = Channel 13 (AN13)(1,2)
1110 = Channel 14 (AN14)(1,2)
1111 = Channel 15 (AN15)(1,2)
bit 1 GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress
0 = A/D Idle
bit 0 ADON: A/D On bit
1 = A/D Converter module is enabled
0 = A/D Converter module is disabled
Note 1: These channels are not implemented on PIC18F6628/6723 devices.
2: Performing a conversion on unimplemented channels will return a floating input measurement.
PIC18F8723 FAMILY
DS39894B-page 32 © 2009 Microchip Technology Inc.
REGISTER 2-2: ADCON1: A/D CONTROL REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0
bit 5-4 VCFG1:VCFG0: Voltage Reference Configuration bits
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits:
A/D VREF+ A/D VREF-
00 AVDD AVSS
01 External VREF+AVSS
10 AVDD External VREF-
11 External VREF+ External VREF-
A = Analog input D = Digital I/O
Note 1: AN15 through AN12 are available only on PIC18F8628/8723 devices.
PCFG<3:0>
AN15(1)
AN14(1)
AN13(1)
AN12(1)
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
0000 A AAAAAAAAAAAAAAA
0001 D DAAAAAAAAAAAAAA
0010 D DDAAAAAAAAAAAAA
0011 D DDDAAAAAAAAAAAA
0100 D DDDDAAAAAAAAAAA
0101 D DDDDDAAAAAAAAAA
0110 D DDDDDDAAAAAAAAA
0111 D D DDD DDD A A AAAAAA
1000 D D DDDDDDD A AAAAAA
1001 D DDDDDDDDDAAAAAA
1010 D DDDDDDDDDDAAAAA
1011 D DDDDDDDDDDDAAAA
1100 D DDDDDDDDDDDDAAA
1101 D DDDDDDDDDDDDDAA
1110 D DDDDDDDDDDDDDDA
1111 D DDDDDDDDDDDDDDD
© 2009 Microchip Technology Inc. DS39894B-page 33
PIC18F8723 FAMILY
REGISTER 2-3: ADCON2: A/D CONTROL REGISTER 2
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
bit 6 Unimplemented: Read as ‘0
bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits
111 = 20 T
AD
110 = 16 TAD
101 = 12 TAD
100 = 8 TAD
011 = 6 TAD
010 = 4 TAD
001 = 2 TAD
000 = 0 TAD(1)
bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits
111 = FRC (clock derived from A/D RC oscillator)(1)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock derived from A/D RC oscillator)(1)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
PIC18F8723 FAMILY
DS39894B-page 34 © 2009 Microchip Technology Inc.
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS), or the voltage level on the RA3/AN3/
VREF+ and RA2/AN2/VREF-/CVREF pins.
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D Converter can be
configured as an analog input or a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0<1>) is cleared
and the A/D Interrupt Flag bit, ADIF, is set. The block
diagram of the A/D module is shown in Figure 2-1.
FIGURE 2-1: A/D BLOCK DIAGRAM
(Input Voltage)
VAIN
VREF+
Reference
Voltage
AVDD(2)
VCFG1:VCFG0
CHS3:CHS0
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
0111
0110
0101
0100
0011
0010
0001
0000
12-Bit
A/D
VREF-
AVSS(2)
Converter
AN12(1)
AN11
AN10
AN9
AN8
1100
1011
1010
1001
1000
Note 1: Channels AN12 through AN15 are not available on PIC18F6628/6723 devices.
2: I/O pins have diode protection to VDD and VSS.
0X
1X
X1
X0
AN15(1)
AN14(1)
AN13(1)
1111
1110
1101
© 2009 Microchip Technology Inc. DS39894B-page 35
PIC18F8723 FAMILY
The value in the ADRESH:ADRESL registers is
unknown following Power-on and Brown-out Resets and
is not affected by any other Reset.
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 2.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
The following steps should be followed to perform an A/D
conversion:
1. Configure the A/D module:
Configure analog pins, voltage reference and
digital I/O (ADCON1)
Select A/D input channel (ADCON0)
Select A/D acquisition time (ADCON2)
Select A/D conversion clock (ADCON2)
Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
Clear ADIF bit
Set ADIE bit
Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
Set GO/DONE bit (ADCON0<1>)
5. Wait for A/D conversion to complete by either:
Polling for the GO/DONE bit to be cleared
OR
Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit, ADIF, if required.
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as T
AD. A minimum wait of 2 TAD is
required before the next acquisition starts.
FIGURE 2-2: A/D TRANSFER FUNCTION
FIGURE 2-3: ANALOG INPUT MODEL
Digital Code Output
FFEh
003h
002h
001h
000h
0.5 LSB
1 LSB
1.5 LSB
2 LSB
2.5 LSB
4094 LSB
4094.5 LSB
3 LSB
Analog Input Voltage
FFFh
4095 LSB
4095.5 LSB
VAIN CPIN
Rs ANx
5 pF
VT = 0.6V
VT = 0.6V ILEAKAGE
RIC 1k
Sampling
Switch
SS RSS
CHOLD = 25 pF
VSS
VDD
±100 nA
Legend: CPIN
VT
ILEAKAGE
RIC
SS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance (from DAC)
various junctions
= Sampling Switch ResistanceRSS
VDD
6V
Sampling Switch
5V
4V
3V
2V
123 4
(kΩ)
PIC18F8723 FAMILY
DS39894B-page 36 © 2009 Microchip Technology Inc.
2.1 A/D Acquisition Requirements
For the A/D Converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 2-3. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor, CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
source impedance affects the offset voltage at the ana-
log input (due to pin leakage current). The maximum
recommended impedance for analog sources is
2.5 kΩ. After the analog input channel is selected
(changed), the channel must be sampled for at least
the minimum acquisition time before starting a
conversion.
To calculate the minimum acquisition time, Equation 2-1
may be used. This equation assumes that 1/2 LSb error
is used (4096 steps for the 12-bit A/D). The 1/2 LSb error
is the maximum error allowed for the A/D to meet its
specified resolution.
Example 2-3 shows the calculation of the minimum
required acquisition time, T
ACQ. This calculation is
based on the following application system
assumptions:
CHOLD = 25 pF
Rs = 2.5 kΩ
Conversion Error 1/2 LSb
VDD =3V Rss = 4 kΩ
Temperature = 85°C (system max.)
EQUATION 2-1: ACQUISITION TIME
EQUATION 2-2: A/D MINIMUM CHARGING TIME
EQUATION 2-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
Note: When the conversion is started, the
holding capacitor is disconnected from the
input pin.
TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
=T
AMP + TC + TCOFF
VHOLD = (VREF – (VREF/4096)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))
or
TC = (CHOLD)(RIC + RSS + RS) ln(1/4096)
TACQ =TAMP + TC + TCOFF
TAMP =0.2 µs
TCOFF = (Temp – 25°C)(0.02 µs/°C)
(85°C – 25°C)(0.02 µs/°C)
1.2 µs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 µs.
TC = -(CHOLD)(RIC + RSS + RS) ln(1/4096) µs
-(25 pF) (1 kΩ + 4 kΩ + 2.5 kΩ) ln(0.0002441) µs
1.56 µs
TACQ = 0.2 µs + 1.56 μs + 1.2 µs
2.96 µs
© 2009 Microchip Technology Inc. DS39894B-page 37
PIC18F8723 FAMILY
2.2 Selecting and Configuring
Acquisition Time
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set. It also gives users the option to use an
automatically determined acquisition time.
Acquisition time may be set with the ACQT2:ACQT0
bits (ADCON2<5:3>), which provide a range of 2 to
20 TAD. When the GO/DONE bit is set, the A/D module
continues to sample the input for the selected acquisi-
tion time, then automatically begins a conversion.
Since the acquisition time is programmed, there may
be no need to wait for an acquisition time between
selecting a channel and setting the GO/DONE bit.
Manual acquisition is selected when
ACQT2:ACQT0 = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT2:ACQT0 bits
and is compatible with devices that do not offer
programmable acquisition times.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
2.3 Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 13 TAD per 12-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for T
AD:
•2 T
OSC
•4 TOSC
•8 TOSC
•16 TOSC
•32 TOSC
•64 TOSC
Internal RC Oscillator
For correct A/D conversions, the A/D conversion clock
(T
AD) must be as short as possible, but greater than the
minimum TAD (see parameter 130 for more
information).
Table 2-1 shows the resultant T
AD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 2-1: TAD vs. DEVICE OPERATING FREQUENCIES
A/D Clock Source (TAD)Assumes TAD Min. = 0.8 μs
Operation ADCS2:ADCS0 Maximum FOSC
2 TOSC 000 2.50 MHz
4 TOSC 100 5.00 MHz
8 T
OSC 001 10.00 MHz
16 TOSC 101 20.00 MHz
32 TOSC 010 40.00 MHz
64 TOSC 110 40.00 MHz
RC(1) x11 1.00 MHz(2)
Note 1: The RC source has a typical TAD time of 2.5 μs.
2: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or a FOSC
divider should be used instead; otherwise, the A/D accuracy specification may not be met.
PIC18F8723 FAMILY
DS39894B-page 38 © 2009 Microchip Technology Inc.
2.4 Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ADCS2:ADCS0 bits in
ADCON2 should be updated in accordance with the
clock source to be used. The ACQT2:ACQT0 bits do
not need to be adjusted as the ADCS2:ADCS0 bits
adjust the TAD time for the new clock speed. After enter-
ing the mode, an A/D acquisition or conversion may be
started. Once started, the device should continue to be
clocked by the same clock source until the conversion
has been completed.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D RC
clock source should be selected.
Operation in Sleep mode requires the A/D FRC clock to
be selected. If the ACQT2:ACQT0 bits are set to ‘000
and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEP instruction and entry to Sleep mode. The IDLEN
bit (OSCCON<7>) must have already been cleared
prior to starting the conversion.
2.5 Configuring Analog Port Pins
The ADCON1, TRISA, TRISF and TRISH registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Analog con-
version on pins configured as digital pins
can be performed. The voltage on the pin
will be accurately converted.
2: Analog levels on any pin defined as a dig-
ital input may cause the digital input buffer
to consume current out of the device’s
specification limits.
© 2009 Microchip Technology Inc. DS39894B-page 39
PIC18F8723 FAMILY
2.6 A/D Conversions
Figure 2-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 2-5 shows the operation of the A/D Converter
after the GO/DONE bit has been set, the
ACQT2:ACQT0 bits are set to ‘010’ and a 4 TAD acqui-
sition time has been selected before the conversion
starts.
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2T
CY wait is required before the next acquisition can
be started. After this wait, acquisition on the selected
channel is automatically started.
2.7 Discharge
The discharge phase is used to initialize the value of
the holding capacitor. The array is discharged before
every sample. This feature helps to optimize the unity
gain amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measure values.
FIGURE 2-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
FIGURE 2-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Code should wait at least 2 μs after
enabling the A/D before beginning an
acquisition and conversion cycle.
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD11
Set GO/DONE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
TAD9 TAD10TCY – TAD
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input
Conversion starts
b2
b11 b8 b7 b6 b5 b4 b3
b10 b9
On the following cycle:
Discharge
TAD13TAD12
b0b1
TAD1
(typically 200 ns)
1234567813
Set GO/DONE bit
(Holding capacitor is disconnected)
912
Conversion starts
1234
(Holding capacitor continues
acquiring input)
T
ACQT Cycles TAD Cycles
Automatic
Acquisition
Time
b0b11 b8 b7 b6 b5 b4 b1
b10 b9
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input
On the following cycle:
TAD1
Discharge
10 11
b3 b2
(typically
200 ns)
PIC18F8723 FAMILY
DS39894B-page 40 © 2009 Microchip Technology Inc.
2.8 Use of the ECCP2 Trigger
An A/D conversion can be started by the Special Event
Trigger of the ECCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be
programmed as1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion, and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to automat-
ically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH:ADRESL to the
desired location). The appropriate analog input chan-
nel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
TACQ time selected before the Special Event Trigger
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
TABLE 2-2: REGISTERS ASSOCIATED WITH A/D OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF (3)
PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF (3)
PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE (3)
IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP (3)
PIR2 OSCFIF CMIF EEIF BCL1IF HLVDIF TMR3IF CCP2IF (3)
PIE2 OSCFIE CMIE EEIE BCL1IE HLVDIE TMR3IE CCP2IE (3)
IPR2 OSCFIP CMIP EEIP BCL1IP HLVDIP TMR3IP CCP2IP (3)
ADRESH A/D Result Register High Byte (3)
ADRESL A/D Result Register Low Byte (3)
ADCON0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON (3)
ADCON1 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 (3)
ADCON2 ADFM ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 (3)
TRISA TRISA7(1) TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 (3)
TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 (3)
TRISH(2) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 (3)
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
2: These registers are not implemented on PIC18F6628/6723 devices.
3: For these Reset values, see the “PIC18F8722 Family Data Sheet” (DS39646).
© 2009 Microchip Technology Inc. DS39894B-page 41
PIC18F8723 FAMILY
3.0 SPECIAL FEATURES OF THE
CPU
PIC18F8723 family devices include several features
intended to maximize reliability and minimize cost
through elimination of external components. These
include:
Device ID Registers
3.1 Device ID Registers
The Device ID registers are “read-only” registers.
They identify the device type and revision to device
programmers and can be read by firmware using table
reads.
TABLE 3-1: DEVICE IDs
Note: For additional details on the Configuration
bits, refer to Section 25.1 “Configuration
Bits” in the “PIC18F8722 Family Data
Sheet” (DS39646). Device ID information
presented in this section is for the
PIC18F8723 family only.
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Default/
Unprogrammed
Value
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(1)
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 xxxx xxxx(1)
Legend: x = unknown
Note 1: See Register 3-1 and Register 3-2 for DEVID values. DEVID registers are read-only and cannot be programmed by the
user.
PIC18F8723 FAMILY
DS39894B-page 42 © 2009 Microchip Technology Inc.
REGISTER 3-1: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F8723 FAMILY DEVICES
RRRRRRRR
DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0
bit 7 bit 0
Legend:
R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
bit 7-5 DEV2:DEV0: Device ID bits
See Register 3-2 for a complete listing.
bit 4-0 REV4:REV0: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 3-2: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F8723 FAMILY DEVICES
RRRRRRRR
DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3
bit 7 bit 0
Legend:
R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
bit 7-0 DEV10:DEV3: Device ID bits
DEV10:DEV3
(DEVID2<7:0>)
DEV2:DEV0
(DEVID1<7:5>) Device
0100 1001 110 PIC18F6628
0100 1010 000 PIC18F6723
0100 1001 111 PIC18F8628
0100 1010 001 PIC18F8723
© 2009 Microchip Technology Inc. DS39894B-page 43
PIC18F8723 FAMILY
4.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD IOH} + {(VDDVOH) x IOH} + (VOL x IOL)
2: Voltage spikes below VSS at the RG5/MCLR/VPP pin, inducing currents greater than 80 mA, may cause
latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the RG5/MCLR/
VPP pin, rather than pulling this pin directly to VSS.
Note: Other than some basic data, this section documents only the PIC18F8723 family’s specifications that differ
from those of the PIC18F8722 family devices. For detailed information on the electrical specifications shared
by the PIC18F8723 family and PIC18F8722 family devices, see the “PIC18F8722 Family Data Sheet”
(DS39646).
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
PIC18F8723 FAMILY
DS39894B-page 44 © 2009 Microchip Technology Inc.
FIGURE 4-1: PIC18F8723 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
FIGURE 4-2: PIC18F8723 FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED)
Frequency
Voltage
6.0V
5.5V
4.5V
4.0V
2.0V
FMAX
5.0V
3.5V
3.0V
2.5V
PIC18F8723 Family
4.2V
FMAX = 20 MHz in 8-Bit External Memory mode.
FMAX = 40 MHz in all other modes.
Frequency
Voltage
6.0V
5.5V
4.5V
4.0V
2.0V
FMAX
5.0V
3.5V
3.0V
2.5V
4.2V
FMAX = 20 MHz in 8-Bit External Memory mode.
FMAX = 25 MHz in all other modes.
PIC18F8723 Family
© 2009 Microchip Technology Inc. DS39894B-page 45
PIC18F8723 FAMILY
FIGURE 4-3: PIC18LF8723 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
Frequency
Voltage
6.0V
5.5V
4.5V
4.0V
2.0V
FMAX
5.0V
3.5V
3.0V
2.5V
In 8-Bit External Memory mode:
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
4 MHz
4.2V
FMAX = (9.55 MHz/V) (VDDAPPMIN2.0V) + 4 MHz, if VDDAPPMIN 4.2V;
FMAX = 25 MHz, if VDDAPPMIN > 4.2V.
In all other modes:
FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz;
FMAX = 40 MHz, if VDDAPPMIN > 4.2V.
PIC18LF8723 Family
PIC18F8723 FAMILY
DS39894B-page 46 © 2009 Microchip Technology Inc.
TABLE 4-1: A/D CONVERTER CHARACTERISTICS: PIC18F8723 FAMILY (INDUSTRIAL)
Param
No. Sym Characteristic Min Typ Max Units Conditions
A01 NRResolution 12 bit ΔVREF 3.0V
A03 EIL Integral Linearity Error <±1 ±2.0 LSB VDD = 3.0V ΔVREF 3.0V
——±2.0LSBV
DD = 5.0V
A04 EDL Differential Linearity Error <±1 +1.5/-1.0 LSB VDD = 3.0V ΔVREF 3.0V
——+1.5/-1.0LSBV
DD = 5.0V
A06 EOFF Offset Error <±1 ±5 LSB VDD = 3.0V ΔVREF 3.0V
——±3LSBV
DD = 5.0V
A07 EGN Gain Error <±1 ±1.25 LSB VDD = 3.0V ΔVREF 3.0V
——±2.00LSBV
DD = 5.0V
A10 Monotonicity Guaranteed(1) —VSS VAIN VREF
A20 ΔVREF Reference Voltage Range
(VREFH – VREFL)
3—V
DD – VSS V For 12-bit resolution
A21 VREFH Reference Voltage High VSS + 3.0V VDD + 0.3V V For 12-bit resolution
A22 VREFL Reference Voltage Low VSS0.3V VDD – 3.0V V For 12-bit resolution
A25 VAIN Analog Input Voltage VREFL —VREFH V
A30 ZAIN Recommended
Impedance of Analog
Voltage Source
——2.5kΩ
A50 IREF VREF Input Current(2)
5
150
μA
μA
During VAIN acquisition.
During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: VREFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from
the RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.
© 2009 Microchip Technology Inc. DS39894B-page 47
PIC18F8723 FAMILY
FIGURE 4-4: A/D CONVERSION TIMING
TABLE 4-2: A/D CONVERSION REQUIREMENTS
131
130
132
BSF ADCON0, GO
Q4
A/D CLK(1)
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Note 2)
11 10 9 3 2 1
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction
to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
. . . . . .
TCY
0
Param
No. Symbol Characteristic Min Max Units Conditions
130 TAD A/D Clock Period PIC18FXXXX 0.8 12.5(1) μsTOSC based, VREF 3.0V
PIC18LFXXXX 1.4 25.0(1) μsVDD = 3.0V;
T
OSC based, VREF full range
PIC18FXXXX 1 μs A/D RC mode
PIC18LFXXXX 3 μsVDD = 3.0V; A/D RC mode
131 TCNV Conversion Time
(not including acquisition time)(2)
13 14 TAD
132 TACQ Acquisition Time(3) 1.4 μs
135 TSWC Switching Time from Convert Sample (Note 4)
137 TDIS Discharge Time 0.2 μs
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following T
CY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
4: On the following cycle of the device clock.
PIC18F8723 FAMILY
DS39894B-page 48 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS39894B-page 49
PIC18F8723 FAMILY
5.0 PACKAGING INFORMATION
For packaging information, see the “PIC18F8722 Family
Data Sheet” (DS39646).
PIC18F8723 FAMILY
DS39894B-page 50 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS39894B-page 51
PIC18F8723 FAMILY
APPENDIX A: REVISION HISTORY
Revision A (August 2007)
Original data sheet for the PIC18F8723 family of
devices.
Revision B (October 2009)
Updated to remove Preliminary status.
APPENDIX B: DEVICE
DIFFERENCES
The differences between the devices listed in this data
sheet are shown in Table B-1.
TABLE B-1: PIC18F8723 FAMILY DEVICE DIFFERENCES
Features PIC18F6628 PIC18F6723 PIC18F8628 PIC18F8723
Program Memory (Bytes) 96K 128K 96K 128K
Program Memory (Instructions) 49152 65536 49152 65536
Interrupt Sources 28 28 29 29
I/O Ports Ports A, B, C, D, E,
F, G
Ports A, B, C, D, E,
F, G
Ports A, B, C, D, E,
F, G, H , J
Ports A, B, C, D, E,
F, G, H, J
Capture/Compare/PWM Modules2222
Enhanced
Capture/Compare/PWM Modules
3333
Parallel Communications (PSP) Yes Yes Yes Yes
External Memory Bus No No Yes Yes
12-Bit Analog-to-Digital Module 12 Input Channels 12 Input Channels 16 Input Channels 16 Input Channels
Packages 64-Pin TQFP 64-Pin TQFP 80-Pin TQFP 80-Pin TQFP
PIC18F8723 FAMILY
DS39894B-page 52 © 2009 Microchip Technology Inc.
APPENDIX C: CONVERSION
CONSIDERATIONS
This appendix discusses the considerations for
converting from previous versions of a device to the
ones listed in this data sheet. Typically, these changes
are due to the differences in the process technology
used. An example of this type of conversion is from a
PIC16C74A to a PIC16C74B.
Not Applicable
APPENDIX D: MIGRATION FROM
BASELINE TO
ENHANCED DEVICES
This section discusses how to migrate from a Baseline
device (i.e., PIC16C5X) to an Enhanced MCU device
(i.e., PIC18FXXX).
The following are the list of modifications over the
PIC16C5X microcontroller family:
Not Currently Available
© 2009 Microchip Technology Inc. DS39894B-page 53
PIC18F8723 FAMILY
APPENDIX E: MIGRATION FROM
MID-RANGE TO
ENHANCED DEVICES
A detailed discussion of the differences between the
mid-range MCU devices (i.e., PIC16CXXX) and the
enhanced devices (i.e., PIC18FXXX) is provided in
AN716, “Migrating Designs from PIC16C74A/74B to
PIC18C442”. The changes discussed, while device
specific, are generally applicable to all mid-range to
enhanced device migrations.
This Application Note is available on our web site,
www.microchip.com, as Literature Number DS00716.
APPENDIX F: MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
A detailed discussion of the migration pathway and
differences between the high-end MCU devices (i.e.,
PIC17CXXX) and the enhanced devices (i.e.,
PIC18FXXX) is provided in AN726, “PIC17CXXX to
PIC18CXXX Migration”.
This Application Note is available on our web site,
www.microchip.com, as Literature Number DS00726.
PIC18F8723 FAMILY
DS39894B-page 54 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS39894B-page 55
PIC18F8723 FAMILY
INDEX
A
A/D ...................................................................................... 31
A/D Converter Interrupt, Configuring .......................... 35
Acquisition Requirements ........................................... 36
ADCON0 Register....................................................... 31
ADCON1 Register....................................................... 31
ADCON2 Register....................................................... 31
ADRESH Register................................................. 31, 34
ADRESL Register ....................................................... 31
Analog Port Pins, Configuring..................................... 38
Associated Registers .................................................. 40
Configuring the Module............................................... 35
Conversion Clock (TAD) .............................................. 37
Conversion Status (GO/DONE Bit) ............................. 34
Conversions ................................................................ 39
Converter Characteristics ........................................... 46
Discharge.................................................................... 39
Operation in Power-Managed Modes ......................... 38
Selecting and Configuring Acquisition Time ............... 37
Special Event Trigger (ECCP2) .................................. 40
Transfer Function........................................................ 35
Use of the ECCP2 Trigger .......................................... 40
Absolute Maximum Ratings ................................................ 43
ADCON0 Register............................................................... 31
GO/DONE Bit.............................................................. 34
ADCON1 Register............................................................... 31
ADCON2 Register............................................................... 31
ADRESH Register............................................................... 31
ADRESL Register ......................................................... 31, 34
Analog-to-Digital Converter. See A/D.
B
Block Diagrams
A/D .............................................................................. 34
Analog Input Model ..................................................... 35
PIC18F6628/6723....................................................... 11
PIC18F8628/8723....................................................... 12
C
Compare (ECCP2 Module)
Special Event Trigger.................................................. 40
Conversion Considerations................................................. 52
Customer Change Notification Service ............................... 57
Customer Notification Service............................................. 57
Customer Notification System............................................... 7
Customer Support ............................................................... 57
D
Device Differences.............................................................. 51
Device ID Registers ............................................................ 41
Device Overview
Features (table)........................................................... 10
Special Features ........................................................... 9
E
Electrical Characteristics..................................................... 43
Equations
A/D Acquisition Time................................................... 36
A/D Minimum Charging Time...................................... 36
Calculating the Minimum Required Acquisition Time.. 36
Errata .................................................................................... 7
External Memory Interface.................................................... 3
F
Features Summary Table ..................................................... 3
I
Internet Address ................................................................. 57
Interrupt Sources
A/D Conversion Complete .......................................... 35
M
Microchip Internet Web Site................................................ 57
Migration From Baseline to Enhanced Devices.................. 52
Migration From High-End to Enhanced Devices................. 53
Migration From Mid-Range to Enhanced Devices .............. 53
More Information................................................................... 7
Customer Notification System ...................................... 7
Errata............................................................................ 7
O
Overview
External Memory Interface ........................................... 3
Features Summary Table ............................................. 3
Peripheral Highlights .................................................... 3
Power-Managed Modes ............................................... 3
Special Microcontroller Features .................................. 3
P
Packaging Information........................................................ 49
Peripheral Highlights............................................................. 3
Pin Diagrams
64-Pin TQFP................................................................. 4
80-Pin TQFP................................................................. 5
Pin Functions
AVDD (64-pin) ............................................................. 20
AVDD (80-pin) ............................................................. 30
AVSS (64-pin).............................................................. 20
AVSS (80-pin).............................................................. 30
OSC1/CLKI/RA7................................................... 13, 21
OSC2/CLKO/RA6 ................................................. 13, 21
RA0/AN0............................................................... 14, 22
RA1/AN1............................................................... 14, 22
RA2/AN2/VREF- .................................................... 14, 22
RA3/AN3/VREF+ ................................................... 14, 22
RA4/T0CKI ........................................................... 14, 22
RA5/AN4/HLVDIN ................................................ 14, 22
RB0/INT0/FLT0 .................................................... 15, 23
RB1/INT1.............................................................. 15, 23
RB2/INT2.............................................................. 15, 23
RB3/INT3.................................................................... 15
RB3/INT3/ECCP2/P2A ............................................... 23
RB4/KBI0.............................................................. 15, 23
RB5/KBI1/PGM..................................................... 15, 23
RB6/KBI2/PGC ..................................................... 15, 23
RB7/KBI3/PGD ..................................................... 15, 23
RC0/T1OSO/T13CKI ............................................ 16, 24
RC1/T1OSI/ECCP2/P2A ...................................... 16, 24
RC2/ECCP1/P1A.................................................. 16, 24
RC3/SCK1/SCL1 .................................................. 16, 24
RC4/SDI1/SDA1 ................................................... 16, 24
RC5/SDO1............................................................ 16, 24
RC6/TX1/CK1....................................................... 16, 24
RC7/RX1/DT1....................................................... 16, 24
RD0/AD0/PSP0 .......................................................... 25
RD0/PSP0 .................................................................. 17
PIC18F8723 FAMILY
DS39894B-page 56 © 2009 Microchip Technology Inc.
RD1/AD1/PSP1........................................................... 25
RD1/PSP1................................................................... 17
RD2/AD2/PSP2........................................................... 25
RD2/PSP2................................................................... 17
RD3/AD3/PSP3........................................................... 25
RD3/PSP3................................................................... 17
RD4/AD4/PSP4/SDO2................................................ 25
RD4/PSP4/SDO2 ........................................................ 17
RD5/AD5/PSP5/SDI2/SDA2 ....................................... 25
RD5/PSP5/SDI2/SDA2 ............................................... 17
RD6/AD6/PSP6/SCK2/SCL2 ...................................... 25
RD6/PSP6/SCK2/SCL2 .............................................. 17
RD7/AD7/PSP7/SS2................................................... 25
RD7/PSP7/SS2........................................................... 17
RE0/AD8/RD/P2D....................................................... 26
RE0/RD/P2D............................................................... 18
RE1/AD9/WR/P2C ...................................................... 26
RE1/WR/P2C .............................................................. 18
RE2/AD10/CS/P2B ..................................................... 26
RE2/CS/P2D ............................................................... 18
RE3/AD11/P3C ........................................................... 26
RE3/P3C ..................................................................... 18
RE4/AD12/P3B ........................................................... 26
RE4/P3B ..................................................................... 18
RE5/AD13/P1C ........................................................... 26
RE5/P1C ..................................................................... 18
RE6/AD14/P1B ........................................................... 26
RE6/P1B ..................................................................... 18
RE7/AD15/ECCP2/P2A .............................................. 26
RE7/ECCP2/P2A ........................................................ 18
RF0/AN5 ............................................................... 19, 27
RF1/AN6/C2OUT .................................................. 19, 27
RF2/AN7/C1OUT .................................................. 19, 27
RF3/AN8 ............................................................... 19, 27
RF4/AN9 ............................................................... 19, 27
RF5/AN10/CVREF.................................................. 19, 27
RF6/AN11 ............................................................. 19, 27
RF7/SS1 ............................................................... 19, 27
RG0/ECCP3/P3A.................................................. 20, 28
RG1/TX2/CK2 ....................................................... 20, 28
RG2/RX2/DT2....................................................... 20, 28
RG3/CCP4/P3D .................................................... 20, 28
RG4/CCP5/P1D .................................................... 20, 28
RG5....................................................................... 20, 28
RG5/MCLR/VPP .................................................... 13, 21
RH0/A16 ..................................................................... 29
RH1/A17 ..................................................................... 29
RH2/A18 ..................................................................... 29
RH3/A19 ..................................................................... 29
RH4/AN12/P3C ........................................................... 29
RH5/AN13/P3B ........................................................... 29
RH6/AN14/P1C ........................................................... 29
RH7/AN15/P1B ........................................................... 29
RJ0/ALE...................................................................... 30
RJ1/OE ....................................................................... 30
RJ2/WRL..................................................................... 30
RJ3/WRH .................................................................... 30
RJ4/BA0...................................................................... 30
RJ5/CE........................................................................ 30
RJ6/LB ........................................................................ 30
RJ7/UB........................................................................ 30
VDD.............................................................................. 20
VDD.............................................................................. 30
VSS.............................................................................. 20
VSS.............................................................................. 30
Pinout I/O Descriptions
PIC18F6628/6723 ...................................................... 13
PIC18F8628/8723 ...................................................... 21
Power-Managed Modes........................................................ 3
and A/D Operation...................................................... 38
Product Identification System ............................................. 59
R
Reader Response............................................................... 58
Registers
ADCON0 (A/D Control 0)............................................ 31
ADCON1 (A/D Control 1)............................................ 32
ADCON2 (A/D Control 2)............................................ 33
DEVID1 (Device ID 1)................................................. 42
DEVID2 (Device ID 2)................................................. 42
Revision History.................................................................. 51
S
Special Features of the CPU .............................................. 41
Device ID Registers .................................................... 41
Special Microcontroller Features .......................................... 3
T
Timing Diagrams
A/D Conversion........................................................... 47
Timing Diagrams and Specifications
A/D Conversion Requirements ................................... 47
V
Voltage-Frequency Graphs
Extended (PIC18F8723) ............................................. 44
Industrial (PIC18F8723).............................................. 44
Industrial (PIC18LF8723)............................................ 45
W
WWW Address ................................................................... 57
WWW, On-Line Support ....................................................... 7
© 2009 Microchip Technology Inc. DS39894B-page 57
PIC18F8723 FAMILY
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
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listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
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customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
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Notification and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
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Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers should contact their distributor,
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customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
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DS39894B-page 58 © 2009 Microchip Technology Inc.
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DS39894BPIC18F8723 Family
1. What are the best features of this document?
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3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
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© 2009 Microchip Technology Inc. DS39894B-page 59
PIC18F8723 FAMILY
PIC18F8723 FAMILY PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device(1) (2) PIC18F6628/6723, PIC18F8628/8723,
VDD range 4.2V to 5.5V
PIC18LF6628/6723, PIC18LF6628/6723(
VDD range 2.0V to 5.5V
Temperature
Range
I= -40°C to +85°C (Industrial)
E= -40°C to +125°C (Extended)
Package PT = TQFP (Thin Quad Flatpack)
Pattern QTP, SQTP, Code or Special Requirements
(blank otherwise)
Examples:
a) PIC18LF6723-I/PT 301 = Industrial temp.,
TQFP package, Extended VDD
limits, QTP pattern #301.
b) PIC18F6723-E/PT = Extended temp.,
TQFP package, standard VDD limits.
Note 1: F = Standard Voltage Range
LF = Wide Voltage Range
2: T = in tape and reel TQFP
packages only.
DS39894B-page 60 © 2009 Microchip Technology Inc.
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