DS90C032 LVDS Quad CMOS Differential Line Receiver General Description Features The DS90C032 is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. The DS90C032 accepts low voltage (350 mV) differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE (R) function that may be used to multiplex outputs. The receiver also supports OPEN, shorted and terminated (100) input Fail-safe. Receiver output will be HIGH for all fail-safe conditions. The DS90C032 and companion line driver (DS90C031) provide a new alternative to high power psuedo-ECL devices for high speed point-to-point interface applications. n n n n n n n n n n n n n > 155.5 Mbps (77.7 MHz) switching rates Accepts small swing (350 mV) differential signal levels Ultra low power dissipation 600 ps maximum differential skew (5V, 25C) 6.0 ns maximum propagation delay Industrial operating temperature range Military operating temperature range option Available in surface mount packaging (SOIC) and (LCC) Pin compatible with DS26C32A, MB570 (PECL) and 41LF (PECL) Supports OPEN, short and terminated input fail-safe Compatible with IEEE 1596.3 SCI LVDS standard Conforms to ANSI/TIA/EIA-644 LVDS standard Available to Standard Microcircuit Drawing (SMD) 5962-95834 Connection Diagrams Dual-In-Line LCC Package DS011945-1 Order Number DS90C032TM See NS Package Number M16A DS011945-20 Order Number DS90C032E-QML See NS Package Number E20A For complete Military Specifications, refer to appropriate SMD or MDS. TRI-STATE (R) is a registered trademark of National Semiconductor Corporation. (c) 1998 National Semiconductor Corporation DS011945 www.national.com DS90C032 LVDS Quad CMOS Differential Line Receiver June 1998 Functional Diagram and Truth Tables DS011945-2 RECEIVER INPUTS OUTPUT EN ENABLES EN* RIN+ - RIN- ROUT L H X Z VID 0.1V H VID -0.1V L Full Fail-safe OPEN/SHORT H All other combinations of ENABLE inputs or Terminated www.national.com 2 Absolute Maximum Ratings (Note 1) Maximum Junction Temperature (DS90C032T) Maximum Junction Temperature (DS90C032E) ESD Rating (Note 7) (HBM, 1.5 k, 100 pF) (EIAJ, 0 , 200 pF) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) -0.3V to +6V -0.3V to (VCC +0.3V) Input Voltage (RIN+, RIN-) Enable Input Voltage -0.3V to (VCC +0.3V) (EN, EN*) -0.3V to (VCC +0.3V) Output Voltage (ROUT) Maximum Package Power Dissipation @ +25C M Package 1025 mW E Package 1830 mW Derate M Package 8.2 mW/C above +25C Derate E Package 12.2 mW/C above +25C Storage Temperature Range -65C to +150C Lead Temperature Range Soldering (4 sec.) +260C +150C +175C 3,500V 250V Recommended Operating Conditions Min Typ +4.5 +5.0 Supply Voltage (VCC) Receiver Input Voltage GND Operating Free Air Temperature (TA) DS90C032T -40 +25 DS90C032E -55 +25 Max +5.5 2.4 Units V V +85 +125 C C Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Note 2) Symbol Parameter VTH Differential Input High Threshold VTL Differential Input Low Threshold IIN Input Current VOH Output High Voltage Conditions RIN+, RIN- VIN = +2.4V VCC = 5.5V VIN = 0V IOH = -0.4 mA, VID = +200 mV IOH = -0.4 mA, DS90C032T VOL Output Low Voltage IOS Output Short Circuit Current Input terminated IOL = 2 mA, VID = -200 mV Enabled, VOUT = 0V (Note 8) Disabled, VOUT = 0V or VCC IOZ Output TRI-STATE Current VIH Input High Voltage VIL Input Low Voltage II Input Current VCL Input Clamp Voltage ICC No Load Supply Current Min EN, EN* Max Units +100 mV -100 mV -10 1 1 3.8 4.9 V 3.8 4.9 V -10 ROUT Typ +10 A +10 A 0.07 0.3 V -15 -60 -100 mA -10 1 +10 A 2.0 V 0.8 V +10 A 3.5 10 mA 3.5 11 mA 3.7 11 mA No Load Supply Current Inputs Open DS90C032E EN, EN* = 2.4 or 0.5, Inputs Open EN = GND, EN* = VCC DS90C032T 3.5 10 mA Receivers Disabled Inputs Open 3.5 11 mA Receivers Enabled ICCZ Pin VCM = +1.2V ICL = -18 mA EN, EN* = VCC or GND, DS90C032T DS90C032E 3 VCC -10 1 -1.5 -0.8 V www.national.com Switching Characteristics VCC = +5.0V, TA = +25C DS90C032T (Notes 3, 4, 5, 9) Symbol tPHLD Differential Propagation Delay High to Low Parameter tPLHD Differential Propagation Delay Low to High Conditions CL = 5 pF VID = 200 mV (Figure 1 and Figure 2) Min Typ Max 1.5 3.40 5.0 Units ns 1.5 3.48 5.0 ns 0 80 600 ps 0 0.6 1.0 ns ns tSKD Differential Skew |tPHLD - tPLHD| tSK1 Channel-to-Channel Skew (Note 5) tTLH Rise Time 0.5 2.0 tTHL Fall Time 0.5 2.0 ns tPHZ Disable Time High to Z 10 15 ns tPLZ Disable Time Low to Z RL = 2 k CL = 10 pF 10 15 ns tPZH Enable Time Z to High (Figure 3 and Figure 4) 4 10 ns tPZL Enable Time Z to Low 4 10 ns Min Typ Max Units 1.0 3.40 6.0 ns 1.0 3.48 6.0 ns 0 0.08 1.2 ns 0 0.6 1.5 ns 5.0 ns ns Switching Characteristics VCC = +5.0V 10%, TA = -40C to +85C DS90C032T (Notes 3, 4, 5, 6, 9) Symbol tPHLD Differential Propagation Delay High to Low Parameter tPLHD Differential Propagation Delay Low to High Conditions CL = 5 pF VID = 200 mV (Figure 1 and Figure 2) tSKD Differential Skew |tPHLD - tPLHD| tSK1 Channel-to-Channel Skew (Note 5) tSK2 Chip to Chip Skew (Note 6) tTLH Rise Time 0.5 2.5 tTHL Fall Time 0.5 2.5 ns tPHZ Disable Time High to Z 10 20 ns tPLZ Disable Time Low to Z RL = 2 k CL = 10 pF 10 20 ns tPZH Enable Time Z to High (Figure 3 and Figure 4) 4 15 ns tPZL Enable Time Z to Low 4 15 ns Min Typ Max Units 1.0 3.40 8.0 ns 1.0 3.48 8.0 ns 0 0.08 3.0 ns 0 0.6 3.0 ns Switching Characteristics VCC = +5.0V 10%, TA = -55C to +125C DS90C032E (Notes 3, 4, 5, 6, 9, 10) Symbol tPHLD Differential Propagation Delay High to Low Parameter tPLHD Differential Propagation Delay Low to High Conditions CL = 20 pF VID = 200 mV tSKD Differential Skew |tPHLD - tPLHD| (Figure 1 and Figure 2) tSK1 Channel-to-Channel Skew (Note 5) tSK2 Chip to Chip Skew (Note 6) tPHZ Disable Time High to Z tPLZ tPZH tPZL Enable Time Z to Low 7.0 ns 10 20 ns Disable Time Low to Z RL = 2 k CL = 10 pF 10 20 ns Enable Time Z to High (Figure 3 and Figure 4) 4 20 ns 4 20 ns www.national.com 4 Parameter Measurement Information DS011945-3 FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit DS011945-4 FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms DS011945-5 CL includes load and test jig capacitance. S1 = VCC for tPZL and tPLZ measurements. S1 = GND for tPZH and tPHZ measurements. FIGURE 3. Receiver TRI-STATE Delay Test Circuit DS011945-6 FIGURE 4. Receiver TRI-STATE Delay Waveforms 5 www.national.com Typical Application DS011945-7 FIGURE 5. Point-to-Point Application resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. Twisted pair cable will offer better balance than flat ribbon cable. 3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not supported across the common-mode range of the device (GND to 2.4V). It is only supported with inputs shorted and no external common-mode voltage applied. The footprint of the DS90C032 is the same as the industry standard 26LS32 Quad Differential (RS-422) Receiver. Applications Information LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 5. This configuration provides a clean signaling environment for the quick edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the range of 100. A termination resistor of 100 should be selected to match the media, and is located as close to the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS90C032 differential line receiver is capable of detecting signals as low as 100 mV, over a 1V common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The driven signal is centered around this voltage and may shift 1V around this center point. The 1V shifting may be the result of a ground potential difference between the driver's ground reference and the receiver's ground reference, the common-mode effects of coupled noise, or a combination of the two. Both receiver input pins should honor their specified operating input voltage range of 0V to +2.4V (measured from each pin to ground), exceeding these limits may turn on the ESD protection circuitry which will clamp the bus voltages. Receiver Fail-Safe: The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs. 1. Open Input Pins. The DS90C032 is a quad receiver device, and if an application requires only 1, 2 or 3 receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry will guarantee a HIGH, stable output state for open inputs. 2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a TRI-STATE or power-off condition, the receiver output will again be in a HIGH state, even with the end of cable 100 termination www.national.com 6 Pin Descriptions Pin No. Name (SOIC) Pin No. Name (SOIC) Description 8 2, 6, 10, 14 RIN+ Non-inverting receiver input pin 1, 7, 9, 15 RIN- Inverting receiver input pin 3, 5, 11, 13 ROUT 4 EN Active high enable pin, OR-ed with EN* EN* Active low enable pin, OR-ed with EN 16 VCC Power supply pin, +5V 10% Ground pin Ordering Information Receiver output pin 12 GND Description Operating Package Type/ Temperature Number -40C to +85C SOP/M16A DS90C032TM -55C to +125C LCC/E20A DS90C032E-QML DS90C032E-QML (NSID) 5962-95834 (SMD) Order Number Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation. Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified. Note 3: All typicals are given for: VCC = +5.0V, TA = +25C. Note 4: Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50, tr and tf (0%-100%) 1 ns for RIN and tr and tf 6 ns for EN or EN*. Note 5: Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same chip with an event on the inputs. Note 6: Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays. Note 7: ESD Rating: HBM (1.5 k, 100 pF) 3,500V EIAJ (0, 200 pF) 250V Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature specification. Note 9: CL includes probe and jig capacitance. Note 10: For DS90C032E propagation delay measurements are from 0V on the input waveform to the 50% point on the output (ROUT). Typical Performance Characteristics Output High Voltage vs Power Supply Voltage Output High Voltage vs Ambient Temperature DS011945-8 DS011945-9 7 www.national.com Typical Performance Characteristics (Continued) Output Low Voltage vs Power Supply Voltage Output Low Voltage vs Ambient Temperature DS011945-10 Output Short Circuit Current vs Power Supply Voltage DS011945-11 Output Short Circuit Current vs Ambient Temperature DS011945-12 Differential Propagation Delay vs Power Supply Voltage DS011945-13 Differential Propagation Delay vs Ambient Temperature DS011945-14 www.national.com DS011945-15 8 Typical Performance Characteristics (Continued) Differential Skew vs Power Supply Voltage Differential Skew vs Ambient Temperature DS011945-17 DS011945-16 Transition Time vs Power Supply Voltage Transition Time vs Ambient Temperature DS011945-18 DS011945-19 9 www.national.com 10 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Ceramic Leadless Chip Carrier, Type C Order Number DS90C032E-QML NS Package Number E20A 16-Lead (0.150" Wide) Molded Small Outline Package, JEDEC Order Number DS90C032TM NS Package Number M16A 11 www.national.com DS90C032 LVDS Quad CMOS Differential Line Receiver LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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