The FTS88130 device provides asynchronous opera-
tions with matching access and cycle times. Memory
locations are specified on address pins A0 to A16.
Reading is accomplished by device selection (CE1 low
and CE2 high) and output enabling (OE) while write
enable (WE) remains HIGH. By presenting the ad-
dress under these conditions, the data in the ad-
dressed memory location is presented on the data
input/output pins. The input/output pins stay in the
HIGH Z state when either CE1 or OE is HIGH or WE
or CE2 is LOW.
The FT88130 is a 1,048,576-bit high-speed CMOS
static RAM organized as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 15 nanoseconds permit greatly en-
hanced system operating speeds. CMOS is utilized to
reduce power consumption to a low level. The FTS88130
is a member of a family of FT SRAM products offer-
ing fast access times.
Advanced CMOS Technology
Fast tOE
Automatic Power Down
Packages
—32-Pin 300 mil DIP and SOJ
—32-Pin 400 mil SOJ
—32-Pin 600 mil Ceramic DIP
—32-Pin 400 mil Ceramic DIP
—32-Pin Solder Seal Flatpack
—32-Pin LCC (400 x 820 mil) [Two-Sided]
—32-Pin Ceramic SOJ
High Speed (Equal Access and Cycle Times)
— 15/20/25/35 ns (Commercial)
— 20/25/35/45 ns (Industrial)
— 20/25/35/45/55/70/85/100/120 ns (Military)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CECE
CECE
CE1, CE2 and OEOE
OEOE
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION
DESCRIPTION
FEATURES
DIP (P300, C10, C11),
SOJ (J300, J400, CJ),
SOLDER SEAL
FLATPACK (FS-3) SIMILAR
LCC (L6)
FTS88130
128Kx8 High Speed SRAM
1
MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VCC Power Supply Pin with –0.5 to +7 V
Respect to GND
Terminal Voltage with –0.5 to
VTERM Respect to GND VCC +0.5 V
(up to 7.0V)
TAOperating Temperature –55 to +125 °C
Symbol Parameter Value Unit
TBIAS Temperature Under –55 to +125 °C
Bias
TSTG Storage Temperature –65 to +150 °C
PTPower Dissipation 1.0 W
IOUT DC Output Current 50 mA
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
ISB
Standby Power Supply
Current (TTL Input Levels)
CE1 ≥ VIH or Mil.
CE2 ≤VIL, Ind./Com’l.
VCC= Max,
f = Max., Outputs Open
___
___ 35
30
___
___
___
___
25
20
25
n/a
2
n/a
mA
mA
___
___
CE1 ≥ VHC or Mil.
CE2 ≤VLC, Ind./Com’l.
VCC= Max,
f = 0, Outputs Open
VIN ≤ VLC or VIN ≥ VHC
Standby Power Supply
Current
(CMOS Input Levels)
ISB1
Grade(2) Ambient
Temperature GND VCC
0V
0V
5.0V ± 10%
5.0V ± 10%
0V 5.0V ± 10%
–55°C to +125°C
Military
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
VOUT = 0V
8
10
Unit
pF
pF
CAPACITANCES(4)
VCC = 5.0V, TA = 25°C, f = 1.0MHz
Symbol
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
VIH
VIL
VHC
VLC
VCD
VOL
VOH
ILI
ILO
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
Output Leakage Current
Test Conditions
VCC = Min., IIN = –18 mA
IOL = +8 mA, VCC = Min.
IOH = –4 mA, VCC = Min.
VCC = Max. Mil.
VIN = GND to VCC Ind./Com’l.
VCC = Max., CE = VIH, Mil.
VOUT = GND to VCC Ind./Com’l.
FTS88130
Min
2.2
–0.5(3)
VCC –0.2
–0.5(3)
2.4
–10
–5
–10
–5
Max
VCC +0.5
0.8
VCC +0.5
0.2
–1.2
0.4
+10
+5
+10
+5
FTS88130L
Min Max
2.2
–0.5(3)
VCC –0.2
–0.5(3)
2.4
–5
n/a
–5
n/a
VCC +0.5
0.8
VCC +0.5
0.2
0.4
–1.2
+5
n/a
+5
n/a
Unit
V
V
V
V
V
V
V
µA
µA
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Typ.
Industrial
Commercial
–40°C to +85°C
0°C to +70°C
2
DATA RETENTION CHARACTERISTICS (FTS88130L, Military Temperature Only)
Typ.* Max
Symbol Parameter Test Condition Min VCC=V
CC=Unit
2.0V 3.0V 2.0V 3.0V
VDR VCC for Data Retention 2.0 V
ICCDR Data Retention Current 50 200 400 600 µA
tCDR Chip Deselect to ns
Data Retention Time
tR
†Operation Recovery Time tRC
§ns
*TA = +25°C
§tRC = Read Cycle Time
†This parameter is guaranteed but not tested.
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE1 = VIL, CE2 = VIH, OE = VIH
POWER DISSIPATION CHARACTERISTICS VS. SPEED
DATA RETENTION WAVEFORM
CE1 ≥ VCC – 0.2V or
CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V
or VIN ≤ 0.2V
Symbol Parameter Temperature
Range -15 -20 -25 -35 -45 -55 -70 -85 -100 -120 Unit
Commercial 190 160 150 145 N/A N/A N/A N/A N/A N/A mA
Industrial N/A 175 165 160 155 N/A N/A N/A N/A N/A mA
Military N/A 150 140 135 130 125 115 110 105 100 mA
Dynamic Operating Current*ICC
3
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
tRC
Read Cycle
Time 15 20 25 35 45 55 70 85 100 120 ns
tAA
Address
Access Time 15 20 25 35 45 55 70 85 100 120 ns
tAC
Chip Enable
Access Time 15 20 25 35 45 55 70 85 100 120 ns
tOH
Output Hold
from Address
Change
3333333333ns
tLZ
Chip Enable to
Output in Low Z 3333333333ns
tHZ
Chip Disable
to Output in
High Z
8 9 11 15 20 25 30 35 40 50 ns
tOE
Output Enable
Low to Data
Valid
7 9 11 15 20 25 30 35 40 50 ns
tOLZ
Output Enable
Low to Low Z 0000000000ns
tOHZ
Output Enable
High to High Z 7 9 11 15 20 25 30 35 40 50 ns
tPU
Chip Enable to
Power Up
Time
0000000000ns
tPD
Chip Disable
to Power Down
Time
12 20 20 20 25 30 35 40 45 50 ns
Symbol Parameter
-15 -20 -25 -35 -45
Unit
-55 -70 -85 -100 -120
Notes:
5. WE is HIGH for READ cycle.
6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE1
transition
LOW and CE2 transition HIGH.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
TIMING WAVEFORM OF READ CYCLE NO. 1 (OEOE
OEOE
OE CONTROLLED)(5)
4
TIMINIG WAVERFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CECE
CECE
CE1, CE2 CONTROLLED)(5,7,10)
Notes:
9. READ Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays
irrespective of whether CE1 or CE2 causes them.
5
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
tWC Write Cycle Time 15 20 25 35 45 55 70 85 100 120 ns
tCW
Chip Enable
Time to End of
Write
12 15 18 22 30 35 45 50 60 75 ns
tAW
Address Valid to
End of Write 12 15 20 25 35 45 60 70 85 100 ns
tAS
Address Set-up
Time 0000000000ns
tWP
Write Pulse
Width 12 15 18 22 25 30 40 45 55 70 ns
tAH
Address Hold
Time 0000000000ns
tDW
Data Valid to
End of Write 7 8 10 15 20 25 30 35 45 60 ns
tDH Date Hold Time0000000000ns
tWZ
Write Enable to
Output in High Z 8 101115182025304050ns
tOW
Output Active
from End of
Write
3333333333ns
Symbol Parameter -15 -20 -25 -35 -45 Unit
-55 -70 -85 -100 -120
Notes:
11. CE1 and WE must be LOW, and CE2 HIGH for WRITE cycle.
12. OE is LOW for this WRITE cycle to show tWZ and tOW.
13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH,
the output remains in a high impedance state.
14. Write Cycle Time is measured from the last valid address to the first
transitioning address.
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WEWE
WEWE
WE CONTROLLED)(11)
6
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CECE
CECE
CE CONTROLLED)(11)
1.5V
Write
Active
Read
* including scope and test fixture.
Note:
Because of the ultra-high speed of the FTS88130, care must be
taken when testing this device; an inadequate setup can cause a
normal functioning part to be rejected as faulty. Long high-
inductance leads that cause supply bounce must be avoided by
bringing the VCC and ground planes directly up to the contactor
fingers. A 0.01 µF high frequency capacitor is also required
between VCC and ground.
To avoid signal reflections, proper termination must be used; for
example, a 50Ω test environment should be terminated into a 50Ω load
with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω
resistor must be used in series with DOUT to match 166Ω (Thevenin
Resistance).
AC TEST CONDITIONS TRUTH TABLE
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
GND to 3.0V
3ns
1.5V
See Fig. 1 and 2
Mode
Standby
Standby
DOUT Disabled
Standby
PowerI/O
WEWE
WEWE
WE
OEOE
OEOE
OECE2
CECE
CECE
CE1
High Z
High Z
DOUT
High Z
X
X
H
H
L
X
X
H
L
X
X
L
H
H
H
H
X
L
L
L
Standby
Active
Active
High Z
Figure 1. Output Load Figure 2. Thevenin Equivalent
7
The FTS88130 is avaliable in the following temperatures, speed and package options.
* Military temperature range with MIL-STD-883 M5004
N/A = Not Available
8
FTS88130 L XX XX X
Mil Temp with MIL-STD-883 M5004
9
2-SIDED LEADLESS CHIP CARRIER
Pkg # L1
# Pins 32
Symbol Min Max
A0.080 0.100
b 0.022 0.028
b1 0.006 0.022
b2 0.040 -
D 0.820 0.840
E 0.392 0.400
e 0.050 BSC
h 0.012 REF
L 0.070 0.080
L1 0.090 0.110
L2 0.003 0.015
N 32
* Military temperature range with MIL-STD-883, Class B compliance.
Temperature
Range Package Speed
55 70 85 100 120
Commercial Plastic DIP (300 mil)
Plastic SOJ (300 mil)
Plastic SOJ (400 mil)
Industrial Plastic DIP (300 mil)
Plastic SOJ (300 mil)
Plastic SOJ (400 mil)
Military
Temperature
Ceramic DIP (600 mil) -55C6M -70C6M -85C6M -100C6M -120C6M
Ceramic DIP (400 mil) -55C4M -70C4M -85C4M -100C4M -120C4M
Solder Seal Flatpack -55FSM -70FSM -85FSM -100FSM -120FSM
-55LM -70LM -85LM -100LM -120LM
-55L1M -70L1M -85L1M -100L1M -120L1M
Ceramic SOJ -55CJM -70CJM -85CJM -100CJM -120CJM
Military
Processed*
Ceramic DIP (600 mil) -55C6MB -70C6MB -85C6MB -100C6MB -120C6MB
Ceramic DIP (400 mil) -55C4MB -70C4MB -85C4MB -100C4MB -120C4MB
Solder Seal Flatpack -55FSMB -70FSMB -85FSMB -100FSMB -120FSMB
-55LMB -70LMB -85LMB -100LMB -120LMB
-55L1MB -70L1MB -85L1MB -100L1MB -120L1MB
Ceramic SOJ -55CJMB -70CJMB -85CJMB -100CJMB -120CJMB
Pkg #
# Pins
Symbol Min Max
A 0.128 0.148
A1 0.082 -
b 0.016 0.020
C 0.007 0.010
D 0.820 0.830
e
E
E1 0.295 0.305
E2
Q0.025-
J300
32 (300 mil)
0.050 BSC
0.267 BSC
0.335 BSC
Pkg #
# Pins
Symbol Min Max
A 0.128 0.148
A1 0.082 -
b 0.015 0.020
C 0.007 0.013
D 0.820 0.830
e
E 0.435 0.445
E1 0.395 0.405
E2
Q0.025-
J400
32 (400 mil)
0.050 BSC
0.370 BSC
SOJ SMALL OUTLINE IC PACKAGE (300 mil)
SOJ SMALL OUTLINE IC PACKAGE (400 mil)
10
Pkg #
# Pins
Symbol Min Max
A - 0.200
A1 0.015 -
b 0.014 0.022
b2 0.048 0.054
C 0.008 0.014
D 1.580 1.620
E1 0.270 0.300
E 0.300 0.310
e
eB 0.320 0.390
L 0.120 0.140
0° 15°
P300
32 (300 mil)
0.100 BSC
α
PLASTIC DUAL IN-LINE PACKAGE
SOLDER SEAL FLAT PACKAGE
Pkg #
# Pins
Symbol Min Max
A 0.097 0.125
b 0.015 0.019
c 0.003 0.009
D - 0.830
E 0.400 0.420
E1 - 0.450
E2 0.180 -
E3 0.030 -
e
L 0.250 0.370
Q 0.020 0.045
S - 0.045
S1 0.000 -
M - 0.0015
N
FS-3
32
0.050 BSC
32
11
SIDEBRAZED DUAL IN-LINE PACKAGE (600 mil)
SIDEBRAZED DUAL IN-LINE PACKAGE (400 mil)
Pkg #
# Pins
Symbol Min Max
A-0.225
b 0.014 0.026
b2 0.045 0.065
C 0.008 0.018
D-1.680
E 0.510 0.620
eA
e
L 0.125 0.200
Q 0.015 0.070
S1 0.005 -
S2 0.005 -
0.600 BSC
0.100 BSC
C10
32 (600 mil)
Pkg #
# Pins
Symbol Min Max
A-0.232
b 0.014 0.023
b2 0.038 0.065
C 0.008 0.018
D-1.700
E 0.350 0.410
eA
e
L 0.125 0.200
Q 0.015 0.060
S1 0.005 -
S2 0.005 -
C11
32 (400 mil)
0.400 BSC
0.100 BSC
12
Pkg #
# Pins
Symbol Min Max
A 0.060 0.075
A1 0.050 0.065
B1 0.022 0.028
D 0.442 0.458
D1
D2
D3 - 0.458
E 0.540 0.560
E1
E2
E3 - 0.558
e
h
j
L 0.045 0.055
L1 0.045 0.055
L2 0.075 0.095
ND
NE
L6
32
0.300 BSC
0.150 BSC
0.020 REF
7
9
0.400 BSC
0.200 BSC
0.050 BSC
0.040 REF
RECTANGULAR LEADLESS CHIP CARRIER
CERAMIC SOJ SMALL OUTLINE IC PACKAGE
Pkg #
# Pins
Symbol Min Max
A 0.120 0.165
A1 0.088 0.120
A2 0.070 REF
B0.010REF
B1 0.030R TYP
B2 0.020 REF
B3 0.025 0.045
D 0.816 0.838
D1 0.750 REF
E 0.419 0.431
E1 0.430 0.445
E2 0.360 0.380
e
e1 0.038 TYP
e2 0.005
j0.005TYP
S 0.030 0.040
S1 0.020 TYP
CJ1
32
0.050 BSC
13
REVISIONS
DOCUMENT NUMBER: SRAM128
DOCUMENT TITLE: FTS88130 HIGH SPEED 128K x 8 DUAL CHIP ENABLE CMOS STATIC RAM
REV. ISSUE
DATE
ORIG. OF
CHANGE DESCRIPTION OF CHANGE
OR 1997 DAB New Data Sheet
A Oct-04 B.S Data Sheet Review
14
B Jun-08 B.S Added L1 Package
Ashley Crt, Henley,
Marlborough, Wilts, SN8 3RH UK
Tel: +44(0)1264 731200
Fax:+44(0)1264 731444
E-mail
info@forcetechnologies.co.uk
tech@forcetechnologies.co.uk
sales@forcetechnologies.co.uk
www.forcetechnologies.co.uk
Life Support Applications
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for use in such applications do so at their own risk and agree to fully indemnify Force Technologies for any damages resulting from such
improper use or sale.
All trademarks acknowledged Copyright Force Technologies Ltd 2004
Unless otherwise stated in this SCD/Data sheet, Force Technologies Ltd reserve the right to make changes, without notice, in the products, Includ
-ing circuits, cells and/or software, described or contained herein in order to improve design and/or performance. Force Technologies resumes no
responsibility or liability for the use of any of these products, conveys no licence or any title under patent, copyright, or mask work to these
products, and makes no representation or warranties that that these products are free from patent, copyright or mask work infringement, unless
otherwise specified.
15
