1
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
■Very Low Dropout Voltage: 0.6Ω PMOS Pass
Device
■Accurate Output Voltage: 2% over Temperature
■Guaranteed 500mA Output Current: SP6205
■Ultra Low Noise Output: 12µVRMS with 10nF
Bypass
■Unconditionally Stable with 2.2µF Ceramic
■Low Quiescent Current: 45µA
■Very Low Ground Current: 350µA at 500 mA
■Power-Saving Shutdown Mode: < 1µA
■Fast Turn-On and Turn-Off: 60us
■Fast Transient Response
■Current Limit and Thermal Shutdown Protection
■Very Good Load/Line Regulation: 0.07/0.04%
■Excellent PSRR: 67dB<1kHz
■Industry Standard 5 pin SOT-23 and Small 8
pin DFN Package
■Fixed Output Voltages: 2.5V, 2.7V, 2.8V,
2.85V, 3.0V and 3.3V
■Adjustable Output Available
Low Noise, 300mA and 500mA CMOS LDO Regulators
SP6203/6205
DESCRIPTION
■ Cellular / GSM Phones
■ Laptop / Palmtop Computers
■ Battery-Powered Systems
■ Pagers
■ Medical Devices
■ MP3/CD Players
■ Digital Still Cameras
FEATURES
APPLICATIONS
®
The SP6203/6205 are ultra low noise CMOS LDOs with very low dropout and ground current. The noise
performance is achieved by means of an external bypass capacitor without sacrificing turn-on and turn-off
speed critical to portable applications. Extremely stable and easy to use, these devices offer excellent PSRR
and Line/Load regulation. Target applications include battery-powered equipment such as portable and
wireless products. Regulators' ground current increases only slightly in dropout. Fast turn-on/turn-off enable
control and an internal 30Ω pull down on output allows quick discharge of output even under no load
conditions. Both LDOs are protected with current limit and thermal shutdown.
Both LDO's are availiable in fixed & adjustable output voltage versions and come in an industry standard
5 pin SOT-23 and small 8 pin DFN package. For SC-70 100mA CMOS LDO, SP6213 is available.
TYPICAL APPLICATION CIRCUIT
3
2
1
COUT
2.2µF Ceramic
VOUT
VIN
EN BYP
4
5
SP6203
SP6205
5-Pin
FIXED
CIN
2.2µF
3
2
1
C
OUT
2.2µF Ceramic
V
OUT
V
IN
EN ADJ
4
5
SP6203
SP6205
5-Pin
ADJUSTABLE
C
IN
2.2µF
Fixed Adjustable
Now Available in Lead Free Packaging
V
OUTSENSE
SP6203
SP6205
8 Pin DFN
V
IN
NC
V
OUT
BYP
GND
EN
NC
1
2
3
4
8
7
6
5
SP6203
SP6205
8 Pin DFN
V
IN
NC
V
OUT
ADJ
NC
GND
EN
NC
1
2
3
4
8
7
6
5
2
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
ELECTRICALCHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Supply Input Voltage (VIN)...................................................... -2V to 6V
Output Voltage (VOUT) ................................................. -0.6V to VIN +1V
Enable Input Voltage (VEN)..................................................... -2V to 6V
Power Dissipation (PD) ................................... Internally Limited, Note 1
Lead Temperature (soldering 5s) .............................................. +260°C
Storage Temperature .................................................. -65°C to +150°C
Junction Temperature ............................................................... +150°C
These are stress ratings only and functional operation of the device at these
ratings or any other above those indicated in the operation sections of the
specifications below is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
Unless otherwise specified: VIN=VOUT + 0.5V to 6V, COUT = 2.2µF ceramic, CIN = 2.2µF, IOUT =100µA,
-40°C < T < 125°C. The ♦ denotes the specifications which apply over full operating temperature range -40°C to
+125°C, unless otherwise specified.
PARAMETER MIN TYP MAX UNITS ♦CONDITIONS
Input Voltage 6 V ♦
Output Voltage Accuracy -2 +2 % ♦Variation from specified V
OUT
Output Voltage 50 ppm/°C∆V
OUT
/∆T
Temperature Coefficient, Note2
Reference Voltage 1.225 1.25 1.275 V ♦Adjustable version only
Line Regulation 0.04 0.3 %/V ∆V
OUT
(V
IN
below 6V)
Load Regulation, Note 3 0.07 0.3 % I
OUT
= 0.1mA to 300mA (SP6203)
0.13 0.5 I
OUT
= 0.1mA to 500mA (SP6205)
Dropout Voltage, Note 4 0.06 I
OUT
= 0.1mA
(For V
OUT
≥ 3.0V) 60 I
OUT
= 100mA
120 mV I
OUT
= 200mA
180 300 ♦I
OUT
= 300mA (SP6203)
300 500 ♦I
OUT
= 500mA (SP6205)
Ground Pin Current, Note 5 45 100 ♦I
OUT
= 0.1mA (I
QUIESCENT
)
110 I
OUT
= 100mA
175 µAI
OUT
= 200mA
235 330 ♦I
OUT
= 300mA (SP6203)
350 490 ♦I
OUT
= 500mA (SP6205)
Shutdown Supply Current 0.01 1 µA♦V
EN
< 0.4V (shutdown)
Current Limit 0.33 0.50 0.8 A V
OUT
= 0V (SP6203)
0.55 0.85 1.4 V
OUT
= 0V (SP6205)
Thermal Shutdown Junction 170 °CRegulator Turns off
Temperature
Thermal Shutdown Hysteresis 12 °CRegulator turns on again at 158°C
Power Supply Rejection Ratio 67 dB f ≤ 1kHz
Output Noise Voltage, Note 6 150 C
BYP
= 0nF, I
OUT
= 0.1mA
630 C
BYP
= 0nF, I
OUT
=300mA
12 µV
RMS
C
BYP
= 10nF, I
OUT
= 0.1mA
50 75 C
BYP
= 10nF, I
OUT
= 300mA
Thermal Regulation, Note 7 0.05 %/W ∆V
OUT
/∆P
D
Wake-Up Time (T
WU
), Note 8 25 5 0 µsV
IN
≥ 4V, Note 10
(from shutdown mode) I
OUT
= 30mA
Turn-On Time (T
ON
), Note 9 60 120 µsV
IN
≥ 4V, Note 10
(from shutdown mode) I
OUT
= 30mA
Turn-Off Time (T
OFF
), 100 250 µsI
OUT
= 0.1mA, V
IN
≥ 4V, Note 10
15 25 I
OUT
= 300mA, V
IN
≥ 4V, Note 10
Output Discharge Resistance 30 ΩNo Load
Enable Input Logic Low Voltage 0.4 V ♦Regulator Shutdown
Enable Input Logic High Voltage 1.6 V ♦Regulator Enabled
Input Voltage (VIN) ......................................................... +2.7V to +5.5V
Enable Input Voltage (VEN)...................................................... 0 to 5.5V
Junction Temperature (TJ)........................................... -40°C to +125°C
Thermal Resistance, SOT-23-5 (θJA) ...........................................Note 1
Thermal Resistance, 8 Pin DFN (θJA) ..........................................Note 1
Remark: The device is not guaranteed to function outside its operating rating.
OPERATING RATINGS
3
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
ELECTRICAL CHARACTERISTIC NOTES
Note 1: Maximum power dissipation can be calculated using the formula: PD = (TJ(max) - TA) / θθ
θθ
θJA, where TJ(max) is
the junction temperature, TA is the ambient temperature and θJA is the junction-to-ambient thermal resistance. θJC
is 6ºC/W for this package. Exceeding the maximum allowable power dissipation will result in excessive die
temperature and thermal shutdown protection. For 5 Pin SOT-23 θJA is 191°C/W and 59°C/W for the 8 Pin DFN. A
part mounted on a PC board will deliver improved thermal perfformance based on copper surface area.
Note 2: Output voltage temperature coefficient is defined as the worst case voltage change divided by the total
temperature range.
Note 3: Regulation is measured at constant junction temperature using low duty cycle pulse testing. Changes in
output voltage due to heating effects are covered by the thermal regulation specification.
Note 4: Dropout-voltage is defined as the input to output differential at which the output voltage drops 2% below its
nominal value measured at 1V differential.
Note 5: Ground pin current is the regulator quiescent current. The total current drawn from the supply is the sum of
the load current plus the ground pin current.
Note 6: Output noise voltage is defined within a certain bandwidth, namely 10Hz < BW < 100kHz. An external
bypass cap (10nF) from reference output (BYP pin) to ground significantly reduces noise at output.
Note 7: Thermal regulation is defined as the change in output voltage at a time “t” after a change in power
dissipation is applied, excluding load and line regulation effects.
Specifications are for a 300mA load pulse at VIN = 6V for t = 1ms.
Note 8: The wake-up time (TWU) is defined as the time it takes for the output to start rising after enable is brought
high.
Note 9: The total turn-on time is called the settling time (TS), which is defined as the condition when both the
output and the bypass node are within 2% of their fully enabled values when released from shutdown.
Note 10: For output voltage versions requiring VIN to be lower than 4V, timing (TON & TOFF) increases slightly.
(optional)
Cbyp
V
OUT
BYP
EN
VIN
GND
bandgap
reference
thermal shutdown
&
current limit
1.25V
R2
R1
ADJ
V
OUT
EN
V
IN
GND
bandgap
reference
thermal shutdown
&
current limit
1.25V
Low Noise Fixed Regulator - 5 Pin Low Noise Adjustable Regulator - 5 Pin
FUNCTIONAL DIAGRAM
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Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
PIN DESCRIPTION
PIN NUMBER NAME FUNCTION
1V
IN Power Supply Input
2GND Ground Terminal
3ENEnable/Shutdown (Logic high = enable, logic
low = shutdown)
4 (Fixed) BYP Reference bypass input for ultra-quiet operation.
Connecting a 10nF cap on this pin reduces
output noise.
4 (adj.) ADJ Adjustable (Input): Adjustable regulator feed-
back input. Connect to a resistive voltage-
divider network.
5V
OUT Regulator Output Voltage
5 PIN OPTION
V
IN
GND
EN
V
OUT
BYP
SIPEX
4
3
5
1
2
V
IN
GNDEN
V
OUT
ADJ
SIPEX
4
3
5
12
Fixed Voltage Regulator Adjustable Voltage Regulator
PINOUTS
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Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISTICS
V
OUT
I
O
(200mA/DIV)
V
OUT
V
EN
VOUT
VEN
V
OUT
V
EN
V
OUT
(AC)
I
OUT
V
OUT
(AC)
V
IN
Current Limit Turn on Time, RLOAD = 50Ω (60mA)
Turn off Time, RLOAD = 6Ω (500mA) Turn off Time, RLOAD = 30K (0.1mA)
Line Regulation, Line Step from 4V to 6V, IO = 1mA
Load Regulation, IO = 100µA ~ 500mA
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Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISTICS: Continued
V
EN
V
OUT
V
IN
= 3.5V, I
O
= 500mA
V
IN
V
OUT
BYP
V
IN
V
OUT
BYP
V
IN
V
OUT
BYP
V
IN
V
OUT
BYP
Start Up Waveform, VIN = 3.5V, IO = 500mA Start Up Waveform, Slow VIN , No Load
Start Up Waveform, Slow VIN , COUT=1000µF, IO=0mA
Start Up Waveform, Slow VIN , 500mA Output Load
Start Up Waveform, Slow VIN, COUT=1000µF, IO=500mA
V
IN
V
OUT
BYP
Fast VIN , No Load
7
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISTICS: Continued
VIN
VOUT
BYP
Fast VIN = 1000µF Output Load
Fast VIN , 500mA Output Load
V
IN
V
OUT
BYP
Fast VIN , COUT=1000µF, IO=500mA
8
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
General Overview
The SP6203/6205 is intended for applications
where very low dropout voltage, low supply
current and low output noise are critical, even
with high load conditions (500mA maximum).
Unlike bipolar regulators, the SP6203/6205
(CMOS LDO) supply current increases only
slightly with load current.
The SP6203/6205 contains an internal bandgap
reference which is fed into the inverting input of
the LDO-amplifier. The output voltage is then
set by means of a resistor divider and compared
to the bandgap reference voltage. The error
LDO-amplifier drives the gate of a P-channel
MOSFET pass device that has a RDS(ON) of 0.6Ω
at 500mA producing a 300mV drop at the out-
put.
Furthermore, the SP6203/6205 has its own cur-
rent limit circuitry (500mA/850mA) to ensure
that the output current will not damage the
device during output short, overload or start-up.
Also, the SP6203/6205 includes thermal shut-
down circuitry to turn off the device when the
junction temperature exceeds 170°C and it re-
mains off until the temperature drops by 12°C.
Enable/Shutdown Operation
The SP6203/6205 is turned off by pulling the
VEN pin below 0.4V and turned on by pulling it
above 1.6V.
If this enable/shutdown feature is not required,
it should be tied directly to the input supply
voltage to keep the regulator output on at all
time.
While in shutdown, VOUT quickly falls to zero
(turn-off time is dependent on load conditions
and output capacitance on VOUT) and power
consumption drops nearly to zero.
Input Capacitor
A small capacitor of 2.2µF is required from VIN
to GND if a battery is used as the power
source. Any good quality electrolytic, ceramic
or tantalum capacitor may be used at the input.
Output Capacitor
An output capacitor is required between VOUT
and GND to prevent oscillation. A 2.2µF output
capacitor is recommended.
Larger values make the chip more stable which
means an improvement of the regulator’s tran-
sient response. Also, when operating from other
sources than batteries, supply-noise rejection
can be improved by increasing the value of the
input and output capacitors and using passive
filtering techniques.
For a lower output current, a smaller output
capacitance can be chosen.
Finally, the output capacitor should have an
effective series resistance (ESR) of 0.5Ω or less.
Therefore, the use of good quality ceramic or
tantalum capacitors is advised.
Bypass Capacitor
A bypass pin (BYP) is provided to decouple the
bandgap reference. A 10nF external capacitor
connected from BYP to GND reduces noise
present on the internal reference, which in turn
significantly reduces output noise and also im-
proves power supply rejection. Note that the
minimum value of COUT must be increased to
maintain stability when the bypass capacitor is
used because CBYP reduces the regulator phase
margin. If output noise is not a concern, this
input may be left unconnected. Larger capacitor
values may be used to further improve power
supply rejection, but result in a longer time
period (slower turn on) to settle output voltage
when power is initially applied.
No Load Stability
The SP6203/6205 will remain stable and in
regulation with no external load (other than the
internal voltage driver) unlike many other volt-
age regulators. This is especially important in
CMOS RAM battery back-up applications.
THEORY OF OPERATION
9
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
THEORY OF OPERATION: Continued
Turn On Time
The turn on response is split up in two separate
response categories: the wake up time (TWU)
and the settlling time (TS). The wake up time is
defined as the time it takes for the output to rise
to 2% of its total value after being released from
shutdown (EN > 0.4V). The settling time is
defined as the condition where the output reaches
98% of its total value after being released from
shutdown. The latter is also called the turn on
time and is dependent on the output capacitor, a
little bit on load and, if present, on a bypass
capacitor.
TJ(max) is the maximum junction temperature of
the die and is 125°C. TA is the ambient tempera-
ture. θJA is the junction-to-ambient thermal re-
sistance for the regulator and is layout depen-
dent. The SOT-23-5 package has a θJA of
approximately 191°C/W for minimum PCB cop-
per footprint area.
This results in a maximum power dissipation of:
PD(max) = [(125°C - 25°C)/(256°C/W)] = 390mW
The actual power dissipation of the regulator
circuit can be determined using one simple
equation:
PD = (VIN - VOUT) * IOUT + VIN * IGND
To prevent the device from entering thermal
shutdown. maximum power dissipation can not
be exceeded.
Substituting PD(max) for PD and solving for the
operating conditions that are critical to the ap-
plication will give the maximum operating con-
ditions for the regulator circuit. For example, if
we are operating the SP6203 3.0V at room
temperature, with a minimum footprint layout
and and output current of 300mA, the maximum
input voltage can be determined, based on the
equation below. Ground pin current can be taken
from the electrical specifications table (0.23mA
at 300mA).
390mW = (VIN-3.0V) * 300mA + VIN *0.23mA
After calculations, we find that the maximum
input voltage of a 3.0V application at 300mA of
output current in a SOT-23-5 package is 4.3V.
So if the intend is to operate a 5V output version
from a 6V supply at 300mA load and at a 25°C
ambient temperature, then the actual total power
dissipation will be:
PD=([6V-5V]*[300mA])+(6V*0.23mA)=301.4 mW
This is well below the 390mW package maxi-
mum. Therefore, the regulator can be used.
Turn Off Time
The turn off time is defined as the condition
where the output voltage drops about 66% (θ) of
its total value. 5θ to 7θ is the constant where the
output voltage drops nearly to zero. There will
always be a small voltage drop in shutdown
because of the switch unless we short-circuit it.
The turn off time of the output voltage is depen-
dent on load conditions, output capacitance on
VOUT (time constant τ = RLCL) and also on the
difference in voltage between input and output.
Thermal Considerations
The SP6203/6205 is designed to provide 300/
500 mA of continuous current in a tiny package.
Maximum power dissipation can be calculated
based on the output current and the voltage drop
across the part. To determine the maximum
power dissipation of the package, use the junc-
tion-to-ambient thermal resistance of the device
and the following basic equation:
PD = (TJ(max) - TA) / θJA
2%
t(s) = T(on)
98%
t(wu)
VOUT
VENABLE
10
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
Note that the regulator cannot always be used at
its maximum current rating. For example, in a
5V input to 3.0V output application at an ambi-
ent temperature of 25°C and operating at the full
500mA (IGND = 0.355mA) load, the regulator is
limited to a much lower load current, deter-
mined by the following equation:
390mW = ( [5V-3V]*[ Iload(max)]) +(5V*0.355mA)
After calculation, we find that in such an appli-
cation (SP6205) the regulator is limited to
194.1mA. Doing the same calculations for the
300mA LDO (SP6203) will limit the regulator’s
output current to 194.4mA.
Also, taking advantage of the very low dropout
voltage characteristics of the SP6203/6205,
power dissipation can be reduced by using the
lowest possible input voltage to minimize the
input-to-output drop.
Adjustable Regulator Applications
The SP6203/6205 can be adjusted to a specific
output voltage by using two external resistors
(see functional diagram). The resistors set the
output voltage based on the following equation:
VOUT = VREF *(R1/R2 + 1)
Resistor values are not critical because ADJ
(adjust) has a high input impedance, but for best
performance use resistors of 470KΩ or less. A
bypass capacitor from ADJ to VOUT provides
improved noise performance.
Dual-Supply Operation
When used in dual supply systems where the
regulator load is returned to a negative supply,
the output voltage must be diode clamped to
ground.
Layout Considerations
The primary path of heat conduction out of the
package is via the package leads. Therefore,
careful considerations have to be taken into
account:
1) Attaching the part to a larger copper footprint
will enable better heat transfer from the device,
especially on PCB’s where there are internal
ground and power planes.
2) Place the input, output and bypass capacitors
close to the device for optimal transient re-
sponse and device behavior.
3) Connect all ground connections directly to
the ground plane. In case there’s no ground
plane, connect to a common local ground point
before connecting to board ground.
Such layouts will provide a much better thermal
conductivity (lower θJA) for, a higher maximum
allowable power dissipation limit.
THEORY OF OPERATION: Continued
11
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
PACKAGE: 5 PIN SOT-23
AA2
A1
SIDE VIEW
D
E
E/2
e1
N/22
1
b
e
E1
E1/2
NN/2
+1
L1
L
L2
Ø1
Seating Plane
Gauge Plane
VIEW C
SEE VIEW C
B
B
c
WITH PLATING
BASE METAL
b
Ø1 Ø
- - 1.45
0 - 0.15
Dimensions in (mm)
5 PIN SOT-23
JEDEC MO-178
(AA) Variation
0.90 1.15 1.30
0.30 - 0.50
0.08 - 0.22
2.90 BSC
2.80 BSC
1.60 BSC
0.30 0.45 0.60
0.60 REF
0º 4º 8º
A
A1
A2
b
c
D
E
E1
L
L1
L2
Ø
5º 10º 15º
Ø1
MIN NOM MAX
0.25 BSC
e
e1 1.90 BSC
0.95 BSC
SECTION B-B
Seating Plane
VIEW A-A
5 PIN SOT-23
12
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
PACKAGE: 8 PIN DFN
Top View
D
A
D2
Bottom View
E2
b
e
L
A1 A3
E
E/2
D/2 12
K
K
Side View
Pin 1 identifier to be located within this shaded area.
Terminal #1 Index Area (D/2 * E/2)
2x3 8 Pin DFN
JEDEC mo-229C
(VCED-2) Variation Dimensions in (mm)
Symbol MIN NOM MAX
A
A1
A3
b
D
D2
E2
e
L
0.80 0.90 1.00
0 0.02 0.05
0.20
2.00 BSC
1.50 1.75
0.30 0.40 0.50
1.60 1.90
0.18 0.25 0.30
0.50
2x3 8 Pin DFN
E3.00 BSC
--
-
--
-
0.20 --
13
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
ORDERING INFORMATION
Part Number Top Mark Temperature Range Package Type
SP6203EM5-2.5..................... L2WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-2.5/TR ............... L2WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-2.7..................... G2WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-2.7/TR ............... G2WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-2.8..................... Q3WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-2.8/TR ............... Q3WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-2.85................... H2WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-2.85/TR ............. H2WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-3.0..................... M2WW .....................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-3.0/TR ............... M2WW .....................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-3.3......................J2WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-3.3/TR ................J2WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-ADJ ................... Q2WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-ADJ/TR ............. Q2WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203ER-2.5 .................. 620325YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-2.5/TR ............ 620325YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-2.7 .................. 620327YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-2.7/TR ............ 620327YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-2.8 .................. 620328YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-2.8/TR ............ 620328YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-2.85 ................ 620385YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-2.85/TR .......... 620385YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-3.0 .................. 620330YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-3.0/TR ............ 620330YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-3.3 .................. 620333YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-3.3/TR ............ 620333YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-ADJ ................6203ERYWW ................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-ADJ/TR ..........6203ERYWW ................-40˚C to +125˚C......................... 8 Pin DFN
ANALOG EXCELLENCE
Corporation
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
/TR = Tape and Reel
Pack quantity is 2,500 for SOT-23 and 3,000 for DFN.
Available in lead free packaging. To order add "-L" suffix to part number.
Example: SP6205ER-ADJ/TR = standard; SP6205ER-L-ADJ/TR = lead free
14
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
ORDERING INFORMATION
Part Number Top Mark Temperature Range Package Type
SP6205EM5-2.5..................... V2WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-2.5/TR ............... V2WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-2.7..................... R2WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-2.7/TR ............... R2WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-2.8..................... E3WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-2.8/TR ............... E3WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-2.85................... S2WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-2.85/TR ............. S2WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-3.0.....................W2WW .....................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-3.0/TR ...............W2WW .....................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-3.3..................... T2WW ......................-40˚C to +125˚C....................5 Pin SOT-23
SP6205EM5-3.3/TR ............... T2WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-ADJ ................... A3WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-ADJ/TR ............. A3WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205ER-2.5 .................. 620525YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-2.5/TR ............ 620525YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-2.7 .................. 620527YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-2.7/TR ............ 620527YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-2.8 .................. 620528YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-2.8/TR ............ 620528YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-2.85 ................ 620585YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-2.85/TR .......... 620585YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-3.0 .................. 620530YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-3.0/TR ............ 620530YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-3.3 .................. 620533YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-3.3/TR ............ 620533YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-ADJ ................6203ERYWW ................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-ADJ/TR ..........6203ERYWW ................-40˚C to +125˚C......................... 8 Pin DFN
Corporation
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
/TR = Tape and Reel
Pack quantity is 2,500 for SOT-23 and 3,000 for DFN.
Available in lead free packaging. To order add "-L" suffix to part number.
Example: SP6205ER-ADJ/TR = standard; SP6205ER-L-ADJ/TR = lead free
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
