19-2411; Rev 0; 4/02 Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs Low Power 120mW (Normal Operation) 9mW (Sleep Mode) 0.3W (Shutdown Mode) 0.05dB Gain and 0.05 Phase Matching Wide 1VP-P Differential Analog Input Voltage Range 400MHz -3dB Input Bandwidth On-Chip 2.048V Precision Bandgap Reference User-Selectable Output Format--Two's Complement or Offset Binary Pin-Compatible 8-Bit and 10-Bit Upgrades Available Ordering Information PART MAX1197ECM TEMP RANGE -40C to +85C PIN-PACKAGE 48 TQFP-EP* *EP = Exposed paddle Functional Diagram and Pin Compatible Upgrades table appear at end of data sheet. 37 38 39 40 41 42 43 44 45 46 47 48 REFN REFP REFIN REFOUT D7A D6A D5A D4A D3A D2A D1A D0A Pin Configuration COM VDD 1 36 2 35 GND INA+ INAVDD 3 34 4 33 5 32 6 31 GND INBINB+ GND VDD CLK 7 MAX1197 30 OVDD OGND N.C. N.C. D0B D1B D2B D3B 24 23 22 21 N.C. N.C. OGND OVDD VDD GND T/B SLEEP PD OE D7B D6B D5B D4B 20 25 19 26 12 18 27 11 17 28 10 16 29 9 15 8 14 WLAN, WWAN, WLL, MMDS Modems Set-Top Boxes VSAT Terminals Excellent Dynamic Performance 48.5dB/45.3dB SINAD at fIN = 30MHz/200MHz 69dBc/53.5dBc SFDR at fIN = 30MHz/200MHz -72dB Interchannel Crosstalk at fIN = 20MHz 13 Baseband I/Q Sampling Multichannel IF Sampling Ultrasound and Medical Imaging Battery-Powered Instrumentation Single 2.7V to 3.6V Operation GND VDD Applications Features TQFP-EP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX1197 General Description The MAX1197 is a 3V, dual, 8-bit analog-to-digital converter (ADC) featuring fully differential wideband trackand-hold (T/H) inputs, driving two ADCs. The MAX1197 is optimized for low-power, small size, and high-dynamic performance for applications in imaging, instrumentation and digital communications. This ADC operates from a single 2.7V to 3.6V supply, consuming only 120mW while delivering a typical signal-to-noise and distortion (SINAD) of 48.5dB at an input frequency of 30MHz and a sampling rate of 60Msps. The T/H-driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters may also be operated with singleended inputs. In addition to low operating power, the MAX1197 features a 3mA sleep mode as well as a 0.1A power-down mode to conserve power during idle periods. An internal 2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of this internal or an externally applied reference, if desired, for applications requiring increased accuracy or a different input voltage range. The MAX1197 features parallel, CMOS-compatible threestate outputs. The digital output format can be set to two's complement or straight offset binary through a single control pin. The device provides for a separate output power supply of 1.7V to 3.6V for flexible interfacing with various logic families. The MAX1197 is available in a 7mm x 7mm, 48-pin TQFP package, and is specified for the extended industrial (-40C to +85C) temperature range. Pin-compatible lower and higher speed versions of the MAX1197 are also available. Refer to the MAX1195 data sheet for 40Msps and the MAX1198 data sheet for 100Msps. In addition to these speed grades, this family will include a multiplexed output version (MAX1196, 40Msps), for which digital data is presented time interleaved and on a single, parallel 8-bit output port. For a 10-bit, pin-compatible upgrade, refer to the MAX1182 data sheet. With the N.C. pins of the MAX1197 internally pulled down to ground, this ADC becomes a drop-in replacement for the MAX1182. MAX1197 Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V INA+, INA-, INB+, INB- to GND ...............................-0.3V to VDD REFIN, REFOUT, REFP, REFN, COM, CLK to GND .................................-0.3V to (VDD + 0.3V) OE, PD, SLEEP, T/B, D7A-D0A, D7B-D0B to OGND .............................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 48-Pin TQFP (derate 12.5mW/C above +70C).........1000mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = OVDD = 3V, 0.1F and 2.2F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 60MHz, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, < +25C guaranteed by design and characterization. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 8 Bits INL fIN = 7.5MHz (Note 1) 0.3 1 LSB DNL fIN = 7.5MHz, no missing codes guaranteed (Note 1) 0.2 1 LSB Offset Error 4 %FS Gain Error 4 Integral Nonlinearity Differential Nonlinearity Gain Temperature Coefficient %FS 100 ppm/C 1.0 V VDD / 2 0.2 V 95 k 5 pF 5 Clock Cycles ANALOG INPUT Differential Input Voltage Range VDIFF Common-Mode Input Voltage Range VCM Input Resistance RIN Input Capacitance CIN Differential or single-ended inputs Switched capacitor load CONVERSION RATE Maximum Clock Frequency fCLK 60 Data Latency MHz DYNAMIC CHARACTERISTICS (fCLK = 60MHz, 4096-point FFT) fINA or B = 7.5MHz at -1dB FS Signal-to-Noise Ratio 2 SNR fINA or B = 20MHz at -1dB FS 48.7 47 48.7 fINA or B = 30MHz at -1dB FS 48.6 fINA or B = 115.1MHz at -1dB FS 48.3 _______________________________________________________________________________________ dB Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs (VDD = OVDD = 3V, 0.1F and 2.2F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 60MHz, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, < +25C guaranteed by design and characterization. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN fINA or B = 7.5MHz at -1dB FS Signal-to-Noise and Distortion SINAD fINA or B = 20MHz at -1dB FS 46.5 SFDR Third-Harmonic Distortion HD3 48.6 fINA or B = 30MHz at -1dB FS 48.5 fINA or B = 115.1MHz at -1dB FS 48.2 fINA or B = 20MHz at -1dB FS fINA or B = 30MHz at -1dB FS MAX UNITS 48.6 fINA or B = 7.5MHz at -1dB FS Spurious-Free Dynamic Range TYP dB 71 60 69 dBc 69 fINA or B = 115.1MHz at -1dB FS 68 fINA or B = 7.5MHz at -1dB FS -75 fINA or B = 20MHz at -1dB FS -72 fINA or B = 30MHz at -1dB FS -72 fINA or B = 115.1MHz at -1dB FS -68 dBc Intermodulation Distortion (First Five Odd-Order IMDs) IMD fIN1(A or B) = 1.985MHz at -7dB FS fIN2(A or B) = 2.029MHz at -7dB FS (Note 2) -70 dBc Third-Order Intermodulation Distortion IM3 fIN1(A or B) = 1.985MHz at -7dB FS fIN2(A or B) = 2.029MHz at -7dB FS (Note 2) -71.8 dBc Total Harmonic Distortion (First Four Harmonics) THD Small-Signal Bandwidth Full-Power Bandwidth FPBW Gain Flatness (12MHz Spacing) Aperture Delay tAD Aperture Jitter tAJ Overdrive Recovery Time fINA or B = 7.5MHz at -1dB FS -69 fINA or B = 20MHz at -1dB FS -67 fINA or B = 30MHz at -1dB FS -67 fINA or B = 115.1MHz at -1dB FS -65 Input at -20dB FS, differential inputs 500 MHz Input at -1dB FS, differential inputs 400 MHz fIN1(A or B) = 106 MHz at -1dB FS fIN2(A or B) = 118 MHz at -1dB FS (Note 3) 0.05 dB 1 ns 1dB SNR degradation at Nyquist 2 psRMS For 1.5 x full-scale input 2 ns -57 dBc INTERNAL REFERENCE (REFIN = REFOUT through 10k resistor; REFP, REFN, and COM levels are generated internally.) Reference Output Voltage VREFOUT (Note 4) 2.048 3% V Positive Reference Output Voltage VREFP (Note 5) 2.012 V Negative Reference Output Voltage VREFN (Note 5) 0.988 V Common-Mode Level VCOM (Note 5) VDD / 2 0.1 V _______________________________________________________________________________________ 3 MAX1197 ELECTRICAL CHARACTERISTICS (continued) MAX1197 Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs ELECTRICAL CHARACTERISTICS (continued) (VDD = OVDD = 3V, 0.1F and 2.2F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 60MHz, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, < +25C guaranteed by design and characterization. Typical values are at TA = +25C.) PARAMETER SYMBOL Differential Reference Output Voltage Range VREF Reference Temperature Coefficient TCREF CONDITIONS MIN VREF = VREFP - VREFN TYP MAX UNITS 1.024 3% V 100 ppm/C BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V) Positive Reference Output Voltage VREFP (Note 5) 2.012 V Negative Reference Output Voltage VREFN (Note 5) 0.988 V Common-Mode Level VCOM (Note 5) VDD / 2 0.1 V Differential Reference Output Voltage Range VREF VREF = VREFP - VREFN 1.024 2% V REFIN Resistance RREFIN 750 M ISOURCE 5 mA ISINK -250 A ISOURCE 250 A ISINK -5 mA Maximum REFP, COM Source Current Maximum REFP, COM Sink Current Maximum REFN Source Current Maximum REFN Sink Current UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM) REFP, REFN Input Resistance REFP, REFN, COM Input Capacitance RREFP, RREFN Measured between REFP, COM, REFN, and COM CIN 4 k 15 pF 1.024 10% V Differential Reference Input Voltage Range VREF COM Input Voltage Range VCOM VDD / 2 5% V REFP Input Voltage VREFP VCOM + VREF / 2 V REFN Input Voltage VREFN VCOM VREF / 2 V VREF = VREFP - VREFN DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B) Input High Threshold 4 CLK 0.8 x VDD PD, OE, SLEEP, T/B 0.8 x OVDD VIH _______________________________________________________________________________________ V Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs (VDD = OVDD = 3V, 0.1F and 2.2F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 60MHz, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, < +25C guaranteed by design and characterization. Typical values are at TA = +25C.) PARAMETER Input Low Threshold Input Hysteresis SYMBOL CONDITIONS MIN Input Capacitance MAX CLK 0.2 x VDD PD, OE, SLEEP, T/B 0.2 x OVDD VIL VHYST Input Leakage TYP 0.15 V V IIH VIH = VDD = OVDD 20 IIL VIL = 0 20 CIN UNITS 5 A pF DIGITAL OUTPUTS (D7A-D0A, D7B-D0B) Output Voltage Low VOL ISINK = -200A Output Voltage High VOH ISOURCE = 200A Three-State Leakage Current ILEAK OE = OVDD Three-State Output Capacitance COUT OE = OVDD 0.2 OVDD - 0.2 V V 10 5 A pF POWER REQUIREMENTS Analog Supply Voltage Range VDD Output Supply Voltage Range OVDD CL = 15pF Operating, fINA & B = 20MHz at -1dB FS applied to both channels Analog Supply Current IVDD Sleep mode Shutdown, clock idle, PD = OE = OVDD Output Supply Current IOVDD Power-Supply Rejection PDISS PSRR 3 3.6 V 1.7 3 3.6 V 40 50 20 9 Sleep mode 3 Shutdown, clock idle, PD = OE = OVDD 3 10 120 150 Sleep mode mA 3 0.1 Operating, fINA & B = 20MHz at -1dB FS applied to both channels (Note 6) Operating, fINA & B = 20MHz at -1dB FS applied to both channels Analog Power Dissipation 2.7 A mA A mW 9 Shutdown, clock idle, PD = OE = OVDD 0.3 Offset, VDD 5% 3 Gain, VDD 5% 3 CL = 20pF (Notes 1, 7) 6 60 W mV/V TIMING CHARACTERISTICS CLK Rise to Output Data Valid Time tDO OE Fall to Output Enable Time tENABLE OE Rise to Output Disable Time tDISABLE 5 9 ns ns 5 ns CLK Pulse Width High tCH Clock period: 16.67ns (Note 7) 8.33 1.5 ns CLK Pulse Width Low tCL Clock period: 16.67ns (Note 7) 8.33 1.5 ns _______________________________________________________________________________________ 5 MAX1197 ELECTRICAL CHARACTERISTICS (continued) MAX1197 Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs ELECTRICAL CHARACTERISTICS (continued) (VDD = OVDD = 3V, 0.1F and 2.2F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 60MHz, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, < +25C guaranteed by design and characterization. Typical values are at TA = +25C.) PARAMETER Wake-Up Time SYMBOL tWAKE CONDITIONS MIN TYP Wake up from sleep mode 1 Wake up from shutdown mode (Note 11) 20 MAX UNITS s CHANNEL-TO-CHANNEL MATCHING Crosstalk fINA or B = 20MHz at -1dB FS (Note 8) -72 dB Gain Matching fINA or B = 20MHz at -1dB FS (Note 9) 0.05 dB Phase Matching fINA or B = 20MHz at -1dB FS (Note 10) 0.05 Degrees Note 1: Guaranteed by design. Not subject to production testing. Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the total input power. Note 3: Analog attenuation is defined as the amount of attenuation of the fundamental bin from a converted FFT between two applied input signals with the same magnitude (peak-to-peak) at fIN1 and fIN2. Note 4: REFIN and REFOUT should be bypassed to GND with a 0.1F (min) and 2.2F (typ) capacitor. Note 5: REFP, REFN, and COM should be bypassed to GND with a 0.1F (min) and 2.2F (typ) capacitor. Note 6: Typical analog output current at fINA&B = 20MHz. For digital output currents vs. analog input frequency, see Typical Operating Characteristics. Note 7: See Figure 3 for detailed system timing diagrams. Clock to data valid timing is measured from 50% of the clock level to 50% of the data output level. Note 8: Crosstalk rejection is tested by applying a test tone to one channel and holding the other channel at DC level. Crosstalk is measured by calculating the power ratio of the fundamental of each channel's FFT. Note 9: Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the fundamental of the calculated FFT. Note 10: Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test. Note 11: SINAD settles to within 0.5dB of its typical value in unbuffered external reference mode. 6 _______________________________________________________________________________________ Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs -30 fINA -40 -50 HD3 -30 -50 HD2 -20 HD3 fINB -30 -40 -60 -70 -80 -80 -90 -90 10 15 20 25 30 fINA -50 -70 5 fCLK = 60.056789MHz fINA = 114.974441MHz fINB = 99.945816MHz AIN = -1dB FS COHERENT SAMPLING HD2 HD3 fINB -90 0 5 10 15 20 25 0 30 5 10 15 20 25 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) TWO-TONE IMD PLOT (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) TWO-TONE IMD PLOT (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY -30 -40 -50 fIN1 fIN2 -60 -20 -30 -40 -50 fIN1 fIN2 49 -70 -80 -80 CHB 46 45 6 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 7 8 9 10 11 12 13 14 0 40 80 120 160 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) SIGNAL-TO-NOISE + DISTORTION vs. ANALOG INPUT FREQUENCY TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY -50 CHB CHB 47 46 SFDR (dBc) THD (dBc) 48 -60 CHA -70 -80 45 80 120 160 ANALOG INPUT FREQUENCY (MHz) 200 70 CHA 60 50 -90 40 80 CHB CHA 200 MAX1197 toc09 49 90 MAX1197 toc08 -40 MAX1197 toc07 50 0 48 47 -90 0 CHA -60 -70 -90 30 MAX1197 toc06 fCLK = 60.00640MHz fIN1 = 9.969325MHz fIN2 = 10.013275MHz AIN = -7dB FS COHERENT SAMPLING SNR (dB) -20 50 MAX1197 toc05 -10 0 -10 AMPLITUDE (dB) fCLK = 60.00640MHz fIN1 = 1.985075MHz fIN2 = 2.029025MHz AIN = -7dB FS COHERENT SAMPLING MAX1197 toc03 MAX1197 toc02 fINA -40 -60 0 -10 -80 0 SINAD (dB) FFT PLOT CHA (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) -70 0 AMPLITUDE (dB) fINB HD2 -60 fCLK = 60.056789MHz fINA = 29.859778MHz fINB = 19.9333995MHz AIN = -1dB FS COHERENT SAMPLING -20 MAX1197 toc04 AMPLITUDE (dB) -20 0 -10 AMPLITUDE (dB) fCLK = 60.056789MHz fINA = 7.4851051MHz fINB = 19.9333995MHz AIN = -1dB FS COHERENT SAMPLING MAX1197 toc01 0 -10 FFT PLOT CHA (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) AMPLITUDE (dB) FFT PLOT CHA (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) 40 0 40 80 120 160 ANALOG INPUT FREQUENCY (MHz) 200 0 40 80 120 160 200 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 7 MAX1197 Typical Operating Characteristics (VDD = 3V, OVDD = 3V, VREFIN = 2.048V, differential input at -1dB FS, fCLK = 40MHz, CL 10pF TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 3V, VREFIN = 2.048V, differential input at -1dB FS, fCLK = 40MHz, CL 10pF TA = +25C, unless otherwise noted.) 0 VIN = 100mVP-P 1 SFDR 0 GAIN (dB) 60 THD SNR 50 40 SINAD GAIN (dB) -1 70 30 -2 -15 10 35 60 -1 -3 -2 -4 -3 -4 -5 -40 85 1 10 1 1000 100 10 1000 100 TEMPERATURE (C) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) SIGNAL-TO-NOISE RATIO vs. INPUT POWER (fIN = 19.9333995MHz) SIGNAL-TO-NOISE + DISTORTION vs. INPUT POWER (fIN = 19.9333995MHz) TOTAL HARMONIC DISTORTION vs. INPUT POWER (fIN = 19.9333995MHz) 50 -50 40 -55 THD (dBc) 45 SINAD (dB) 45 40 -60 35 35 -65 30 30 -70 25 25 -20 -16 -12 -8 -4 0 MAX1197 toc15 50 -45 MAX1197 toc14 55 MAX1197 toc13 55 -75 -20 -16 -12 -8 -4 0 -20 -16 -12 -8 -4 INPUT POWER (dB FS) INPUT POWER (dB FS) INPUT POWER (dB FS) SPURIOUS-FREE DYNAMIC RANGE vs. INPUT POWER (fIN = 19.9333995MHz) INTEGRAL NONLINEARITY (262144-POINT DATA RECORD) DIFFERENTIAL NONLINEARITY (262144-POINT DATA RECORD) 0.3 INL (LSB) 65 60 55 50 -20 -16 -12 -8 INPUT POWER (dB FS) -4 0 0.4 0.3 0.2 0.2 0.1 0.1 0 -0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 45 0.5 DNL (LSB) 70 0.4 0 MAX1197 toc18 0.5 MAX1197 toc16 75 MAX1197 toc17 SNR (dB) MAX1197 toc12 80 2 MAX1197 toc11 fIN = 19.9333995MHz SNR/SINAD, THD/SFDR (dB, dBc) 1 MAX1197 toc10 90 8 SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY SNR/SINAD, THD/SFDR vs. TEMPERATURE SFDR (dBc) MAX1197 Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs -0.5 0 32 64 98 128 160 192 224 256 DIGITAL OUTPUT CODE 0 32 64 98 128 160 192 224 256 DIGITAL OUTPUT CODE _______________________________________________________________________________________ Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs OFFSET ERROR (%FS) 0.2 CHA 0.1 CHA -0.7 -0.8 CHB 0 -0.9 -0.1 -15 10 35 60 85 60 40 SNR 20 SINAD 0 -20 -40 THD -60 -80 -40 -15 10 35 0 85 60 20 40 60 80 TEMPERATURE (C) TEMPERATURE (C) SAMPLING SPEED (Msps) ANALOG SUPPLY CURRENT vs. TEMPERATURE DIGITAL SUPPLY CURRENT vs. ANALOG INPUT FREQUENCY SNR/SINAD, THD/SFDR vs. CLOCK DUTY CYCLE 12 IOVDD (mA) 44 42 40 9 6 3 38 -15 10 35 60 0 85 5 10 15 20 25 THD 60 SNR 50 SINAD 40 30 30 40 50 60 70 CLOCK DUTY CYCLE (%) INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 2.036 VREFOUT (V) 2.0319 2.0317 MAX1197 toc26 2.040 MAX1197 toc25 2.0321 SFDR 70 ANALOG INPUT FREQUENCY (MHz) TEMPERATURE (C) VREFOUT (V) fIN = 19.9333995MHz 100 30 0 36 80 SNR/SINAD, THD/SFDR (dB, dBc) 15 MAX1197 toc22 46 -40 fIN = 19.9333995MHz -100 -1.0 -40 IVDD (mA) -0.6 MAX1197 toc23 GAIN ERROR (%FS) 0.3 SFDR 80 MAX1197 toc21 -0.5 CHB 100 SNR/SINAD, THD/SFDR (dB, dBc) 0.4 MAX1197 toc20 -0.4 MAX1197 toc19 0.5 SNR/SINAD, THD/SFDR vs. SAMPLING SPEED OFFSET ERROR vs. TEMPERATURE, EXTERNAL REFERENCE VREFIN = 2.048V MAX1195 toc24 GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE VREFIN = 2.048V 2.032 2.028 2.0315 2.024 2.0313 2.020 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 -40 -15 10 35 60 85 TEMPERATURE (C) _______________________________________________________________________________________ 9 MAX1197 Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 3V, VREFIN = 2.048V, differential input at -1dB FS, fCLK = 40MHz, CL 10pF TA = +25C, unless otherwise noted.) MAX1197 Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs Pin Description PIN NAME 1 COM Common-Mode Voltage I/O. Bypass to GND with a 0.1F capacitor. FUNCTION 2, 6, 11, 14, 15 VDD Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2F in parallel with 0.1F. 3, 7, 10, 13, 16 GND Analog Ground 4 INA+ Channel A Positive Analog Input. For single-ended operation connect signal source to INA+. 5 INA- Channel A Negative Analog Input. For single-ended operation connect INA- to COM. 8 INB- Channel B Negative Analog Input. For single-ended operation connect INB- to COM. 9 INB+ Channel B Positive Analog Input. For single-ended operation connect signal source to INB+. 12 CLK Converter Clock Input 17 T/B T/B Selects the ADC Digital Output Format High: Two's complement Low: Straight offset binary 18 SLEEP 19 PD High-Active Power Down Input High: Power-down mode Low: Normal operation 20 OE Low-Active Output Enable Input High: Digital outputs disabled Low: Digital outputs enabled 21 D7B Three-State Digital Output, Bit 7 (MSB), Channel B 22 D6B Three-State Digital Output, Bit 6, Channel B 23 D5B Three-State Digital Output, Bit 5, Channel B 24 D4B Three-State Digital Output, Bit 4, Channel B 25 D3B Three-State Digital Output, Bit 3, Channel B 26 D2B Three-State Digital Output, Bit 2, Channel B 27 D1B Three-State Digital Output, Bit 1, Channel B 28 D0B Three-State Digital Output, Bit 0, Channel B 29, 30, 35, 36 N.C. No Connect 31, 34 OGND Output Driver Ground 32, 33 OVDD Output Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2F in parallel with 0.1F. 37 D0A Three-State Digital Output, Bit 0, Channel A 38 D1A Three-State Digital Output, Bit 1, Channel A 39 D2A Three-State Digital Output, Bit 2, Channel A 40 D3A Three-State Digital Output, Bit 3, Channel A 41 D4A Three-State Digital Output, Bit 4, Channel A 10 Sleep Mode Input High: Disables both quantizers, but leaves the reference bias circuit active Low: Normal operation ______________________________________________________________________________________ Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs PIN NAME FUNCTION 42 D5A Three-State Digital Output, Bit 5, Channel A 43 D6A Three-State Digital Output, Bit 6, Channel A 44 D7A Three-State Digital Output, Bit 7 (MSB), Channel A 45 REFOUT 46 REFIN Reference Input. VREFIN = 2 x (VREFP - VREFN). Bypass to GND with a > 0.1F capacitor. 47 REFP Positive Reference I/O. Conversion range is (VREFP - VREFN). Bypass to GND with a > 0.1F capacitor. 48 REFN Negative Reference I/O. Conversion range is (VREFP - VREFN). Bypass to GND with a > 0.1F capacitor. Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor divider. 2-BIT FLASH ADC STAGE 1 STAGE 2 STAGE 6 2-BIT FLASH ADC STAGE 7 STAGE 1 DIGITAL ALIGNMENT LOGIC T/H VINA 8 D7A-D0A STAGE 2 STAGE 6 STAGE 7 DIGITAL ALIGNMENT LOGIC T/H VINB 8 D7B-D0B VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED) VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED) Figure 1. Pipelined Architecture--Stage Blocks Detailed Description The MAX1197 uses a seven-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. Including the delay through the output latch, the total clock-cycle latency is five clock cycles. Flash ADCs convert the held input voltages into a digital code. Internal MDACs convert the digitized results back into analog voltages, which are then subtracted from the original held input signals. The resulting error signals are then multiplied by two, and the residues are passed along to the next pipeline stages where the process is repeated until the signals have been processed by all seven stages. Input Track-and-Hold Circuits Figure 2 displays a simplified functional diagram of the input T/H circuits in both track and hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b ______________________________________________________________________________________ 11 MAX1197 Pin Description (continued) MAX1197 Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs INTERNAL BIAS COM S5a S2a C1a S3a S4a INA+ OUT C2a S4c S1 OUT INAS4b C2b C1b S3b S5b S2b INTERNAL BIAS COM HOLD INTERNAL BIAS TRACK COM CLK HOLD TRACK INTERNAL NONOVERLAPPING CLOCK SIGNALS S5a S2a C1a S3a S4a INB+ OUT C2a S4c S1 OUT INBS4b MAX1197 C2b C1b S3b S2b INTERNAL BIAS S5b COM Figure 2. MAX1197 T/H Amplifiers are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the amplifier input, and open simultaneously with S1 sampling the input waveform. Switches S4a, S4b, S5a, and S5b are then opened before switches S3a and S3b connects capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on 12 capacitors C2a and C2b. The amplifiers are used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the MAX1197 to track and sample/hold analog inputs of high frequencies (>Nyquist). Both ADC inputs (INA+, INB+ and INA-, INB-) can be driven either differentially or single-ended. ______________________________________________________________________________________ Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1197 5-CLOCK-CYCLE LATENCY N N+1 N+2 N+3 N+4 N+5 N+6 ANALOG INPUT tAD CLOCK INPUT tCH tDO tCL DATA OUTPUT D7A-D0A N-6 N-5 N-4 N-3 N-2 N-1 N N+1 DATA OUTPUT D7B-D0B N-6 N-5 N-4 N-3 N-2 N-1 N N+1 Figure 3. System Timing Diagram Match the impedance of INA+ and INA-, as well as INB+ and INB-, and set the common-mode voltage to mid-supply (VDD/2) for optimum performance. Analog Inputs and Reference Configurations The full-scale range of the MAX1197 is determined by the internally generated voltage difference between REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The full-scale range for both on-chip ADCs is adjustable through the REFIN pin, which is provided for this purpose. The MAX1197 provides three modes of reference operation: * Internal reference mode * Buffered external reference mode * Unbuffered external reference mode In internal reference mode, connect the internal reference output REFOUT to REFIN through a resistor (e.g., 10k) or resistor divider, if an application requires a reduced full-scale range. For stability and noise-filtering purposes, bypass REFIN with a >10nF capacitor to GND. In internal reference mode, REFOUT, COM, REFP, and REFN become low-impedance outputs. In buffered external reference mode, adjust the reference voltage levels externally by applying a stable and accurate voltage at REFIN. In this mode, COM, REFP, and REFN are outputs. REFOUT can be left open or connected to REFIN through a >10k resistor. In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for REFP, COM, and REFN. With their buffers shut down, these nodes become high-impedance inputs and can be driven through separate, external reference sources. For detailed circuit suggestions and how to drive this dual ADC in buffered/unbuffered external reference mode, see the Applications Information section. Clock Input (CLK) The MAX1197's CLK input accepts a CMOS-compatible clock signal. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the on-chip ADCs as follows: ______________________________________________________________________________________ 13 MAX1197 Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs Table 1. MAX1197 Output Codes For Differential Inputs OE tDISABLE tENABLE OUTPUT D7A-D0A HIGH-Z OUTPUT D7B-D0B HIGH-Z VALID DATA VALID DATA HIGH-Z HIGH-Z VREF x 255/256 +Full Scale -1LSB 1111 1111 0111 1111 VREF x 1/256 +1LSB 1000 0001 0000 0001 Figure 4. Output Timing Diagram SNR = 20 x log 1 2 x x fIN x t AJ where fIN represents the analog input frequency and tAJ is the time of the aperture jitter. Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines. The MAX1197 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50% must meet the specifications for high and low periods as stated in the Electrical Characteristics table. System Timing Requirements Figure 3 depicts the relationship between the clock input, analog input, and data output. The MAX1197 samples at the rising edge of the input clock. Output data for channels A and B is valid on the next rising edge of the input clock. The output data has an internal latency of five clock cycles. Figure 3 also determines the relationship between the input clock parameters and the valid output data on channels A and B. Digital Output Data (D0A/B-D7A/B), Output Data Format Selection (T/B), Output Enable (OE) All digital outputs, D0A-D7A (channel A) and D0B-D7B (channel B), are TTL/CMOS-logic compatible. There is a five-clock-cycle latency between any particular sample and its corresponding output data. The output coding can either be straight offset binary or two's complement (Table 1) controlled by a single pin (T/B). Pull T/B low to select offset binary and high to activate two's complement output coding. The capacitive load on the digital outputs D0A-D7A and D0B-D7B should be kept as low as possible (<15pF), to avoid large digital currents that could feed back into the analog portion of the MAX1197, thereby degrading its dynamic performance. Using 14 STRAIGHT TWO'S OFFSET COMPLEMENT BINARY T/B = 0 T/B = 1 DIFFERENTIAL DIFFERENTIAL INPUT INPUT VOLTAGE* 0 Bipolar zero 1000 0000 0000 0000 -VREF x 1/256 -1LSB 0111 1111 1111 1111 -VREF x 255/256 -Full Scale +1LSB 0000 0001 1000 0001 -VREF x 256/256 -Full Scale 0000 0000 1000 0000 *VREF = VREFP - VREFN buffers on the digital outputs of the ADCs can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1197, small series resistors (e.g., 100) may be added to the digital output paths close to the MAX1197. Figure 4 displays the timing relationship between output enable and data output valid, as well as powerdown/wake-up and data output valid. Power-Down and Sleep Modes The MAX1197 offers two power-save modes--sleep mode (SLEEP) and full power-down (PD) mode. In sleep mode (SLEEP = 1), only the reference bias circuit is active (both ADCs are disabled), and current consumption is reduced to 3mA. To enter full power-down mode, pull PD high. With OE simultaneously low, all outputs are latched at the last value prior to the power down. Pulling OE high forces the digital outputs into a high-impedance state. Applications Information Figure 5 depicts a typical application circuit containing two single-ended-to-differential converters. The internal reference provides a VDD/2 output voltage for levelshifting purposes. The input is buffered and then split to a voltage follower and inverter. One lowpass filter per amplifier suppresses some of the wideband noise associated with high-speed operational amplifiers. The user can select the RISO and CIN values to optimize the filter performance, to suit a particular application. For the application in Figure 5, a RISO of 50 is placed before the capacitive load to prevent ringing and oscil- ______________________________________________________________________________________ Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1197 +5V 0.1F LOWPASS FILTER 300 0.1F INA- MAX4108 RIS0 50 CIN 22pF 0.1F -5V 600 600 300 +5V COM 0.1F +5V 0.1F 600 INPUT 0.1F LOWPASS FILTER MAX4108 300 -5V 0.1F INA+ MAX4108 RIS0 50 300 CIN 22pF 0.1F -5V 300 300 +5V 600 MAX1197 0.1F LOWPASS FILTER 300 0.1F INB- MAX4108 RIS0 50 0.1F -5V +5V CIN 22pF 600 600 300 0.1F +5V 0.1F INPUT 600 0.1F LOWPASS FILTER MAX4108 300 -5V 0.1F INB+ MAX4108 RIS0 50 300 -5V CIN 22pF 0.1F 300 300 600 Figure 5. Typical Application for Single-Ended-to-Differential Conversion ______________________________________________________________________________________ 15 MAX1197 Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs 25 REFP INA+ 22pF VIN 0.1F 1 VIN T1 0.1F 6 1k RISO 50 INA+ MAX4108 N.C. 2 5 3 4 100 COM 2.2F 1k CIN 22pF 0.1F COM REFN MINICIRCUITS TT1-6-KK81 0.1F RISO 50 25 INA- INA- 100 CIN 22pF 22pF MAX1197 REFP 25 MAX1197 INB+ 22pF VIN 0.1F 1k RISO 50 0.1F 1 VIN T1 6 INB+ MAX4108 100 N.C. 2 5 3 4 2.2F 0.1F 1k REFN MINICIRCUITS TT1-6-KK81 25 100 INB22pF 0.1F CIN 22pF RISO 50 INBCIN 22pF Figure 6. Transformer-Coupled Input Drive Figure 7. Using an Op Amp for Single-Ended, AC-Coupled Input Drive lation. The 22pF CIN capacitor acts as a small filter capacitor. balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended mode. Using Transformer Coupling Single-Ended AC-Coupled Input Signal An RF transformer (Figure 6) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1197 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a stepup transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. In general, the MAX1197 provides better SFDR and THD with fully differential input signals than singleended drive, especially for very high input frequencies. In differential input mode, even-order harmonics are lower as both inputs (INA+, INA- and/or INB+, INB-) are Figure 7 shows an AC-coupled, single-ended application. Amplifiers like the MAX4108 provide high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal. 16 Buffered External Reference Drives Multiple ADCs Multiple-converter systems based on the MAX1197 are well suited for use with a common reference voltage. The REFIN pin of those converters can be connected directly to an external reference source. A precision bandgap reference like the MAX6062 generates an external DC level of 2.048V (Figure 8), and exhibits a noise voltage density of 150nV/Hz. Its output passes through a 1-pole lowpass filter (with 10Hz ______________________________________________________________________________________ Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1197 3.3V 3.3V 0.1F 2.048V 0.1F N.C. 31 1 2 16.2k 3 REFIN REFP 1 REFN 2 COM 5 MAX4250 1F 162 1 4 3 REFOUT 32 0.1F MAX6062 29 10Hz LOWPASS FILTER N=1 MAX1197 100F 2 0.1F 0.1F 0.1F 10Hz LOWPASS FILTER NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 1000 ADCs. 0.1F N.C. 29 31 32 0.1F 1 2 2.2F 10V REFOUT REFIN REFP N = 1000 REFN MAX1197 COM 0.1F 0.1F 0.1F Figure 8. External Buffered (MAX4250) Reference Drive Using a MAX6062 Bandgap Reference cutoff frequency) to the MAX4250, which buffers the reference before its output is applied to a second 10Hz lowpass filter. The MAX4250 provides a low offset voltage (for high gain accuracy) and a low noise level. The passive 10Hz filter following the buffer attenuates noise produced in the voltage reference and buffer stages. This filtered noise density, which decreases for higher frequencies, meets the noise levels specified for precision ADC operation. Unbuffered External Reference Drives Multiple ADCs Connecting each REFIN to analog ground disables the internal reference of each device, allowing the internal reference ladders to be driven directly by a set of external reference sources. Followed by a 10Hz lowpass filter and precision voltage divider, the MAX6066 generates a DC level of 2.500V. The buffered outputs of this divider are set to 2.0V, 1.5V, and 1.0V, with an accuracy that depends on the tolerance of the divider resistors. These three voltages are buffered by the MAX4252, which provides low noise and low DC offset. The individual voltage followers are connected to 10Hz lowpass filters, which filter both the reference voltage and amplifier noise to a level of 3nV/Hz. The 2.0V and 1.0V reference voltages set the differential full-scale range of the associated ADCs at 2VP-P. The 2.0V and 1.0V buffers drive the ADC's internal ladder resistances between them. Note that the common power supply for all active components removes any concern regarding power-supply sequencing when powering up or down. With the outputs of the MAX4252 matching better than 0.1%, the buffers and subsequent lowpass filters can be replicated to support as many as 32 ADCs. For applications that require more than 32 matched ADCs, a voltage reference and divider string common to all converters is highly recommended. Typical QAM Demodulation Application A frequently used modulation technique in digital communications applications is quadrature amplitude ______________________________________________________________________________________ 17 MAX1197 Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs 3.3V 0.1F N.C. 29 31 1 2.0V 2 MAX6066 3 4 REFP 1 REFN 2.0V AT 8mA 1/4 MAX4252 1 47k 2 2 3 10F 6V 1.47k 11 21.5k 1.5V REFIN 32 3.3V 21.5k REFOUT N=1 MAX1197 COM 330F 6V 0.1F 0.1F 0.1F 3.3V 5 4 1.5V AT 0mA 1/4 MAX4252 7 47k 6 1F 10F 6V 1.47k 11 21.5k 3.3V 1.0V 0.1F 4 47k 9 11 21.5k 2.2F 10V 1.0V AT -8mA 1/4 MAX4252 8 MAX4254 POWER SUPPLY BYPASSING. PLACE CAPACITOR AS CLOSE AS POSSIBLE TO THE OP AMP. 0.1F 3.3V 10 21.5k 330F 6V 10F 6V 1.47k 330F 6V N.C. 29 31 32 1 2 REFOUT REFIN REFP N = 32 REFN MAX1197 COM 0.1F 0.1F 0.1F NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 32 ADCs. Figure 9. External Unbuffered Reference Drive with MAX4252 and MAX6066 modulation (QAM). Typically found in spread-spectrumbased systems, a QAM signal represents a carrier frequency modulated in both amplitude and phase. At the transmitter, modulating the baseband signal with quadrature outputs, a local oscillator followed by subsequent upconversion can generate the QAM signal. The result is an in-phase (I) and a quadrature (Q) carrier component, where the Q component is 90 phase shifted with respect to the in-phase component. At the receiver, the QAM signal is divided down into its I and Q components, essentially representing the modulation process reversed. Figure 10 displays the demodulation process performed in the analog domain, using the dual matched 3V, 8-bit ADC MAX1197 and the MAX2451 quadrature demodulator to recover and digi18 tize the I and Q baseband signals. Before being digitized by the MAX1197, the mixed-down signal components may be filtered by matched analog filters, such as Nyquist or pulse-shaping filters which remove unwanted images from the mixing process, thereby enhancing the overall signal-to-noise (SNR) performance and minimizing intersymbol interference. Grounding, Bypassing, and Board Layout The MAX1197 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum ______________________________________________________________________________________ Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1197 MAX2451 INA+ INA0 90 MAX1197 DSP POSTPROCESSING INB+ INBDOWNCONVERTER /8 Figure 10. Typical QAM Application Using the MAX1197 from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from the sensitive analog traces of either channel. Make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep all signal lines short and free of 90 turns. CLK ANALOG INPUT tAD Static Parameter Definitions tAJ SAMPLED DATA (T/H) T/H Integral Nonlinearity TRACK HOLD TRACK Figure 11. T/H Aperture Timing inductance. Bypass VDD, REFP, REFN, and COM with two parallel 0.1F ceramic capacitors and a 2.2F bipolar capacitor to GND. Follow the same rules to bypass the digital supply (OVDD) to OGND. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output driver ground (OGND) on the ADC's package. The two ground planes should be joined at a single point so the noisy digital ground currents do not interfere with the analog ground plane. The ideal location for this connection can be determined experimentally at a point along the gap between the two ground planes, which produces optimum results. Make this connection with a low-value, surface-mount resistor (1 to 5), a ferrite bead, or a direct short. Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1197 are measured using the best-straight-line-fit method. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. Dynamic Parameter Definitions Aperture Jitter Figure 11 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Aperture Delay Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 11). Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated ______________________________________________________________________________________ 19 MAX1197 Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs Signal-to-Noise Ratio Total Harmonic Distortion For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N-bits): THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as: 2 THD = 20 x log 2 2 V2 + V3 + V4 + V5 V1 2 SNRdB[max] = 6.02dB N + 1.76dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset. Effective Number of Bits Effective number of bits (ENOB) specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: SINAD -1.76 ENOB = 6.02 20 where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. Intermodulation Distortion The two-tone intermodulation distortion (IMD) is the ratio expressed in decibels of either input tone to the worst third-order (or higher) intermodulation products. The individual input tone levels are at -7dB full scale and their envelope is at -1dB full scale. Chip Information TRANSISTOR COUNT: 11,601 PROCESS: CMOS ______________________________________________________________________________________ Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs VDD OGND OVDD GND INA+ 8 ADC T/H DEC OUTPUT DRIVERS 8 D7A-D0A INA- CONTROL CLK OE INB+ 8 T/H ADC DEC OUTPUT DRIVERS 8 D7B-D0B INB- REFERENCE MAX1197 T/B PD SLEEP REFOUT REFN COM REFP REFIN Pin-Compatible Upgrades (Sampling Speed and Resolution) 8-BIT PART 10-BIT PART MAX1195 MAX1183 SAMPLING SPEED (Msps) 40 MAX1197 MAX1182 60 MAX1198 MAX1180 100 MAX1196* MAX1186 40, multiplexed *Future product, please contact factory for availability. ______________________________________________________________________________________ 21 MAX1197 Functional Diagram Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 48L,TQFP.EPS MAX1197 Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.