General Description
The MAX1197 is a 3V, dual, 8-bit analog-to-digital con-
verter (ADC) featuring fully differential wideband track-
and-hold (T/H) inputs, driving two ADCs. The MAX1197
is optimized for low-power, small size, and high-dynam-
ic performance for applications in imaging, instrumenta-
tion and digital communications. This ADC operates
from a single 2.7V to 3.6V supply, consuming only
120mW while delivering a typical signal-to-noise and
distortion (SINAD) of 48.5dB at an input frequency of
30MHz and a sampling rate of 60Msps. The T/H-driven
input stages incorporate 400MHz (-3dB) input ampli-
fiers. The converters may also be operated with single-
ended inputs. In addition to low operating power, the
MAX1197 features a 3mA sleep mode as well as a
0.1µA power-down mode to conserve power during idle
periods.
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of this internal or an externally
applied reference, if desired, for applications requiring
increased accuracy or a different input voltage range.
The MAX1197 features parallel, CMOS-compatible three-
state outputs. The digital output format can be set to two’s
complement or straight offset binary through a single con-
trol pin. The device provides for a separate output power
supply of 1.7V to 3.6V for flexible interfacing with various
logic families. The MAX1197 is available in a 7mm x 7mm,
48-pin TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Pin-compatible lower and higher speed versions of the
MAX1197 are also available. Refer to the MAX1195 data
sheet for 40Msps and the MAX1198 data sheet for
100Msps. In addition to these speed grades, this family
will include a multiplexed output version (MAX1196,
40Msps), for which digital data is presented time inter-
leaved and on a single, parallel 8-bit output port.
For a 10-bit, pin-compatible upgrade, refer to the
MAX1182 data sheet. With the N.C. pins of the
MAX1197 internally pulled down to ground, this ADC
becomes a drop-in replacement for the MAX1182.
Applications
Features
♦Single 2.7V to 3.6V Operation
♦Excellent Dynamic Performance
48.5dB/45.3dB SINAD at fIN = 30MHz/200MHz
69dBc/53.5dBc SFDR at fIN = 30MHz/200MHz
♦-72dB Interchannel Crosstalk at fIN = 20MHz
♦Low Power
120mW (Normal Operation)
9mW (Sleep Mode)
0.3µW (Shutdown Mode)
♦0.05dB Gain and ±0.05°Phase Matching
♦Wide ±1VP-P Differential Analog Input Voltage
Range
♦400MHz -3dB Input Bandwidth
♦On-Chip 2.048V Precision Bandgap Reference
♦User-Selectable Output Format—Two’s
Complement or Offset Binary
♦Pin-Compatible 8-Bit and 10-Bit Upgrades
Available
MAX1197
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
________________________________________________________________ Maxim Integrated Products 1
N.C.
N.C.
OGND
OVDD
OVDD
OGND
N.C.
N.C.
D0B
D1B
D2B
D3B
COM
VDD
GND
INA+
INA-
VDD
GND
INB-
INB+
GND
VDD
CLK
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
TQFP-EP
GND
VDD
GND
VDD
T/B
SLEEP
PD
OE
D7B
D6B
D5B
D4B
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
REFN
REFP
REFIN
REFOUT
D7A
D6A
D5A
D4A
D3A
D2A
D1A
D0A
MAX1197
Pin Configuration
Ordering Information
19-2411; Rev 0; 4/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Functional Diagram and Pin Compatible Upgrades table
appear at end of data sheet.
*EP = Exposed paddle
Baseband I/Q Sampling
Multichannel IF Sampling
Ultrasound and Medical
Imaging
Battery-Powered
Instrumentation
WLAN, WWAN, WLL,
MMDS Modems
Set-Top Boxes
VSAT Terminals
PART TEMP RANGE PIN-PACKAGE
MAX1197ECM -40°C to +85°C 48 TQFP-EP*
MAX1197
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = OVDD = 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, VIN = 2VP-P (differential with respect to COM), CL= 10pF at digital outputs, fCLK = 60MHz, TA= TMIN to TMAX, unless otherwise
noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, OVDD to GND ...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND ...............................-0.3V to VDD
REFIN, REFOUT, REFP, REFN,
COM, CLK to GND .................................-0.3V to (VDD + 0.3V)
OE, PD, SLEEP, T/B, D7A–D0A,
D7B–D0B to OGND .............................-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
48-Pin TQFP (derate 12.5mW/°C above +70°C).........1000mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN T YP MAX UNITS
DC ACCURACY
Resolution 8 Bits
Integral Nonlinearity INL fIN = 7.5MHz (Note 1) ±0.3 ±1 LSB
Differential Nonlinearity DNL fIN = 7.5MHz, no missing codes guaranteed
(Note 1) ±0.2 ±1 LSB
Offset Error ±4%FS
Gain Error ±4%FS
Gain Temperature Coefficient ±100 ppm/°C
ANALOG INPUT
Differential Input Voltage Range VDIFF Differential or single-ended inputs ±1.0 V
Common-Mode Input Voltage
Range VCM V
D D
/ 2
±0.2 V
Input Resistance RIN Switched capacitor load 95 kΩ
Input Capacitance CIN 5pF
CONVERSION RATE
Maximum Clock Frequency fCLK 60 MHz
Data Latency 5Clock
Cycles
DYNAMIC CHARACTERISTICS (fCLK = 60MHz, 4096-point FFT)
fINA or B = 7.5MHz at -1dB FS 48.7
fINA or B = 20MHz at -1dB FS 47 48.7
fINA or B = 30MHz at -1dB FS 48.6
Signal-to-Noise Ratio SNR
fINA or B = 115.1MHz at -1dB FS 48.3
dB
MAX1197
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = OVDD = 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, VIN = 2VP-P (differential with respect to COM), CL= 10pF at digital outputs, fCLK = 60MHz, TA= TMIN to TMAX, unless otherwise
noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN T YP MAX UNITS
fINA or B = 7.5MHz at -1dB FS 48.6
fINA or B = 20MHz at -1dB FS 46.5 48.6
fINA or B = 30MHz at -1dB FS 48.5
Signal-to-Noise
and Distortion SINAD
fINA or B = 115.1MHz at -1dB FS 48.2
dB
fINA or B = 7.5MHz at -1dB FS 71
fINA or B = 20MHz at -1dB FS 60 69
fINA or B = 30MHz at -1dB FS 69
Spurious-Free
Dynamic Range SFDR
fINA or B = 115.1MHz at -1dB FS 68
dBc
fINA or B = 7.5MHz at -1dB FS - 75
fINA or B = 20MHz at -1dB FS - 72
fINA or B = 30MHz at -1dB FS - 72
Third-Harmonic
Distortion HD3
fINA or B = 115.1MHz at -1dB FS - 68
dBc
Intermodulation Distortion
(First Five Odd-Order IMDs) IMD
fIN1(A or B) = 1.985MHz at -7dB FS
fIN2(A or B) = 2.029MHz at -7dB FS
(Note 2)
- 70 dBc
Third-Order Intermodulation
Distortion IM3
fIN1(A or B) = 1.985MHz at -7dB FS
fIN2(A or B) = 2.029MHz at -7dB FS
(Note 2)
- 71.8 dBc
fINA or B = 7.5MHz at -1dB FS - 69
fINA or B = 20MHz at -1dB FS - 67 - 57
fINA or B = 30MHz at -1dB FS - 67
Total Harmonic Distortion
(First Four Harmonics) THD
fINA or B = 115.1MHz at -1dB FS - 65
dBc
Small-Signal Bandwidth Input at -20dB FS, differential inputs 500 MHz
Full-Power Bandwidth FPBW Input at -1dB FS, differential inputs 400 MHz
Gain Flatness
(12MHz Spacing)
fIN1(A or B) = 106 MHz at -1dB FS
fIN2(A or B) = 118 MHz at -1dB FS
(Note 3)
0.05 dB
Aperture Delay tAD 1ns
Aperture Jitter tAJ 1dB SNR degradation at Nyquist 2 psRMS
Overdrive Recovery Time For 1.5 × full-scale input 2 ns
IN T ER N A L REF ER EN C E ( RE FIN = RE FOU T thr oug h 10kΩ r esi stor ; RE FP , RE FN , and C OM l evel s ar e g ener ated i nter nal l y.)
Reference Output Voltage VREFOUT (Note 4) 2.048
± 3% V
Positive Reference Output
Voltage VREFP (Note 5) 2.012 V
Negative Reference Output
Voltage VREFN (Note 5) 0.988 V
Common-Mode Level VCOM (Note 5) V
D D
/ 2
±0.1 V
MAX1197
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = OVDD = 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, VIN = 2VP-P (differential with respect to COM), CL= 10pF at digital outputs, fCLK = 60MHz, TA= TMIN to TMAX, unless otherwise
noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN T YP MAX UNITS
Differential Reference Output
Voltage Range ∆VREF ∆VREF = VREFP - VREFN 1.024
± 3% V
Reference Temperature
Coefficient TCREF ±100 ppm/°C
BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V)
Positive Reference Output
Voltage VREFP (Note 5) 2.012 V
Negative Reference Output
Voltage VREFN (Note 5) 0.988 V
Common-Mode Level VCOM (Note 5) V
D D
/ 2
± 0.1 V
Differential Reference Output
Voltage Range ∆VREF ∆VREF = VREFP - VREFN 1.024
± 2% V
REFIN Resistance RREFIN 750 MΩ
Maximum REFP, COM Source
Current ISOURCE 5mA
Maximum REFP, COM Sink
Current ISINK - 250 µA
Maximum REFN Source Current ISOURCE 250 µA
Maximum REFN Sink Current ISINK - 5mA
U N B U F F ER ED EXT ER N A L R EF ER EN C E ( V
RE F IN
= AGN D , r efer ence vol tag e ap p l i ed to RE FP , RE FN , and C OM )
REFP, REFN Input Resistance RREFP,
RREFN
Measured between REFP, COM, REFN,
and COM 4kΩ
REFP, REFN, COM Input
Capacitance CIN 15 pF
Differential Reference Input
Voltage Range ∆VREF ∆VREF = VREFP - VREFN 1.024
±10% V
COM Input Voltage Range VCOM V
D D / 2
±5% V
REFP Input Voltage VREFP V
C OM +
∆V
RE F
/ 2 V
REFN Input Voltage VREFN V
C OM -
∆V
RE F
/ 2 V
DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)
CLK 0.8 ×
VDD
Input High Threshold VIH
PD, OE, SLEEP, T/B 0.8 ×
OVDD
V
MAX1197
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(VDD = OVDD = 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, VIN = 2VP-P (differential with respect to COM), CL= 10pF at digital outputs, fCLK = 60MHz, TA= TMIN to TMAX, unless otherwise
noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN T YP MAX UNITS
CLK 0.2 ×
VDD
Input Low Threshold VIL
PD, OE, SLEEP, T/B 0.2 ×
OVDD
V
Input Hysteresis VHYST 0.15 V
IIH VIH = VDD = OVDD ±20
Input Leakage IIL VIL = 0 ±20 µA
Input Capacitance CIN 5pF
DIGITAL OUTPUTS (D7A–D0A, D7B–D0B)
Output Voltage Low VOL ISINK = -200µA 0.2 V
Output Voltage High VOH ISOURCE = 200µAOVDD
- 0.2 V
Three-State Leakage Current ILEAK OE = OVDD ±10 µA
Three-State Output Capacitance COUT OE = OVDD 5pF
POWER REQUIREMENTS
Analog Supply Voltage Range VDD 2.7 3 3.6 V
Output Supply Voltage Range OVDD CL = 15pF 1.7 3 3.6 V
Operating, fINA & B = 20MHz at
-1dB FS applied to both channels 40 50
Sleep mode 3
mA
Analog Supply Current IVDD
Shutdown, clock idle, PD = OE = OVDD 0.1 20 µA
Operating, fINA & B = 20MHz at
-1dB FS applied to both channels (Note 6) 9mA
Sleep mode 3
Output Supply Current IOVDD
Shutdown, clock idle, PD = OE = OVDD 310µA
Operating, fINA & B = 20MHz at
-1dB FS applied to both channels 120 150
Sleep mode 9
mW
Analog Power Dissipation PDISS
Shutdown, clock idle, PD = OE = OVDD 0.3 60 µW
Offset, VDD ±5% ±3
Power-Supply
Rejection PSRR Gain, VDD ±5% ±3mV/V
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Time tDO CL = 20pF (Notes 1, 7) 6 9 ns
OE Fall to Output Enable Time tENABLE 5ns
OE Rise to Output Disable Time tDISABLE 5ns
CLK Pulse Width High tCH Clock period: 16.67ns (Note 7) 8.33 ± 1.5 ns
CLK Pulse Width Low tCL Clock period: 16.67ns (Note 7) 8.33 ± 1.5 ns
MAX1197
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = OVDD = 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, VIN = 2VP-P (differential with respect to COM), CL= 10pF at digital outputs, fCLK = 60MHz, TA= TMIN to TMAX, unless otherwise
noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)
Note 1: Guaranteed by design. Not subject to production testing.
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the total input power.
Note 3: Analog attenuation is defined as the amount of attenuation of the fundamental bin from a converted FFT between two
applied input signals with the same magnitude (peak-to-peak) at fIN1 and fIN2.
Note 4: REFIN and REFOUT should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor.
Note 5: REFP, REFN, and COM should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor.
Note 6: Typical analog output current at fINA&B = 20MHz. For digital output currents vs. analog input frequency,
see Typical Operating Characteristics.
Note 7: See Figure 3 for detailed system timing diagrams. Clock to data valid timing is measured from 50% of the clock
level to 50% of the data output level.
Note 8: Crosstalk rejection is tested by applying a test tone to one channel and holding the other channel at DC level.
Crosstalk is measured by calculating the power ratio of the fundamental of each channel’s FFT.
Note 9: Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-
mental of the calculated FFT.
Note 10: Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental
of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
Note 11: SINAD settles to within 0.5dB of its typical value in unbuffered external reference mode.
PARAMETER SYMBOL CONDITIONS MIN T YP MAX UNITS
Wake up from sleep mode 1
Wake-Up Time tWAKE Wake up from shutdown mode (Note 11) 20 µs
CHANNEL-TO-CHANNEL MATCHING
Crosstalk fINA or B = 20MHz at -1dB FS (Note 8) - 72 dB
Gain Matching fINA or B = 20MHz at -1dB FS (Note 9) 0.05 dB
Phase Matching fINA or B = 20MHz at -1dB FS (Note 10) ± 0.05 Degrees
MAX1197
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
_______________________________________________________________________________________ 7
Typical Operating Characteristics
(VDD = 3V, OVDD = 3V, VREFIN = 2.048V, differential input at -1dB FS, fCLK = 40MHz, CL≈10pF TA= +25°C, unless otherwise
noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
MAX1197 toc09
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBc)
1601208040
50
60
70
80
90
40
0 200
CHA
CHB
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
MAX1197 toc08
ANALOG INPUT FREQUENCY (MHz)
THD (dBc)
1601208040
-80
-70
-60
-50
-40
-90
0 200
CHA
CHB
SIGNAL-TO-NOISE + DISTORTION
vs. ANALOG INPUT FREQUENCY
MAX1197 toc07
ANALOG INPUT FREQUENCY (MHz)
SINAD (dB)
1601208040
46
47
48
49
50
45
0 200
CHA
CHB
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
MAX1197 toc06
ANALOG INPUT FREQUENCY (MHz)
SNR (dB)
1601208040
46
47
48
49
50
45
0 200
CHA
CHB
TWO-TONE IMD PLOT (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1197 toc05
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
1412 138 9 10 117
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
6
fIN1 fIN2
fCLK = 60.00640MHz
fIN1 = 9.969325MHz
fIN2 = 10.013275MHz
AIN = -7dB FS
COHERENT SAMPLING
TWO-TONE IMD PLOT (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1197 toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
4.54.03.0 3.51.0 1.5 2.0 2.50.5
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
05.0
fIN1 fIN2
fCLK = 60.00640MHz
fIN1 = 1.985075MHz
fIN2 = 2.029025MHz
AIN = -7dB FS
COHERENT SAMPLING
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1197 toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
255101520030
fCLK = 60.056789MHz
fINA = 114.974441MHz
fINB = 99.945816MHz
AIN = -1dB FS
COHERENT SAMPLING
fINA
HD2 HD3 fINB
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1197 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
255101520
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
030
fINA
HD2 HD3
fINB
fCLK = 60.056789MHz
fINA = 29.859778MHz
fINB = 19.9333995MHz
AIN = -1dB FS
COHERENT SAMPLING
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1197 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
fINA
HD2
252015105030
fCLK = 60.056789MHz
fINA = 7.4851051MHz
fINB = 19.9333995MHz
AIN = -1dB FS
COHERENT SAMPLING
fINB
HD3
MAX1197
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 3V, VREFIN = 2.048V, differential input at -1dB FS, fCLK = 40MHz, CL≈10pF TA= +25°C, unless otherwise
noted.)
DIFFERENTIAL NONLINEARITY
(262144-POINT DATA RECORD)
MAX1197 toc18
DIGITAL OUTPUT CODE
DNL (LSB)
224192128 16064 9832
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
0 256
INTEGRAL NONLINEARITY
(262144-POINT DATA RECORD)
MAX1197 toc17
DIGITAL OUTPUT CODE
INL (LSB)
224192128 16064 9832
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
0 256
SPURIOUS-FREE DYNAMIC RANGE
vs. INPUT POWER (fIN = 19.9333995MHz)
MAX1197 toc16
INPUT POWER (dB FS)
SFDR (dBc)
-4-8-12-16
50
55
60
65
70
75
45
-20 0
TOTAL HARMONIC DISTORTION
vs. INPUT POWER (fIN = 19.9333995MHz)
MAX1197 toc15
INPUT POWER (dB FS)
THD (dBc)
-4-8-12-16
-70
-65
-60
-55
-50
-45
-75
-20 0
SIGNAL-TO-NOISE + DISTORTION
vs. INPUT POWER (fIN = 19.9333995MHz)
MAX1197 toc14
INPUT POWER (dB FS)
SINAD (dB)
-4-8-12-16
30
35
40
45
50
55
25
-20 0
SIGNAL-TO-NOISE RATIO vs. INPUT POWER
(fIN = 19.9333995MHz)
MAX1197 toc13
INPUT POWER (dB FS)
SNR (dB)
-4-8-12-16
30
35
40
45
50
55
25
-20 0
SMALL-SIGNAL INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY
MAX1197 toc12
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
10010
-3
-2
-1
0
1
2
-4
1 1000
VIN = 100mVP-P
FULL-POWER INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY
MAX1197 toc11
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
10010
-4
-3
-2
-1
0
1
-5
1 1000
SNR/SINAD, THD/SFDR
vs. TEMPERATURE
MAX1197 toc10
TEMPERATURE (°C)
SNR/SINAD, THD/SFDR (dB, dBc)
603510-15
50
40
60
70
80
90
30
-40 85
THD
SFDR
SNR
SINAD
fIN = 19.9333995MHz
MAX1197
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
_______________________________________________________________________________________ 9
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 3V, VREFIN = 2.048V, differential input at -1dB FS, fCLK = 40MHz, CL≈10pF TA= +25°C, unless otherwise
noted.)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1197 toc26
TEMPERATURE (°C)
VREFOUT (V)
603510-15
2.024
2.028
2.032
2.036
2.040
2.020
-40 85
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX1197 toc25
VDD (V)
VREFOUT (V)
3.453.303.153.002.85
2.0315
2.0317
2.0319
2.0321
2.0313
2.70 3.60
SNR/SINAD, THD/SFDR
vs. CLOCK DUTY CYCLE
MAX1195 toc24
CLOCK DUTY CYCLE (%)
SNR/SINAD, THD/SFDR (dB, dBc)
605040
40
50
60
70
80
30
30 70
SNR
SINAD
THD
SFDR
fIN = 19.9333995MHz
DIGITAL SUPPLY CURRENT
vs. ANALOG INPUT FREQUENCY
MAX1197 toc23
ANALOG INPUT FREQUENCY (MHz)
IOVDD (mA)
2015105
3
6
9
12
15
0
025
30
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
MAX1197 toc22
TEMPERATURE (°C)
IVDD (mA)
6035-15 10
38
40
42
44
46
36
-40 85
SNR/SINAD, THD/SFDR
vs. SAMPLING SPEED
MAX1197 toc21
SAMPLING SPEED (Msps)
SNR/SINAD, THD/SFDR (dB, dBc)
80604020
-80
-60
-40
-20
0
20
40
60
80
100
-100
0 100
SNR SINAD
THD
fIN = 19.9333995MHz
SFDR
MAX1197 toc20
TEMPERATURE (°C)
OFFSET ERROR (%FS)
603510-15
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-1.0
-40 85
OFFSET ERROR vs. TEMPERATURE, EXTERNAL
REFERENCE VREFIN = 2.048V
CHA
CHB
GAIN ERROR vs. TEMPERATURE, EXTERNAL
REFERENCE VREFIN = 2.048V
MAX1197 toc19
TEMPERATURE (°C)
GAIN ERROR (%FS)
603510-15
0
0.1
0.2
0.3
0.4
0.5
-0.1
-40 85
CHB
CHA
MAX1197
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
10 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 COM Common-Mode Voltage I/O. Bypass to GND with a ≥ 0.1µF capacitor.
2, 6, 11, 14, 15 VDD Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with
0.1µF.
3, 7, 10, 13, 16 GND Analog Ground
4 INA+ Channel A Positive Analog Input. For single-ended operation connect signal source to INA+.
5 INA- Channel A Negative Analog Input. For single-ended operation connect INA- to COM.
8 INB- Channel B Negative Analog Input. For single-ended operation connect INB- to COM.
9 INB+ Channel B Positive Analog Input. For single-ended operation connect signal source to INB+.
12 CLK Converter Clock Input
17 T/B
T/B Selects the ADC Digital Output Format
High: Two’s complement
Low: Straight offset binary
18 SLEEP
Sleep Mode Input
High: Disables both quantizers, but leaves the reference bias circuit active
Low: Normal operation
19 PD
High-Active Power Down Input
High: Power-down mode
Low: Normal operation
20 OE
Low-Active Output Enable Input
High: Digital outputs disabled
Low: Digital outputs enabled
21 D7B Three-State Digital Output, Bit 7 (MSB), Channel B
22 D6B Three-State Digital Output, Bit 6, Channel B
23 D5B Three-State Digital Output, Bit 5, Channel B
24 D4B Three-State Digital Output, Bit 4, Channel B
25 D3B Three-State Digital Output, Bit 3, Channel B
26 D2B Three-State Digital Output, Bit 2, Channel B
27 D1B Three-State Digital Output, Bit 1, Channel B
28 D0B Three-State Digital Output, Bit 0, Channel B
29, 30, 35, 36 N.C. No Connect
31, 34 OGND Output Driver Ground
32, 33 OVDD Output Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2µF in parallel
with 0.1µF.
37 D0A Three-State Digital Output, Bit 0, Channel A
38 D1A Three-State Digital Output, Bit 1, Channel A
39 D2A Three-State Digital Output, Bit 2, Channel A
40 D3A Three-State Digital Output, Bit 3, Channel A
41 D4A Three-State Digital Output, Bit 4, Channel A
Detailed Description
The MAX1197 uses a seven-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is five clock cycles.
Flash ADCs convert the held input voltages into a digi-
tal code. Internal MDACs convert the digitized results
back into analog voltages, which are then subtracted
from the original held input signals. The resulting error
signals are then multiplied by two, and the residues are
passed along to the next pipeline stages where the
process is repeated until the signals have been
processed by all seven stages.
Input Track-and-Hold Circuits
Figure 2 displays a simplified functional diagram of the
input T/H circuits in both track and hold mode. In track
mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b
MAX1197
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
______________________________________________________________________________________ 11
Pin Description (continued)
PIN NAME FUNCTION
42 D5A Three-State Digital Output, Bit 5, Channel A
43 D6A Three-State Digital Output, Bit 6, Channel A
44 D7A Three-State Digital Output, Bit 7 (MSB), Channel A
45 REFOUT Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor
divider.
46 REFIN Reference Input. VREFIN = 2 x (VREFP – VREFN).
Bypass to GND with a > 0.1µF capacitor.
47 REFP Positive Reference I/O. Conversion range is ±(VREFP – VREFN).
Bypass to GND with a > 0.1µF capacitor.
48 REFN Negative Reference I/O. Conversion range is ±(VREFP – VREFN).
Bypass to GND with a > 0.1µF capacitor.
8
VINA
STAGE 1 STAGE 2
D7A–D0A
VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED)
VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED)
DIGITAL ALIGNMENT LOGIC
STAGE 6 STAGE 7
2-BIT FLASH
ADC
T/H 8
VINB
STAGE 1 STAGE 2
D7B–D0B
DIGITAL ALIGNMENT LOGIC
STAGE 6 STAGE 7
2-BIT FLASH
ADC
T/H
Figure 1. Pipelined Architecture—Stage Blocks
MAX1197
are closed. The fully differential circuits sample the
input signals onto the two capacitors (C2a and C2b)
through switches S4a and S4b. S2a and S2b set the
common mode for the amplifier input, and open simul-
taneously with S1 sampling the input waveform.
Switches S4a, S4b, S5a, and S5b are then opened
before switches S3a and S3b connects capacitors C1a
and C1b to the output of the amplifier and switch S4c is
closed. The resulting differential voltages are held on
capacitors C2a and C2b. The amplifiers are used to
charge capacitors C1a and C1b to the same values
originally held on C2a and C2b. These values are then
presented to the first-stage quantizers and isolate the
pipelines from the fast-changing inputs. The wide input
bandwidth T/H amplifiers allow the MAX1197 to track
and sample/hold analog inputs of high frequencies
(>Nyquist). Both ADC inputs (INA+, INB+ and INA-,
INB-) can be driven either differentially or single-ended.
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
12 ______________________________________________________________________________________
S3b
S3a
COM
S5b
S5a
INB+
INB-
S1
OUT
OUT
C2a
C2b
S4c
S4a
S4b
C1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
HOLD HOLD CLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
TRACK TRACK
S2a
S2b
S3b
S3a
COM
S5b
S5a
INA+
INA-
S1
OUT
OUT
C2a
C2b
S4c
S4a
S4b
C1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
S2a
S2b
MAX1197
Figure 2. MAX1197 T/H Amplifiers
Match the impedance of INA+ and INA-, as well as
INB+ and INB-, and set the common-mode voltage to
mid-supply (VDD/2) for optimum performance.
Analog Inputs and Reference
Configurations
The full-scale range of the MAX1197 is determined by
the internally generated voltage difference between
REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4).
The full-scale range for both on-chip ADCs is
adjustable through the REFIN pin, which is provided for
this purpose.
The MAX1197 provides three modes of reference oper-
ation:
•Internal reference mode
•Buffered external reference mode
•Unbuffered external reference mode
In internal reference mode, connect the internal refer-
ence output REFOUT to REFIN through a resistor (e.g.,
10kΩ) or resistor divider, if an application requires a
reduced full-scale range. For stability and noise-filtering
purposes, bypass REFIN with a >10nF capacitor to
GND. In internal reference mode, REFOUT, COM,
REFP, and REFN become low-impedance outputs.
In buffered external reference mode, adjust the refer-
ence voltage levels externally by applying a stable and
accurate voltage at REFIN. In this mode, COM, REFP,
and REFN are outputs. REFOUT can be left open or
connected to REFIN through a >10kΩresistor.
In unbuffered external reference mode, connect REFIN
to GND. This deactivates the on-chip reference buffers
for REFP, COM, and REFN. With their buffers shut
down, these nodes become high-impedance inputs
and can be driven through separate, external reference
sources.
For detailed circuit suggestions and how to drive this
dual ADC in buffered/unbuffered external reference
mode, see the Applications Information section.
Clock Input (CLK)
The MAX1197’s CLK input accepts a CMOS-compati-
ble clock signal. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). In particular,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide lowest possible jitter. Any
significant aperture jitter would limit the SNR perfor-
mance of the on-chip ADCs as follows:
MAX1197
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
______________________________________________________________________________________ 13
N - 6
N
N - 5
N + 1
N - 4
N + 2
N - 3
N + 3
N - 2
N + 4
N - 1
N + 5
N
N + 6
N + 1
5-CLOCK-CYCLE LATENCY
ANALOG INPUT
CLOCK INPUT
DATA OUTPUT
D7A–D0A
tDO tCH tCL
N - 6 N - 5 N - 4 N - 3 N - 2 N - 1 N N + 1
DATA OUTPUT
D7B–D0B
tAD
Figure 3. System Timing Diagram
MAX1197
where fIN represents the analog input frequency and
tAJ is the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log input or other digital signal lines.
The MAX1197 clock input operates with a voltage thresh-
old set to VDD/2. Clock inputs with a duty cycle other
than 50% must meet the specifications for high and low
periods as stated in the Electrical Characteristics table.
System Timing Requirements
Figure 3 depicts the relationship between the clock
input, analog input, and data output. The MAX1197
samples at the rising edge of the input clock. Output
data for channels A and B is valid on the next rising
edge of the input clock. The output data has an internal
latency of five clock cycles. Figure 3 also determines
the relationship between the input clock parameters
and the valid output data on channels A and B.
Digital Output Data (D0A/B–D7A/B), Output
Data Format Selection (T/B), Output
Enable (OE)
All digital outputs, D0A–D7A (channel A) and D0B–D7B
(channel B), are TTL/CMOS-logic compatible. There is a
five-clock-cycle latency between any particular sample
and its corresponding output data. The output coding
can either be straight offset binary or two’s complement
(Table 1) controlled by a single pin (T/B). Pull T/B low to
select offset binary and high to activate two’s comple-
ment output coding. The capacitive load on the digital
outputs D0A–D7A and D0B–D7B should be kept as low
as possible (<15pF), to avoid large digital currents that
could feed back into the analog portion of the MAX1197,
thereby degrading its dynamic performance. Using
buffers on the digital outputs of the ADCs can further
isolate the digital outputs from heavy capacitive loads.
To further improve the dynamic performance of the
MAX1197, small series resistors (e.g., 100Ω) may be
added to the digital output paths close to the MAX1197.
Figure 4 displays the timing relationship between out-
put enable and data output valid, as well as power-
down/wake-up and data output valid.
Power-Down and Sleep Modes
The MAX1197 offers two power-save modes—sleep
mode (SLEEP) and full power-down (PD) mode. In
sleep mode (SLEEP = 1), only the reference bias circuit
is active (both ADCs are disabled), and current con-
sumption is reduced to 3mA.
To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
value prior to the power down. Pulling OE high forces
the digital outputs into a high-impedance state.
Applications Information
Figure 5 depicts a typical application circuit containing
two single-ended-to-differential converters. The internal
reference provides a VDD/2 output voltage for level-
shifting purposes. The input is buffered and then split
to a voltage follower and inverter. One lowpass filter per
amplifier suppresses some of the wideband noise
associated with high-speed operational amplifiers. The
user can select the RISO and CIN values to optimize the
filter performance, to suit a particular application. For
the application in Figure 5, a RISO of 50Ωis placed
before the capacitive load to prevent ringing and oscil-
SNR ft
IN AJ
log=× ×× ×
20 1
2π
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
14 ______________________________________________________________________________________
OUTPUT
D7A–D0A
OE
tDISABLE
tENABLE
HIGH-ZHIGH-Z VALID DATA
OUTPUT
D7B–D0B
HIGH-ZHIGH-Z VALID DATA
Figure 4. Output Timing Diagram
ST RA IG HT
O F FSET
B INA R Y
T WO’S
C O M PL EM EN T
D IFF ER EN T IAL
IN PU T
VO LT A G E*
D IFF ER EN T IAL
IN PU T
T/B = 0 T/B = 1
VREF x 255/256 +Full Scale
-1LSB 1111 1111 0111 1111
VREF x 1/256 +1LSB 1000 0001 0000 0001
0 Bipolar zero 1000 0000 0000 0000
-VREF x 1/256 -1LSB 0111 1111 1111 1111
-VREF x 255/256 -Full Scale
+1LSB 0000 0001 1000 0001
-VREF x 256/256 -Full Scale 0000 0000 1000 0000
Table 1. MAX1197 Output Codes For
Differential Inputs
*VREF = VREFP - VREFN
MAX1197
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
______________________________________________________________________________________ 15
INPUT
300Ω
-5V
+5V
0.1µF
0.1µF
0.1µF
-5V
600Ω
300Ω
INA-
INA+
LOWPASS FILTER
COM
600Ω
+5V
-5V
0.1µF
600Ω
300Ω
300Ω
600Ω
300Ω
0.1µF
0.1µF
0.1µF
+5V
0.1µF
300Ω
MAX4108
MAX1197
INB-
INB+
MAX4108
MAX4108
LOWPASS FILTER
INPUT
300Ω
-5V
+5V
0.1µF
0.1µF
0.1µF
CIN
22pF
-5V
600Ω
300Ω
LOWPASS FILTER
600Ω
+5V
-5V
0.1µF
600Ω
300Ω
600Ω
300Ω
0.1µF
0.1µF
0.1µF
+5V
0.1µF
300Ω
MAX4108
MAX4108
MAX4108
LOWPASS FILTER
RIS0
50ΩCIN
22pF
RIS0
50ΩCIN
22pF
RIS0
50ΩCIN
22pF
RIS0
50Ω
300Ω
Figure 5. Typical Application for Single-Ended-to-Differential Conversion
MAX1197
lation. The 22pF CIN capacitor acts as a small filter
capacitor.
Using Transformer Coupling
An RF transformer (Figure 6) provides an excellent
solution to convert a single-ended source signal to a
fully differential signal, required by the MAX1197 for
optimum performance. Connecting the center tap of the
transformer to COM provides a VDD/2 DC level shift to
the input. Although a 1:1 transformer is shown, a step-
up transformer can be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, can also improve the overall
distortion.
In general, the MAX1197 provides better SFDR and
THD with fully differential input signals than single-
ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower as both inputs (INA+, INA- and/or INB+, INB-) are
balanced, and each of the ADC inputs only requires
half the signal swing compared to single-ended mode.
Single-Ended AC-Coupled Input Signal
Figure 7 shows an AC-coupled, single-ended applica-
tion. Amplifiers like the MAX4108 provide high speed,
high bandwidth, low noise, and low distortion to main-
tain the integrity of the input signal.
Buffered External Reference Drives
Multiple ADCs
Multiple-converter systems based on the MAX1197 are
well suited for use with a common reference voltage.
The REFIN pin of those converters can be connected
directly to an external reference source.
A precision bandgap reference like the MAX6062 gen-
erates an external DC level of 2.048V (Figure 8), and
exhibits a noise voltage density of 150nV/√Hz. Its out-
put passes through a 1-pole lowpass filter (with 10Hz
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
16 ______________________________________________________________________________________
Figure 7. Using an Op Amp for Single-Ended, AC-Coupled
Input Drive
MAX1197
T1
N.C.
VIN 6
1
5
2
43
22pF
22pF
0.1µF
0.1µF
2.2µF
25Ω
25Ω
MINICIRCUITS
TT1–6-KK81
T1
N.C.
VIN 6
1
5
2
4
3
22pF
22pF
0.1µF
0.1µF
2.2µF
25Ω
25Ω
MINICIRCUITS
TT1–6-KK81
INA-
INA+
INB-
INB+
COM
Figure 6. Transformer-Coupled Input Drive
MAX1197
0.1µF
1kΩ
1kΩ
100Ω
100Ω
CIN
22pF
CIN
22pF
INB+
INB-
COM
INA+
INA-
0.1µFRISO
50Ω
RISO
50Ω
REFP
REFN
VIN
MAX4108
0.1µF
1kΩ
1kΩ
100Ω
100Ω
CIN
22pF
CIN
22pF
0.1µFRISO
50Ω
RISO
50Ω
REFP
REFN
VIN
MAX4108
MAX1197
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
______________________________________________________________________________________ 17
cutoff frequency) to the MAX4250, which buffers the
reference before its output is applied to a second 10Hz
lowpass filter. The MAX4250 provides a low offset volt-
age (for high gain accuracy) and a low noise level. The
passive 10Hz filter following the buffer attenuates noise
produced in the voltage reference and buffer stages.
This filtered noise density, which decreases for higher
frequencies, meets the noise levels specified for preci-
sion ADC operation.
Unbuffered External Reference Drives
Multiple ADCs
Connecting each REFIN to analog ground disables the
internal reference of each device, allowing the internal
reference ladders to be driven directly by a set of
external reference sources. Followed by a 10Hz low-
pass filter and precision voltage divider, the MAX6066
generates a DC level of 2.500V. The buffered outputs
of this divider are set to 2.0V, 1.5V, and 1.0V, with an
accuracy that depends on the tolerance of the divider
resistors. These three voltages are buffered by the
MAX4252, which provides low noise and low DC offset.
The individual voltage followers are connected to 10Hz
lowpass filters, which filter both the reference voltage
and amplifier noise to a level of 3nV/√Hz. The 2.0V and
1.0V reference voltages set the differential full-scale
range of the associated ADCs at 2VP-P. The 2.0V and
1.0V buffers drive the ADC’s internal ladder resistances
between them.
Note that the common power supply for all active com-
ponents removes any concern regarding power-supply
sequencing when powering up or down. With the out-
puts of the MAX4252 matching better than 0.1%, the
buffers and subsequent lowpass filters can be replicat-
ed to support as many as 32 ADCs. For applications
that require more than 32 matched ADCs, a voltage
reference and divider string common to all converters
is highly recommended.
Typical QAM Demodulation Application
A frequently used modulation technique in digital com-
munications applications is quadrature amplitude
MAX4250
MAX6062
16.2kΩ
162Ω
3.3V
2
4
235
10Hz LOWPASS
FILTER
10Hz LOWPASS
FILTER
1
1
REFOUT
REFP
REFIN
1µFMAX1197
N = 1
REFN
29N.C.
2.048V
N.C.
31
32
1
2
29
31
32
1
2
COM
REFOUT
NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 1000 ADCs.
REFP
REFIN
MAX1197
N = 1000
REFN
COM
3
0.1µF
0.1µF
3.3V
0.1µF0.1µF0.1µF
0.1µF
0.1µF2.2µF
10V
0.1µF0.1µF
0.1µF
100µF
0.1µF
Figure 8. External Buffered (MAX4250) Reference Drive Using a MAX6062 Bandgap Reference
MAX1197
modulation (QAM). Typically found in spread-spectrum-
based systems, a QAM signal represents a carrier fre-
quency modulated in both amplitude and phase. At the
transmitter, modulating the baseband signal with quad-
rature outputs, a local oscillator followed by subse-
quent upconversion can generate the QAM signal. The
result is an in-phase (I) and a quadrature (Q) carrier
component, where the Q component is 90°phase shift-
ed with respect to the in-phase component. At the
receiver, the QAM signal is divided down into its I and
Q components, essentially representing the modulation
process reversed. Figure 10 displays the demodulation
process performed in the analog domain, using the
dual matched 3V, 8-bit ADC MAX1197 and the
MAX2451 quadrature demodulator to recover and digi-
tize the I and Q baseband signals. Before being digi-
tized by the MAX1197, the mixed-down signal compo-
nents may be filtered by matched analog filters, such
as Nyquist or pulse-shaping filters which remove
unwanted images from the mixing process, thereby
enhancing the overall signal-to-noise (SNR) perfor-
mance and minimizing intersymbol interference.
Grounding, Bypassing,
and Board Layout
The MAX1197 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface-mount devices for minimum
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
18 ______________________________________________________________________________________
1/4 MAX4252
MAX6066
1/4 MAX4252
1/4 MAX4252
1.47kΩ
21.5kΩ
21.5kΩ
21.5kΩ
21.5kΩ
21.5kΩ
47kΩ
3.3V
3.3V
11
2
234
1
1
REFOUT
REFP
REFIN
1µF
10µF
6V
MAX1197
N = 1
REFN
29N.C.
N.C.
31
32
1
2
29
31
32
1
2
COM
REFOUT
NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 32 ADCs.
REFP
REFIN
MAX1197
N = 32
REFN
COM
2.0V AT 8mA
3
0.1µF
0.1µF
MAX4254 POWER SUPPLY
BYPASSING. PLACE CAPACITOR
AS CLOSE AS POSSIBLE TO
THE OP AMP.
3.3V
1.47kΩ
47kΩ
3.3V
1.5V
11
6
54
7
10µF
6V
1.5V AT 0mA
1.47kΩ
47kΩ
3.3V
11
9
10 4
8
10µF
6V
0.1µF0.1µF0.1µF
0.1µF
0.1µF2.2µF
10V
0.1µF0.1µF
1.0V AT -8mA
330µF
6V
330µF
6V
330µF
6V
2.0V
1.0V
Figure 9. External Unbuffered Reference Drive with MAX4252 and MAX6066
inductance. Bypass VDD, REFP, REFN, and COM with
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OVDD) to OGND. Multilayer
boards with separated ground and power planes pro-
duce the highest level of signal integrity. Consider the
use of a split ground plane arranged to match the
physical location of the analog ground (GND) and the
digital output driver ground (OGND) on the ADC’s
package. The two ground planes should be joined at a
single point so the noisy digital ground currents do not
interfere with the analog ground plane. The ideal loca-
tion for this connection can be determined experimen-
tally at a point along the gap between the two ground
planes, which produces optimum results. Make this
connection with a low-value, surface-mount resistor (1Ω
to 5Ω), a ferrite bead, or a direct short.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy, digital systems ground plane (e.g.,
downstream output buffer or DSP ground plane). Route
high-speed digital signal traces away from the sensitive
analog traces of either channel. Make sure to isolate
the analog input lines to each respective converter to
minimize channel-to-channel crosstalk. Keep all signal
lines short and free of 90°turns.
Static Parameter Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1197 are mea-
sured using the best-straight-line-fit method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
Dynamic Parameter Definitions
Aperture Jitter
Figure 11 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 11).
MAX1197
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
______________________________________________________________________________________ 19
0°
90°
÷8
DOWNCONVERTER
MAX2451 INA+
MAX1197
INA-
INB+
INB-
DSP
POST-
PROCESSING
Figure 10. Typical QAM Application Using the MAX1197
HOLD
ANALOG
INPUT
SAMPLED
DATA (T/H)
T/H
tAD
tAJ
TRACK TRACK
CLK
Figure 11. T/H Aperture Timing
MAX1197
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
20 ______________________________________________________________________________________
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N-bits):
SNRdB[max] = 6.02dB ✕N + 1.76dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components minus the fundamental
and the DC offset.
Effective Number of Bits
Effective number of bits (ENOB) specifies the dynamic
performance of an ADC at a specific input frequency
and sampling rate. An ideal ADC’s error consists of
quantization noise only. ENOB for a full-scale sinusoidal
input waveform is computed from:
Total Harmonic Distortion
THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:
where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio
expressed in decibels of the RMS amplitude of the fun-
damental (maximum signal component) to the RMS
value of the next largest spurious component, exclud-
ing DC offset.
Intermodulation Distortion
The two-tone intermodulation distortion (IMD) is the
ratio expressed in decibels of either input tone to the
worst third-order (or higher) intermodulation products.
The individual input tone levels are at -7dB full scale
and their envelope is at -1dB full scale.
THD VVVV
V
log=× +++
20 22324252
1
ENOB SINAD
.
.
=−176
602
Chip Information
TRANSISTOR COUNT: 11,601
PROCESS: CMOS
MAX1197
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
______________________________________________________________________________________ 21
Pin-Compatible Upgrades
(Sampling Speed and Resolution)
Functional Diagram
GND
REFERENCE
OUTPUT
DRIVERS
CONTROL
T/H
T/H ADC DEC OUTPUT
DRIVERS
REFOUT
REFN COM REFP REFIN
INA+
INA-
CLK
INB+
INB-
VDD
DEC
ADC
OGND
OVDD
D7A–D0A
OE
D7B–D0B
T/B
PD
SLEEP
MAX1197
8
88
8
8-BIT PART 10-BIT PART SAMPLING SPEED (Msps)
MAX1195 MAX1183 40
MAX1197 MAX1182 60
MAX1198 MAX1180 100
MAX1196* MAX1186 40, multiplexed
*Future product, please contact factory for availability.
MAX1197
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
48L,TQFP.EPS
