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User’s Manual U16580EE3V1UD00
Figure 16-16: Continuous Mode (Slave Mode, Transmission/Reception Mode) ............................. 662
Figure 16-17: Continuous Mode (Slave Mode, Reception Mode).................................................... 663
Figure 16-18: CSIBn Clock Timing (1/2).......................................................................................... 664
Figure 16-19: Operation Flow of Single Transmission..................................................................... 667
Figure 16-20: Operation Flow of Single Reception (Master)............................................................ 668
Figure 16-21: Operation Flow of Single Reception (Slave) ............................................................. 669
Figure 16-22: Operation Flow of Continuous Transmission............................................................. 670
Figure 16-23: Operation Flow of Continuous Reception (Master) ................................................... 671
Figure 16-24: Operation Flow of Continuous Reception (Slave) ..................................................... 672
Figure 16-25: Block Diagram of Baud Rate Generators 0 and 1 (BRG0, BRG1) ............................ 673
Figure 16-26: Block Diagram of CSIBn Baud Rate Generators....................................................... 673
Figure 16-27: Prescaler Mode Registers 0 and 1 (PRSM0, PRSM1) ............................................ 674
Figure 16-28: Prescaler Compare Registers 0 and 1 (PRSCM0, PRSCM1) ................................. 675
Figure 17-1: Block Diagram of Clocked Serial Interface 3n (CSI3n).............................................. 679
Figure 17-2: Clocked Serial Interface Mode Register 3n (CSIM3n) (1/2) .................................... 680
Figure 17-3: Clocked Serial Interface Clock Select Register 3n (CSIC3n) (1/3) .......................... 682
Figure 17-4: Receive Data Buffer Register 3n (SIRB3n, SIRB3nL, SIRB3nH) ............................ 685
Figure 17-5: Chip Select CSI Buffer Register 3n (SFCS3n, SFCS3nL) ........................................ 686
Figure 17-6: Transmit Data CSI Buffer Register 3n (SFDB3n, SFDB3nL, SFDB3nH) ................ 687
Figure 17-7: CSIBUF Status Register 3n (SFA3n)(1/3) ............................................................... 688
Figure 17-8: Transfer Data Length Select Register 3n (CSIL3n) ................................................. 691
Figure 17-9: Transfer Data Number Specification Register 3n (SFN3n) ..................................... 692
Figure 17-10: Transfer Clock of CSI3n ............................................................................................693
Figure 17-11: Function of CSI Data Buffer Register n (CSIBUFn)................................................... 696
Figure 17-12: Data Transfer Direction Specification (MSB first) ...................................................... 697
Figure 17-13: Data Transfer Direction Specification (LSB first) ....................................................... 698
Figure 17-14: Transfer Data Length Changing Function ................................................................. 699
Figure 17-15: Clock Timing.............................................................................................................. 700
Figure 17-16: Master Mode ............................................................................................................. 701
Figure 17-17: Slave Mode ............................................................................................................... 702
Figure 17-18: Single Mode .............................................................................................................. 704
Figure 17-19: Consecutive Mode..................................................................................................... 706
Figure 17-20: Delay Control of Transmission/Reception Completion Interrupt (INTC3n):............... 708
Figure 17-21: Transfer Wait Function (1/3)...................................................................................... 709
Figure 17-22: Single Mode (Master Mode, Transmission Mode)..................................................... 714
Figure 17-23: Single Mode (Master Mode, Reception Mode) .......................................................... 716
Figure 17-24: Single Mode (Master Mode, Transmission/Reception Mode).................................... 718
Figure 17-25: Single Mode (Slave Mode, Transmission Mode)....................................................... 720
Figure 17-26: Single Mode (Slave Mode, Reception Mode)............................................................ 722
Figure 17-27: Single Mode (Slave Mode, Transmission/Reception Mode)...................................... 724
Figure 17-28: Consecutive Mode (Master Mode, Transmission Mode) ........................................... 726
Figure 17-29: Consecutive Mode (Master Mode, Reception Mode) ................................................ 728
Figure 17-30: Consecutive Mode (Master Mode, Transmission/Reception Mode).......................... 730
Figure 17-31: Consecutive Mode (Slave Mode, Transmission Mode) ............................................. 732
Figure 17-32: Consecutive Mode (Slave Mode, Reception Mode) .................................................. 734
Figure 17-33: Consecutive Mode (Slave Mode, Transmission/Reception Mode)............................ 736
Figure 18-1: Block Diagram of CAN Module.................................................................................. 741
Figure 18-2: Composition of Layers...............................................................................................742
Figure 18-3: Data Frame ............................................................................................................... 743
Figure 18-4: Remote Frame .......................................................................................................... 744
Figure 18-5: Start of frame (SOF).................................................................................................. 744
Figure 18-6: Arbitration field (in standard format mode) ................................................................ 745
Figure 18-7: Arbitration field (in extended format mode) ............................................................... 745
Figure 18-8: Control field ............................................................................................................... 746
Figure 18-9: Data field ................................................................................................................... 747
Figure 18-10: CRC field ................................................................................................................... 747
Figure 18-11: ACK field ................................................................................................................... 748
Figure 18-12: End of frame (EOF) ................................................................................................... 748