DS1249Y/AB DS1249Y/AB 2048K Nonvolatile SRAM FEATURES PIN ASSIGNMENT * 10 years minimum data retention in the absence of external power NC 1 32 VCC A16 2 31 A15 A14 3 30 A17 A12 4 29 WE A7 5 28 A13 * Read and write access times as fast as 70 ns A6 6 27 A8 * Lithium energy source is electrically disconnected to A5 7 26 A9 A4 8 25 A11 A3 9 24 OE * Data is automatically protected during power loss * Unlimited write cycles * Low-power CMOS operation retain freshness until power is applied for the first time * Full 10% VCC operating range (DS1249Y) A2 10 23 A10 * Optional 5% VCC operating range (DS1249AB) A1 11 22 CE * Optional A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 16 17 DQ3 industrial temperature range of -40C to +85C, designated IND * JEDEC standard 32-pin DIP package GND 32-PIN ENCAPSULATED PACKAGE 740 MIL EXTENDED PIN DESCRIPTION A0 - A17 DQ0 - DQ7 CE WE OE VCC GND NC - - - - - - - - Address Inputs Data In/Data Out Chip Enable Write Enable Output Enable Power (+5V) Ground No Connect DESCRIPTION The DS1249 2048K Nonvolatile SRAMs are 2,097,152-bit, fully static, nonvolatile SRAMs organized as 262,144 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. There is no limit on the number of write cycles which can be executed and no additional support circuitry is required for microprocessor interfacing. 021998 1/9 DS1249Y/AB READ MODE DATA RETENTION MODE The DS1249 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 18 address inputs (A0 - A17) defines which of the 262,144 bytes of data is accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later occurring signal (CE or OE) and the limiting parameter is either tCO for CE or tOE for OE rather than tACC. The DS1249AB provides full functional capability for VCC greater than 4.75 volts and write protects by 4.5 volts. The DS1249Y provides full functional capability for VCC greater than 4.5 volts and write protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write protects themselves, all inputs become "don't care," and all outputs become high impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuit connects external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1249AB and 4.5 volts for the DS1249Y. WRITE MODE The DS1249 devices execute a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The later occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active) then WE will disable the outputs in tODW from its falling edge. 021998 2/9 FRESHNESS SEAL Each DS1249 device is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithium energy source is enabled for battery backup operation. DS1249Y/AB ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.3V to +7.0V 0C to 70C, -40C to +85C for Ind parts -40C to +70C, -40C to +85C for Ind parts 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER (tA: See Note 10) SYMBOL MIN TYP MAX UNITS DS1249AB Power Supply Voltage VCC 4.75 5.0 5.25 V DS1249Y Power Supply Voltage VCC 4.5 5.0 5.5 V Logic 1 VIH 2.2 VCC V Logic 0 VIL 0.0 +0.8 V (VCC=5V 5% for DS1249AB) (tA: See Note 10) (VCC=5V 10% for DS1249Y) DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL MIN MAX UNITS Input Leakage Current IIL -2.0 +2.0 A I/O Leakage Current CE > VIH < VCC IIO -2.0 +2.0 A Output Current @ 2.4V IOH -1.0 mA Output Current @ 0.4V IOL 2.0 mA TYP Standby Current CE=2.2V ICCS1 1.0 1.5 mA Standby Current CE=VCC-0.5V ICCS2 100 150 A Operating Current ICCO1 85 mA Write Protection Voltage (DS1249AB) VTP 4.50 4.62 4.75 V Write Protection Voltage (DS1249Y) VTP 4.25 4.37 4.50 V NOTES (tA = 25C) CAPACITANCE PARAMETER NOTES TYP MAX UNITS Input Capacitance SYMBOL CIN MIN 10 20 pF Input/Output Capacitance CI/O 10 20 pF NOTES 021998 3/9 DS1249Y/AB (VCC=5V 5% for DS1249AB) (tA: See Note 10) (VCC=5V 10% for DS1249Y) AC ELECTRICAL CHARACTERISTICS DS1249AB-70 DS1249Y-70 DS1249AB-100 DS1249Y-100 SYMBOL MIN MIN Read Cycle Time tRC 70 Access Time tACC 70 100 ns OE to Output Valid tOE 35 50 ns 100 ns PARAMETER MAX MAX 100 NOTES ns CE to Output Valid tCO OE or CE to Output Active tCOE Output High-Z from Deselection tOD Output Hold from Address Change tOH 5 5 ns Write Cycle Time tWC 70 100 ns Write Pulse Width tWP 55 75 ns Address Setup Time tAW 0 0 ns Write Recovery Time tWR1 tWR2 5 15 5 15 ns ns 12 13 Output High-Z from WE tODW ns 5 Output Active from WE tOEW 5 5 ns 5 Data Setup Time tDS 30 40 ns 4 Data Hold Time tDH1 tDH2 0 10 0 10 ns ns 12 13 021998 4/9 70 UNITS 5 5 25 35 25 35 ns 5 ns 5 3 DS1249Y/AB READ CYCLE tRC VIH VIL ADDRESSES VIH VIL VIH VIL tOH tACC VIH CE tOD VIH OE VIH tCO VIL tOE VIH VIL tOD tCOE tCOE VOH OUTPUT VOH VOL DATA VALID VOL DOUT SEE NOTE 1 WRITE CYCLE 1 tWC ADDRESSES VIH VIH VIH VIL VIL VIL tAW CE VIL VIL tWP tWR1 WE VIH VIH VIL VIL tOEW tODW HIGH IMPEDANCE DOUT tDS tDH1 VIH DIN VIH DATA IN STABLE VIL VIL SEE NOTES 2, 3, 4, 6, 7, 8, and 12 021998 5/9 DS1249Y/AB WRITE CYCLE 2 tWC ADDRESSES VIH VIH VIH VIL VIL VIL tWP tAW tWR2 CE VIH VIH VIL VIL VIL VIH WE VIL VIL tCOE tODW DOUT tDS tDH2 VIH VIH DATA IN STABLE DIN VIL VIL SEE NOTES 2, 3, 4, 6, 7, 8 AND 13 POWER-DOWN/POWER-UP CONDITION VCC VTP 3.0V tR tF tREC tPD tPU CE, WE BACKUP CURRENT SUPPLIED FROM LITHIUM BATTERY tDR SEE NOTE 11 021998 6/9 DS1249Y/AB POWER-DOWN/POWER-UP TIMING PARAMETER VCC Fail Detect to CE and WE Inactive SYMBOL (tA: See Note 10) MIN TYP tPD MAX UNITS NOTES 1.5 s 11 VCC Slew from VTP to 0V tF 150 s VCC Slew from 0V to VTP tR 150 s VCC Valid to CE and WE Inactive tPU 2 ms VCC Valid to End of Write Protection tREC 125 ms (tA = 25C) PARAMETER Expected Data Retention Time SYMBOL MIN tDR 10 TYP MAX UNITS NOTES years 9 WARNING: Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. NOTES: 1. WE is high throughout read cycle. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDS is measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output buffers remain in a high impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in high impedance state during this period. 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period. 9. Each DS1249 has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. 10. All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial products, this range is 0C to 70C for industrial products (IND), this range is -40C to +85C. 11. In a power down condition the voltage on any pin may not exceed the voltage on VCC. 12. tWR1, tDH1 are measured from WE going high. 13. tWR2, tDH2 are measured from CE going high. 021998 7/9 DS1249Y/AB DC TEST CONDITIONS AC TEST CONDITIONS Outputs Open Cycle = 200 ns for operating current All voltages are referenced to ground Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0V to 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input pulse Rise and Fall Times: 5 ns ORDERING INFORMATION DS1249 TTP- SSS - III Operating Temperature Range blank: 0 to 70 IND: -40 to 85C Access Speed 70 ns 70: 100: 100 ns Package blank: 32-pin 600 mil DIP VCC Tolerance Y: 10% AB: 5% 021998 8/9 DS1249Y/AB DS1249Y/AB NONVOLATILE SRAM, 32-PIN 740 MIL EXTENDED MODULE PKG 1 A C F D K J G 32-PIN DIM MIN MAX A IN. MM 2.080 52.83 2.100 53.34 B IN. MM 0.715 18.16 0.740 18.80 C IN. MM 0.395 10.03 0.405 10.29 D IN. MM 0.280 7.11 0.310 7.49 E IN. MM 0.015 0.38 0.030 0.76 F IN. MM 0.120 3.05 0.160 4.06 G IN. MM 0.090 2.29 0.110 2.79 H IN MM 0.590 14.99 0.630 16.00 J IN MM 0.008 0.20 0.012 0.30 K IN. MM 0.015 0.43 0.025 0.58 E H B 021998 9/9