Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. A
04/01/03
IS61LPD25632T/D/J
IS61LPD25636T/D/J
IS61LPD51218T/D/J
ISSI ®
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Linear burst sequence control using MODE
input
•
Three chip enable option for simple depth
expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Power Supply
+3.3V VDD
+3.3V or 2.5 VDDQ (I/O)
• Auto Power-down during deselect
• Double cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• T Version (three chips selects)
• D Version (two chips selects)
• J Version (PBGA Package with JTAG)
DESCRIPTION
The ISSI IS61LPD25632T/D/J, IS61LPD25636T/D/J, and
IS61LPD51218T/D/J are high-speed, low-power synchro-
nous static
RAMs
designed to provide burstable,
high-
performance
memory for communication and networking
applications. The IS61LPD25632T/D/J is organized as
262,144 words by 32 bits and the IS61LPD25636T/D/J is
organized as 262,144 words by 36 bits. The IS61LPD51218T/
D/J is organized as 524,288 words by 18 bits. Fabricated
with ISSI's advanced CMOS technology, the device inte-
grates a 2-bit burst counter, high-speed SRAM core, and
high-drive capability outputs into a single monolithic circuit.
All synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be one to four
bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write enable
(BWE). Input combined with one or more individual byte
write signals (BWx). In addition, Global Write (GW) is
available for writing all bytes at one time, regardless of the
byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address ad-
vance) input pin.
The mode pin is used to select the burst sequence order.
Linear burst is achieved when this pin is tied LOW. Inter-
leave burst is achieved when this pin is tied HIGH or left
floating.
256K x 32, 256K x 36, 512K x 18
SYNCHRONOUS PIPELINED,
DOUBLE-CYCLE DESELECT STATIC RAM APRIL 2003
FAST ACCESS TIME
Symbol Parameter -250 -225 -200 -166 Units
tKQ Cl o c k Ac c e s s Ti m e 2.6 2.8 3.1 3.5 ns
tKC Cycle Time 4 4. 4 5 6 n s
Frequency 250 225 200 166 MHz
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
04/01/03
BLOCK DIAGRAM
18/19
BINARY
COUNTER
BWa
GW
CLR
CE
CLK Q0
Q1
MODE
A0'
A0
A1 A1'
CLK
ADV
ADSC
ADSP
16/17 18/19
ADDRESS
REGISTER
CE
D
CLK
Q
DQd
BYTE WRITE
REGISTERS
D
CLK
Q
DQc
BYTE WRITE
REGISTERS
D
CLK
Q
DQb
BYTE WRITE
REGISTERS
D
CLK
Q
DQa
BYTE WRITE
REGISTERS
D
CLK
Q
ENABLE
REGISTER
CE
D
CLK
Q
ENABLE
DELAY
REGISTER
D
CLK
Q
BWE
BWd
CE (T,D)
CE2 (T)
CE2 (T,D)
BWb
BWc
256Kx32; 256Kx36;
512Kx18
MEMORY ARRAY
32, 36,
or 18
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
OE
4
OE DQa - DQd
32, 36,
or 18
32, 36,
or 18
A
(x32/x36)
(x32/x36/x18)
(x32/x36)
(x32/x36/x18)
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
3
Rev. A
04/01/03
PIN CONFIGURATION
119-pin PBGA (D Version)
(Top View)
256K x 32
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa-BWd Individual Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VDD +3.3V Power Supply
GND Ground
VDDQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ Snooze Enable
DQPa-DQPd Parity Data I/O
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
A
CE2
A
NC
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
NC
A
NC
NC
A
A
A
GND
GND
GND
BWc
GND
NC
GND
BWd
GND
GND
GND
MODE
A
NC
ADSP
ADSC
V
DD
NC
CE
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
A
NC
A
A
A
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
NC
A
NC
A
A
A
NC
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
NC
A
NC
NC
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
1 2 3 4 5 6 7
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
04/01/03
PIN CONFIGURATION
100-Pin TQFP (T Version)
256K x 32
NC
DQb
DQb
V
DDQ
GND
DQb
DQb
DQb
DQb
GND
V
DDQ
DQb
DQb
GND
NC
V
DD
ZZ
DQa
DQa
V
DDQ
GND
DQa
DQa
DQa
DQa
GND
V
DDQ
DQa
DQa
NC
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
V
DD
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
NC
DQc
DQc
V
DDQ
GND
DQc
DQc
DQc
DQc
GND
V
DDQ
DQc
DQc
NC
V
DD
NC
GND
DQd
DQd
V
DDQ
GND
DQd
DQd
DQd
DQd
GND
V
DDQ
DQd
DQd
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
GND
V
DD
NC
A
A
A
A
A
A
A
A
46 47 48 49 50
100-Pin TQFP (D Version)
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa-BWd Individual Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VDD +3.3V Power Supply
GND Ground
VDDQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ Snooze Enable
DQPa-DQPd Parity Data I/O
NC
DQb
DQb
V
DDQ
GND
DQb
DQb
DQb
DQb
GND
V
DDQ
DQb
DQb
GND
NC
V
DD
ZZ
DQa
DQa
V
DDQ
GND
DQa
DQa
DQa
DQa
GND
V
DDQ
DQa
DQa
NC
A
A
CE
CE2
BWd
BWc
BWb
BWa
A
V
DD
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
NC
DQc
DQc
V
DDQ
GND
DQc
DQc
DQc
DQc
GND
V
DDQ
DQc
DQc
NC
V
DD
NC
GND
DQd
DQd
V
DDQ
GND
DQd
DQd
DQd
DQd
GND
V
DDQ
DQd
DQd
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
GND
V
DD
NC
NC
A
A
A
A
A
A
A
46 47 48 49 50
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
5
Rev. A
04/01/03
PIN CONFIGURATION
119-pin PBGA (D Version) 119-pin PBGA (J Version)
(Top View) (Top View)
256K x 36
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa-BWd Individual Byte Write Enable
BWE Synchronous Byte Write Enable
TMS, TDI JTAG BoundryScan Pins
TCK, TDO
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VDD +3.3V Power Supply
GND Ground
VDDQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ Snooze Enable
DQPa-DQPd Parity Data I/O
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
A
CE2
A
DQPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DQPd
A
NC
NC
A
A
A
GND
GND
GND
BWc
GND
NC
GND
BWd
GND
GND
GND
MODE
A
NC
ADSP
ADSC
V
DD
NC
CE
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
A
NC
A
A
A
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
NC
A
NC
A
A
A
DQPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQPa
A
NC
NC
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
1 2 3 4 5 6 7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
A
CE2
A
DQPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DQPd
A
NC
TMS
A
A
A
GND
GND
GND
BWc
GND
NC
GND
BWd
GND
GND
GND
MODE
A
TDI
ADSP
ADSC
V
DD
NC
CE
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
A
TCK
A
A
A
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
NC
A
TDO
A
A
A
DQPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQPa
A
NC
NC
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
1 2 3 4 5 6 7
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
6
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
04/01/03
100-Pin TQFP (T Version)
256K x 36
100-Pin TQFP (D Version)
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa-BWd Individual Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VDD +3.3V Power Supply
GND Ground
VDDQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ Snooze Enable
DQPa-DQPd Parity Data I/O
PIN CONFIGURATION
DQPb
DQb
DQb
VDDQ
GND
DQb
DQb
DQb
DQb
GND
VDDQ
DQb
DQb
GND
NC
VDD
ZZ
DQa
DQa
VDDQ
GND
DQa
DQa
DQa
DQa
GND
VDDQ
DQa
DQa
DQPa
A
A
CE
CE2
BWd
BWc
BWb
BWa
A
V
DD
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
DQPc
DQc
DQc
VDDQ
GND
DQc
DQc
DQc
DQc
GND
VDDQ
DQc
DQc
NC
VDD
NC
GND
DQd
DQd
VDDQ
GND
DQd
DQd
DQd
DQd
GND
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
GND
V
DD
NC
NC
A
A
A
A
A
A
A
46 47 48 49 50
DQPb
DQb
DQb
VDDQ
GND
DQb
DQb
DQb
DQb
GND
VDDQ
DQb
DQb
GND
NC
VDD
ZZ
DQa
DQa
VDDQ
GND
DQa
DQa
DQa
DQa
GND
VDDQ
DQa
DQa
DQPa
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VDD
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
DQPc
DQc
DQc
VDDQ
GND
DQc
DQc
DQc
DQc
GND
VDDQ
DQc
DQc
NC
VDD
NC
GND
DQd
DQd
VDDQ
GND
DQd
DQd
DQd
DQd
GND
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
GND
VDD
NC
A
A
A
A
A
A
A
A
46 47 48 49 50
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
7
Rev. A
04/01/03
PIN CONFIGURATION
512K x 18
119-pin PBGA (J Version)
(Top Version)
119-pin PBGA (D Version)
(Top Version)
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa-BWd Individual Byte Write Enable
BWE Synchronous Byte Write Enable
TMS, TDI JTAG BoundryScan Pins
TCK, TDO
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VDD +3.3V Power Supply
GND Ground
VDDQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ Snooze Enable
DQPa-DQPd Parity Data I/O
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQb
NC
V
DD
Q
NC
DQb
V
DDQ
NC
DQb
V
DDQ
DQb
NC
NC
NC
V
DDQ
A
CE2
A
NC
DQb
NC
DQb
NC
V
DD
DQb
NC
DQb
NC
DQPb
A
A
NC
A
A
A
GND
GND
GND
BWb
GND
NC
GND
GND
GND
GND
GND
MODE
A
NC
ADSP
ADSC
V
DD
NC
CE
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
NC
NC
A
A
A
GND
GND
GND
GND
GND
NC
GND
BWa
GND
GND
GND
NC
A
NC
A
A
A
DQPa
NC
DQa
NC
DQa
V
DD
NC
DQa
NC
DQa
NC
A
A
NC
V
DDQ
NC
NC
NC
DQa
V
DDQ
DQa
NC
V
DDQ
DQa
NC
V
DDQ
NC
DQa
NC
ZZ
V
DDQ
1 2 3 4 5 6 7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQb
NC
V
DDQ
NC
DQb
V
DDQ
NC
DQb
V
DDQ
DQb
NC
NC
NC
V
DDQ
A
CE2
A
NC
DQb
NC
DQb
NC
V
DD
DQb
NC
DQb
NC
DQPb
A
A
TMS
A
A
A
GND
GND
GND
BWb
GND
NC
GND
GND
GND
GND
GND
MODE
A
TDI
ADSP
ADSC
V
DD
NC
CE
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
NC
TCK
A
A
A
GND
GND
GND
GND
GND
NC
GND
BWa
GND
GND
GND
NC
A
TDO
A
A
A
DQPa
NC
DQa
NC
DQa
V
DD
NC
DQa
NC
DQa
NC
A
A
NC
V
DDQ
NC
NC
NC
DQa
V
DDQ
DQa
NC
V
DDQ
DQa
NC
V
DDQ
NC
DQa
NC
ZZ
V
DDQ
1 2 3 4 5 6 7
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
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1-800-379-4774
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04/01/03
PIN CONFIGURATION
512K x 18
100-Pin TQFP (D Version) 100-Pin TQFP (T Version)
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa-BWd Individual Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VDD +3.3V Power Supply
GND Ground
VDDQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ Snooze Enable
DQPa-DQPd Parity Data I/O
A
NC
NC
VDDQ
GND
NC
DQPa
DQa
DQa
GND
VDDQ
DQa
DQa
GND
NC
VDD
ZZ
DQa
DQa
VDDQ
GND
DQa
DQa
NC
NC
GND
VDDQ
NC
NC
NC
A
A
CE
CE2
NC
NC
BWb
BWa
A
VDD
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
NC
NC
NC
VDDQ
GND
NC
NC
DQb
DQb
GND
VDDQ
DQb
DQb
VDD
VDD
NC
GND
DQb
DQb
VDDQ
GND
DQb
DQb
DQPb
NC
GND
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
GND
VDD
NC
NC
A
A
A
A
A
A
A
46 47 48 49 50
A
NC
NC
V
DDQ
GND
NC
DQPa
DQa
DQa
GND
V
DDQ
DQa
DQa
GND
NC
V
DD
ZZ
DQa
DQa
V
DDQ
GND
DQa
DQa
NC
NC
GND
V
DDQ
NC
NC
NC
A
A
CE
CE2
NC
NC
BWb
BWa
CE2
VDD
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
NC
NC
NC
V
DDQ
GND
NC
NC
DQb
DQb
GND
V
DDQ
DQb
DQb
V
DD
V
DD
NC
GND
DQb
DQb
V
DDQ
GND
DQb
DQb
DQPb
NC
GND
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
GND
VDD
NC
A
A
A
A
A
A
A
A
46 47 48 49 50
ISSI ®
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1-800-379-4774
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Rev. A
04/01/03
TRUTH TABLE(1-8)
OPERATION ADDRESS CECE
CECE
CE CE2CE2
CE2CE2
CE2 CE2 ZZ ADSPADSP
ADSPADSP
ADSP ADSCADSC
ADSCADSC
ADSC ADVADV
ADVADV
ADV WRITEWRITE
WRITEWRITE
WRITE OEOE
OEOE
OE CLK DQ
Deselect Cycle, Power-Down None H X X L X L X X X L-H High-Z
Deselect Cycle, Power-Down None L X L L L XXXXL-HHigh-Z
Deselect Cycle, Power-Down None L H X L L XXXXL-HHigh-Z
Deselect Cycle, Power-Down None L X L L H L X X X L-H High-Z
Deselect Cycle, Power-Down None L H X L H L X X X L-H High-Z
Snooze Mode, Power-Down None X X X H XXXXXX High-Z
Read Cycle, Begin Burst External L L H L L X X X L L-H Q
Read Cycle, Begin Burst External L L H L L X X X H L-H High-Z
Write Cycle, Begin Burst External L L H L H L X L X L-H D
Read Cycle, Begin Burst External L L H L H L X H L L-H Q
Read Cycle, Begin Burst External L L H L H L X H H L-H High-Z
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H High-Z
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H H L-H High-Z
Write Cycle, Continue Burst Next X X X L H H L L X L-H D
Write Cycle, Continue Burst Next H X X L X H L L X L-H D
Read Cycle, Suspend Burst Current X X X L HHHHLL-H Q
Read Cycle, Suspend Burst Current X X X L HHHHHL-HHigh-Z
Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q
Read Cycle, Suspend Burst Current H X X L X HHHHL-HHigh-Z
Write Cycle, Suspend Burst Current X X X L H H H L X L-H D
Write Cycle, Suspend Burst Current H X X L X H H L X L-H D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GW is LOW.
WRITE = H for all BWx, BWE, GW HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc
and DQPd are only available on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during
the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte
write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for
clarification.
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INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
1,0
0,1A1', A0' = 1,1
Function GWGW
GWGW
GW BWEBWE
BWEBWE
BWE BWaBWa
BWaBWa
BWa BWbBWb
BWbBWb
BWb BWcBWc
BWcBWc
BWc BWdBWd
BWdBWd
BWd
Read H H XXXX
Read H L HHHH
Write Byte 1 H L L H H H
Write All Bytes H LLLLL
Write All Bytes L XXXXX
OPERATING RANGE
Range Ambient Temperature VDD VDDQ
Commercial 0°C to +70°C 3.3V ± 5% 3.3V ± 5%
2.5V ± 5%
Industrial -40°C to +85°C 3.3V ± 5% 3.3V ± 5%
2.5V ± 5%
PARTIAL TRUTH TABLE
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
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Rev. A
04/01/03
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
TSTG Storage Temperature –55 to +150 ° C
PDPower Dissipation 1.6 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to GND for I/O Pins –0.5 to VDDQ + 0.5 V
VIN Voltage Relative to GND for –0.5 to VDD + 0.5 V
for Address and Control Inputs
VDD Voltage on Vdd Supply Relatiive to GND –0.5 to 4.6 V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions
may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
2.5V (I/O) 3.3V (I/O)
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
VOH Output HIGH Voltage IOH = –4.0 mA (3.3V) 2.0 — 2.4 — V
IOH = 1.0 mA (2.5V)
VOL Output LOW Voltage IOL = 8.0 mA (3.3V) — 0. 4 — 0. 4 V
IOL = 1.0 mA (2.5V)
VIH Input HIGH Voltage 1.7 VDD + 0.3 2.0 VDD + 0.3 V
VIL Input LOW Voltage –0.3 0.7 –0.3 0.8 V
ILI Input Leakage Current GND ≤ VIN ≤ VDD
(1)
–5 5 –5 5 µA
ILO Output Leakage Current GND ≤ VOUT ≤ VDDQ, OE = VI–5 5 –5 5 µA
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
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Integrated Silicon Solution, Inc. — www.issi.com —
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POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-200 -166
Max Max Max Max
Symbol Parameter Test Conditions
x18 x36 x18 x36 Uni
t
ICC AC Operating Device Selected, Com. 125 130 120 125 mA
Supply Current OE = VIH, ZZ ≤ VIL,IND. 135 140 130 135
All Inputs ≤ VIL or ≥ VIH,
Cycle Time ≥ tKC min.
ISB Standby Current Device Deselected, COM.5555 5050 mA
TTL Input VDD = Max., Ind. 60 60 55 55
All Inputs ≤ VIL or ≥ VIH,
ZZ ≤ VIL, f = Max.
ISBI Standby Current Device Deselected, Com. 30 30 30 30 mA
CMOS Input VDD = Max., Ind. 40 40 40 40
VIN
≤
GND + 0.2V or ≥ VDD – 0.2V
f = 0
Note:
1. MODE pin has an internal pullup and should be tied to Vdd or GND. It exhibits ±30 µA maximum leakage current when tied to
≤ GND + 0.2V or ≥ VDD – 0.2V.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-250 -225
Max Max Max Max
Symbol Parameter Test Conditions
x18 x36 x18 x36 Uni
t
ICC AC Operating Device Selected, Com. 135 140 130 135 mA
Supply Current OE = VIH, ZZ ≤ VIL,IND. 140 145
All Inputs ≤ VIL or ≥ VIH,
Cycle Time ≥ tKC min.
ISB Standby Current Device Deselected, COM.6565 6060 mA
TTL Input VDD = Max., Ind. — — 65 65
All Inputs ≤ VIL or ≥ VIH,
ZZ ≤ VIL, f = Max.
ISBI Standby Current Device Deselected, Com. 30 30 30 30 mA
CMOS Input VDD = Max., Ind. — — 40 40
VIN
≤
GND + 0.2V or ≥ VDD – 0.2V
f = 0
Note:
1. MODE pin has an internal pullup and should be tied to Vdd or GND. It exhibits ±30 µA maximum leakage current when tied to
≤ GND + 0.2V or ≥ Vdd – 0.2V.
ISSI ®
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3.3V I/O AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 1ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
Figure 1 Figure 2
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 p F
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
3.3V I/O OUTPUT LOAD EQUIVALENT
ZO = 50Ω
1.5V
50Ω
OUTPUT
317 Ω
5 pF
Including
jig and
scope
351 Ω
OUTPUT
+3.3V
ISSI ®
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2.5V I/O AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 2.5V
Input Rise and Fall Times 1 ns
Input and Output Timing 1.25V
and Reference Level
Output Load See Figures 3 and 4
Figure 3 Figure 4
ZO = 50Ω
1.25V
50Ω
OUTPUT
1,667 Ω
5 pF
Including
jig and
scope
1,538 Ω
OUTPUT
+2.5V
2.5V I/O OUTPUT LOAD EQUIVALENT
ISSI ®
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Rev. A
04/01/03
Read/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166 -200 -225 -250
Symbol Parameter Min. Max. Min. Max. Min. Max Min. Max Unit
fMAX Clock Frequency — 166 — 200 — 225 — 250 ns
tKC Cycle Time 6 — 5 — 4.4 — 4 — ns
tKH Clock High Pulse Width 2 .3 — 2 — 1. 8 — 1. 7 — n s
tKL Clock Low Pulse Width 2.3 — 2 — 1.8 — 1.7 — n s
tKQ Clock Access Time — 3.5 — 3.1 — 2.8 — 2.6 ns
tKQX
(1)
Clock High to Output Invalid 1.5 — 1 . 0 — 1 .0 — 0.8 — ns
tKQLZ
(1,2)
Clock High to Output Low-Z 0 — 0 — 0 — 0 — ns
tKQHZ
(1,2)
Clock High to Output High-Z — 3.5 — 3. 0 — 2. 8 — 2.6 ns
tOEQ Output Enable to Output Valid — 3.5 — 3.1 — 2. 8 — 2.6 ns
tOELZ
(1,2)
Output Enable to Output Low-Z 0 — 0 — 0 — 0 — ns
tOEHZ
(1,2)
Output Enable to Output High-Z — 3. 5 — 3.0 — 2.8 — 2.6 n s
tAS Address Setup Time 1.5 — 1.4 — 1.4 — 1.2 — ns
tSS Address Status Setup Time 1.5 — 1.4 — 1.4 — 1.2 — n s
tWS Write Setup Time 1.5 — 1. 4 — 1.4 — 1. 2 — ns
tCES Chip Enable Setup Time 1.5 — 1. 4 — 1 . 4 — 1. 2 — ns
tAVS Address Advance Setup Time 1.5 — 1.4 — 1.4 — 1.2 — ns
tAH Address Hold Time 0.5 — 0.4 — 0.4 — 0.3 — ns
tSH Address Status Hold Time 0.5 — 0.4 — 0.4 — 0.3 — ns
tWH Write Hold Time 0.5 — 0. 4 — 0.4 — 0.3 — ns
tCEH Chip Enable Hold Time 0.5 — 0. 4 — 0.4 — 0.3 — ns
tAVH Address Advance Hold Time 0.5 — 0.4 — 0.4 — 0.3 — ns
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 1,2,3,4.
ISSI ®
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READ/WRITE CYCLE TIMING
Single Read
High-Z
High-Z
DATAOUT
DATAIN
OE
CE2
CE2
CE
BWx
BWE
GW
Address
ADV
ADSC
ADSP
CLK
RD1 RD2
1a 2c 2d 3a
Unselected
Burst Read
tKQX
tKC
tKLtKH
tSS tSH
tSS tSH
tAS tAH
tWS tWH
tWS tWH
RD3
tCES tCEH
tCES tCEH
tCES tCEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
tOEQ
tOEQX
tOELZ
tKQLZ
tKQ
tOEHZ
tKQHZ
ADSC initiate read
ADSP is blocked by CE inactive
tAVH
tAVS
Suspend Burst
Pipelined Read
2a 2b
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Rev. A
04/01/03
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166 -200 -225 -250
Symbol Parameter Min. Max. Min. Max. Min. Max Min. Max Unit
tKC Cycle Time 6 — 5 — 4.4 — 4 — ns
tKH Clock High Pulse Width 2 .3 — 2 — 1. 8 — 1.7 — ns
tKL Clock Low Pulse Width 2.3 — 2 — 1.8 — 1.7 — n s
tAS Address Setup Time 1.5 — 1.4 — 1.4 — 1.2 — ns
tSS Address Status Setup Time 1.5 — 1.4 — 1.4 — 1.2 — ns
tWS Write Setup Time 1.5 — 1. 4 — 1. 4 — 1.2 — ns
tDS Data In Setup Time 1 .5 — 1.4 — 1.4 — 1.2 — n s
tCES Chip Enable Setup Time 1.5 — 1. 4 — 1.4 — 1. 2 — ns
tAVS Address Advance Setup Time 1.5 — 1.4 — 1.4 — 1.2 — ns
tAH Address Hold Time 0.5 — 0.4 — 0.4 — 1.2 — ns
tSH Address Status Hold Time 0.5 — 0.4 — 0.4 — 0.3 — ns
tDH Data In Hold Time 0.5 — 0.4 — 0. 4 — 0.3 — ns
tWH Write Hold Time 0.5 — 0. 4 — 0.4 — 0.3 — ns
tCEH Chip Enable Hold Time 0.5 — 0. 4 — 0.4 — 0.3 — ns
tAVH Address Advance Hold Time 0.5 — 0.4 — 0.4 — 0.3 — ns
ISSI ®
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WRITE CYCLE TIMING
Single Write
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BWx
BWE
GW
Address
ADV
ADSC
ADSP
CLK
WR1 WR2
Unselected
Burst Write
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
WR3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
ADSC initiate Write
ADSP is blocked by CE inactive
t
AVH
t
AVS
ADV must be inactive for ADSP Write
WR1 WR2
t
WS
t
WH
WR3
t
WS
t
WH
High-Z
High-Z 1a 3a
t
DS
t
DH
BW4-BW1 only are applied to first cycle of WR2
Write
2c 2d2a 2b
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Rev. A
04/01/03
SNOOZE MODE TIMING
Don't Care
Deselect or Read Only Deselect or Read Only
tRZZI
CLK
ZZ
Isupply
All Inputs
(except ZZ)
Outputs
(Q)
ISB2
ZZ setup cycle ZZ recovery cycle
Normal
operation
cycle
tPDS tPUS
tZZI
High-Z
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol Parameter Conditions Min. Max. Unit
ISB2Current during SNOOZE MODE ZZ ≥ Vih, Com. — 30 mA
ZZ ≥ Vih, Ind. — 40
tPUS ZZ inactive to input sampled 2 — cycle
tZZI ZZ active to SNOOZE current — 2 cycle
tRZZI ZZ inactive to exit SNOOZE current 0 — ns
ISSI ®
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IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
The IS61LPD25636T/D/J and IS61LPD51218T/D/JT/D/
JT/D/J have a serial boundary scan Test Access Port (TAP)
in the PBGA package only. (Not available in TQFP package
or with the IS61LPD25632T/D/J.) This port operates in
accordance with
IEEE
Standard 1149.1-1900, but does not
include all functions required for full 1149.1 compliance.
These functions from the
IEEE specification
are excluded
because they place added delay in the critical speed path
of the SRAM. The TAP controller operates in a manner that
does not conflict with the performance of other devices
using 1149.1 fully compliant TAPs. The TAP operates using
JEDEC standard 2.5V I/O logic levels.
DISABLING THE JTAG FEATURE
The SRAM can operate without using the JTAG feature. To
disable the TAP controller, TCK must be tied LOW (GND)
to prevent clocking of the device. TDI and TMS are
internally pulled up and may be disconnected. They may
alternately be connected to VDD through a pull-up resistor.
TDO should be left disconnected. On power-up, the device
will start in a reset state which will not interfere with the
device operation.
TEST ACCESS PORT (TAP) - TEST CLOCK
The test clock is only used with the TAP controller. All
inputs are captured on the rising edge of TCK and outputs
are driven from the falling edge of TCK.
TEST MODE SELECT (TMS)
The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This pin
may be left disconnected if the TAP is not used. The pin is
internally pulled up, resulting in a logic HIGH level.
TEST DATA-IN (TDI)
The TDI pin is used to serially input information to the
registers and can be connected to the input of any register.
The register between TDI and TDO is chosen by the
instruction loaded into the TAP instruction register. For
information on instruction register loading, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be disconnected if the TAP is unused in an application. TDI
is connected to the Most Significant Bit (MSB) on any
register.
31 30 29 . . . 2 1 0
2 1 0
0
x . . . . . 2 1 0
Bypass Register
Instruction Register
Identification Register
Boundary Scan
Register*
TAP CONTROLLER
Selection Circuitry Selection Circuitry TDOTDI
TCK
TMS
TAP CONTROLLER BLOCK DIAGRAM
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TEST DATA OUT (TDO)
The TDO output pin is used to serially clock data-out from
the registers. The output is active depending on the current
state of the
TAP
state machine (see
TAP
Controller State
Diagram). The output changes on the falling edge of TCK
and TDO is connected to the Least Significant Bit (LSB) of
any register.
PERFORMING A TAP RESET
A Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At
power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
TAP REGISTERS
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI
pin on the rising edge of TCK and output on the TDO pin on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruc-
tion register. This register is loaded when it is placed
between the
TDI
and
TDO
pins. (See
TAP
Controller Block
Diagram) At power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the
IDCODE instruction if the controller is placed in a reset state
as previously described.
When the TAP controller is in the CaptureIR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers,
it is sometimes advantageous to skip certain states. The
bypass register is a single-bit register that can be placed
between TDI and TDO pins. This allows data to be shifted
through the
SRAM
with minimal delay. The bypass register
is set LOW (GND) when the BYPASS instruction is ex-
ecuted.
Boundary Scan Register
The boundary scan register is connected to all input and
output pins on the
SRAM
. Several no connect
(NC)
pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 70-bit-long
register and the x18 configuration has a 51-bit-long register.
The boundary scan register is loaded with the contents of
the RAM Input and Output ring when the TAP controller is
in the Capture-DR state and then placed between the
TDI
and
TDO
pins when the controller is moved to the
Shift-DR
state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z in-
structions can be used to capture the contents of the Input
and Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
TAP INSTRUCTION SET
Eight instructions are possible with the three-bit instruction
register and all combinations are listed in the Instruction Code
table. Three instructions are listed as
RESERVED
and should
not be used and the other five instructions are described
below. The TAP controller used in this SRAM is not fully
compliant with the 1149.1 convention because some man-
datory instructions are not fully implemented. The TAP
controller cannot be used to load address, data or control
signals and cannot preload the
Input
or
Output
buffers. The
SRAM
does not implement the
1149.1
commands
EXTEST
or
INTEST
or the
PRELOAD
portion of
SAMPLE/PRELOAD
; instead
it performs a capture of the
Inputs and Output
ring when these
instructions are executed. Instructions are loaded into the
TAP controller during the Shift-IR state when the instruction
register is placed between TDI and TDO. During this state,
instructions are shifted from the instruction register through
the TDI and TDO pins. To execute an instruction once it is
shifted in, the TAP controller must be moved into the
Update-IR state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
when the TAP controller is in a Shift-DR state. It also places
all SRAM outputs into a High-Z state.
Scan Register Sizes
Register Name Bit Size (x18) Bit Size (x36)
Instruction 3 3
Bypass 1 1
ID 32 32
Boundary Scan 51 70
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SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction.
The PRELOAD portion of this instruction is not imple-
mented, so the TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded to the
instruction register and the TAP controller is in the Capture-
DR state, a snapshot of data on the inputs and output pins
is captured in the boundary scan register.
It is important to realize that the TAP controller clock
operates at a frequency up to 10 MHz, while the SRAM
clock runs more than an order of magnitude faster. Because
of the clock frequency differences, it is possible that during
the Capture-DR state, an input or output will under-go a
transition. The TAP may attempt a signal capture while in
transition (metastable state). The device will not be harmed,
but there is no guarantee of the value that will be captured
or repeatable results.
To guarantee that the boundary scan register will capture
the correct signal value, the SRAM signal must be stabi-
lized long enough to meet the TAP controller’s capture set-
up plus hold times (tCS and tCH). To insure that the SRAM
clock input is captured correctly, designs need a way to stop
(or slow) the clock during a SAMPLE/PRELOAD instruc-
tion. If this is not an issue, it is possible to capture all other
signals and simply ignore the value of the CLK and CLK
captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data
by putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the
PRELOAD
part of the command is not
implemented, putting the
TAP
into the
Update
to the
Update-DR
state while performing a
SAMPLE/PRELOAD
instruction will
have the same effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the
bypass register is placed between the TDI and TDO pins.
The advantage of the BYPASS instruction is that it shortens
the boundary scan path when multiple devices are con-
nected together on a board.
RESERVED
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
IDENTIFICATION (ID) REGISTER
The ID Register is a 32-bit register that is loaded with a
device and vendor specific 32-bit code when the controller
is put in Capture-DR state with the IDCODE command
loaded in the Instruction Register. The code is loaded from
a 32-bit on-chip ROM. It describes various attributes of the
RAM as indicated below. The register is then placed
ID REGISTER CONTENTS
Die Vendor ISSI Technology
Revision Part Configuration
Defomotopm
JEDEC Vendor
Code ID Code
Presence Register
Part #313029282726252423222120191817161514 13121110 9 8 7 6 5 4 3 2 1 0
256K X X X X 0 0 1 1 0 0 0 1 0 0 X X X X X X 0 0 0 1 1 0 1 0 1 0 1 1
512K X X X X 0 0 1 1 1 0 0 0 1 1 X X X X X X 0 0 0 1 1 0 1 0 1 0 1 1
between the TDI and TDO pins when the controller is moved
into Shift-DR state. Bit 0 in the register is the LSB and the
first to reach TDO when shifting begins.The IDCODE
instruction is loaded into the instruction register upon power-
up or whenever the TAP controller is given a test logic reset
state.
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INSTRUCTION CODES
Code Instruction Description
001 IDCODE Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
0 10 SAMPLE Z Captures the Input/Output contents. Places the boundary scan register between TDI
and TDO. Forces all SRAM output drivers to a High-Z state.
0 1 1 RESERVED Do Not Use: This instruction is reserved for future use.
100
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register between
TDI and TDO. Does not affect the SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.
1 0 1 RESERVED Do Not Use: This instruction is reserved for future use.
1 1 0 RESERVED Do Not Use: This instruction is reserved for future use.
111 BYPASS Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
Test Logic Reset
Run Test/Idle 11 1
11
11
1
1
11
11
1
0
0
0
0
1
00
0
0
0
0
0
0
0
0
0
10
TAP CONTROLLER STATE DIAGRAM
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
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TAP Electrical Characteristics Over the Operating Range(1,2)
Symbol Parameter Test Conditions Min. Max. Units
VOH1 Output HIGH Voltage IOH = –2.0 mA 1. 7 — V
VOH2 Output HIGH Voltage IOH = –100 mA 2. 1 — V
VOL1 Output LOW Voltage IOL = 2.0 mA — 0.7 V
VOL2 Output LOW Voltage IOL = 100 mA — 0.2 V
VIH Input HIGH Voltage 1.7 VDD +0.3 V
VIL Input LOW Voltage IOLT = 2mA – 0 . 3 0. 7 V
IXInput Load Current GND ≤ V I ≤ VDDQ –5 5 mA
Notes:
1. All Voltage referenced to Ground.
2. Overshoot: VIH (AC) ≤ VDD +1.5V for t ≤ tTCYC/2,
Undershoot:VIL (AC) ≤ 0.5V for t ≤ tTCYC/2,
Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
TAP AC ELECTRICAL CHARACTERISTICS(1) (OVER OPERATING RANGE)
Symbol Parameter Min. Max. Unit
tTCYC TCK Clock cycle time 100 — ns
fTF TCK Clock frequency — 1 0 MHz
tTH TCK Clock HIGH 4 0 — ns
tTL TCK Clock LOW 4 0 — ns
tTMSS TMS setup to TCK Clock Rise 10 — ns
tTDIS TDI se tup to TCK Clock Rise 10 — ns
tCS Capture setup to TCK Rise 1 0 — ns
tTMSH
TMS hold after TCK Clock Rise
10 — ns
tTDIH TDI Hold after Clock Rise 1 0 — ns
tCH Capture hold after Clock Rise 1 0 — ns
tTDOV TCK LOW to TDO valid — 2 0 ns
tTDOX TCK LOW to TDO invalid 0 — ns
Notes:
1. tCS and tCHrefer to the set-up and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
ISSI ®
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Rev. A
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DON'T CARE
UNDEFINED
TCK
TMS
TDI
TDO
t
THTL
t
TLTH
t
THTH
t
MVTH
t
THMX
t
DVTH
t
THDX
1 2 3 4 5 6
t
TLOX
t
TLOV
TAP TIMING
20 pF
TDO
GND
50Ω
1.25V
Z
0
= 50Ω
TAP Output Load Equivalent
TAP AC TEST CONDITIONS
Input pulse levels 0 to 2.5V
Input rise and fall times 1n s
Input timing reference levels 1.25V
Output reference levels 1.25V
Test load termination supply voltage 1.25V
ISSI ®
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Integrated Silicon Solution, Inc. — www.issi.com —
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BOUNDARY SCAN ORDER (256K X 36)
Signal Bump Signal Bump Signal Bump Signal Bump
Bit # Na me ID Bit # Nam e ID Bit # Nam e ID Bit # Nam e ID
1 A 2R 19 DQb 7G 37 BWa 5L 55 DQd 2K
2 A 3T 20 DQb 6F 38 BWb 5G 56 DQd 1L
3 A 4T 21 DQb 7E 39 BWc 3G 57 DQd 2M
4 A 5T 22 DQb 7D 40 BWd 3L 58 DQd 1N
5 A 6R 23 DQb 7H 41 CE2 2B 59 DQd 1P
6 A 3B 24 DQb 6G 42 CE 4E 60 DQd 1K
7 A 5B 25 DQb 6E 43 A 3A 61 DQd 2L
8 DQa 6P 26 DQb 6D 44 A 2A 62 DQd 2N
9 DQa 7N 27 A 6A 45 DQc 2D 63 DQd 2P
10 DQa 6M 28 A 5A 46 DQc 1E 64 MODE 3R
11 DQa 7L 29 ADV 4G 47 DQc 2F 65 A 2C
12 DQa 6K 30 ADSP 4A 48 DQc 1G 66 A 3C
13 DQa 7P 31 ADSC 4B 49 DQc 2H 67 A 5C
14 DQa 6N 32 OE 4F 50 DQc 1D 68 A 6C
15 DQa 6L 33 BWE 4M 51 DQc 2E 69 A1 4N
16 DQa 7K 34 GW 4H 52 DQc 2G 70 A0 4P
17 ZZ 7T 35 CLK 4K 53 DQc 1H
18 DQb 6H 36 A 6B 54 NC 5R
BOUNDARY SCAN ORDER (512K X 18)
Signal Bump Signal Bump Signal Bump Signal Bump
Bit # Na me ID Bit # Nam e ID Bit # Nam e ID Bit # Nam e ID
1 A 2R 14 DQa 7G 27 CLK 4K 40 DQb 2K
2 A 2T 15 DQa 6F 28 A 6B 41 DQb 1L
3 A 3T 16 DQa 7E 29 BWa 5L 42 DQb 2M
4 A 5T 17 DQa 6D 30 BWb 3G 43 DQb 1N
5 A 6R 18 A 6T 31 CE2 2B 44 DQb 2P
6A3B 19A6A 32CE 4E 45 MODE 3R
7 A 5B 20 A 5A 33 A 3A 46 A 2C
8 DQa 7P 21 ADV 4G 34 A 2A 47 A 3C
9 DQa 6N 22 ADSP 4A 35 DQb 1D 48 A 5C
10 DQa 6L 23 ADSC 4B 36 DQb 2E 49 A 6C
11 DQa 7K 24 OE 4F 37 DQb 2G 50 A1 4N
12 ZZ 7T 25 BWE 4M 38 DQb 1H 51 A0 4P
13 DQa 6H 26 GW 4H 39 NC 5R
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Rev. A
04/01/03
ORDERING INFORMATION
(T Version)
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
166Mhz IS61LPD25632T-166TQ TQFP
200Mhz IS61LPD25632T-200TQ TQFP
225Mhz IS61LPD25632T-225TQ TQFP
250Mhz IS61LPD25632T-250TQ TQFP
(T Version)
Industrial Range: -40°C to +85°C
Speed Order Part Number Package
166Mhz IS61LPD25632T-166TQI TQFP
200Mhz IS61LPD25632T-200TQI TQFP
225Mhz IS61LPD25632T-225TQI TQFP
(D Version)
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
166 MHz IS61LPD25632D-166B BGA
166Mhz IS61LPD25632D-166TQ TQFP
200 MHz IS61LPD25632D-200B BGA
200Mhz IS61LPD25632D-200TQ TQFP
225 MHz IS61LPD25632D-225B BGA
225Mhz IS61LPD25632D-225TQ TQFP
250 MHz IS61LPD25632D-250B BGA
250Mhz IS61LPD25632D-250TQ TQFP
(D Version)
Industrial Range: -40°C to +85°C
Speed Order Part Number Package
166 MHz IS61LPD25632D-166BI BGA
166Mhz IS61LPD25632D-166TQI TQFP
200 MHz IS61LPD25632D-200BI BGA
200Mhz IS61LPD25632D-200TQI TQFP
225 MHz IS61LPD25632D-225BI BGA
225Mhz IS61LPD25632D-225TQI TQFP
ORDERING INFORMATION
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
28
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
04/01/03
ORDERING INFORMATION
(T Version)
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
166Mhz IS61LPD25636T-166TQ TQFP
200Mhz IS61LPD25636T-200TQ TQFP
225Mhz IS61LPD25636T-225TQ TQFP
250Mhz IS61LPD25636T-250TQ TQFP
ORDERING INFORMATION
(T Version)
Industrial Range: -40°C to +85°C
Speed Order Part Number Package
166Mhz IS61LPD25636T-166TQI TQFP
200Mhz IS61LPD25636T-200TQI TQFP
225Mhz IS61LPD25636T-225TQI TQFP
(D Version)
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
166 MHz IS61LPD25636D-166B BGA
166Mhz IS61LPD25636D-166TQ TQFP
200 MHz IS61LPD25636D-200B BGA
200Mhz IS61LPD25636D-200TQ TQFP
225 MHz IS61LPD25636D-225B BGA
225Mhz IS61LPD25636D-225TQ TQFP
250 MHz IS61LPD25636D-250B BGA
250Mhz IS61LPD25636D-250TQ TQFP
(D Version)
Industrial Range: -40°C to +85°C
Speed Order Part Number Package
166 MHz IS61LPD25636D-166BI BGA
166Mhz IS61LPD25636D-166TQI TQFP
200 MHz IS61LPD25636D-200BI BGA
200Mhz IS61LPD25636D-200TQI TQFP
225 MHz IS61LPD25636D-225BI BGA
225Mhz IS61LPD25636D-225TQI TQFP
(J Version)
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
166 MHz IS61LPD25636J-166B BGA
200 MHz IS61LPD25636J-200B BGA
225 MHz IS61LPD25636J-225B BGA
250 MHz IS61LPD25636J-250B BGA
(J Version)
Industrial Range: -40°C to +85°C
Speed Order Part Number Package
166 MHz IS61LPD25636J-166BI BGA
200 MHz IS61LPD25636J-200BI BGA
225 MHz IS61LPD25636J-225BI BGA
ISSI ®
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Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
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Rev. A
04/01/03
ORDERING INFORMATION
(T Version)
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
166Mhz IS61LPD51218T-166TQ TQFP
200Mhz IS61LPD51218T-200TQ TQFP
225Mhz IS61LPD51218T-225TQ TQFP
250Mhz IS61LPD51218T-250TQ TQFP
ORDERING INFORMATION
(T Version)
Industrial Range: -40°C to +85°C
Speed Order Part Number Package
166Mhz IS61LPD51218T-166TQI TQFP
200Mhz IS61LPD51218T-200TQI TQFP
225Mhz IS61LPD51218T-225TQI TQFP
(D Version)
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
166 MHz IS61LPD51218D-166B BGA
166Mhz IS61LPD51218D-166TQ TQFP
200 MHz IS61LPD51218D-200B BGA
200Mhz IS61LPD51218D-200TQ TQFP
225 MHz IS61LPD51218D-225B BGA
225Mhz IS61LPD51218D-225TQ TQFP
250 MHz IS61LPD51218D-250B BGA
250Mhz IS61LPD51218D-250TQ TQFP
(D Version)
Industrial Range: -40°C to +85°C
Speed Order Part Number Package
166 MHz IS61LPD51218D-166BI BGA
166Mhz IS61LPD51218D-166TQI TQFP
200 MHz IS61LPD51218D-200BI BGA
200Mhz IS61LPD51218D-200TQI TQFP
225 MHz IS61LPD51218D-225BI BGA
225Mhz IS61LPD51218D-225TQI TQFP
(J Version)
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
166 MHz IS61LPD51218J-166B BGA
200 MHz IS61LPD51218J-200B BGA
225 MHz IS61LPD51218J-225B BGA
250 MHz IS61LPD51218J-250B BGA
(J Version)
Industrial Range: -40°C to +85°C
Speed Order Part Number Package
166 MHz IS61LPD51218J-166BI BGA
200 MHz IS61LPD51218J-200BI BGA
225 MHz IS61LPD51218J-225BI BGA
