LTC2704
1
2704fd
REFM1 REFG1 REF1
24
42 23
21
REFM2REFG2
2704 BD
REF2
43
44 2
V+1
32
AGND
25
V+2
V–
1,8,15,22,31,36
12
SRO
SDI
11
SCK
13
LDAC
9
CLR
14
CS/LD
10
RFLAG
35
VDD
34
GND
33
DAC C
DAC D
26
29
28
27
30
20
17
18
19
16
AGNDC
C1D
RFBD
OUTD
AGNDD
OUTC
RFBC
C1C
VOSC
VOSD
DAC A
AGNDA
OUTA
RFBA
C1A
VOSA
3
6
5
4
7
DAC B
C1B
RFBB
OUTB
AGNDB
VOSB
41
38
39
40
37
–1
–1
LTC2704-16
Integral Nonlinearity (INL)
CODE
0
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
16384 32768
2704 TA01b
–0.6
0.6
0.8
0.2
49152 65535
V+/V
–
= ±15V
V
REF
= 5V
±10V RANGE
ALL 4 DACS
SUPERIMPOSED
BLOCK DIAGRAM
FEATURES
APPLICATIONS
DESCRIPTION
Quad 12-, 14- and 16-Bit
Voltage Output SoftSpan
DACs with Readback
n Six Programmable Output Ranges:
Unipolar: 0V to 5V, 0V to 10V
Bipolar: ±5V, ±10V, ±2.5V, –2.5V to 7.5V
n Serial Readback of All On-Chip Registers
n 1LSB INL and DNL Over the Industrial
Temperature Range (LTC2704-14/LTC2704-12)
n Force/Sense Outputs Enable Remote Sensing
n Glitch Impulse: < 2nV-sec
n Outputs Drive ±5mA
n Pin Compatible 12-, 14- and 16-Bit Parts
n Power-On and Clear to Zero Volts
n 44-Lead SSOP Package
n Process Control and Industrial Automation
n Direct Digital Waveform Generation
n Software Controlled Gain Adjustment
n Automated Test Equipment
The LTC
®
2704-16/LTC2704-14/LTC2704-12 are serial
input, 12-, 14- or 16-bit, voltage output SoftSpan™ DACs
that operate from 3V to 5V logic and ±5V to ±15V analog
supplies. SoftSpan offers six output spans—two unipolar
and four bipolar—fully programmable through the 3-wire
SPI serial interface. INL is accurate to 1LSB (2LSB for the
LTC2704-16). DNL is accurate to 1LSB for all versions.
Readback commands allow verifi cation of any on-chip
register in just one 24- or 32- bit instruction cycle. All other
commands produce a “rolling readback” response from
the LTC2704, dramatically reducing the needed number
of instruction cycles.
A Sleep command allows any combination of DACs to be
powered down. There is also a reset fl ag and an offset
adjustment pin for each channel.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. SoftSpan is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
LTC2704
2
2704fd
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
(Note 1)
Total Supply Voltage V+1, V+2 to V– ........... –0.3V to 36V
V+1, V+2, REF1, REF2, REFM1, REFM2,
OUTx, RFBx, VOSx to GND, AGND,
AGNDx, C1x, REFG1, REFG2 .....................................18V
GND, AGND, AGNDx, C1x, REFG1, REFG2 to V+1,
V+2, V–, REF1, REF2, REFM1, REFM2, OUTx,
RFBx, VOSx ...............................................................18V
OUTA, RFBA, VOSA, OUTB, RFBB, VOSB, REF1,
REFM1 to GND, AGND ............... V– – 0.3V to V+1 + 0.3V
OUTC, RFBC, VOSC, OUTD, RFBD, VOSD, REF2, REFM2
to GND, AGND ............................ V– – 0.3V to V+2 + 0.3V
VDD, Digital Inputs/Outputs to GND ............. –0.3V to 7V
Digital Inputs/Outputs to VDD ..................................0.3V
GND, AGNDx, REFG1, REFG2 to AGND ..................±0.3V
C1x to AGNDx ........................................................±0.3V
V– to Any Pin ...........................................................0.3V
Maximum Junction Temperature.......................... 150°C
Operating Temperature Range
LTC2704C ................................................ 0°C to 70°C
LTC2704I..............................................– 40°C to 85°C
Storage Temperature Range ...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
ORDER INFORMATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
TOP VIEW
GW PACKAGE
44-LEAD PLASTIC SSOP
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V–
REFG1
AGNDA
VOSA
C1A
OUTA
RFBA
V–
LDAC
CS/LD
SDI
SRO
SCK
CLR
V–
RFBD
OUTD
C1D
VOSD
AGNDD
REFG2
V–
REFM1
REF1
V+1
AGNDB
VOSB
C1B
OUTB
RFBB
V–
RFLAG
VDD
GND
AGND
V–
RFBC
OUTC
C1C
VOSC
AGNDC
V+2
REF2
REFM2
TJMAX = 125°C, θJA = 80°C/W
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2704CGW-16#PBF LTC2704CGW-16#TRPBF LTC2704CGW-16 44-Lead Plastic SSOP 0°C to 70°C
LTC2704IGW-16#PBF LTC2704IGW-16#TRPBF LTC2704IGW-16 44-Lead Plastic SSOP –40°C to 85°C
LTC2704CGW-14#PBF LTC2704CGW-14#TRPBF LTC2704CGW-14 44-Lead Plastic SSOP 0°C to 70°C
LTC2704IGW-14#PBF LTC2704IGW-14#TRPBF LTC2704IGW-14 44-Lead Plastic SSOP –40°C to 85°C
LTC2704CGW-12#PBF LTC2704CGW-12#TRPBF LTC2704CGW-12 44-Lead Plastic SSOP 0°C to 70°C
LTC2704IGW-12#PBF LTC2704IGW-12#TRPBF LTC2704IGW-12 44-Lead Plastic SSOP –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi
cations, go to: http://www.linear.com/tapeandreel/
LTC2704
3
2704fd
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS
LTC2704-12 LTC2704-14 LTC2704-16
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
Accuracy
Resolution l12 14 16 Bits
Monotonicity l12 14 16 Bits
INL Integral Nonlinearity VREF = 5V l±1 ±1 ±2 LSB
DNL Differential Nonlinearity VREF = 5V l±1 ±1 ±1 LSB
GE Gain Error VREF = 5V l±0.5 ±2 ±1 ±5 ±4 ±20 LSB
Gain Temperature
Coeffi cient
∆Gain/∆Temperature l±2 ±2 ±2 ppm/°C
VOS Unipolar Zero-Scale
Error
Span = 0V to 5V, TA = 25°C
Span = 0V to 10V, TA = 25°C
Span = 0V to 5V
Span = 0V to 10V
l
l
±80
±100
±140
±150
±200
±300
±400
±600
± 80
±100
±140
±150
±200
±300
±400
±600
±80
±100
±140
±150
±200
±300
±400
±600
V
V
V
V
VOS Temperature
Coeffi cient
0V to 5V Range
0V to 10V Range
l
l
±2
±2
±2
±2
±2
±2
V/°C
V/°C
BZE Bipolar Zero
Error
All Bipolar Ranges
l
±0.25 ±1
±2
±0.5 ±2
±2.5
±2 ±8
±12
LSB
LSB
PSRR Power Supply
Rejection Ratio
VDD = 5V ±10% (Note 3)
VDD = 3V ±10% (Note 3)
0V to 10V Range, Code = 0
V+/V– = ±15V ±10% (Note 2)
V+/V– = ±5V ±10%, VREF = 2V (Note 2)
l
l
±0.003
±0.006
±0.001
±0.002
±0.06
±0.05
±0.013
±0.025
±0.005
±0.01
±0.25
±0.13
±0.05
±0.1
±0.02
±0.04
±0.1
±0.5
LSB/V
LSB/V
LSB/V
LSB/V
Analog Outputs (Note 4)
Settling Time 0V to 5V Range, 5V Step, to ±1LSB
0V to 10V or ±5V Range,
10V Step, to ±1LSB
±10V Range, 20V Step, to ±1LSB
3
5
8
3.5
5.5
9
4
6
10
µs
µs
µs
Output Swing V+/V– = ±15V, VREF = ±7.25V,
0V to 10V Range, ILOAD = ±3mA (Note 2)
l–14.3 14.3 –14.3 14.3 –14.3 14.3 V
V+/V– = ±5V, VREF = ±2.25V,
0V to 10V Range, ILOAD = ±2.5mA (Note 2)
l–4.5 4.5 –4.5 4.5 –4.5 4.5 V
Load Current V+/V– = ±10.8V to ±16.5V, VREF = ±5V,
0V to 10V Range, VOUT = ±10V (Note 2) l
±5
±4
±5
±4
±5
±4
mA
mA
V+/V– = ±4.5V to ±16.5V, VREF = ±2V,
0V to 10V Range, VOUT = ±4V (Note 2) l
±3
±2.7
±3
±2.7
±3
±2.7
mA
mA
Load Regulation V+/V– = ±15V, VREF = 5V,
0V to 10V Range, Code = 0, ±5mA Load
(Note 2)
l±0.005 ±0.01 ±0.04 LSB/mA
V+/V– = ±5V, VREF = 2V,
0V to 10V Range, Code = 0, ±3mA Load
(Note 2)
l±0.01 ±0.013 ±0.05 LSB/mA
Output
Impedance
VREF = 5V, 0V to 10V Range,
Code = 0, ±5mA Load
l0.015 0.006 0.006
ISC Short-Circuit
Current
V+/V– = ±16.5V, VREF = 5V, ±10V Range
Code = 0, VOUT Shorted to V+ (Note 2)
Code = Full Scale, VOUT Shorted to V–l
l–36
38
–36
38
–36
38 mA
mA
V+/V– = ±5.5V, VREF = 2V, ±10V Range
Code = 0, VOUT Shorted to V+ (Note 2)
Code = Full Scale, VOUT Shorted to V–l
l–36
38
–36
38
–36
38 mA
mA
The l denotes specifi cations which apply over the full operating
temperature range, otherwise specifi cations are TA = 25°C, V+1 = V+2 = 15V, V– = –15V, VDD = 5V, REF1 = REF2 = 5V, AGND = AGNDx =
REFG1 = REFG2 = GND = 0V.
LTC2704
4
2704fd
ELECTRICAL CHARACTERISTICS
The l denotes specifi cations which apply over the full operating temperature range, otherwise specifi cations are TA = 25°C,
V+1 = V+2 = 15V, V– = –15V, VDD = 5V, REF1 = REF2 = 5V, AGND = AGNDx = REFG1 = REFG2 = GND = 0V.
SYMBOL PARAMETER CONDITIONS
LTC2704-12 LTC2704-14 LTC2704-16
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
SR Slew Rate RL= 2k, V+/V– = ±15V (Note 2)
RL= 2k, V+/V– = ±5V (Note 2)
l
l
2.2
2.0
3
2.8
2.2
2.0
3
2.8
2.2
2.0
3
2.8
V/µs
V/µs
Capacitive Load
Driving
Within Maximum Load Current 1000 1000 1000 pF
The l denotes specifi cations which apply over the full operating
temperature range, otherwise specifi cations are TA = 25°C, V+1 = V+2 = 15V, V– = –15V, VDD = 5V, REF1 = REF2 = 5V, AGND = AGNDx =
REFG1 = REFG2 = GND = 0V.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Inputs
REF1, REF2 Input Voltage V+/V– = ±15V, 0V to 5V Span (Note 2) l–14.5 14.5 V
Resistances
RREF1, RREF2 Reference Input Resistance l57 k
RFBx Output Feedback Resistance l710 k
RVOSX Offset Adjust Input Resistance l700 1000 k
AC Performance (Note 4)
Glitch Impulse 0V to 5V Range, Midscale Transition 2 nV-s
Crosstalk 10V Step on VOUTA
DAC B: 0V to 5V Range, Full Scale
DAC B: 0V to 10V Range, Full Scale
2
3
nV-s
nV-s
Digital Feedthrough ±10V Range, Midscale 0.2 nV-s
Multiplying Feedthrough Error 0V to 10V Range, VREF = ±5V, 10kHz Sine Wave 0.35 mVP-P
Multiplying Bandwidth Span = 0V to 5V, Full Scale
Span = 0V to 10V, Full Scale
300
250
kHz
kHz
Output Noise Voltage Density 10kHz
Span = 0V to 5V, Midscale
Span = 0V to 10V, Midscale
30
50
nV/√Hz
nV/√Hz
Output Noise Voltage 0.1Hz to 10Hz
Span = 0V to 5V, Midscale
Span = 0V to 10V, Midscale
0.8
1.2
µVRMS
µVRMS
Power Supply
IDD Supply Current, VDD Digital Inputs = 0V or VDD l0.5 2 µA
ISSupply Current, V+/V–V+/V– = ±15V, ±10%; VREF = 5V, VOUT = 0V (Note 2)
V+/V– = ±5V, ±10%; VREF = 2V, VOUT = 0V (Note 2)
Sleep Mode—All DACs (Note 4)
l
l
17.5
17.0
20
18
1
mA
mA
mA
VDD Logic Supply Voltage l2.7 5.5 V
V+1/V+2Positive Analog Supply Voltage l4.5 16.5 V
V–Negative Analog Supply Voltage l–16.5 –4.5 V
Digital Inputs/Outputs
VIH Digital Input High Voltage VDD = 2.7V to 5.5V
VDD = 2.7V to 3.3V
l
l
2.4
2.0
V
V
VIL Digital Input Low Voltage VDD = 2.7V to 5.5V
VDD = 4.5V to 5.5V
l
l
0.6
0.8
V
V
VOH Digital Output High Voltage IOH = 200µA lVCC – 0.4 V
VOL Digital Output Low Voltage IOL = 200µA l0.4 V
IIN Digital Input Current l0.001 ±1 µA
LTC2704
5
2704fd
The l denotes specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The notation V+ is used to denote both V+1 and V+2 when the same
voltage is applied to both pins.
Note 3: Guaranteed by design, not subject to test.
Note 4: Measured in unipolar 0V to 5V mode.
Note 5: When using SRO, maximum SCK frequency fMAX is limited by SRO
propagation delay as follows:
fMAX =1
2t
9+tS
()
, where ts is the setup time of the receiving device.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CIN Digital Input Capacitance VIN = 0V (Note 3) l5pF
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD = 4.5V to 5.5V
t1SDI Valid to SCK Setup l7ns
t2SDI Valid to SCK Hold l7ns
t3SCK High Time l11 ns
t4SCK Low Time l11 ns
t5CS/LD Pulse Width l9ns
t6LSB SCK High to CS/LD High l0ns
t7CS/LD Low to SCK Positive Edge l12 ns
t8CS/LD High to SCK Positive Edge l12 ns
t9SRO Propagation Delay CLOAD = 10pF l18 ns
t10 CLR Pulse Width l50 ns
t11 LDAC Pulse Width l15 ns
t12 CLR Low to RFLAG Low CLOAD = 10pF (Note 3) l50 ns
t13 CS/LD High to RFLAG High CLOAD = 10pF (Note 3) l40 ns
SCK Frequency 50% Duty Cycle (Note 5) l40 MHz
VDD = 2.7V to 3.3V
t1SDI Valid to SCK Setup l9ns
t2SDI Valid to SCK Hold l9ns
t3SCK High Time l15 ns
t4SCK Low Time l15 ns
t5CS/LD Pulse Width l12 ns
t6LSB SCK High to CS/LD High l0ns
t7CS/LD Low to SCK Positive Edge l12 ns
t8CS/LD High to SCK Positive Edge l12 ns
t9SRO Propagation Delay CLOAD = 10pF l26 ns
t10 CLR Pulse Width l90 ns
t11 LDAC Pulse Width l20 ns
t12 CLR Low to RFLAG Low CLOAD = 10pF l70 ns
t13 CS/LD High to RFLAG High CLOAD = 10pF l60 ns
SCK Frequency 50% Duty Cycle (Note 5) l25 MHz
TIMING CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
The l denotes specifi cations which apply over the full operating
temperature range, otherwise specifi cations are TA = 25°C, V+1 = V+2 = 15V, V– = –15V, VDD = 5V, REF1 = REF2 = 5V, AGND = AGNDx =
REFG1 = REFG2 = GND = 0V.
LTC2704
6
2704fd
TYPICAL PERFORMANCE CHARACTERISTICS
TEMPERATURE (°C)
–50
LSB
4
90
2704 G07
–8 –30 –10 10 30 50 70
8
2
6
0
–4
–6
–2
V+/V– = ±15V
VREF = 5V
±10V RANGE
TEMPERATURE (°C)
–50
GAIN ERROR (LSB)
12
16
–16
–12
30
2704 G08
0
4
–4
8
–8
–30 –10 10 50 70 90
V+/V– = ±15V
VREF = 5V
±10V RANGE
TEMPERATURE (°C)
–50
INL (LSB)
0.2
0.6
1.0
30
2704 G04
–0.2
–O.6
0
0.4
0.8
–0.4
–0.8
–1.0 –30 –10 10 50 70 90
V+/V– = ±15V
VREF = 5V
±10V RANGE
MAX
MIN
TEMPERATURE (°C)
–50
DNL (LSB)
0.2
0.6
1.0
30
2704 G05
–0.2
–O.6
0
0.4
0.8
–0.4
–0.8
–1.0 –30 –10 10 50 70 90
V+/V– = ±15V
VREF = 5V
±10V RANGE
MAX
MIN
TEMPERATURE (°C)
–50
OFFSET (µV)
200
400
600
30
2704 G06
–200
–600
0
–400
–30 –10 10 50 70 90
V+/V– = ±15V
VREF = 5V
0V TO 10V RANGE
LTC2704-16
Integral Nonlinearity (INL)
CODE
0
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
16384 32768
2704 G01
–0.6
0.6
0.8
0.2
49152 65535
V+/V– = ±15V
VREF = 5V
±10V RANGE
CODE
0
–1.0
DNL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
16384 32768
2704 G02
–0.6
0.6
0.8
0.2
49152 65535
V+/V– = ±15V
VREF = 5V
±10V RANGE
VREF (V)
–10
INL (LSB)
0.2
0.6
1.0
6
2704 G03
–0.2
–0.6
0
0.4
0.8
–0.4
–0.8
–1.0 –6–8 –2–4 24 8
010
V+/V– = ±15V
±5V RANGE
MAX MAX
MIN MIN
Differential Nonlinearity (DNL) INL vs VREF
Bipolar Zero vs Temperature Gain Error vs Temperature
INL vs Temperature Offset vs Temperature
DNL vs Temperature
LTC2704
7
2704fd
TYPICAL PERFORMANCE CHARACTERISTICS
2.5µs/DIV
VOUT
5V/DIV
VOUT
1mV/DIV
CS/LD
5V/DIV
2704 G18
Settling 0V to 5V
2.5µs/DIV
VOUT
5V/DIV
VOUT
1mV/DIV
CS/LD
5V/DIV
2704 G19 2.5µs/DIV
VOUT
10V/DIV
VOUT
1mV/DIV
CS/LD
5V/DIV
2704 G20
Settling 0V to 10V Settling ±10V
LTC2704-14
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
CODE
0
–1.0
LSB
–0.8
–0.4
–0.2
0
1.0
0.4
4096 8192
2704 G09
–0.6
0.6
0.8
0.2
12288 16383
V+/V– = ±15V
VREF = 5V
±10V RANGE
CODE
0
–1.0
LSB
–0.8
–0.4
–0.2
0
1.0
0.4
4096 8192
2704 G10
–0.6
0.6
0.8
0.2
12288 16383
V+/V– = ±15V
VREF = 5V
±10V RANGE
LTC2704-12
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
CODE
0
–1.0
LSB
–0.8
–0.4
–0.2
0
1.0
0.4
1536 2048
2704 G11
–0.6
0.6
0.8
0.2
3072
512 1024 2560 3584 4095
V+/V– = ±15V
VREF = 5V
±10V RANGE
CODE
0
–1.0
LSB
–0.8
–0.4
–0.2
0
1.0
0.4
1536 2048
2704 G12
–0.6
0.6
0.8
0.2
3072
512 1024 2560 3584 4095
V+/V– = ±15V
VREF = 5V
±10V RANGE
LTC2704-16
LTC2704
8
2704fd
TYPICAL PERFORMANCE CHARACTERISTICS
V– (Pins 1, 8, 15, 22, 31, 36): Analog Negative Supply,
Typically –15V. –4.5V to –16.5V Range.
REFG1 (Pin 2): Reference 1 Ground. High impedance
input, does not carry supply currents. Tie to clean analog
ground.
AGNDA (Pin 3): DAC A Signal Ground. High impedance
input, does not carry supply currents. Tie to clean analog
ground.
VOSA (Pin 4): Offset Adjust for DAC A. Nominal input
range is ±5V. VOS(DAC A) = –0.01• V(VOSA) [0V to 5V,
±2.5V modes]. See Operation section.
C1A (Pin 5): Feedback Capacitor Connection for DAC A
Output. This pin provides direct access to the negative
input of the channel A output amplifi er.
OUTA (Pin 6): DAC A Voltage Output Pin. For best load
regulation, this open-loop amplifi er output is connected
to RFBA as close to the load as possible.
RFBA (Pin 7): DAC A Output Feedback Resistor Pin.
LDAC (Pin 9): Asynchronous DAC Load Input. When LDAC
is a logic low, all DACs are updated.
0.1Hz to 10Hz Noise
VCC Supply Current
vs Logic Voltage
1s/DIV
1µV/DIV
2704 G16
V+/V– = ±15V
VREF = 5V
0V TO 5V RANGE
CODE = 0
LOGIC VOLTAGE (V)
0
0
ICC (mA)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.5 2.5 3.5
2704 G17
2.0 4.5 5.0
1.0 1.5 3.0 4.0
VDD = 5V
SCK, SDI, CS/LD, LDAC
CLR TIED TOGETHER
PIN FUNCTIONS
LTC2704-16/LTC2704-14/LTC2704-12
Positive Slew Negative Slew
2.5µs/DIV
5V/DIV
2704 G13
V+/V– = ±15V
VREF = 5V
±10V RANGE
20V STEP
2.5µs/DIV
5V/DIV
2704 G14
V+/V– = ±15V
VREF = 5V
±10V RANGE
20V STEP
2.5µs/DIV
CS/LD
5V/DIV
VOUT
2mV/DIV
2704 G15
Midscale Glitch
LTC2704
9
2704fd
CS/LD (Pin 10): Synchronous Chip Select and Load Pin.
SDI (Pin 11): Serial Data Input. Data is clocked in on the
rising edge of the serial clock when CS/LD is low.
SRO (Pin 12): Serial Readback Data Output. Data is clocked
out on the falling edge of SCK. Readback data begins
clocking out after the last address bit A0 is clocked in.
SCK (Pin 13): Serial Clock.
CLR (Pin 14): Asynchronous Clear Pin. When this pin is
low, all code and span B2 registers are cleared to zero.
All DAC outputs are cleared to zero volts.
RFBD (Pin 16): DAC D Voltage Output Feedback Resis-
tor Pin.
OUTD (Pin 17): DAC D Voltage Output Pin. For best load
regulation, this open-loop amplifi er output is connected
to RFBD as close to the load as possible.
C1D (Pin 18): Feedback Capacitor Connection for DAC
D Output.
This pin provides direct access to the negative
input of the channel D output amplifi er.
VOSD (Pin 19): Offset Adjust for DAC D. Nominal input
range is ±5V. VOS(DAC D) = –0.01• V(VOSD) [0V to 5V,
±2.5V modes]. See Operation section.
AGNDD (Pin 20):
DAC D Signal Ground. High impedance
input, does not carry supply currents. Tie to clean analog
ground.
REFG2 (Pin 21): Reference 2 Ground. High impedance
input, does not carry supply currents. Tie to clean analog
ground.
REFM2 (Pin 23): Reference 2 Inverting Amp Output. The
gain from REF2 to REFM2 is –1. Can swing to within 0.5V
of the analog supplies V+/V–.
REF2 (Pin 24): DAC C and DAC D Reference Input.
V+2 (Pin 25): Analog Positive Supply for DACs C and D.
Typically 15V. 4.5V to 16.5V Range. Can be different from
V+1.
AGNDC (Pin 26):
DAC C Signal Ground. High impedance
input, does not carry supply currents. Tie to clean analog
ground.
VOSC (Pin 27): Offset Adjust for DAC C. Nominal input
range is ±5V. VOS(DAC C) = –0.01• V(VOSC) [0V to 5V,
±2.5V modes]. See Operation section.
C1C (Pin 28): Feedback Capacitor Connection for DAC C
Output. This pin provides direct access to the negative
input of the channel C output amplifi er.
OUTC (Pin 29): DAC C Voltage Output Pin. For best load
regulation, this open-loop amplifi er output is connected
to RFBC as close to the load as possible.
RFBC (Pin 30): DAC C Output Feedback Resistor Pin.
AGND (Pin 32):
Analog Ground Pin. Tie to clean analog
ground.
GND (Pin 33):
Ground Pin. Tie to clean analog ground.
VDD (Pin 34):
Logic Supply. 2.7V to 5.5V Range.
RFLAG (Pin 35): Reset Flag Pin. An active low output is
asserted when there is a power on reset or a clear event.
Returns high when an update command is executed.
RFBB (Pin 37): DAC B Output Feedback Resistor Pin.
OUTB (Pin 38): DAC B Voltage Output Pin. For best load
regulation, this open-loop amplifi er output is connected
to RFBB as close to the load as possible.
C1B (Pin 39): Feedback Capacitor Connection for DAC B
Output. This pin provides direct access to the negative
input of the channel B output amplifi er.
VOSB (Pin 40): Offset Adjust for DAC B. Nominal input
range is ±5V. VOS(DAC B) = –0.01 • V(VOSB) [0V to 5V,
±2.5V modes]. See Operation section.
AGNDB (Pin 41): DAC B Signal Ground. High impedance
input, does not carry supply currents. Tie to clean analog
ground.
V+1 (Pin 42): Analog Positive Supply for DACs A DND
B. Typically 15V. 4.5V to 16.5V Range. Can be different
from V+2.
REF1 (Pin 43): DAC A and DAC B Reference Input.
REFM1 (Pin 44): Reference 1 Inverting Amp Output. The
gain from REF1 to REFM1 is –1. Can swing to within 0.5V
of the analog supplies V+/V–.
PIN FUNCTIONS
LTC2704
10
2704fd
42
12
SRO
2704 BD
32
AGND
25
V+2
V–
1,8,15,22,31,36
COMMAND
DECODE
INPUT
SHIFT REGS
READBACK
SHIFT REGS
DAC
BUFFERS
SDI
11
SCK
13
LDAC
9
CLR
14
CS/LD
10
RFLAG
35
VDD
34
GND POR
33
REF1
43
V+1
AGNDA
OUTA
RFBA
C1A
VOSA
3
6
5
4
7
DAC A
+
–
AGNDB
OUTB
RFBB
C1B
VOSB
41
REFM1
44
REFG1
AGNDC
OUTC
RFBC
C1C
VOSC
REF2
AGNDD
OUTD
RFBD
C1D
VOSD
REFM2
REFG2
2
38
39
40
37
26
29
28
24
27
30
20
23
21
17
18
19
16
DAC B
+
–
–
+
+
–
+
–
–
+
DAC C
DAC D
BLOCK DIAGRAM
TIMING DIAGRAM
LTC2704
11
2704fd
SERIAL INTERFACE
When the CS/LD pin is taken low, the data on the SDI pin
is loaded into the shift register on the rising edge of the
clock signal (SCK pin). The minimum (24-bit wide) loading
sequence required for the LTC2704 is a 4-bit command
word (C3 C2 C1 C0), followed by a 4-bit address word
(A3 A2 A1 A0) and 16 data (span or code) bits, MSB
fi rst. Figure 1 shows the SDI input word syntax to use
when writing a code or span. If a 32-bit input sequence is
needed, the fi rst eight bits must be zeros, followed by the
same sequence as for a 24-bit wide input. Figure 2 shows
the input and readback sequences for both 24-bit and
32-bit operations.
When CS/LD is low, the Serial Readback Output (SRO)
pin is an active output. The readback data begins after
the command (C3-C0) and address (A3-A0) words have
been shifted into SDI. For a 24-bit load sequence, the 16
readback bits are shifted out on the falling edges of clocks
8-23, suitable for shifting into a microprocessor on the
rising edges of clocks 9-24. For a 32-bit load sequence,
add 8 to these clock cycle counts; see Figure 2b.
When CS/LD is high, the SRO pin presents a high impedance
(three-state) output. At the beginning of a load sequence,
when CS/LD is taken low, SRO outputs a logic low until
the readback data begins.
When the asynchronous load pin, LDAC, is taken low, all
DACs are updated with code and span data (data in B1
buffers is copied into B2 buffers). CS/LD must be high
during this operation. The use of LDAC is functionally
identical to the “Update B1→B2” commands.
The codes for the command word (C3-C0) are defi ned in
Table 1; Table 2 defi nes the codes for the address word
(A3-A0).
READBACK
Each DAC has two pairs of double-buffered digital regis-
ters, one pair for DAC code and the other for the output
span (four buffers per DAC). Each double-buffered pair
comprises two registers called buffer 1 (B1) and buffer
2 (B2).
B1 is the holding buffer. When data is shifted into B1 via
a write operation, DAC outputs are not affected. The con-
tents of B2 can only be changed by copying the contents
of B1 into B2 via an update operation (B1 and B2 can be
changed together, see commands 0110-1001 in Table 1).
The contents of B2 (DAC code or DAC span) directly control
the DAC output voltage or the DAC output range.
Additionally each DAC has one readback register associated
with it. When a readback command is issued to a DAC, the
contents of one of its four buffers is copied into its readback
register and serially shifted out onto the SRO pin. Figure 2
shows the loading and readback sequences. In the 16-bit
data fi eld (D15-D0 for the LTC2704-16, see Figure 2a) of
any write or update command, the readback pin (SRO)
shifts out the contents of the buffer which was specifi ed in
the preceding command. This “rolling readback” mode of
operation can be used to reduce the number of operations,
since any command can be verifi ed during succeeding
commands with no additional overhead. Table 1 shows
the location (readback pointer) of the data which will be
output from SRO during the next instruction.
For readback commands, the data is shifted out during the
readback instruction itself (on the 16 falling SCK edges im-
mediately after the last address bit is shifted in on SDI).
When programming the span of a DAC, the span bits are
the last four bits shifted in; and when checking the span of
a DAC using SRO, the span bits are likewise the last four
bits shifted out. Table 3 shows the span codes.
When span information is read back on SRO, the sleep
status of the addressed DAC is also output. The sleep status
bit, SLP, occurs sequentially just before the four span bits.
The sequence is shown in Figures 2a and 2b. See Table 4
for SLP codes. Note that SLP is an output bit only; sleep
is programmed by using command code 1110 along with
the desired address. Any update command, including the
use of LDAC, wakes the addressed DAC(s).
OPERATION
LTC2704
12
2704fd
OUTPUT RANGES
The LTC2704 is a quad DAC with software-programmable
output ranges. SoftSpan provides two unipolar output
ranges (0V to 5V and 0V to 10V), and four bipolar ranges
(±2.5V, ±5V, ±10V and – 2.5V to 7.5V). These ranges are
obtained when an external precision 5V reference and
analog supplies of ±12V to ±15V are used. When a refer-
ence voltage of 2V and analog supplies of ±5V are used,
the SoftSpan ranges become: 0V to 2V, 0V to 4V, ±1V, ±2V,
±4V and –1V to 3V. The output ranges are linearly scaled
for references other than 2V and 5V (appropriate analog
supplies should be used within the range ±5V to ±15V).
Each of the four DACs can be programmed to any one of
the six output ranges. DAC outputs can swing to ±10V
on ±10.8V supplies (±12V supplies with ±10% tolerance)
while sourcing or sinking 5mA of load current.
OPERATION
Table 1. Command Codes
CODE READBACK POINTER— READBACK POINTER—
C3 C2 C1 C0 COMMAND CURRENT INPUT WORD WONEXT INPUT WORD W+1
0 0 1 0 Write to B1 Span DAC n Set by Previous Command B1 Span DAC n
0 0 1 1 Write to B1 Code DAC n Set by Previous Command B1 Code DAC n
0 1 0 0 Update B1→B2 DAC n Set by Previous Command B2 Span DAC n
0 1 0 1 Update B1→B2 All DACs Set by Previous Command B2 Code DAC n
0 1 1 0 Write to B1 Span DAC n
Update B1→B2 DAC n
Set by Previous Command B2 Span DAC n
0 1 1 1 Write to B1 Code DAC n
Update B1→B2 DAC n
Set by Previous Command B2 Code DAC n
1 0 0 0 Write to B1 Span DAC n
Update B1→B2 All DACs
Set by Previous Command B2 Span DAC n
1 0 0 1 Write to B1 Code DAC n
Update B1→B2 All DACs
Set by Previous Command B2 Code DAC n
1 0 1 0 Read B1 Span DAC n B1 Span DAC n
1 0 1 1 Read B1 Code DAC n B1 Code DAC n
1 1 0 0 Read B2 Span DAC n B2 Span DAC n
1 1 0 1 Read B2 Code DAC n B2 Code DAC n
1 1 1 0 Sleep DAC n (Note 1) Set by Previous Command B2 Span DAC n
1 1 1 1 No Operation Set by Previous Command B2 Code DAC n
Codes not shown are reserved and should not be used.
Note 1: Normal operation can be resumed by issuing any update B1→B2 command to the sleeping DAC.
Table 2. Address Codes
A3 A2 A1 A0 n READBACK POINTER n
0 0 0 0 DAC A DAC A
0 0 1 0 DAC B DAC B
0 1 0 0 DAC C DAC C
0 1 1 0 DAC D DAC D
1 1 1 1 All DACs DAC A
Codes not shown are reserved and should not be used.
Table 3. Span Codes
S3 S2 S1 S0 SPAN
0 0 0 0 Unipolar 0V to 5V
0 0 0 1 Unipolar 0V to 10V
0 0 1 0 Bipolar –5V to 5V
0 0 1 1 Bipolar –10V to 10V
0 1 0 0 Bipolar –2.5V to 2.5V
0 1 0 1 Bipolar –2.5V to 7.5V
Codes not shown are reserved and should not be used.
LTC2704
13
2704fd
C2 C1 C0 A3 A2 A1 A0 D15
MSB
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LSB
C3
LTC2704-16
(WRITE CODE)
CONTROL WORD ADDRESS WORD 16-BIT CODE
C2 C1 C0 A3 A2 A1 A0 D13
MSB
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0
LSB
C3
LTC2704-14
(WRITE CODE)
CONTROL WORD
SDI ADDRESS WORD 14-BIT CODE 2 ZEROS
C2 C1 C0 A3 A2 A1 A0 D11
MSB
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0
LSB
C3
LTC2704-12
(WRITE CODE)
CONTROL WORD ADDRESS WORD 12-BIT CODE 4 ZEROS
C2 C1 C0 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 S3 S2 S1 S0C3
LTC2704-12
LTC2704-14
LTC2704-16
(WRITE SPAN)
CONTROL WORD ADDRESS WORD 12 ZEROS SPAN
2704 F01
Figure 1. Input Words
OPERATION
LTC2704
14
2704fd
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24
C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3
0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D00
CS/LD
SCK
SDI
SRO Hi-Z
Hi-Z
CONTROL WORD
READBACK CODE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLP S3 S2 S1 S00
SRO
READBACK SPAN
ADDRESS WORD DAC CODE OR DAC SPAN
24-BIT DATA STREAM
2704 F02a
SLEEP
STATUS
SPAN
Figure 2a. 24-Bit Load Sequence
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C300000000
CS/LD
SCK
SDI
CONTROL WORD ADDRESS WORD DAC CODE OR DAC SPAN
32-BIT DATA STREAM
0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0000000000
SRO
t2
t3t4
t1
t9
D15
17
SCK
SDI
SRO D14D15
18
D14
8 ZEROS
Hi-Z
Hi-Z
READBACK CODE
2704 F02b
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLP S3 S2 S1 S0000000000
SRO
READBACK SPAN
SLEEP
STATUS
SPAN
Figure 2b. 32-Bit Load Sequence
OPERATION
LTC2704
15
2704fd
Examples
1. Using a 24-bit loading sequence, load DAC A with the
unipolar range of 0V to 10V, output at zero volts and all
other DACs with the bipolar range of ±10V, outputs at
zero volts. Note all DAC outputs should change at the
same time.
a) CS/LD↓
b) Clock SDI = 0010 1111 0000 0000 0000 0011
c) CS/LD↑
B1-Range of all DACs set to bipolar ±10V.
d) CS/LD↓
Clock SDI = 0010 0000 0000 0000 0000 0001
e) CS/LD↑
B1-Range of DAC A set to unipolar 0V to 10V.
f) CS/LD↓
Clock SDI = 0011 1111 1000 0000 0000 0000
g) CS/LD↑
B1-Code of all DACs set to midscale.
h) CS/LD↓
Clock SDI = 0011 0000 0000 0000 0000 0000
i) CS/LD↑
B1-Code of DAC A set to zero code.
j) CS/LD↓
Clock SDI = 0100 1111 XXXX XXXX XXXX XXXX
k) CS/LD↑
Update all DACs B1s into B2s for both Code and
Range.
l) Alternatively steps j and k could be replaced with
LDAC .
2. Using a 32-bit load sequence, load DAC C with bipolar
±2.5V and its output at zero volts. Use readback to
check B1 contents before updating the DAC output
(i.e., before copying B1 contents into B2).
a) CS/LD↓ (Note that after power-on, the Code in B1 is
zero)
b) Clock SDI = 0000 0000 0011 0100 1000 0000 0000
0000
c) CS/LD↑
B1-Code of DAC C set to midscale setting.
d) CS/LD↓
Clock SDI = 0000 0000 0010 0100 0000 0000 0000
0100
e) Read Data out on SRO = 1000 0000 0000 0000
Verifi es that B1-Code DAC C is at midscale setting.
f) CS/LD↑
B1-Range of DAC C set to Bipolar ±2.5V range.
g) CS/LD↓
Clock SDI = 0000 0000 1010 0100 xxxx xxxx xxxx
xxxx
Data Out on SRO = 0000 0000 0000 0100
Verifi es that B1-Range of DAC C set to Bipolar ±2.5V
Range.
CS/LD↑
h) CS/LD↓
Clock SDI = 0000 0000 0100 0100 xxxx xxxx xxxx
xxxx
i) CS/LD↑
Update DAC C B1 into B2 for both Code and Range
j) Alternatively steps h and i could be replaced with
LDAC .
System Offset Adjustment
Many systems require compensation for overall system
offset, which may be an order of magnitude or more greater
than the excellent offset of the LTC2704.
The LTC2704 has individual offset adjust pins for each
of the four DACs. VOSA, VOSB, VOSC and VOSD are
referred to their corresponding signal grounds, AGNDA,
AGNDB, AGNDC and AGNDD. For noise immunity and
ease of adjustment, the control voltage is attenuated to
the DAC output:
VOS = –0.01 • V(VOSx) [0V to 5V, ±2.5V spans]
VOS = –0.02 • V(VOSx) [0V to 10V, ±5V,
–2.5V to 7.5V spans]
VOS = –0.04 • V(VOSx) [±10V span]
The nominal input range of these pins is ±5V; other refer-
ence voltages of up to ±15V may be used if needed.
The VOSx pins have an input impedance of 1M. To pre-
serve the settling performance of the LTC2704, these pins
OPERATION
LTC2704
16
2704fd
should be driven with a Thevenin-equivalent impedance
of 10k or less. If not used, they should be shorted to
their respective signal grounds, AGNDx.
POWER-ON RESET AND CLEAR
When power is fi rst applied to the LTC2704, all DACs
power-up in 5V unipolar mode (S3 S2 S1 S0 = 0000). All
internal DAC registers are reset to 0 and the DAC outputs
are zero volts.
When the CLR pin is taken low, a system clear results. The
command and address shift registers, and the code and
confi guration B2 buffers, are reset to 0; the DAC outputs
are all reset to zero volts. The B1 buffers are left intact, so
that any subsequent “Update B1→B2” command (includ-
ing the use of LDAC) restores the addressed DACs to their
respective previous states.
If CLR is asserted during an operation, i.e., when CS/LD
is low, the operation is aborted. Integrity of the relevant
input (B1) buffers is not guaranteed under these condi-
tions, therefore the contents should be checked using
readback or replaced.
The RFLAG pin is used as a fl ag to notify the system of a
loss of data integrity. The RFLAG output is asserted low
at power-up, system clear, or if the logic supply VDD dips
below approximately 2V; and stays asserted until any valid
update command is executed.
SLEEP MODE
When a sleep command (C3 C2 C1 C0 = 1110) is issued,
the addressed DAC or DACs go into power-down mode.
DACs A and B share a reference inverting amplifi er as do
DACs C and D. If either DAC A or DAC B (similarly for DACs
C and D) is powered down, its shared reference inverting
amplifi er remains powered on. When both DAC A and DAC B
are powered down together, their shared reference invert-
ing amplifi er is also powered down (similarly for DACs C
and D). To determine the sleep status of a particular DAC,
a direct read span command is performed by addressing
the DAC and reading its status on the readback pin SRO.
The fi fth LSB is the sleep status bit (see Figures 2a and
2b). Table 4 shows the sleep status bit’s functionality.
Table 4. Readback Sleep Status Bit
SLP STATUS
0 DAC n Awake
1 DAC n in Sleep Mode
OPERATION
LTC2704
17
2704fd
APPLICATIONS INFORMATION
Overview
The LTC2704 is a highly integrated device, greatly sim-
plifying design and layout as compared to a design using
multiple current output DACs and separate amplifi ers. A
similar design using four separate current output DACs
would require six precision op amps, compensation capaci-
tors, bypass capacitors for each amplifi er, several times as
much PCB area and a more complicated serial interface.
Still, it is important to avoid some common mistakes in
order to achieve full performance. DC752A is the evalu-
ation board for the LTC2704. It is designed to meet all
data sheet specifi cations, and to allow the LTC2704 to be
integrated into other prototype circuitry. All force/sense
lines are available to allow the addition of current booster
stages or other output circuits.
The DC752A design is presented as a tutorial on properly
applying the LTC2704. This board shows how to properly
return digital and analog ground currents, and how to
compensate for small differences in ground potential
between the two banks of two DACs. There are other ways
to ground the LTC2704, but the one requirement is that
analog and digital grounds be connected at the LTC2704
by a very low impedance path. It is NOT advisable to split
the ground planes and connect them with a jumper or
inductor. When in doubt, use a single solid ground plane
rather than separate planes.
The LTC2704 does allow the ground potential of the DACs
to vary by ±300mV with respect to analog ground, allowing
compensation for ground return resistance.
Power Supply Grounding and Noise
LTC2704 V+ and V– pins are the supplies to all of the
output amplifi ers, ground sense amplifi ers and reference
inversion amplifi ers. These amplifi ers have good power
supply rejection, but the V+ and V– supplies must be free
from wideband noise. The best scheme is to prefi lter low
noise regulators such as the LT
®
1761 (positive) and LT1964
(negative). Refer to Linear Technology Application Note
101, Minimizing Switching Regulator Residue in Linear
Regulator Outputs.
The LTC2704 VDD pin is the supply for the digital logic
and analog DAC switches and is very sensitive to noise. It
must be treated as an analog supply. The evaluation board
uses an LT1790 precision reference as the VDD supply to
minimize noise.
The GND pin is the return for digital currents and the
AGND pin is a bias point for internal analog circuitry. Both
of these pins must be tied to the same point on a quiet
ground plane.
Each DAC has a separate ground sense pin that can be used
to compensate for small differences in ground potential
within a system. Since DACs A and B are associated with
REF1 and DACs C and D are associated with REF2, the
grounds must be grouped together as follows:
AGNDA, AGNDB and REFG1 tied together (“GND1” on
DC752A)
AGNDC, AGNDD and REFG2 tied together (“GND2” on
DC752A)
This scheme allows compensation for ground return IR
drops, as long as the resistance is shared by both DACs
in a group. This implies that the ground return for DACs
A and B must be as close as possible, and GND1 must
be connected to this point through a low current, low
resistance trace. (Similar for DACs C and D.)
Figure 3 shows the top layer of the evaluation board. The
GND1 trace connects REFG1, AGNDA, AGNDB and the
ground pin of the LT1236 precision reference (U4.) This
point is the ground reference for DACs A and B. The GND2
trace connects REFG2, AGNDC, AGNDD and the ground pin
of the other LT1236 precision reference (U5). This point
is the ground reference for DACs C and D.
Voltage Reference
A high quality, low noise reference such as the LT1236
or LT1027 must be used to achieve full performance.
The ground terminal of this reference must be connected
directly to the common ground point. If GND1 and GND2
are separate, then two references must be used.
LTC2704
18
2704fd
Voltage Output/Feedback and Compensation
The LTC2704 provides separate voltage output and feedback
pins for each DAC. This allows compensation for resistance
between the output and load, or a current boosting stage
such as an LT1970 may be inserted without affecting ac-
curacy. When OUTx is connected directly to RFBx and no
GND1 TRACE,
SEPARATED FROM
AGND UNDER LTC2704
EXPOSED GROUND PLANE AROUND EDGE
ALLOWS GROUNDING TO PROTOTYPE CIRCUITS
2704 F03
GND2 TRACE,
SEPARATED FROM
AGND UNDER LTC2704
CUTOUT PREVENTS DIGITAL RETURN CURRENTS
FROM COUPLING INTO ANALOG GROUND PLANE. NOTE
THAT THERE IS A PLANE IN THIS REGION ON LAYER 3
2704 F04
Figure 3. DC752 Top Layer Figure 4. DC752 Analog Ground Layer. No Currents Are Returned
to this Plane, so it May Be Used As a Reference Point for Precise
Voltage Measurements
additional capacitance is present, the internal frequency
compensation is suffi cient for stability and is optimized
for fast settling time. If a low bandwidth booster stage is
used, then a compensation capacitor from OUTx to C1x
may be required. Similarly, extra compensation may be
required to drive a heavy capacitive load.
APPLICATIONS INFORMATION
LTC2704
19
2704fd
DIGITAL RETURN CURRENTS
FLOW IN THIS REGION
2704 F05
V
OUTA
AND V
OUTB
LOAD
RETURN CURRENTS FLOW
IN THIS REGION WHEN
JP8 IS SET TO “TIE”
V
OUTC
AND V
OUTD
LOAD
RETURN CURRENTS FLOW
IN THIS REGION WHEN
JP9 IS SET TO “TIE”
POWER AND LOAD RETURN
CURRENTS FLOW IN THIS REGION
SMALL GROUND POUR ALLOWS
LOW IMPEDANCE BYPASSING
OF V
+
AND V
–
2704 F06
Figure 5. DC752A Load Return, Power Return and Digital Return Figure 6. DC752A Routing, Bypass
APPLICATIONS INFORMATION
LTC2704
20
2704fd
PACKAGE DESCRIPTION
G44 SSOP 0204
0° – 8° TYP
0.355
REF
0.231 – 0.3175
(.0091 – .0125)
0.40 – 1.27
(.015 – .050)
7.417 – 7.595**
(.292 – .299)
= 45°
0.254 – 0.406
(.010 – .016)
2.286 – 2.388
(.090 – .094)
0.1 – 0.3
(.004 – .0118)
2.44 – 2.64
(.096 – .104)
0.800
(.0315)
BSC
0.28 – 0.51
(.011 – .02)
TYP
17.73 – 17.93*
(.698 – .706)
123456789101112131415161718192021
10.11 – 10.55
(.398 – .415)
22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
*
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
**
MILLIMETERS
(INCHES)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
10.804 MIN
RECOMMENDED SOLDER PAD LAYOUT
7.75 – 8.258
2344
221
0.800 BSC0.520 ±0.0635
1.40 ±0.127
GW Package
44-Lead Plastic SSOP (Wide .300 Inch)
(Reference LTC DWG # 05-08-1642)
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC2704
21
2704fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
B 10/09 Title Change to Block Diagram
Electrical Characteristics Text Changes to Analog Outputs Section
Text and Figure Deletion in Operation Section
1
3
16
C 08/10 Revised Note 1 to remove power supply sequencing reference
Changed “DAC A” to DAC n in Table 1
5
12
D 12/12 Corrected Output Noise Voltage Density Units From µV/√Hz to nV/√Hz 4
(Revision history begins at Rev B)
LTC2704
22
2704fd
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
LT 1212 REV D • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
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LTC1857/LTC1858
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12-/14-/16-Bit, Serial 100ksps SoftSpan
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Software-Selectable Spans, 40mW, Fault Protected to ±25V
LT1970 500mA Power Op Amp Adjustable Sink/Source Current Limits
Evaluation Board Schematic. Force/Sense Lines Allow for Remote Sensing and Optimal Grounding
LDAC
CS/LD
SDI
SRO
SCK
CLR
RFLAG
REFG1
REF1
REFM1
REFG2
REF2
REFM2
VDD
GND
AGND
CS/LD
SDI
SRO
SCK
VOSA
C1A
RFBA
OUTA
AGNDA
VOSB
C1B
RFBB
OUTB
AGNDB
VOSC
C1C
RFBC
OUTC
AGNDC
VOSD
C1D
RFBD
OUTD
AGNDD
9
10
11
12
13
14
35
4
5
7
6
3
40
39
37
38
41
27
28
30
29
26
19
18
16
17
20
2
43
44
21
24
23
14
33
32
V+1
25 42 1,8,15,22,31,36
V+2V–
LTC2704
LDAC VOSA
VOSB
GND1
GND1
GND2
OUTA
1
2
3
BAV99LT1
BAV99LT1
BAV99LT1
TIE
REMOTE
OUTSA
OUTA
OUTSB
OUTB
OUTSC
OUTC
10k
VDD
10k
VDD
VDD
VDD
BAT54S
0.1µF
1µF
1µF
15V –15V
1µF 1µF
CLR
REFM1
GND1
GND2
REFM2
SPI
INTERFACE
RFLAG
1k
VDD
1
2
3
1
2
3
1
2
3
VDD
5VREGULATOR
REF
REF2
REF1
REMOTE
VOSx
5V
REMOTE
5V 5VREF2
5VREF1
1
12
12
VS
24.7µF0.1µF
7V
15V
12
3
VIN
64 VOUT
LT1790ACS6-5
GND GND
VOSC
OUTB
TIE
REMOTE
OUTC
TIE
REMOTE
1
2
3
1
2
3
GND2
BAV99LT1
OUTSD
OUTD
VOSD
OUTD
TIE
REMOTE
1
2
3
GND2
TIE
REMOTE
BAT54S
GND2
1
2
3
3
21
GND1
TIE
REMOTE
BAT54S
GND1
1
2
3
3
21
VIN
6
5
4
2VOUT
TRIM
LT1236ACS8-5
GND
0.1µF 4.7µF
GND1
VS5VREF1
15V
15V
–15V
–15V
4.7µF
25V
4.7µF
25V
VIN
6
5
4
2VOUT
TRIM
LT1236ACS8-5
GND
0.1µF 4.7µF
GND2
VS5VREF2
REFx
OFFSET ADJUSTMENT
FOR VOSA, VOSB,
VOSC, VOSC
20k
REFMx
2704 TA01a