80000966244 - 3M - Pdf.Support

Freescale Semiconductor

Technical Data

Freescale reserves the right to change the detail specifications as may be required

to permit improvements in the design of its products.

This document provides an overview of t he MPC8377E

PowerQUICC II Pro processor features, including a block

diagram show ing the major functional components. This

chip is a cost-ef fective, low-power, highly integrated host

processor that addresses the requirements of several

printing and imaging, consum er, and industrial

applications, including m ain CPUs and I/O processors in

printing systems, networking switches and line cards,

wireless LANs (WLANs), network access servers (NAS),

VPN routers, intelligent NIC, and industrial controllers.

This chip extends the PowerQUICC family, adding higher

CPU performance, additional functionality, and faster

interfac es while addressing the requirements relate d to

time-to-market, price, power consumption, and package

size.

1Overview

This chip incorporates the e300c4s core, which includes

32 KB of L1 instruction and data caches and on-chip

memory management units (MMUs). The device offer s

two enhanced three-speed 10, 100, 1000 Mbps Ethernet

interfac es, a DDR1/DDR2 SDRAM me mory contr olle r, a

flexible, a 32-bit local bus controller, a 32-bit PCI

controller, an optional dedicate d security engine, a USB

2.0 dual-role controller, a programmable interrupt

Document Number: MPC8377EEC

Rev. 8, 05/2012

Contents

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7

3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11

4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 13

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . 15

6. DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . 16

7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8. Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 23

9. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

11. Enhanced Secure Digital Host Controller (eSDHC) 44

12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

13. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

14. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

15. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

16. Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . 69

17. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

18. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

19. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

20. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

21. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 78

22. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 88

23. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

24. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

25. System Design Information . . . . . . . . . . . . . . . . . . 120

26. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 122

27. Document Revision History . . . . . . . . . . . . . . . . . . 124

MPC8377E

PowerQUICC II Pro Processor

Hardware Specifications

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

2Freescale Semiconductor

controller, dual I2C controllers, a 4-channel DMA controller, an enhanced secured digital host controller,

and a general-purpose I/O port. This figure shows the block diagram of the chip.

Figure 1. MPC8377E Block Diagram and Features

The following feature s are supported in the chip:

• e300c4s core built on Power Architecture® technology with 32 KB instruction cache and 32 KB

data cache, a floating point unit, and two integer units

• DDR1/DDR2 memory controller supporting a 32/64-bit interface

• Peripheral i nterfaces , such as a 32-bit PCI inter fac e with up to 66-MH z operatio n

• 32-bit local bus interface running up to 133-MHz

• USB 2.0 (full/high speed) support

• Power management controller for low-power consumption

• High degree of software compatibility with previous-generation Powe rQUICC processor-based

designs for backward compatibility and easier software migration

• Optional security engine provides acceleration for control and data plane security protocols

The optional security engine (SEC 3.0) is noted with the extension “E” at the end. It allows CPU-intensive

cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator

provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms.

MPC8377E

Security Enhanced

e300 Core

32 KB

I-Cache

32 KB

D-Cache

DUART

Dual I2C

Timers

GPIO

SPI

Interrupt

Controller

DDR1/DDR2

SDRAM

Controller

Local Bus

eTSEC

USB 2.0

Hi-Speed

Host Device RGMII, RMII,

RTBI, MII

SATA

PHY PHY

eTSEC

RGMII, RMII,

RTBI, MII

DMA PCI

PCI

Express

SD/MMC

Controller

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor 3

In addition to the security engine, new high-speed interfaces, such as PCI Express and SATA are included.

This table compares the differences between MPC837xE derivatives and provides the number of ports

available for each interface.

1.1 DDR Memory Controller

The DDR1/DDR2 memory controller include s the following features:

• Single 32- or 64-bit interface supporting both DDR1 and DDR2 SDRAM

• Support for up to 400-MHz data rate

• Support up to 4 chip selects

• 64-Mbit to 2-Gbit (for DDR1) and to 4-Gbit (for DDR2) devices with ×8/×16/×32 data ports (no

direct ×4 support)

• Support for up to 32 simultaneous open pages

• Supports auto refresh

• On-the-fly power management using CKE

• 1.8-/2.5-V SSTL2 compatibl e I/O

1.2 USB Dual-Role Controller

The USB controller includes the following feature s:

• Supports USB on-the-go mode , including both device and host functionality, when using an

external ULPI (UTMI + low-pin interface) PHY

• Complies with USB Specification, Rev. 2.0

• Supports operation as a stand-alone USB device

— Supports one upstream facing port

— Supports three programmable USB endpoints

• Supports operation as a stand-alone USB host controller

— Supports USB root hub with one downstream-facing port

— Enhanced host controller interfa ce (EHCI ) compatible

• Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operation;

low-speed operation is supported only in host mode

• Supports UTMI + low pin interface (ULPI)

Table 1. High-Speed Interfaces on the MPC8377E, MPC8378E, and MPC8379E

Descriptions MPC8377E MPC8378E MPC8379E

SGMII 020

PCI Express® 2 2 0

SATA 204

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

4Freescale Semiconductor

1.3 Dual Enhanced Three-Speed Ethernet Controllers (eTSECs)

The eTSECs include the following features:

• Two enhanced Ethernet inter f aces can be used for RGMII /MI I/RM I I/RT BI

• Two controllers conform to IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z,

IEEE 802.3au, IEEE 802.3ab, and IEEE Std 1588™ standards

• Support for W ake-on-Magic Packet™, a method to bring the device from standby to full operating

mode

• MII management interface for external PHY control and status

1.4 Integrated Programmable Interrupt Controller (IPIC)

The integrated programmable interrupt controller (IPIC) implements the necessary functions to provide a

flexible solution for general-purpose interrupt control. The IPIC programming model is compatible with

the MPC8260 interrupt controller, and it supports 8 external and 34 internal discrete interrupt sources.

Interrupts can also be redir ected to an external interrupt controller.

1.5 Power Management Controller (PMC)

The power management controller includes the following features:

• Provides power management when the device is used in both host and agent mode s

• Supports PCI Power Management 1.2 D0, D1, D2, and D3hot states

• Support for PME generation in PCI agent mode, PME detection in PCI host mode

• Supports Wake-on-LAN (Magic Packet), USB, GPIO, and PCI (PME input as host)

• Supports MPC8349E backward-compatibility mode

1.6 Serial Peripheral Interface (SPI)

The serial per ipheral int erface (SPI) allows the device to exchange data between other PowerQUICC

family chips, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs , real-time

clocks, A/D converters, and ISDN devices.

The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface

(rec eiv e, transmit, clock, and slave sele ct). The SPI block consist s of transmitter a nd receiver sections, an

independent baud-rate generator, and a control unit.

1.7 DMA Controller, Dual I2C, DUART, Enhanced Local Bus Controller

(eLBC), and Timers

The device provides an integrated four-channel DMA controller with the following features:

• Allows chaining (both extended and direct) through local memory-mapped chain descriptors

(acces si ble by local ma st er s)

• Supports misaligned transfers

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor 5

There are two I2C controllers. These synchronous, multi-master buses can be connected to additional

devices for expansion and system development.

The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550

programming models. 16-byte FIFOs are supported for both the tra nsmitter and the receiver.

The main component of the enhanced local bus controller (eLBC) is its memory controller, which provides

a seamless interface to many types of memory devices and peripherals. The memory controller is

responsible for controlling e ight memory banks shared by a NAND Flash control machine (FCM), a

general-purpose chip-select machine (GPCM), and up to three user-programmable machines (UPMs). As

such, it supports a minimal glue logic interface to SRAM, EPROM, NOR Flash EP ROM , NAND Flash,

EPROM, burstable RAM, regular DRAM devices, extended data output DRAM devices, and other

peripherals. The eLBC external address latch enable (LALE) signal allows multiplexing of addresses with

data signals to reduce the device pin count.

The enhanced local bus controller also includes a number of data checking and protection features, such

as data parity generation and checking, write protection, and a bus monitor to ensure that each bus cycle

is terminated withi n a user-specified period. The local bus can operate at up to 133 MHz.

The system timers include the following features: periodic interrupt timer, real time clock, software

watchdog timer, and two general-purpose timer blocks.

1.8 Security Engine

The optional security engine is opt imize d to handle all the algorithm s associated with IPSec,

IEEE 802.11i, and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto

execution units (EUs). The execution units are as follows:

• Data encryption standard execution unit (DEU), supporting DES and 3D ES

• Advanced encryption standard unit (AESU), supporting AES

• Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-256, and HMAC with any

algorithm

• One crypto-channel supporting multi-command descriptor chains

1.9 PCI Controller

The PCI controller includes the following features:

•PCI Specification Revision 2.3 compatible

• Single 32-bit data PCI interfac e operates at up to 66 MHz

• PCI 3.3-V compatible (not 5-V compatible)

• Support for host and agent modes

• On-chip arbitration, supporting 5 external masters on PCI

• Selectable hardware-enfor ced coherency

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

6Freescale Semiconductor

1.10 PCI Express Controller

The PCI Express controller includes the following features:

• PCI Express 1.0a compatible

•Two ×1 links or one ×2 link width

• Auto-detection of number of connected lanes

• Selectable operation as root complex or endpoint

• Both 32- and 64-bit addressing

• 128-byte maximum payload size

• Support for MSI and INTx interrupt messages

• Virtual channel 0 only

• Select able Traffic Class

• Full 64-bit decode with 32-bit wide windows

• Dedicated four channel descriptor -based DMA engine per interface

1.11 Serial ATA (SATA) Controllers

The serial ATA (SATA) controllers have the following features:

• Supports Ser ial ATA Rev 2.5 Specification

• Spread spectrum clocking on receive

• Asynchronous notificat ion

• Hot Plug including asynchronous signal recovery

• Link power manageme nt

• Native command queuing

• Staggered spin-up and port multiplier support

• Port multiplier support

• SATA 1.5 and 3.0 Gb/s operation

• Interrupt driven

• Power management support

• Error handling and diagnostic features

— Far end/near end loopback

— Failed CRC error re porting

— Increased ALIGN insertion rates

• Scrambling and CONT override

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor 7

1.12 Enhanced Secured Digital Host Controller (eSDHC)

The enhanced SD host controller (eSDHC) has the following features:

• Conforms to S D Host Controller Standard Specification, Rev 2.0 with Test Event register support.

• Compatible wi th the MMC System Specification, Rev 4.0

• Compatible wi th the SD Memory Card Specification, Rev 2.0, and supports High Capacity SD

memory cards

• Compatible wi th the SDIO Card Specification Rev, 1.2

• Designed to work with SD Memory, miniSD Memory, SDIO, miniSD IO, SD Co mbo, MMC,

MMCplus, MMC 4x, and RS-MMC cards

• SD bus clock frequency up to 50 MHz

• Supports 1-/4-bit SD and SDIO modes, 1-/4-bit MMC modes

• Supports internal DMA capabilities

2 Electrical Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the chip. The

device is currently targeted to these specifications. Some of these specifications are independent of the I/O

cell, but are included for a more complete reference. These are not purely I/O buff er design specifications.

2.1 Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

2.1.1 Absolute Maximum Ratings

This table provides the absolute maximum ratings.

Table 2. Absolute Maximum Ratings1

Characteristic Symbol Max Value Unit Note

Core supply voltage VDD –0.3 to 1.1 V —

PLL supply voltage (e300 core, eLBC, and system) AVDD –0.3 to 1.1 V —

DDR1 and DDR2 DRAM I/O voltage GVDD –0.3 to 2.75

–0.3 to 1.98

V—

Three-speed Ethernet I/O, MII management voltage LVDD[1,2] –0.3 to 3.63 V —

PCI, DUART, system control and power management, I2C, and

JTAG I/O voltage

OVDD –0.3 to 3.63 V —

Local bus LBVDD –0.3 to 3.63 V —

SerDes L[1,2]_

VDD –0.3 to 1.1 V 6

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

8Freescale Semiconductor

2.1.2 Power Supply Voltage Specification

This table provides recommended operating conditions for the device. Note that the values in this table are

the recommended and tested operating conditions. Proper device operation outside of these conditions is

not guaranteed.

Input voltage DDR DRAM signals MVIN –0.3 to (GVDD + 0.3) V 2, 4

DDR DRAM reference MVREF –0.3 to (GVDD + 0.3) V 2, 4

Three-speed Ethernet signals LVIN –0.3 to (LVDD + 0.3) V —

PCI, DUART, CLKIN, system control and power

management, I2C, and JTAG signals

OVIN –0.3 to (OVDD + 0.3) V 3, 4, 5

Local Bus LBIN –0.3 to (LBVDD + 0.3) V —

Storage temperature range TSTG –55 to 150 °C—

Notes:

1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause

permanent damage to the device.

2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

4. (M,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

5. Overshoot/undershoot by OVIN on the PCI interface does not comply to the

PCI Electrical Specification

for 3.3-V operation,

as shown in Figure 2.

6. L[1,2]_

VDD includes SDAVDD_0, XCOREVDD, and XPADVDD power inputs.

Table 3. Recommended Operating Conditions

Characteristic Symbol Recommended

Value Unit Note

Core supply voltage up to 667 MHz VDD 1.0 ± 50 mV V 1

800 MHz 1.05 ± 50 mV V 1

PLL supply voltage (e300 core, eLBC and

system)

up to 667 MHz AVDD 1.0 ± 50 mV V 1, 2

800 MHz 1.05 ± 50 mV V 1, 2

DDR1 and DDR2 DRAM I/O voltage GVDD 2.5 V ± 125 mV

1.8 V ± 90 mV

Three-speed Ethernet I/O, MII management voltage LVDD[1,2] 3.3 V ± 165 mV

2.5 V ± 125 mV

V—

PCI, local bus, DUART, system control and power management, I2C, and

JTAG I/O voltage

OVDD 3.3 V ± 165 mV V 1

Local Bus LBVDD 1.8 V ± 90 mV

2.5 V ± 125 mV

3.3 V ± 165 mV

V—

Table 2. Absolute Maximum Ratings1 (continued)

Characteristic Symbol Max Value Unit Note

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor 9

This figure shows the undershoot and overshoot voltages at the interfaces of the device.

Figure 2. Overshoot/Undershoot Voltage for GVDD/LVDD/OVDD/LBVDD

SerDes up to 667 MHz L[1,2]_

VDD 1.0 ± 50 mV V 1, 3

800 MHz 1.05 V ± 50 mV V 1, 3

Operating temperature range commerical Ta

Ta=0 (min)—

Tj=125 (max)

°C—

extended temperature Ta

Ta=–40 (min)—

Tj=125 (max)

°C—

Notes:

1. GVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or negative

direction.

2. AVDD is the input to the filter discussed in Section 25.1, “PLL Power Supply Filtering,” and is not necessarily the voltage at

the AVDD pin.

3. L[1,2]_

VDD, SDAVDD_0, XCOREVDD, and XPADVDD power inputs.

Table 3. Recommended Operating Conditions (continued)

Characteristic Symbol Recommended

Value Unit Note

GND

GND – 0.3 V

GND – 0.7 V Not to Exceed 10%

G/L/O/LBVDD + 20%

G/L/O/LBVDD

G/L/O/LBVDD + 5%

of tinterface1

1. Note that tinterface refers to the clock period associated with the bus clock interface.

VIH

VIL

Note:

2. Note that with the PCI overshoot allowed (as specified above), the device does

not fully comply with the maximum AC ratings and device protection guideline outlined in

the

PCI Rev. 2.3 Specification

(Section 4.2.2.3).

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

10 Freescale Semiconductor

2.1.3 chipOutput Driver Characteristics

This table provides information on the characteristics of the output driver strengths. The values are

prelimina ry estimates .

2.2 Power Sequencing

The device requires its power rails to be applied in a specific sequence in order to ensure proper device

operation. During the power ramp up, before the power supplies are stable and if the I/O voltages are

supplied before the core voltage, there may be a period of time t hat all input and out put pins will actively

be driven and cause contention and excessive current. To avoid actively driving the I/O pins and to

elimin ate exces sive curre nt dra w, apply the core voltages (VDD and AVDD) before the I/O voltages and

as sert POR ESE T before the power supplies fully ramp up. VDD and AVDD must reach 90% of their

nominal value before GVDD, LV DD, and OVDD reach 10% of the ir value, see the following figure. I/O

Table 4. Output Drive Capability

Driver Type1Output Impedance (Ω) Supply Voltage

Local bus interface utilities signals 45 LBVDD = 2.5 V, 3.3 V

40 LBVDD = 1.8 V

PCI signals 25 OVDD = 3.3 V

DDR1 signal 18 GVDD = 2.5 V

DDR2 signal 18 GVDD = 1.8 V

eTSEC 10/100/1000 signals 45 LVDD = 2.5 V, 3.3 V

DUART, system control, I2C, JTAG, SPI, and USB 45 OVDD = 3.3 V

GPIO signals 45 OVDD = 3.3 V

Note:

1. Specialized SerDes output capabilities are described in the relevant sections of these specifications (such as PCI Express

and SATA)

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor 11

voltage supplies—GVDD, LVDD, and OVDD—do not have any ordering requirements wit h respect to one

another.

Figure 3. Power-Up Sequencing Example

Note that the SerDes power supply (L[1,2]_nVDD) should follow the same timing as the core supply

(VDD).

The device does not require the core supply voltage and I/O supply voltages to be powered down in any

particular orde r.

3 Power Characteristics

The estimated typical power dissipation for the chip device is shown in this table.

Table 5. Power Dissipation 1

Core Frequency

(MHz)

CSB/DDR Frequency

(MHz)

Sleep Power

at Tj=65°C (W) 2

Typical Application

at Tj=65°C (W) 2

Typical Application

at Tj=125°C (W) 3

Max Application

at Tj=125°C (W) 4

333

333 1.45 1.9 3.2 3.8

167 1.45 1.8 3.0 3.6

400

400 1.45 2.0 3.3 4.0

266 1.45 1.9 3.1 3.8

450

300 1.45 2.0 3.2 3.8

225 1.45 1.9 3.1 3.7

500

333 1.45 2.0 3.3 3.9

250 1.45 1.9 3.2 3.8

533

355 1.45 2.0 3.3 4.0

266 1.45 2.0 3.2 3.9

90%

Core Voltage (VDD, AVDD)

I/O Voltage (GVDD, LVDD, and OVDD)

0.7 V

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

12 Freescale Semiconductor

This table shows the estimated typical I/O power dissipation for the device.

600

400 1.45 2.1 3.4 4.1

300 1.45 2.0 3.3 4.0

667

333 1.45 2.1 3.3 4.1

266 1.45 2.0 3.3 3.9

800 400 1.45 2.5 3.8 4.3

Notes:

1. The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD. For I/O power values, see Ta bl e 6 .

2. Typical power is based on a voltage of VDD = 1.0 V for core frequencies ≤667 MHz or VDD = 1.05 V for core frequencies of

800 MHz, and running a Dhrystone benchmark application.

3. Typical power is based on a voltage of VDD = 1.0 V for core frequencies ≤667 MHz or VDD = 1.05 V for core frequencies of

800 MHz, and running a Dhrystone benchmark application.

4. Maximum power is based on a voltage of VDD = 1.0 V for core frequencies ≤667 MHz or VDD = 1.05 V for core frequencies

of 800 MHz, worst case process, and running an artificial smoke test.

Table 6. Typical I/O Power Dissipation

Interface Parameter GVDD

(1.8 V)

GVDD/LBVDD

(2.5 V)

OVDD

(3.3 V)

LVDD

(3.3 V)

LVDD

(2.5 V)

L[1,2]_

VDD

(1.0 V) Unit Comments

DDR I/O

65%

utilization

2 pair of

clocks

200 MHz data

rate, 32-bit

0.28 0.35 — — — — W —

200 MHz data

rate, 64-bit

0.41 0.49 — — — — W

266 MHz data

rate, 32-bit

0.31 0.4 — — — — W

266 MHz data

rate, 64-bit

0.46 0.56 — — — — W

300 MHz data

rate, 32-bit

0.33 0.43 — — — — W

300 MHz data

rate, 64-bit

0.48 0.6 — — — — W

333 MHz data

rate, 32-bit

0.35 0.45 — — — — W

333 MHz data

rate, 64-bit

0.51 0.64 — — — — W

400 MHz

data rate,

32-bit

0.38 — — — — — W

400 MHz

data rate,

64-bit

0.56 — — — — — W

Table 5. Power Dissipation 1 (continued)

Core Frequency

(MHz)

CSB/DDR Frequency

(MHz)

Sleep Power

at Tj=65°C (W) 2

Typical Application

at Tj=65°C (W) 2

Typical Application

at Tj=125°C (W) 3

Max Application

at Tj=125°C (W) 4

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor 13

4 Clock Input Timing

This section provides the clock input DC and AC electrical characteristics for the chip. Note that the

PCI_CLK/PCI_SYNC_IN signal or CLK IN signal is used as the PCI input clock depending on whether

the device is configured as a host or agent device. CLKIN is used when the device is in host mode.

PCI I/O

Load =

30 pf

33 MHz,

32-bit

— — 0.04 — — — W —

66 MHz,

32-bit

— — 0.07 — — — W

Local Bus

I/O

Load =

25 pf

167 MHz,

32-bit

0.09 0.17 0.29 — — — W —

133 MHz,

32-bit

0.07 0.14 0.24 — — — W

83 MHz,

32-bit

0.05 0.09 0.15 — — — W

66 MHz,

32-bit

0.04 0.07 0.13 — — — W

50 MHz,

32-bit

0.03 0.06 0.1 — — — W

eTSEC I/O

Load =

25 pf

MII or RMII — — — 0.02 — — W Multiply by

number of

interfaces used.

RGMII or

RTBI

— — — — 0.05 — W —

USB

(60MHz

Clock)

12 Mbps — — 0.01 — — — W —

480 Mbps — — 0.2 — — — W

SerDes per lane — — — — 0.029 W —

Other I/O — — — 0.01 — — — W —

Note: The values given are for typical, and not worst case, switching.

Table 6. Typical I/O Power Dissipation (continued)

Interface Parameter GVDD

(1.8 V)

GVDD/LBVDD

(2.5 V)

OVDD

(3.3 V)

LVDD

(3.3 V)

LVDD

(2.5 V)

L[1,2]_

VDD

(1.0 V) Unit Comments

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

14 Freescale Semiconductor

4.1 DC Electrical Characteristics

This table provides the clock input (CLKIN/PCI_CLK) DC timing specifications for the device.

4.2 AC Electrical Characteristics

The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, de pending on

whether the device is configured in PCI host or PCI agent mode. This table provides the clock input

(CLKIN/PCI_CLK) AC timing spec ifications for the device.

Table 7. CLKIN DC Electrical Characteristics

Parameter Condition Symbol Min Max Unit Note

Input high voltage — VIH 2.7 OVDD + 0.3 V 1

Input low voltage — VIL –0.3 0.4 V 1

CLKIN Input current 0 V ≤VIN ≤ OVDD IIN —± 10μA—

PCI_CLK Input current 0 V ≤VIN ≤ 0.5 V or

OVDD – 0.5 V ≤VIN ≤ OVDD

IIN —± 30μA—

Note:

1. In PCI agent mode, this specification does not comply with

PCI 2.3 Specification

Table 8. CLKIN AC Timing Specifications

Parameter Symbol Min Typical Max Unit Note

CLKIN/PCI_CLK frequency fCLKIN 25 — 66.666 MHz 1, 6

CLKIN/PCI_CLK cycle time tCLKIN 15 — 40 ns —

CLKIN/PCI_CLK rise and fall time tKH, tKL 0.6 1.0 2.3 ns 2

CLKIN/PCI_CLK duty cycle tKHK/tCLKIN 40 — 60 % 3

CLKIN/PCI_CLK jitter — — — ± 150 ps 4, 5

Notes:

1. Caution: The system, core and security block must not exceed their respective maximum or minimum operating

frequencies.

2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter-short term and long term-and is guaranteed by design.

5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low

to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.

6. Spread spectrum is allowed up to 1% down-spread on CLKIN/PCI_CLK up to 60 KHz.

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor 15

4.3 eTSEC Gigabit Reference Clock Timing

This table provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications.

5 RESET Initialization

This section describes the DC and AC electrical specifications for the reset initialization timing and

electri cal requir ement s of the chip.

5.1 RESET DC Electrical Characteristics

This table provides the DC electri cal chara cteri stics for the RESET pins of the device.

Table 9. EC_GTX_CLK125 AC Timing Specifications

At recommended operating conditions with LVDD = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV

Parameter/Condition Symbol Min Typical Max Unit Note

EC_GTX_CLK125 frequency tG125 — 125 — MHz —

EC_GTX_CLK125 cycle time tG125 —8—ns—

EC_GTX_CLK rise and fall time

LV DD = 2.5 V

LV DD = 3.3 V

tG125R/tG125F ——

0.75

1.0

ns 1

EC_GTX_CLK125 duty cycle

1000Base-T for RGMII, RTBI

tG125H/tG125

—

EC_GTX_CLK125 jitter — — — ±150 ps 2

Notes:

1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for LVDD = 2.5 V and from 0.6 and 2.7 V for

LVDD =3.3V.

2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. The

EC_GTX_CLK125 duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle

generated by the eTSEC GTX_CLK. See Section 8.2.2, “RGMII and RTBI AC Timing Specifications,” for the duty cycle for

10Base-T and 100Base-T reference clock.

Table 10. RESET Pins DC Electrical Characteristics

Characteristic Symbol Condition Min Max Unit

Input high voltage VIH —2.0OV

DD + 0.3 V

Input low voltage VIL — –0.3 0.8 V

Input current IIN ——± 30μA

Output high voltage VOH IOH = –8.0 mA 2.4 — V

Output low voltage VOL IOL = 8.0 mA — 0.5 V

Output low voltage VOL IOL = 3.2 mA — 0.4 V

Notes:

• This table applies for pins PORESET and HRESET. The PORESET is input pin, thus stated output voltages are not relevant.

• HRESET and SRESET are open drain pin, thus VOH is not relevant for these pins.

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

16 Freescale Semiconductor

5.2 RESET AC Electrical Characteristics

This table provides the reset initia lization AC timing specifications of the device.

Table 12 provides the PLL l ock times .

6 DDR1 and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the chip.

Note that DDR1 SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.

Table 11. RESET Initialization Timing Specifications

Parameter/Condition Min Max Unit Note

Required assertion time of HRESET to activate reset flow 32 — tPCI_SYNC_IN 1

Required assertion time of PORESET with stable clock applied to CLKIN when

the device is in PCI host mode

32 — tCLKIN 2

Required assertion time of PORESET with stable clock applied to PCI_CLK when

the device is in PCI agent mode

32 — tPCI_SYNC_IN 1

HRESET assertion (output) 512 — tPCI_SYNC_IN 1

HRESET negation to negation (output) 16 — tPCI_SYNC_IN 1

Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],

CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET

when the device is in PCI host mode

4— t

CLKIN 2

Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],

CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET

when the device is in PCI agent mode

4—t

PCI_SYNC_IN 1

Input hold time for POR config signals with respect to negation of HRESET 0— ns —

Time for the device to turn off POR config signals with respect to the assertion of

HRESET

—4 ns 3

Time for the device to start driving functional output signals multiplexed with the

POR configuration signals with respect to the negation of HRESET

1—t

PCI_SYNC_IN 1, 3

Notes:

1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary

clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the

MPC8379E Integrated Host Processor Reference Manual

for more details.

2. tCLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode. See the

MPC8379E Integrated Host Processor Reference Manual

for more details.

3. POR config signals consists of CFG_RESET_SOURCE[0:3], CFG_LBMUX, and CFG_CLKIN_DIV.

Table 12. PLL Lock Times

Parameter Min Max Unit Note

PLL lock times — 100 μs—

Note:

• The device guarantees the PLL lock if the clock settings are within spec range. The core clock also depends on the core PLL

ratio. See Section 23, “Clocking,” for more information.

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor 17

6.1 DDR1 and DDR2 SDRAM DC Electrical Characteristics

This table provides the recommended operating conditions for the DDR2 SDRAM component(s) of the

device when GVDD(typ) = 1.8 V.

Table 14 provides the DDR2 capacitance when GVDD(typ) = 1.8 V.

This table provides the recommended operating conditions for the DDR SDRAM component(s) when

GVDD(typ) = 2.5 V.

Table 13. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V

Parameter Symbol Min Max Unit Note

I/O supply voltage GVDD 1.71 1.89 V 1

I/O reference voltage MVREF 0.49 ×GVDD 0.51 ×GVDD V2, 5

I/O termination voltage VTT MVREF –0.04 MV

REF +0.04 V 3

Input high voltage VIH MVREF + 0.140 GVDD +0.3 V —

Input low voltage VIL –0.3 MVREF – 0.140 V —

Output leakage current IOZ –50 50 μA4

Output high current (VOUT =1.40V) I

OH –13.4 — mA —

Output low current (VOUT =0.3V) I

OL 13.4 — mA —

Notes:

1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.

2. MVREF is expected to be equal to 0.5 ×GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF

. This rail should track variations in the DC level of MVREF

4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.

5. See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.

Table 14. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V

Parameter Symbol Min Max Unit Note

Input/output capacitance: DQ, DQS, DQS CIO 68pF1

Delta input/output capacitance: DQ, DQS, DQS CDIO —0.5pF1

Note:

1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.

Table 15. DDR SDRAM DC Electrical Characteristics for GVDD (typ) = 2.5 V

Parameter Symbol Min Max Unit Note

I/O supply voltage GVDD 2.375 2.625 V 1

I/O reference voltage MVREF 0.49 × GVDD 0.51 × GVDD V2, 5

I/O termination voltage VTT MVREF – 0.04 MVREF + 0.04 V 3

Input high voltage VIH MVREF + 0.18 GVDD + 0.3 V —

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

18 Freescale Semiconductor

Table 16 provides the DDR capacitance when GVDD(typ) = 2.5 V.

This table provides the current draw c haracteristics for MVREF.

Input low voltage VIL –0.3 MVREF – 0.18 V —

Output leakage current IOZ –50 50 μA4

Output high current (VOUT = 1.9 V) IOH –15.2 — mA —

Output low current (VOUT = 0.38 V) IOL 15.2 — mA —

Notes:

1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.

2. MVREF is expected to be equal to 0.5 × GVDD

, and to track GVDD DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF

. This rail should track variations in the DC level of MVREF

4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD

5. See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.

Table 16. DDR SDRAM Capacitance for GVDD (typ) = 2.5 V

Parameter Symbol Min Max Unit Note

Input/output capacitance: DQ, DQS CIO 68pF1

Delta input/output capacitance: DQ, DQS CDIO —0.5pF1

Note:

1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA= 25°C, VOUT =GV

DD/2, VOUT (peak-to-peak) = 0.2 V.

Table 17. Current Draw Characteristics for MVREF

Parameter Symbol Min Typ Max Unit Note

Current draw for MVREF

DDR1

DDR2

IMVREF

—

250

150

600

400

μA1, 2

Note:

1. The voltage regulator for MVREF must be able to supply up to the stated maximum current.

2. This current is divided equally between MVREF1 and MVREF2, where half the current flows through each pin.

Table 15. DDR SDRAM DC Electrical Characteristics for GVDD (typ) = 2.5 V (continued)

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor 19

6.2 DDR1 and DDR2 SDRAM AC Electrical Characteristics

This section provides the AC electr ical characteristic s for the DDR S DRAM interfac e.

6.2.1 DDR1 and DDR2 SDRAM Input AC Timing Specifications

This table provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8 V.

This table provides the input AC timing specifications for the DDR1 SDRAM when GVDD(typ) = 2.5 V.

This table provides the input AC timing specificati ons for the DDR1 and DDR2 SDRAM interface.

Table 18. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

Parameter Symbol Min Max Unit

AC input low voltage VIL —MV

REF – 0.25 V

AC input high voltage VIH MVREF + 0.25 — V

Table 19. DDR1 SDRAM Input AC Timing Specifications for 2.5-V Interface

Parameter Symbol Min Max Unit

AC input low voltage VIL —MV

REF – 0.31 V

AC input high voltage VIH MVREF + 0.31 — V

Table 20. DDR1 and DDR2 SDRAM Input AC Timing Specifications

Parameter Symbol Min Max Unit Note

Controller skew for MDQS-MDQ/MECC/MDM

400 MHz data rate

333 MHz data rate

266 MHz data rate

tCISKEW

–500

–750

500

750

ps 1, 2

—

Note:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS

and any corresponding bit that

will be captured with MDQS

. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be

determined by the following equation: tDISKEW = ±[T/4 – |tCISKEW|] where T is the MCK clock period and |tCISKEW| is the

absolute value of tCISKEW.

3. This specification applies only to DDR2 interface.

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

20 Freescale Semiconductor

6.2.2 DDR1 and DDR2 SDRAM Output AC Timing Specifications

This table shows the DDR1 and DDR2 SDRAM output AC timing specifications.

Table 21. DDR1 and DDR2 SDRAM Output AC Timing Specifications

Parameter Symbol1Min Max Unit Note

MCK

cycle time, MCK

/MCK

crossing tMCK 510ns2

ADDR/CMD output setup with respect to MCK

400 MHz data rate

333 MHz data rate

266 MHz data rate

200 MHz data rate

tDDKHAS

1.95

2.40

3.15

4.20

—

ns 3, 7

ADDR/CMD output hold with respect to MCK

400 MHz data rate

333 MHz data rate

266 MHz data rate

200 MHz data rate

tDDKHAX

1.95

2.40

3.15

4.20

—

ns 3, 7

MCS

output setup with respect to MCK

400 MHz data rate

333 MHz data rate

266 MHz data rate

200 MHz data rate

tDDKHCS

1.95

2.40

3.15

4.20

—

ns 3

MCS

output hold with respect to MCK

400 MHz data rate

333 MHz data rate

266 MHz data rate

200 MHz data rate

tDDKHCX

1.95

2.40

3.15

4.20

—

ns 3

MCK to MDQS skew tDDKHMH –0.6 0.6 ns 4, 8

MDQ//MDM output setup with respect to MDQS

400 MHz data rate

333 MHz data rate

266 MHz data rate

200 MHz data rate

tDDKHDS,

tDDKLDS 550

800

1100

1200

—

ps 5, 8

MDQ//MDM output hold with respect to MDQS

400 MHz data rate

333 MHz data rate

266 MHz data rate

200 MHz data rate

tDDKHDX,

tDDKLDX 700

800

1100

1200

—

ps 5, 8

MDQS preamble start tDDKHMP –0.5 × tMCK –0.6 –0.5 × tMCK + 0.6 ns 6, 8

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor 21

The minimum frequency for DDR2 is 250 MHz data rate (125 MHz clock), 167 MHz data rate (83 MHz

clock) for DDR1. This figure shows the DDR1 and DDR 2 SDRAM output timing for t he MCK to MDQS

skew measurement (tDDKHMH).

Figure 4. DDR Timing Diagram for tDDKHMH

MDQS epilogue end tDDKHME –0.6 0.6 ns 6, 8

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until

outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock

reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ//MDM/MDQS.

4. Note that tDDKHMH follows the symbol conventions described in Note 1. For example, tDDKHMH describes the DDR timing

(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through

control of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock

adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set

to the same adjustment value. See the

MPC8379E PowerQUICC II Pro Host Processor Reference Manual

for a description

and understanding of the timing modifications enabled by use of these bits.

5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data MDQ, ECC, or

data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

6. All outputs are referenced to the rising edge of MCK

at the pins of the microprocessor. Note that tDDKHMP follows the

symbol conventions described in Note 1.

7. Clock Control register is set to adjust the memory clocks by 1/2 the applied cycle.

8. See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.

Table 21. DDR1 and DDR2 SDRAM Output AC Timing Specifications (continued)

Parameter Symbol1Min Max Unit Note

MDQS

MCK[n]

tMCK

tDDKHMHmax) = 0.6 ns

tDDKHMH(min) = –0.6 ns

MDQS

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

22 Freescale Semiconductor

This figure shows the DDR1 and DDR2 SDRAM output timing diagram.

Figure 5. DDR1 and DDR2 SDRAM Output Timing Diagram

This figure provides AC test load for the DDR bus.

Figure 6. DDR AC Test Load

7DUART

This section describes the DC and AC electrical s pecif ications for the DUART inte rface of the chip.

7.1 DUART DC Electrical Characteristics

This table provides the DC electrical characteristics for the DUART interface of the device.

Table 22. DUART DC Electrical Characteristics

Parameter Symbol Min Max Unit

High-level input voltage VIH 2OV

DD + 0.3 V

Low-level input voltage OVDD VIL –0.3 0.8 V

High-level output voltage,

IOH = –100 μA

VOH OVDD – 0.2 — V

ADDR/CMD

tDDKHAS ,tDDKHCS

tDDKHMH

tDDKLDS

tDDKHDS

MDQ[x]

MDQS[n]

MCK[n]

MCK[n] tMCK

tDDKLDX

tDDKHDX

D1D0

tDDKHAX ,tDDKHCX

Write A0 NOOP

tDDKHME

tDDKHMP

Output Z0 = 50 Ω

RL = 50 Ω

GVDD/2

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor 23

7.2 DUART AC Electrical Specifications

this table provides the AC timing parameters for the DUART interface of the device.

8 Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

This section provides the AC and DC electrical characteristics for the enhanced three-speed Ethernet

controller.

8.1 Enhanced Three-Speed Ethernet Controller (eTSEC)

(10/100/1000 Mbps)—MII/RGMII/RTBI/RMII DC Electrical

Characteristics

The electrical char acter isti cs spe ci fied here apply to media independent interface (MII), r educed gigabit

media independent interface (RGMII), reduced ten-bit interface (RTB I), reduced media independent

interface (RMII) signals, management data input/output (MDIO) and management data clock (MDC).

The MII and RMII interfaces are defined for 3.3 V, while the RGMII and RTBI interfaces can be operated

at 2.5 V. The RGMII and RTBI interfac es follow the R educed Gigabit Media-I ndependent Interface

(RGMI I) Spec ification Version 1.3. The RMII interface foll ows the R MI I Consor tium RMII Spe cific ation

Version 1.2.

Low-level output voltage,

IOL = 100 μA

VOL —0.2 V

Input current,

(0 V ≤VIN ≤ OVDD)

IIN —±30μA

Note: The symbol VIN, in this case, represents the OVIN symbol referenced in Table 2.

Table 23. DUART AC Timing Specifications

Parameter Value Unit Note

Minimum baud rate 256 baud —

Maximum baud rate > 1,000,000 baud 1

Oversample rate 16 — 2

Notes:

1. Actual attainable baud rate will be limited by the latency of interrupt processing.

2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are

sampled each 16th sample.

Table 22. DUART DC Electrical Characteristics (continued)

Parameter Symbol Min Max Unit

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

24 Freescale Semiconductor

8.1.1 MII, RMII, RGMII, and RTBI DC Electrical Characteristics

MII and RMII drivers and receivers comply with the DC parametric attributes specified in Table 24 and

Table 25. The RGMII a n d RTBI sig na l s i n Table 25 are based on a 2.5 V CM OS interface voltage as

defined by JEDEC EIA/JESD8-5.

Table 24. MII and RMII DC Electrical Characteristics

Parameter Symbol Min Max Unit Note

Supply voltage 3.3 V LVDD1

LV DD2

3.13 3.47 V 1

Output high voltage

(LVDD1/LVDD2 = Min, IOH = –4.0 mA)

VOH 2.40 LVDD1/LVDD2 + 0.3 V —

Output low voltage

(LVDD1/LVDD2 = Min, IOL = 4.0 mA)

VOL GND 0.50 V —

Input high voltage VIH 2.0 LVDD1/LVDD2 + 0.3 V —

Input low voltage VIL –0.3 0.90 V —

Input high current

(VIN = LVDD1, VIN = LVDD2)

IIH —30μA1

Input low current

(VIN = GND)

IIL –600 — μA—

Notes:

1. LVDD1 supports eTSEC 1. LVDD2 supports eTSEC 2.

Table 25. RGMII and RTBI DC Electrical Characteristics

Parameter Symbol Min Max Unit Note

Supply voltage 2.5 V LVDD1

LVDD2

2.37 2.63 V 1

Output high voltage

(LVDD1/LVDD2 = Min, IOH = –1.0 mA)

VOH 2.00 LVDD1/LVDD2 + 0.3 V —

Output low voltage

(LVDD1/LVDD2 = Min, IOL = 1.0 mA)

VOL GND – 0.3 0.40 V —

Input high voltage VIH 1.7 LVDD1/LVDD2 + 0.3 V —

Input low voltage VIL –0.3 0.70 V —

Input high current

(VIN = LVDD1, VIN = LVDD2)

IIH —–20μA1

Input low current

(VIN = GND)

IIL –20 — μA—

Notes:

1. LVDD1 supports eTSEC 1. LVDD2 supports eTSEC 2.

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor 25

8.2 MII, RGMII, RMII, and RTBI AC Timing Specifications

The AC timing specifications for MII, RGMII, RMII, and RTBI are presented in this section.

8.2.1 MII AC Timing Specifications

This section describes the MII transm it and receive AC timing specifications.

8.2.1.1 MII Transmit AC Timing Specifications

This table provides the MII trans mit AC timing specifica tions .

This figur e shows the MII transmit AC timing diagra m.

Figure 7. MII Transmit AC Timing Diagram

Table 26. MII Transmit AC Timing Specifications

At recommended operating conditions with LVDD of 3.3 V ± 5%.

Parameter Symbol1Min Typical Max Unit

TX_CLK clock period 10 Mbps tMTX — 400 — ns

TX_CLK clock period 100 Mbps tMTX —40—ns

TX_CLK duty cycle tMTXH/tMTX 35 — 65 %

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay tMTKHDX 1 5 15 ns

TX_CLK data clock rise (20%–80%) tMTXR 1.0 — 4.0 ns

TX_CLK data clock fall (80%–20%) tMTXF 1.0 — 4.0 ns

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII

transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in

general, the clock reference symbol representation is based on two to three letters representing the clock of a particular

functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

TX_CLK

TXD[3:0]

tMTKHDX

tMTX

tMTXH

tMTXR

tMTXF

TX_EN

TX_ER

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

26 Freescale Semiconductor

8.2.1.2 MII Receive AC Timing Specifications

This table provides the MII receive AC timing spec ifications.

This figure provides the AC test load for eTSEC.

Figure 8. eTSEC AC Test Load

Table 27. MII Receive AC Timing Specifications

At recommended operating conditions with LVDD of 3.3 V ± 5%.

Parameter Symbol1Min Typical Max Unit

Input low voltage VIL ——0.7V

Input high voltage VIH 1.9 — — V

RX_CLK clock period 10 Mbps tMRX — 400 — ns

RX_CLK clock period 100 Mbps tMRX —40—ns

RX_CLK duty cycle tMRXH/tMRX 35 — 65 %

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK tMRDVKH 10.0 — — ns

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK tMRDXKH 10.0 — — ns

RX_CLK clock rise time (20%–80%) tMRXR 1.0 — 4.0 ns

RX_CLK clock fall time (80%–20%) tMRXF 1.0 — 4.0 ns

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH

symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the

tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with

respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state

or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock

of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times,

the latter convention is used with the appropriate letter: R (rise) or F (fall).

Output Z0 = 50 ΩLVDD/2

RL = 50 Ω

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor 27

This figure shows the MII receive AC timing diagr am.

Figure 9. MII Receive AC Timing Diagram

8.2.2 RGMII and RTBI AC Timing Specifications

This table presents the RGMII and RTBI AC timing specif ication s.

Table 28. RGMII and RTBI AC Timing Specifications

At recommended operating conditions with LVDD of 2.5 V ± 5%.

Parameter Symbol1Min Typical Max Unit Note

Data to clock output skew (at transmitter) tSKRGT –600 0 600 ps —

Data to clock input skew (at receiver) tSKRGT 1.0 — 2.8 ns 2

Clock period tRGT 7.2 8.0 8.8 ns 3

Duty cycle for 1000Base-T tRGTH/tRGT 45 50 55 % 4

Duty cycle for 10BASE-T and 100BASE-TX tRGTH/tRGT 40 50 60 % 3, 4

Rise time (20%–80%) tRGTR — — 0.75 ns —

Fall time (20%–80%) tRGTF — — 0.75 ns —

EC_GTX_CLK125 reference clock period tG12 —8.0—ns5

EC_GTX_CLK125 reference clock duty cycle

measured at 0.5 ×LV DD1

tG125H/tG125 47 — 53 % —

Notes:

1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent

RGMII and RTBI timing. Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being

represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).

2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns

will be added to the associated clock signal.

3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as

long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed

transitioned between

5. This symbol represents the external EC_GTX_CLK125 and does not follow the original signal naming convention.

RX_CLK

RXD[3:0]

tMRDXKL

tMRX

tMRXH

tMRXR

tMRXF

RX_DV

RX_ER

tMRDVKH

Valid Data

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

28 Freescale Semiconductor

This figure provides the AC test load for eTSEC.

Figure 10. eTSEC AC Test Load

This figure shows the RGMII and RTBI AC timing and multiplexing diagrams.

Figure 11. RGMII and RTBI AC Timing and Multiplexing Diagrams

Output Z0 = 50 ΩLVDD/2

RL = 50 Ω

GTX_CLK

tRGT

tRGTH

tSKRGT_TX

TX_CTL

TXD[8:5]

TXD[7:4]

TXD[9]

TXERR

TXD[4]

TXEN

TXD[3:0]

(At Transmitter)

TXD[8:5][3:0]

TXD[7:4][3:0]

TX_CLK

(At PHY)

RX_CTL

RXD[8:5]

RXD[7:4]

RXD[9]

RXERR

RXD[4]

RXDV

RXD[3:0]

RXD[8:5][3:0]

RXD[7:4][3:0]

RX_CLK

(At PHY)

tSKRGT_RX

tSKRGT_TX

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor 29

8.2.3 RMII AC Timing Specifications

This section describes the RMII transmit and receive AC timing specifications .

8.2.3.1 RMII Transmit AC Timing Specifications

This table shows the RMII transmit AC timing specifications.

This figure shows the RMII transmit AC timing diagram.

Figure 12. RMII Transmit AC Timing Diagram

Table 29. RMII Transmit AC Timing Specifications

At recommended operating conditions with LVDD of 3.3 V ± 5%.

Parameter Symbol1Min Typical Max Unit

REF_CLK clock period tRMT 15.020.025.0 ns

REF_CLK duty cycle tRMTH 35 50 65 %

REF_CLK peak-to-peak jitter tRMTJ — — 250 ps

Rise time REF_CLK (20%–80%) tRMTR 1.0 — 2.0 ns

Fall time REF_CLK (80%–20%) tRMTF 1.0 — 2.0 ns

REF_CLK to RMII data TXD[1:0], TX_EN delay tRMTDX 2.0 — 10.0 ns

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII

transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in

general, the clock reference symbol representation is based on two to three letters representing the clock of a particular

functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

REF_CLK

TXD[1:0]

tRMTDX

tRMT

tRMTH

tRMTR

tRMTF

TX_EN

TX_ER

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

30 Freescale Semiconductor

8.2.3.2 RMII Receive AC Timing Specifications

This table shows the RMII receive AC timing specifications.

This figure provides the AC test load for eTSEC.

Figure 13. eTSEC AC Test Load

Table 30. RMII Receive AC Timing Specifications

At recommended operating conditions with LVDD of 3.3 V ± 5%.

Parameter/Condition Symbol1Min Typical Max Unit

Input low voltage at 3.3 LVDD VIL ——0.8V

Input high voltage at 3.3 LVDD VIH 2.0 — — V

REF_CLK clock period tRMR 15.0 20.0 25.0 ns

REF_CLK duty cycle tRMRH 35 50 65 %

REF_CLK peak-to-peak jitter tRMRJ — — 250 ps

Rise time REF_CLK (20%–80%) tRMRR 1.0 — 2.0 ns

Fall time REF_CLK (80%–20%) tRMRF 1.0 — 2.0 ns

RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge tRMRDV 4.0 — — ns

RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge tRMRDX 2.0 — — ns