DS-CPC7592 - R01 www.clare.com 1
Features
•TTL logic level inputs for 3.3V logic interfaces
•Smart logic for power up / hot plug state control
•Small 16-pin SOIC or Micro-Leadframe Package
•MLP package printed-circuit board footprint is 60
percent smaller than the SOIC version, 70 percent
smaller than 4th generation EMR solutions.
•Monolithic IC reliability
•Low matched RON
•Eliminates the need for zero cross switching
•Flexible switch timing to transition from ringing mode
to talk mode.
•Clean, bounce-free switching
•Tertiary protection consisting of integrated current
limiting, voltage clamping, and thermal shutdown for
SLIC protection
•5 V operation with power consumption < 10 mW
•Intelligent battery monitor
•Latched logic-level inputs, no external drive circuitry
required
Applications
•VoIP Gateways
•Central office (CO)
•Digital Loop Carrier (DLC)
•PBX Systems
•Digitally Added Main Line (DAML)
•Hybrid Fiber Coax (HFC)
•Fiber in the Loop (FITL)
•Pair Gain System
•Channel Banks
Description
The CPC7592 is a member of Clare’s next generation
Line Card Access Switch family. This monolithic 6-pole
solid-state switch is available in either a 16-pin SOIC
or a 16-pin MLP package. It provides the necessary
functions to replace two 2-Form-C electro-mechanical
relays used on traditional analog and contemporary
integrated voice and data (IVD) line cards found in
Central Office, Access, and PBX equipment. Because
this device contains solid state switches for tip and ring
line break, ringing injection/return and test access it
requires only a +5V supply for operation and
logic-level inputs for control.
The CPC7592 is very similar to the Clare CPC7582
with the addition of controlled start-up states and TTL
compatible logic inputs.
The CPC7592xC logic provides alternative test states
from the CPC7592xA/B and while also providing
greater protection SCR trigger and hold current
ratings.
Ordering Information
Specify CPC7592Bx for the SOIC package (47/tube)
or CPC7592Mx for the MLP (94/tube). Add “TR”, sans
quotes, to the part number for tape and reel
packaging. SOIC: 1000/reel or MLP: 2000/reel.
Figure 1. CPC7592 Block Diagram
Part Number Description
CPC7592xA 6-pole LCAS with protection SCR, tubes
CPC7592xB 6-pole LCAS without protection SCR, tubes
CPC7592xC 6-pole LCAS with protection SCR and added
logic state, tubes
CPC7592
TLINE
RLINE
TBAT
VDD
RBAT
DGND
VBAT
FGND
VREF
INACCESS
INRINGING
TSD
LATCH
3
54
14
2
6
78161
13
12
15
9
10
11
L
A
T
C
H
Switch
Control
Logic
+5VDC
SLIC
X
X
X
X
X
XSW5
SW6
SW2
SW4
TTEST
RINGING
300
(min.)
Ω
RTEST
TRINGING
SW3
SW1
VBAT
Secondary
Protection
Tip
Ring
RRINGING SCR Trip Circuit
(CPC7592xA/C)
CPC7592
Line Card Access Switch
CPC7592
2 www.clare.com R01
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.6 Switch Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.6.1 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.6.2 Ringing Return Switch, SW3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.6.3 Ringing Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.6.4 Test Switches, SW5 and SW6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.7 Digital I/O Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.8 Voltage and Power Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.9 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.10 Truth Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.10.1 CPC7592xA and CPC7592xB Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.10.2 CPC7592xC Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.1 CPC7592xA and CPC7592xB Logic States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.2 CPC7592xC Logic States: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Under Voltage Switch Lock Out Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.2 Hot Plug and Power Up Circuit Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 Switch Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.2 Switch Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.3 Make-Before-Break Operation - All Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.3 - Table 1: Make-Before-Break Ringing to Talk Transition Logic Sequence for All Versions . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.4 Break-Before-Make Operation - CPC7592xA/B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.4 - Table 1: Break-Before-Make Ringing to Talk Transition Logic Sequence CPC7592xA/B . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.5 Break-Before-Make Operation - All Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.5 - Table 1: Break-Before-Make Ringing to Talk Transition Logic Sequence for all Versions . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5 TSD Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6 Ringing Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.8 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.9 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.9.1 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.9.2 Current Limiting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.10 Thermal Shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.11 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 Printed-Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 Washing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CPC7592
R01 www.clare.com 3
1. Specifications
1.1 Package Pinout
1.2 Pinout
CPC7592
116
215
314
413
512
611
710
89
TBAT
SD
FGND
TLINE
TRINGING
TTEST
VDD
T
DGND
VBAT
RBAT
RLINE
RRINGING
RTEST
LATCH
INRINGING
INTEST
Pin Name Description
1FGND Fault ground.
2TBAT Tip lead to the SLIC.
3TLINE Tip lead of the line side.
4TRINGING Ringing generator return
5TTEST Tip lead of the test bus.
6VDD +5 V supply.
7TSD Temperature shutdown pin.
8DGND Digital ground.
9INTEST Logic control input.
10 INRINGING Logic control input.
11 LATCH Data latch enable control input.
12 RTEST Ring lead of the test bus.
13 RRINGING Ringing generator source.
14 RLINE Ring lead of the line side.
15 RBAT Ring lead to the SLIC.
16 VBAT Battery supply.
CPC7592
4 www.clare.com R01
1.3 Absolute Maximum Ratings
Absolute maximum ratings are at 25°C.
1.4 ESD Rating
1.5 General Conditions
Unless otherwise specified, minimum and maximum
values are production testing requirements. Typical
values are characteristic of the device and are the
result of engineering evaluations. They are provided
for information purposes only and are not part of the
testing requirements.
Specifications cover the operating temperature range
TA = -40° C to +85° C. Also, unless otherwise specified
all testing is performed with VDD = 5Vdc, logic low input
voltage is 0Vdc and logic high voltage is 5Vdc.
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at conditions
beyond those indicated in the operational sections of this
data sheet is not implied.
Parameter Minimum Maximum Unit
Operating temperature -40 +110 °C
Storage temperature -40 +150 °C
Operating relative humidity 5 95 %
Pin soldering temperature
(10 seconds max) - +220 °C
+5 V power supply (VDD)-0.3 7 V
Battery Supply - -85 V
DGND to FGND Separation -5 +5 V
Logic input voltage -0.3 VDD + 0.3 V
Logic input to switch output
isolation -320V
Switch open-contact
isolation (SW1, SW2, SW3,
SW5, SW6)
-320V
Switch open-contact
Isolation (SW4) -465V
ESD Rating (Human Body Model)
1000 V
CPC7592
R01 www.clare.com 5
1.6 Switch Specifications
1.6.1 Break Switches, SW1 and SW2
Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Off-State
Leakage Current
VSW1 (differential) = TLINE to TBAT
VSW2 (differential) = RLINE to RBAT
All-Off state.
+25° C,
VSW (differential) = -320 V to gnd
VSW (differential) = +260 V to -60 V
ISW -
0.1
1µA
+85° C,
VSW (differential) = -330 V to gnd
VSW (differential) = +270 V to -60 V
0.3
-40° C,
VSW (differential) = -310 V to gnd
VSW (differential) = +250 V to -60 V
0.1
On Resistance
ISW(on) = ±10 mA, ±40 mA,
RBAT and TBAT = -2 V
+25° C
RON -
14.5 -
Ω+85° C20.528
-40° C10.5-
On Resistance
Matching
Per SW1 & SW2 On Resistance test
conditions. ∆RON - 0.15 0.8 Ω
DC current limit
VSW (on) = ±10 V, +25° C
ISW
- 300
-
mA
VSW (on) = ±10 V, +85° C 80 160
VSW (on) = ±10 V, -40° C - 400 425
Dynamic current limit
(t = <0.5 µs)
Break switches on, all other switches
off. Apply ±1 kV 10x1000 µs pulse with
appropriate protection in place.
ISW -2.5- A
Logic input to switch
output isolation
+25° C, Logic inputs = gnd,
VSW (TLINE, RLINE) = ±320 V
ISW
-0.1
1µA
+85° C, Logic inputs = gnd,
VSW (TLINE, RLINE) = ±330 V -0.3
-40° C, Logic inputs = gnd,
VSW (TLINE, RLINE) = ±310 V -0.1
dv/dt sensitivity - - - 500 - V/µs
CPC7592
6 www.clare.com R01
1.6.2 Ringing Return Switch, SW3
Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Off-State
Leakage Current
VSW3 (differential) = TLINE to TRINGING
All-Off state.
+25° C,
VSW (differential) = -320 V to gnd
VSW (differential) = +260 V to -60 V
ISW -
0.1
1µA
+85° C,
VSW (differential) = -330 V to gnd
VSW (differential) = +270 V to -60 V
0.3
-40° C,
VSW (differential) = -310 V to gnd
VSW (differential) = +250 V to -60 V
0.1
On Resistance
ISW(on) = ±0 mA, ±10 mA, +25° C
RON -
60 -
Ω
ISW(on) = ±0 mA, ±10 mA, +85° C 85 100
ISW(on) = ±0 mA, ±10 mA, -40° C 45 -
DC current limit
VSW (on) = ± 10 V, +25° C
ISW
- 135
-mA
VSW (on) = ± 10 V, +85° C 70 85
VSW (on) = ± 10 V, -40° C - 210
Dynamic current limit
(t = <0.5 µs)
Ringing switches on, all other switches
off. Apply ±1 kV 10x1000 µs pulse with
appropriate protection in place.
ISW -2.5- A
Logic input to switch
output isolation
+25° C, Logic inputs = gnd,
VSW (TRINGING, TLINE) = ±320 V
ISW -
0.1
1µA
+85° C, Logic inputs = gnd,
VSW (TRINGING, TLINE) = ±330 V 0.3
-40° C, Logic inputs = gnd,
VSW (TRINGING, TLINE) = ±310 V 0.1
dv/dt sensitivity - -- 500 - V/µs
CPC7592
R01 www.clare.com 7
1.6.3 Ringing Switch, SW4
Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Off-State
Leakage Current
VSW4 (differential) = RLINE to RRINGING
All-Off state.
+25° C
VSW (differential) = -255 V to +210 V
VSW (differential) = +255 V to -210 V
ISW -
0.05
1µA
+85° C
VSW (differential) = -270 V to +210 V
VSW (differential) = +270 V to -210 V
0.1
-40° C
VSW (differential) = -245 V to +210 V
VSW (differential) = +245 V to -210 V
0.05
On Resistance ISW (on) = ±70 mA, ±80 mA RON -1015Ω
On Voltage ISW (on) = ± 1 mA VON -1.53 V
On-State
Leakage Current
Inputs set for ringing -Measure ringing
generator current to ground. IRINGING -0.10.25mA
Steady-State Current* Inputs set for ringing mode. ISW - - 150 mA
Surge Current*
Ringing switches on, all other switches
off. Apply ±1 kV 10x1000 µs pulse with
appropriate protection in place.
ISW --2A
Release Current SW4 transition from on to off. IRINGING - 300 - µA
Logic input to switch
output isolation
+25° C, Logic inputs = gnd,
VSW (RRINGING, RLINE) = ±320 V
ISW -
0.1
1µA
+85° C, Logic inputs = gnd,
VSW (RRINGING, RLINE) = ±330 V 0.3
-40° C, Logic inputs = gnd,
VSW (RRINGING, RLINE) = ±310 V 0.1
dv/dt sensitivity - - - 500 - V/µs
*Secondary protection and current limiting must prevent exceeding this parameter.
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1.6.4 Test Switches, SW5 and SW6
Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Off-State
Leakage Current
VSW1 (differential) = TLINE to TBAT
VSW2 (differential) = RLINE to RBAT
All-Off state.
+25° C,
VSW (differential) = -320 V to gnd
VSW (differential) = +260 V to -60 V
ISW -
0.1
1µA
+85° C,
VSW (differential) = -330 V to gnd
VSW (differential) = +270 V to -60 V
0.3
-40° C,
VSW (differential) = -310 V to gnd
VSW (differential) = +250 V to -60 V
0.1
On Resistance
ISW(on) = ±10 mA, ±40 mA,
RBAT and TBAT = -2 V
+25° C
RON -
38 -
Ω+85° C4670
-40° C28-
DC current limit
VSW (on) = ±10 V, +25° C
ISW
- 175
-
mA
VSW (on) = ±10 V, +85° C 80 110
VSW (on) = ±10 V, -40° C - 210 250
Dynamic current limit
(t = <0.5 µs)
Break switches on, all other switches
off. Apply ±1 kV 10x1000 µs pulse with
appropriate protection in place.
ISW -2.5- A
Logic input to switch
output isolation
+25° C, Logic inputs = gnd,
VSW (TLINE, RLINE) = ±320 V
ISW
-0.1
1µA
+85° C, Logic inputs = gnd,
VSW (TLINE, RLINE) = ±330 V -0.3
-40° C, Logic inputs = gnd,
VSW (TLINE, RLINE) = ±310 V -0.1
dv/dt sensitivity - - - 500 - V/µs
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1.7 Digital I/O Electrical Specifications
1.8 Voltage and Power Specifications
Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Input Characteristics
Input voltage, Logic low Input voltage falling VIL 0.8 1.1 -
V
Input voltage, Logic high Input voltage rising VIH 1.9 2.4
Input leakage current,
INRINGING and INTEST
,
Logic high
VDD = 5.5 V, VBAT = -75 V, VHI =2.4V I
IH -0.11µA
Input leakage current,
INRINGING and INTEST
,
Logic low
VDD = 5.5 V, VBAT = -75 V, VIL = 0.4V IIL -0.11µA
Input leakage current,
LATCH Logic high VDD = 4.5 V, VBAT = -75 V, VIH = 2.4V IIH 10 28 - µA
Input leakage current,
LATCH Logic low VDD = 5.5 V, VBAT = -75 V, VIL = 0.4V IIL - 46 125 µA
Input leakage current,
TSD Logic high VDD = 5.5 V, VBAT = -75 V, VIH = 2.4 IIH 10 16 30 µA
Input leakage current,
TSD Logic low VDD = 5.5 V, VBAT = -75 V, VIL = 0.4V IIL 10 16 30 µA
Output Characteristics
Output voltage,
TSD Logic high VDD = 5.5 V, VBAT = -75 V, ITSD = 10µAV
TSD_off 2.4 VDD -V
Output voltage,
TSD Logic low VDD = 5.5 V, VBAT = -75 V, ITSD = 1mA VTSD_on -00.4V
Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Voltage Requirements
VDD -VDD 4.5 5.0 5.5 V
VBAT
1 -VBAT -19 -48 -72 V
1VBAT is used only for internal protection circuitry. If VBAT rises above-10 V, the device will enter the all-off state and will remain in the all-off state until the battery
drops below approximately -15 V
Power Specifications
Power consumption
VDD = 5 V, VBAT = -48 V, VIH = 2.4V,
VIL = 0.4V, Measure IDD and IBAT
,
Talk and All-Off States P - 5.5 10 mW
All other states P - 6.5 10 mW
VDD current in talk and
all-off states VDD = 5 V, VBAT = -48 V, VIH = 2.4V,
VIL = 0.4V
IDD -1.12.0
mA
VDD current in ringing
state
IDD -1.32.0
VBAT current in any state VDD = 5V, VBAT = -48 V, VIH = 2.4V,
VIL = 0.4V IBAT -0.110µA
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1.9 Protection Circuitry Electrical Specifications
Parameter Conditions Symbol Minimum Typical Maximum Unit
Protection Diode Bridge
Forward Voltage drop,
continuous current
(50/60 Hz)
Apply ± dc current limit of break
switches VF -2.13.0
V
Forward Voltage drop,
surge current
Apply ± dynamic current limit of break
switches VF -5-
Optional Protection SCR
Surge current - - - - * A
Trigger current:
Current into VBAT pin.
SCR activates, +25° C
ITRIG -
60
(CPC7592xA)
70
(CPC7592xC) -mA
SCR activates, +85° C
35
(CPC7592xA)
40
(CPC7592xC)
Hold current: Current
through protection SCR
SCR remains active, +25° C
IHOLD
-
100
(CPC7592xA)
135
(CPC7592xC) -mA
SCR remains active, +85° C
60
(CPC7592xA)
110
(CPC7592xC)
70
(CPC7592xA)
115
(CPC7592xC)
Gate trigger voltage IGATE = ITRIGGER
§
VTBAT or
VRBAT
VBAT -4 -VBAT -2 V
Reverse leakage current VBAT = -48 V IVBAT --1.0µA
On-state voltage
0.5 A, t = 0.5 µsV
TBAT or
VRBAT
-
-3
-V
2.0 A, t = 0.5 µs-5
Temperature Shutdown Specifications
Shutdown activation
temperature Not production tested - limits are
guaranteed by design and Quality
Control sampling audits.
TTSD_on 110 125 150 °C
Shutdown circuit
hysteresis TTSD_off 10 - 25 °C
*Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place.
§VBAT must be capable of sourcing ITRIGGER for the internal SCR to activate.
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1.10 Truth Tables
1.10.1 CPC7592xA and CPC7592xB Truth Table
1.10.2 CPC7592xC Truth Table
State INRINGING INTEST LATCH TSD
Break
Switches
Ringing
Switches
Test
Switches
Ta l k 0 0
0
Z 1
On Off Off
Te s t 0 1 O f f O f f On
Ringing 1 0 Off On Off
All-Off 1 1 Off Off Off
Latched X X 1 Unchanged
All-Off X X X 0 Off Off Off
1 Z = High Impedance. Because TSD has an internal pull up at this pin, it should be controlled with an open-collector or open-drain type device.
State INRINGING INTEST LATCH TSD
Break
Switches
Ringing
Switches
Test
Switches
Ta l k 0 0
0
Z 1
On Off Off
Test/Monitor 0 1 On Off On
Ringing 1 0 Off On Off
Ringing Test 1 1 Off On On
Latched X X 1 Unchanged
All-Off X X X 0 Off Off Off
1 Z = High Impedance. Because TSD has an internal pull up at this pin, it should be controlled with an open-collector or open-drain type device.
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2. Functional Description
2.1 Introduction
2.1.1 CPC7592xA and CPC7592xB Logic States
•Talk. Break switches SW1 and SW2 closed, ringing
switches SW3 and SW4 open, and test switches
SW5 and SW6 open.
•Ringing. Break switches SW1 and SW2 open,
ringing switches SW3 and SW4 closed, and test
switches SW5 and SW6 open.
•Test. Break switches SW1 and SW2 open, ringing
switches SW3 and SW4 open, and loop test
switches SW5 and SW6 closed.
•All-off. Break switches SW1 and SW2 open, ringing
switches SW3 and SW4 open, and test switches
SW5 and SW6 open.
2.1.2 CPC7592xC Logic States:
•Talk. Break switches SW1 and SW2 closed, ringing
switches SW3 and SW4 open, and test switches
SW5 and SW6 open.
•Ringing. Break switches SW1 and SW2 open,
ringing switches SW3 and SW4 closed, and test
switches SW5 and SW6 open.
•Test/Monitor. Break switches SW1 and SW2
closed, ringing switches SW3 and SW4 open, and
test switches SW5 and SW6 closed.
•Ringing Test. Break switches SW1 and SW2 open,
ringing switches SW3 and SW4 closed, and test
switches SW5 and SW6 closed.
•All-off. Break switches SW1 and SW2 open, ringing
switches SW3 and SW4 open, and test switches
SW5 and SW6 open.
The CPC7592 offers break-before-make and
make-before-break switching from the ringing state to
the talk state with simple TTL level logic input control.
Solid-state switch construction means no impulse
noise is generated when switching during ring
cadence or ring trip, eliminating the need for external
zero-cross switching circuitry. State control is via TTL
logic-level input so no additional driver circuitry is
required. The linear break switches SW1 and SW2
have exceptionally low RON and excellent matching
characteristics. The ringing switch, SW4, has a
minimum open contact breakdown voltage of 465 V at
+25°C sufficiently high with proper protection to
prevent breakdown in the presence of a transient fault
condition (i.e., passing the transient on to the ringing
generator).
Integrated into the CPC7592 is an over-voltage
clamping circuit, active current limiting, and a thermal
shutdown mechanism to provide protection for the
SLIC during a fault condition. Positive and negative
lightning surge currents are reduced by the current
limiting circuitry and hazardous potentials are diverted
away from the SLIC via the protection diode bridge or
the optional integrated protection SCR. Power-cross
potentials are also reduced by the current limiting and
thermal shutdown circuits.
To protect the CPC7592 from an over-voltage fault
condition, use of a secondary protector is required.
The secondary protector must limit the voltage seen at
the tip and ring terminals to a level below the
maximum breakdown voltage of the switches. To
minimize the stress on the solid-state contacts, use of
a foldback or crowbar type secondary protector is
highly recommended. With proper selection of the
secondary protector, a line card using the CPC7592
will meet all relevant ITU, LSSGR, TIA/EIA and IEC
protection requirements.
The CPC7592 operates from a single +5 V supply.
This gives the device extremely low power
consumption in any state with virtually any range of
battery voltage. The battery voltage used by the
CPC7592 has a two fold function. It is used as a
reference and as a current source for the internal
integrated protection circuitry under surge conditions.
Second, it is used as a reference. In the event of
battery voltage loss, the CPC7592 enters the all-off
state.
2.2 Under Voltage Switch Lock Out Circuitry
2.2.1 Introduction
Smart logic in the CPC7592 now provides for switch
state control during both power up and power loss
transitions. An internal detector is used to evaluate the
VDD supply to determine when to de-assert the under
voltage switch lock out circuitry with a rising VDD and
when to assert the under voltage switch lock out
circuitry with a falling VDD. Any time unsatisfactory low
VDD conditions exist the lock out circuit overrides user
switch control by blocking the information at the
external input pins and conditioning internal switch
commands to the all off state. Upon restoration of VDD
the switches will remain in the all-off state until the
LATCH input is pulled low.
The rising VDD lock out release threshold is internally
set to ensure all internal logic is properly biased and
functional before accepting external switch commands
from the inputs to control the switch states. For a
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falling VDD event, the lock out threshold is set to
assure proper logic and switch behavior up to the
moment the switches are forced off and external
inputs are suppressed.
To facilitate hot plug insertion and power up control the
LATCH pin has an integrated weak pull up resistor to
the VDD power rail that will hold a non-driven LATCH
pin at a logic high state. This enables board designers
to use the CPC7592 with FPGAs and other devices
that provide high impedance outputs during power up
and configuration. The weak pull up allows a fan out of
up to 32 when the system’s LATCH control driver has
a logic low minimum sink capability of 4mA.
2.2.2 Hot Plug and Power Up Circuit Design
Considerations
There are six possible start up scenarios that can
occur during power up. They are:
1. All inputs defined at power up & LATCH = 0
2. All inputs defined at power up & LATCH = 1
3. All inputs defined at power up & LATCH = Z
4. All inputs not defined at power up & LATCH = 0
5. All inputs not defined at power up & LATCH = 1
6. All inputs not defined at power up & LATCH = Z
Under all of the start up situations listed above the
CPC7592 will hold all of it’s switches in the all-off state
during power up. When VDD requirements have been
satisfied the LCAS will complete it’s start up procedure
in one of three conditions.
For start up scenario 1 the CPC7592 will transition
from the all off state to the state defined by the inputs
when VDD is valid.
For start up scenarios 2, 3, 5, and 6 the CPC7592 will
power up in the all-off state and remain there until the
LATCH pin is pulled low. This allows for an indefinite
all off state for boards inserted into a powered system
but are not configured for service or boards that need
to wait for other devices to be configured first.
Start up scenario 4 will start up with all switches in the
all-off state but upon the acceptance of a valid VDD the
LCAS will revert to one of the legitimate states listed in
the truth tables and there after may randomly change
states based on input pin leakage currents and
loading. Because the LCAS state after power up can
not be predicted with this start up condition it should
never be utilized.
On designs that do not wish to individually control the
LATCH pins of multi-port cards it is possible to bus
many (or all) of the LATCH pins together to create a
single board level input enable control.
2.3 Switch Logic
2.3.1 Start-up
The CPC7592 uses smart logic to monitor the VDD
supply. Any time the VDD is below an internally set
threshold, the smart logic places the control logic to
the all-off state. An internal pullup at the LATCH pin
locks the CPC7592 in the all-off state following
start-up until the LATCH pin is pulled down to a logic
low. Prior to the assertion of a logic low at the LATCH
pin, the switch control inputs must be properly
conditioned.
2.3.2 Switch Timing
The CPC7592 provides, when switching from the
ringing state to the talk state, the ability to control the
release timing of the ringing switches SW3 and SW4
relative to the state of the switches SW1 and SW2
using simple TTL logic-level inputs. The two available
techniques are referred to as make-before-break and
break-before-make operation. When the break switch
contacts of SW1 and SW2 are closed (made) before
the ringing switch contacts of SW3 and SW4 are
opened (broken), this is referred to as
make-before-break operation. Break-before-make
operation occurs when the ringing contacts of SW3
and SW4 are opened (broken) before the switch
contacts of SW1 and SW2 are closed (made). With
the CPC7592, make-before-break and
break-before-make operations can easily be
accomplished by applying the proper sequence of
logic-level inputs to the device.
The logic sequences for either mode of operation are
provided in “Make-Before-Break Ringing to Talk
Transition Logic Sequence for All Versions” on
page 14, “Break-Before-Make Ringing to Talk
Transition Logic Sequence CPC7592xA/B” on
page 14, and “Break-Before-Make Ringing to Talk
Transition Logic Sequence for all Versions” on
page 15. Logic states and input control settings are
provided in “CPC7592xA and CPC7592xB Truth
Table” on page 11 and “CPC7592xC Truth Table” on
page 11.
2.3.3 Make-Before-Break Operation - All Versions
To use make-before-break operation, change the logic
inputs from the ringing state directly to the talk state.
Application of the talk state opens the ringing return
switch, SW3, as the break switches SW1 and SW2
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close. The ringing switch, SW4, remains closed until
the next zero-crossing of the ringing current. While in
the make-before-break state, ringing potentials in
excess of the CPC7592 protection circuitry thresholds
will be diverted away from the SLIC.
2.3.3 - Table 1: Make-Before-Break Ringing to Talk Transition Logic Sequence for All Versions
2.3.4 Break-Before-Make Operation - CPC7592xA/B
Break-before-make operation of the CPC7592xA/B
can be achieved using two different techniques.
The first method uses manipulation of the INRINGING
and INTEST logic inputs as shown in
“Break-Before-Make Ringing to Talk Transition Logic
Sequence CPC7592xA/B” on page 14.
1. At the end of the ringing state apply the all off
state (1,1). This releases the ringing return
switch (SW3) while the ringing switch (SW4)
remains on, waiting for the next zero current
event.
2. Hold the all off state for at least one-half of a
ringing cycle to assure that a zero crossing event
occurs and that SW4, the ringing switch, has
opened.
3. Apply inputs for the next desired state. For the
talk state, the inputs would be (0,0).
Break-before-make operation occurs when the ringing
switches open before the break switches SW1 and
SW2 close.
2.3.4 - Table 1: Break-Before-Make Ringing to Talk Transition Logic Sequence CPC7592xA/B
2.3.5 Break-Before-Make Operation - All Versions
The second break-before-make method for the
CPC7592xA/B is also the only method available for
the CPC7592xC. As shown in “CPC7592xA and
CPC7592xB Truth Table” on page 11 and
“CPC7592xC Truth Table” on page 11, the
bi-directional TSD interface disables all of the
State INRINGING INTEST LATCH TSD Timing Break
Switches
Ringing
Return
Switch
(SW3)
Ringing
Switch
(SW4)
Test
Switches
Ringing 1 0
0Z
-Off
On On Off
Make-
before-
break
00
SW4 waiting for next zero-current
crossing to turn off. Maximum time is
one-half of the ringing cycle. In this
transition state current limited by the dc
break switch current limit value will be
sourced from the ring node of the SLIC.
On Off On Off
Talk 0 0 Zero-cross current has occurred On Off Off Off
State INRINGING INTEST LATCH TSD Timing Break
Switches
Ringing
Return
Switch
(SW3)
Ringing
Switch
(SW4)
Test
Switches
Ringing 1 0
0Z
-Off
On On Off
All-Off 1 1
Hold this state for at least one-half of the
ringing cycle. SW4 waiting for zero
current to turn off.
Off Off On Off
Break-
Before-
Make
11 Zero current has occurred.
SW4 has opened OffOffOffOff
Talk 0 0 Break switches close. On Off Off Off
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CPC7592 switches when pulled to a logic low.
Although logically disabled, an active (closed) ringing
switch (SW4) will remain closed until the next zero
crossing current event.
As shown in the table “Break-Before-Make Ringing to
Talk Transition Logic Sequence for all Versions” on
page 15, this operation is similar to the one shown in
“Break-Before-Make Operation - All Versions” on
page 14, except in the method used to select the all off
state, and in when the INRINGING and INTEST inputs
are reconfigured for the talk state.
1. Pull TSD to a logic low to end the ringing state.
This opens the ringing return switch (SW3) and
prevents any other switches from closing.
2. Keep TSD low for at least one-half the duration of
the ringing cycle period to allow sufficient time for
a zero crossing current event to occur and for the
circuit to enter the break-before-make state.
3. During the TSD low period, set the INRINGING and
INTEST inputs to the talk state (0, 0).
4. Release TSD, allowing the internal pull-up to
activate the break switches.
When using TSD as an input, the two recommended
states are “0” which overrides the logic input pins and
forces an all off state and “Z” which allows normal
switch control via the logic input pins. This requires the
use of an open-collector or open-drain type buffer.
Forcing TSD to a logic high disables the thermal
shutdown circuit and is therefore not recommended as
this could lead to device damage or destruction in the
presence of excessive tip or ring potentials.
2.3.5 - Table 1: Break-Before-Make Ringing to Talk Transition Logic Sequence for all Versions
2.4 Data Latch
The CPC7592 has an integrated transparent data
latch. The latch enable operation is controlled by TTL
logic input levels at the LATCH pin. Data input to the
latch is via the input pins INRINGING and INTEST while
the output of the data latch are internal nodes used for
state control. When the LATCH enable control pin is at
a logic 0 the data latch is transparent and the input
control signals flow directly through the data latch to
the state control circuitry. A change in input will be
reflected by a change in the switch state.
Whenever the LATCH enable control pin is at logic 1,
the data latch is active and data is locked. Subsequent
changes to the input controls INRINGING and INTEST
will not result in a change to the control logic or affect
the existing switch state.
The switches will remain in the state they were in
when the LATCH changes from logic 0 to logic 1 and
will not respond to changes in input as long as the
LATCH is at logic 1. However, neither the TSD input
nor the TSD output control functions are affected by
the latch function. Since internal thermal shutdown
control and external “All-off” control is not affected by
the state of the LATCH enable input, TSD will override
state control.
State INRINGING INTEST LATCH TSD Timing Break
Switches
Ringing
Return
Switch
(SW3)
Ringing
Switch
(SW4)
Test
Switches
Ringing 1 0 0 Z - Off On On Off
All-Off 1 0
X0
Hold this state for at least one-half of the
ringing cycle. SW4 waiting for zero
current to turn off.
Off Off On Off
Break-
Before-
Make
0 0 SW4 has opened Off Off Off Off
Talk 0 0 0 Z Close Break Switches On Off Off Off
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2.5 TSD Pin Description
The TSD pin is a bi-directional I/O structure with an
internal pull-up current source with a nominal value of
16 µA biased from VDD. As an output, this pin
indicates the status of the thermal shutdown circuitry.
Typically, during normal operation, this pin will be
pulled up to VDD but under fault conditions that create
excess thermal loading the CPC7592 will enter
thermal shutdown and a logic low will be output.
As an input, the TSD pin is utilized to place the
CPC7592 into the “All-Off” state by simply pulling the
input low. For applications using low-voltage logic
devices (lower than VDD), Clare recommends the use
of an open-collector or an open-drain type output to
control TSD. This avoids sinking the TSD pull up bias
current to ground during normal operation when the
all-off state is not required. In general, Clare
recommends all applications use an open-collector or
open-drain type device to drive this pin.
Setting TSD to a logic 1 or tying this pin to VCC allows
switch control using the logic inputs. This setting,
however, also disables the thermal shutdown circuit
and is therefore not recommended. As a result the
TSD pin has two recommended operating states when
it is used as an input control. A logic 0, which forces
the device to the all-off state and a high impedance (Z)
state for normal operation. This requires the use of an
open-collector or open-drain type buffer.
2.6 Ringing Switch Zero-Cross Current Turn Off
After the application of a logic input to turn SW4 off,
the ringing switch is designed to delay the change in
state until the next zero-crossing. Once on, the switch
requires a zero-current cross to turn off, and therefore
should not be used to switch a pure DC signal. The
switch will remain in the on state no matter the logic
input until the next zero crossing. These switching
characteristics will reduce and possibly eliminate
overall system impulse noise normally associated with
ringing switches. See Clare’s application note AN-144,
Impulse Noise Benefits of Line Card Access Switches for
more information. The attributes of ringing switch SW4
may make it possible to eliminate the need for a
zero-cross switching scheme. A minimum impedance
of 300 Ω in series with the ringing generator is
recommended.
2.7 Power Supplies
Both a +5 V supply and battery voltage are connected
to the CPC7592. Switch state control is powered
exclusively by the +5 V supply. As a result, the
CPC7592 exhibits extremely low power consumption
during active and idle states.
Although battery power is not used for switch control, it
is required to supply trigger current for the integrated
internal protection circuitry SCR during fault
conditions. This integrated SCR is designed to
activate whenever the voltage at TBAT or RBAT drops 2
to 4 V below the applied voltage on the VBAT pin.
Because the battery supply at this pin is required to
source trigger current during negative overvoltage
fault conditions at tip and ring, it is important that the
net supplying this current be a low impedance path for
high speed transients such as lightning. This will
permit trigger currents to flow enabling the SCR to
activate and thereby prevent a fault induced negative
overvoltage event at the TBAT or RBAT nodes.
2.8 Battery Voltage Monitor
The CPC7592 also uses the VBAT voltage to monitor
battery voltage. If system battery voltage is lost, the
CPC7592 immediately enters the all-off state. It
remains in this state until the battery voltage is
restored. The device also enters the all-off state if the
battery voltage rises more positive than about –10 V
with respect to ground and remains in the all-off state
until the battery voltage drops below approximately
–15 V with respect to ground. This battery monitor
feature draws a small current from the battery (less
than 1 µA typical) and will add slightly to the device’s
overall power dissipation.
This monitor function performs properly if the
CPC7592 and SLIC share a common battery supply
origin. Otherwise, if battery is lost to the CPC7592 but
not to the SLIC, then the VBAT pin will be internally
biased by the potential applied at the TBAT or RBAT
pins via the internal protection circuitry SCR trigger
current path.
2.9 Protection
2.9.1 Diode Bridge/SCR
The CPC7592 uses a combination of current limited
break switches, a diode bridge/SCR clamping circuit,
and a thermal shutdown mechanism to protect the
SLIC device or other associated circuitry from damage
during line transient events such as lightning. During a
positive transient condition, the fault current is
conducted through the diode bridge to ground via
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FGND. Voltage is clamped to a diode drop above
ground. During a negative transient of 2 to 4 V more
negative than the voltage source at VBAT
, the SCR
conducts and faults are shunted to FGND via the SCR
or the diode bridge.
In order for the SCR to crowbar (or foldback), the
SCR’s on-voltage (see “Protection Circuitry Electrical
Specifications” on page 10) must be less than the
applied voltage at the VBAT pin. If the VBAT voltage is
less negative than the SCR on-voltage or if the VBAT
supply is unable to source the trigger current, the SCR
will not crowbar.
For power induction or power-cross fault conditions,
the positive cycle of the transient is clamped to a diode
drop above ground and the fault current directed to
ground. The negative cycle of the transient will cause
the SCR to conduct when the voltage exceeds the
VBAT reference voltage by two to four volts, steering
the fault current to ground.
Note: The CPC7592xB does not contain the
protection SCR but instead uses diodes to clamp both
polarities of a transient fault. These diodes direct the
negative potential’s fault current to the VBAT pin.
2.9.2 Current Limiting function
If a lightning strike transient occurs when the device is
in the talk state, the current is passed along the line to
the integrated protection circuitry and restricted by the
dynamic current limit response of the active switches.
During the talk state, when a 1000V 10x1000 µs
lightning pulse (GR-1089-CORE) is applied to the line
though a properly clamped external protector, the
current seen at TLINE and RLINE will be a pulse with a
typical magnitude of 2.5 A and a duration less than
0.5 µs.
If a power-cross fault occurs with the device in the talk
state, the current is passed though break switches
SW1 and SW2 on to the integrated protection circuit
but is limited by the dynamic DC current limit response
of the two break switches. The DC current limit
specified over temperature is between 80 mA and
425 mA and the circuitry has a negative temperature
coefficient. As a result, if the device is subjected to
extended heating due to a power cross fault condition,
the measured current at TLINE and RLINE will decrease
as the device temperature increases. If the device
temperature rises sufficiently, the temperature
shutdown mechanism will activate and the device will
enter the all-off state.
2.10 Thermal Shutdown
The thermal shutdown mechanism activates when the
device die temperature reaches a minimum of 110° C,
placing the device in the all-off state regardless of
logic input. During thermal shutdown events the TSD
pin will output a logic low with a nominal 0 V level. A
logic high is output from the TSD pin during normal
operation with a typical output level equal to VDD.
If presented with a short duration transient such as a
lightning event, the thermal shutdown feature will
typically not activate. But in an extended power-cross
event, the device temperature will rise and the thermal
shutdown mechanism will activate forcing the switches
to the all-off state. At this point the current measured
into TLINE or RLINE will drop to zero. Once the device
enters thermal shutdown it will remain in the all-off
state until the temperature of the device drops below
the de-activation level of the thermal shutdown circuit.
This permits the device to autonomously return to
normal operation. If the transient has not passed,
current will again flow up to the value allowed by the
dynamic DC current limiting of the switches and
heating will resume, reactivating the thermal shutdown
mechanism. This cycle of entering and exiting the
thermal shutdown mode will continue as long as the
fault condition persists. If the magnitude of the fault
condition is great enough, the external secondary
protector will activate shunting the fault current to
ground.
2.11 External Protection Elements
The CPC7592 requires only over voltage secondary
protection on the loop side of the device. The
integrated protection feature described above negates
the need for additional external protection on the SLIC
side. The secondary protector must limit voltage
transients to levels that do not exceed the breakdown
voltage or input-output isolation barrier of the
CPC7592. A foldback or crowbar type protector is
recommended to minimize stresses on the CPC7592.
Consult Clare’s application note, AN-100, “Designing
Surge and Power Fault Protection Circuits for Solid
State Subscriber Line Interfaces” for equations related
to the specifications of external secondary protectors,
fused resistors and PTCs.
CPC7592
18 www.clare.com R01
3. Manufacturing Information
3.1 Mechanical Dimensions
3.1.1 SOIC
3.1.2 MLP
0.55±0.10
0.80
0.23
0.55±0.10
0.33 +0.07, -0.05
0.20
0.90±0.10
0.02 +0.03, -0.02)
0.40
1.80
Terminal Tip
INDEX AREA
SEATING
PLANE
EXPOSED PAD
TOP VIEW
SIDE VIEW
BOTTOM VIEW
16
1
7.00 0.25±
6.00 0.25±
4.00±0.05
6.00±0.05
0.55±0.10
Dimensions in mm
CPC7592
R01 www.clare.com 19
3.2 Printed-Circuit Board Layout
3.2.1 SOIC
3.2.2 MLP
NOTE: For optimum solder joint size, MLP package
printed-circuit board pads should extend no more than
0.05 mm past the chip post on the short sides, and no
more than 0.025 mm past the chip posts on the long
sides.
As the metallic pad on the bottom of the MLP package
is connected to the substrate of the die, Clare
recommends that no printed circuit board traces or
vias be placed under this area to maintain minimum
creepage and clearance values.
(Top View)
PC Board Pattern
1.193
(0.047)
9.728 ± 0.051
(0.383 ± 0.002)
0.787
(0.031)
1.270
(0.050)
DIMENSIONS
INCHES
(MM)
1.10
6.65
0.45
1.10
0.45
0.73
0.70
5.60
6.05
0.80 on center
5.45 on center
Detail A
Detail A
All dimensions in mm
Not drawn to scale
CPC7592
20 www.clare.com R01
3.3 Tape and Reel Packaging
3.3.1 SOIC
3.3.2 MLP
MLP tape and reel drawing specifications not available
at time of document release. Please contact factory for
details.
3.4 Soldering
3.4.1 Moisture Reflow Sensitivity
Clare has characterized the moisture reflow sensitivity
of LCAS products using IPC/JEDEC standard
J-STD-020A. Moisture uptake from atmospheric
humidity occurs by diffusion. During the solder reflow
process, in which the component is attached to the
PCB, the whole body of the component is exposed to
high process temperatures. The combination of
moisture uptake and high reflow soldering
temperatures may lead to moisture induced
delamination and cracking of the component. To
prevent this, this component must be handled in
accordance with IPC/JEDEC standard J-STD-020A
per the labelled moisture sensitivity level (MSL),
level 1 for the SOIC package, and level 3 for the MLP
package.
3.4.2 Reflow Profile
The maximum ramp rates, dwell times, and
temperatures of the assembly reflow profile should not
exceed those specified in IPC standard IPC-9502,
table 2. Soldering processes are limited to 220°C
component body temperature.
3.5 Washing
Clare does not recommend ultrasonic cleaning of
LCAS parts.
Top Cover
Tape Thickness
0.102 MAX
(0.004 MAX)
330.2 DIA.
(13.00 DIA)
Embossed Carrier
Embossment
K0=2.70 0.15
(0.106 0.01)
+
+
K1=2.30 0.15
(0.0906 0.01)
+
+
P=12.00
(0.47)
A0=6.5 0.15
(0.256 0.01)
+
+
B0=10.30 0.15
(0.4055 0.01)
+
+
W=16.00 0.3
(0.630 0.01)
+
+
For additional information please visit www.clare.com
C
lare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
c
hanges to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set
f
orth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its
p
roducts, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
T
he products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into
t
he body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a
p
erson or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice.
Specification: DS-CPC7592-R01
© Copyright 2004, Clare, Inc.
All rights reserved. Printed in USA.
4/27/2004
