NUP1301,215 - NXP - Pdf.Support

1. Product proﬁle

1.1 General description

Ultra low capacitance ElectroStatic Discharge (ESD) protection array in a small

SOT23 (TO-236AB) Surface-Mounted Device (SMD) plastic package designed to

protect one signal line in rail-to-rail conﬁguration from the damage caused by ESD

and other transients.

1.2 Features

nESD protection of one signal line (rail-to-rail conﬁguration)

nUltra low diode capacitance: Cd= 0.6 pF

nVery low reverse leakage current: ≤30 nA

nESD protection up to 30 kV

nIEC 61000-4-2; level 4 (ESD)

nIEC 61000-4-5 (surge); IPP = 11 A at tp= 8/20 µs

nAEC-Q101 qualiﬁed

1.3 Applications

nTelecommunication networks

nVideo line protection

nMicrocontroller protection

nI2C-bus protection

nAntenna power supply

nAnalog audio

nClass-D ampliﬁer

1.4 Quick reference data

NUP1301

Ultra low capacitance ESD protection array

Rev. 01 — 11 May 2009 Product data sheet

Table 1. Quick reference data

amb

=25

C unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Per diode

VRRM repetitive peak reverse

voltage --80V

Cddiode capacitance f = 1 MHz;

VR=0V - 0.6 0.75 pF

IRreverse current VR= 80 V - - 100 nA

Product data sheet Rev. 01 — 11 May 2009 2 of 13

NXP Semiconductors NUP1301

Ultra low capacitance ESD protection array

2. Pinning information

3. Ordering information

4. Marking

[1] * = -: made in Hong Kong

* = p: made in Hong Kong

* = t: made in Malaysia

* = W: made in China

5. Limiting values

Table 2. Pinning

Pin Symbol Description Simpliﬁed outline Graphic symbol

1 GND ground

CC supply voltage

3 I/O input/output

006aaa763

Table 3. Ordering information

Type number Package

Name Description Version

NUP1301 - plastic surface-mounted package; 3 leads SOT23

Table 4. Marking

Type number Marking code[1]

NUP1301 LJ*

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

Per diode

VRRM repetitive peak reverse

voltage -80V

VRreverse voltage - 80 V

IFforward current [1] - 215 mA

IFRM repetitive peak forward

current tp≤1 ms; δ≤0.25 - 500 mA

Product data sheet Rev. 01 — 11 May 2009 3 of 13

NXP Semiconductors NUP1301

Ultra low capacitance ESD protection array

[1] Pulse test: tp≤300 µs; δ≤0.02.

[2] Tj=25°C prior to surge.

[3] Non-repetitive current pulse 8/20 µs exponential decay waveform according to IEC 61000-4-5.

[4] Measured from pin 3 to pins 1 and 2 (pins 1 and 2 are connected).

[5] Single diode loaded.

[6] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard

footprint.

[1] Device stressed with ten non-repetitive ESD pulses.

[2] Measured from pin 3 to pins 1 and 2 (pins 1 and 2 are connected).

IFSM non-repetitive peak

forward current square wave [2]

tp=1µs-4A

tp=1ms - 1 A

tp= 1 s - 0.5 A

Per device

PPP peak pulse power tp= 8/20 µs[3][4] - 220 W

IPP peak pulse current tp= 8/20 µs[3][4] -11A

Ptot total power dissipation Tamb ≤25 °C[5][6] - 250 mW

Tjjunction temperature - 150 °C

Tamb ambient temperature −55 +150 °C

Tstg storage temperature −65 +150 °C

Table 6. ESD maximum ratings

Symbol Parameter Conditions Min Max Unit

VESD electrostatic discharge

voltage IEC 61000-4-2

(contact discharge) [1][2] -30kV

machine model - 400 V

MIL-STD-883

(human body model) -10kV

Table 7. ESD standards compliance

Standard Conditions

IEC 61000-4-2; level 4 (ESD) > 15 kV (air); > 8 kV (contact)

MIL-STD-883; class 3B (human body model) > 8 kV

Table 5. Limiting values

…continued

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

Product data sheet Rev. 01 — 11 May 2009 4 of 13

NXP Semiconductors NUP1301

Ultra low capacitance ESD protection array

6. Thermal characteristics

[1] Single diode loaded.

[2] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.

Fig 1. 8/20 µs pulse waveform according to

IEC 61000-4-5 Fig 2. ESD pulse waveform according to

IEC 61000-4-2

t (µs)

0403010 20

001aaa630

120

IPP

(%)

e−t

100 % IPP; 8 µs

50 % IPP; 20 µs

001aaa631

IPP

100 %

90 %

30 ns 60 ns

10 %

tr = 0.7 ns to 1 ns

Table 8. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Per device

Rth(j-a) thermal resistance from

junction to ambient in free air [1][2] - - 500 K/W

Rth(j-sp) thermal resistance from

junction to solder point - - 360 K/W

Product data sheet Rev. 01 — 11 May 2009 5 of 13

NXP Semiconductors NUP1301

Ultra low capacitance ESD protection array

7. Characteristics

[1] Pulse test: tp≤300 µs; δ≤0.02.

[2] Non-repetitive current pulse 8/20 µs exponential decay waveform according to IEC 61000-4-5.

[3] Measured from pin 3 to pins 1 and 2 (pins 1 and 2 are connected).

Table 9. Electrical characteristics

amb

=25

C unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Per diode

VBR breakdown voltage IR= 100 µA 100 - - V

VFforward voltage [1]

IF= 1 mA - - 715 mV

IF= 10 mA - - 855 mV

IF=50mA --1V

IF= 150 mA - - 1.25 V

IRreverse current VR=25V --30nA

VR= 80 V - - 100 nA

VR=25V;

Tj= 150 °C--25µA

VR=80V;

Tj= 150 °C--35µA

Cddiode capacitance f = 1 MHz; VR= 0 V - 0.6 0.75 pF

Per device

VCL clamping voltage IPP =1A [2][3] --3V

IPP =11A [2][3] --20V

Product data sheet Rev. 01 — 11 May 2009 6 of 13

NXP Semiconductors NUP1301

Ultra low capacitance ESD protection array

(1) Tamb = 150 °C

(2) Tamb =85°C

(3) Tamb =25°C

(4) Tamb =−40 °C

Based on square wave currents.

Tj=25°C; prior to surge

Fig 3. Forward current as a function of forward

voltage; typical values Fig 4. Non-repetitive peak forward current as a

function of pulse duration; typical values

(1) Tamb = 150 °C

(2) Tamb =85°C

(3) Tamb =25°C

(4) Tamb =−40 °C

Tamb =25°C; f = 1 MHz

Fig 5. Reverse current as a function of reverse

voltage; typical values Fig 6. Diode capacitance as a function of reverse

voltage; typical values

006aab132

102

103

(mA)

10−1

VF (V)

0 1.41.00.4 0.80.2 1.20.6

(1) (2) (3) (4)

mbg704

102

IFSM

(A)

10−1

tp (µs)

110

103

10 102

006aab133

102

(µA)

VR (V)

0 1008040 6020

10−1

10−2

10−3

10−4

10−5

(1)

(2)

(3)

(4)

0816124

0.8

0.6

0.4

0.2

mbg446

VR (V)

(pF)

Product data sheet Rev. 01 — 11 May 2009 7 of 13

NXP Semiconductors NUP1301

Ultra low capacitance ESD protection array

Fig 7. ESD clamping test setup and waveforms

006aab567

50 Ω

CZDUT

(DEVICE

UNDER

TEST)

GND

450 ΩRG 223/U

50 Ω coax

ESD TESTER

acc. to IEC 61000-4-2

CZ = 150 pF; RZ = 330 Ω

4 GHz DIGITAL

OSCILLOSCOPE

10×

ATTENUATOR

unclamped +8 kV ESD pulse waveform

(IEC 61000-4-2 network)

clamped −8 kV ESD pulse waveform

(IEC 61000-4-2 network), pin 3 to 1 and 2

vertical scale = 10 A/div

horizontal scale = 15 ns/div

GND

unclamped −8 kV ESD pulse waveform

(IEC 61000-4-2 network)

vertical scale = 10 A/div

horizontal scale = 15 ns/div

clamped +8 kV ESD pulse waveform

(IEC 61000-4-2 network), pin 3 to 1 and 2

GND

vertical scale = 10 V/div

horizontal scale = 15 ns/div

vertical scale = 10 V/div

horizontal scale = 15 ns/div

Product data sheet Rev. 01 — 11 May 2009 8 of 13

NXP Semiconductors NUP1301

Ultra low capacitance ESD protection array

8. Application information

Protection of a single (high-speed) data line in rail-to-rail conﬁguration. The protected data

line is connected to pin 3. Pin 1 is connected to ground (GND) and pin 2 is connected to

the supply rail (supply voltage VCC.) When the transient voltage exceeds the forward

voltage drop of one diode, the transient is directed either to the supply rail or to GND.

The advantages of these solutions are: low line capacitance (0.6 pF typically), fast

response time, and low clamping voltage.

Circuit board layout and protection device placement:

Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)

and surge transients. The following guidelines are recommended:

1. Place the NUP1301 as close to the input terminal or connector as possible.

2. The path length between the NUP1301 and the protected line should be minimized.

3. Keep parallel signal paths to a minimum.

4. Avoid running protected conductors in parallel with unprotected conductors.

5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and

ground loops.

6. Minimize the length of the transient return path to ground.

7. Avoid using shared transient return paths to a common ground point.

8. Ground planes should be used whenever possible. For multilayer PCBs, use ground

vias.

9. Test information

9.1 Quality information

This product has been qualiﬁed in accordance with the Automotive Electronics Council

(AEC) standard

Q101 - Stress test qualiﬁcation for discrete semiconductors

, and is

suitable for use in automotive applications.

Fig 8. Typical application for the protection of one signal line

006aab568

Audio

interface

NUP1301

VCC

Product data sheet Rev. 01 — 11 May 2009 9 of 13

NXP Semiconductors NUP1301

Ultra low capacitance ESD protection array

10. Package outline

11. Packing information

[1] For further information and the availability of packing methods, see Section 15.

Fig 9. Package outline SOT23 (TO-236AB)

04-11-04Dimensions in mm

0.45

0.15

1.9

1.1

0.9

3.0

2.8

2.5

2.1 1.4

1.2

0.48

0.38 0.15

0.09

Table 10. Packing methods

The indicated -xxx are the last three digits of the 12NC ordering code.

[1]

Type number Package Description Packing quantity

3000 10000

NUP1301 SOT23 4 mm pitch, 8 mm tape and reel -215 -235

Product data sheet Rev. 01 — 11 May 2009 10 of 13

NXP Semiconductors NUP1301

Ultra low capacitance ESD protection array

12. Soldering

Fig 10. Reﬂow soldering footprint SOT23 (TO-236AB)

Fig 11. Wave soldering footprint SOT23 (TO-236AB)

solder lands

solder resist

occupied area

solder paste

sot023_fr

0.5

(3×)

0.6

(3×)

0.6

(3×)

0.7

(3×)

3.3

2.9

1.7

1.9

Dimensions in mm

solder lands

solder resist

occupied area

preferred transport direction during soldering

sot023_fw

2.8

4.5

1.4

4.6

1.4

(2×)

1.2

(2×)

2.2

2.6

Dimensions in mm

Product data sheet Rev. 01 — 11 May 2009 11 of 13

NXP Semiconductors NUP1301

Ultra low capacitance ESD protection array

13. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

NUP1301_1 20090511 Product data sheet - -

Product data sheet Rev. 01 — 11 May 2009 12 of 13

NXP Semiconductors NUP1301

Ultra low capacitance ESD protection array

14. Legal information

14.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

14.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

14.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

14.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

15. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors NUP1301

Ultra low capacitance ESD protection array

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 11 May 2009

Document identifier: NUP1301_1

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

16. Contents

1 Product proﬁle . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4

7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Application information. . . . . . . . . . . . . . . . . . . 8

9 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 8

9.1 Quality information . . . . . . . . . . . . . . . . . . . . . . 8

10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

11 Packing information. . . . . . . . . . . . . . . . . . . . . . 9

12 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11

14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12

14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12

14.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

14.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

14.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

15 Contact information. . . . . . . . . . . . . . . . . . . . . 12

16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13