Semiconductor Components Industries, LLC, 2004
September, 2004 − Rev. 4 1Publication Order Number:
LM211/D
LM211, LM311
Single Comparators
The ability to operate from a single power supply of 5.0 V to 30 V or
15 V split supplies, as commonly used with operational amplifiers,
makes the LM211/LM311 a truly versatile comparator. Moreover, the
inputs of the device can be isolated from system ground while the
output can drive loads referenced either to ground, the VCC or the VEE
supply. This flexibility makes it possible to drive DTL, RTL, TTL, or
MOS logic. The output can also switch voltages to 50 V at currents to
50 mA, therefore, the LM211/LM311 can be used to drive relays,
lamps or solenoids.
Features
•Pb−Free Packages are Available
Figure 1. Typical Comparator Design Configurations
Split Power Supply with Offset Balance Single Supply
Ground−Referred Load
Load Referred to Positive Supply Strobe Capability
−
Output
VEE
Inputs
VCC
RL
1
2
3
4
5
6
7
8
5.0k
3.0k
VCC
VCC
VCC
VCC
VCC
Output
Output
Output
Output
Output
RL
RL
RL
RL
RL
Inputs
Inputs
Inputs
Inputs
Inputs
VEE
VEE
VEE
VEE
VEE
2
3
2
3
2
3
2
3
2
3
4
4
4
4
4
7
8
1
Input polarity is reversed when
GND pin is used as an output.
7
1
8
8
7
6
1
1.0k
TTL Strobe
1
7
8
Load Referred to Negative Supply
1
7
8
Input polarity is reversed when
GND pin is used as an output.
−
+
+
+
+
+
+
−−
−
−
PDIP−8
N SUFFIX
CASE 626
1
8
SOIC−8
D SUFFIX
CASE 751
1
8
GN
D
Inputs
VEE
VCC
Output
Balance/Strobe
Balance
(Top View)
1
2
3
4
8
7
6
5
PIN CONNECTIONS
+
−
See detailed ordering and shipping information and marking
information in the package dimensions section on page 7 of
this data sheet.
ORDERING & DEVICE MARKING
INFORMATION
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LM211, LM311
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2
MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.)
Rating Symbol LM211 LM311 Unit
Total Supply Voltage VCC +VEE36 36 Vdc
Output to Negative Supply Voltage VO −VEE 50 40 Vdc
Ground to Negative Supply Voltage VEE 30 30 Vdc
Input Differential Voltage VID ±30 ±30 Vdc
Input Voltage (Note 2) Vin ±15 ±15 Vdc
Voltage at Strobe Pin − VCC to VCC−5 VCC to VCC−5 Vdc
Power Dissipation and Thermal Characteristics
Plastic DIP PD625 mW
Derate Above TA = +25°C RJA 5.0 mW/°C
Operating Ambient Temperature Range TA−25 to +85 0 to +70 °C
Operating Junction Temperature TJ(max) +150 +150 °C
Storage Temperature Range Tstg −65 to +150 −65 to +150 °C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted) Note 1
LM211 LM311
Characteristic Symbol Min Typ Max Min Typ Max Unit
Input Offset Voltage (Note 3) VIO mV
RS ≤ 50 k, TA = +25°C − 0.7 3.0 − 2.0 7.5
RS ≤ 50 k, Tlow ≤ TA ≤ Thigh* − − 4.0 − − 10
Input Offset Current (Note 3) TA = +25°C IIO − 1.7 10 − 1.7 50 nA
Tlow ≤ TA ≤ Thigh* − − 20 − − 70
Input Bias Current TA = +25°C IIB − 45 100 − 45 250 nA
Tlow ≤ TA ≤ Thigh* − − 150 − − 300
Voltage Gain AV40 200 − 40 200 − V/mV
Response Time (Note 4) − 200 − − 200 − ns
Saturation Voltage VOL V
VID ≤ −5.0 mV, IO = 50 mA, TA = 25°C − 0.75 1.5 − − −
VID ≤−10 mV, IO = 50 mA, TA = 25°C − − − − 0.75 1.5
VCC ≥ 4.5 V, VEE = 0, Tlow ≤ TA ≤ Thigh*
VID ≤6.0 mV, Isink ≤ 8.0 mA − 0.23 0.4 − − −
VID ≤10 mV, Isink ≤ 8.0 mA − − − − 0.23 0.4
Strobe ”On” Current (Note 5) IS− 3.0 − − 3.0 − mA
Output Leakage Current
VID ≥5.0 mV, VO= 35 V, TA = 25°C, Istrobe= 3.0 mA − 0.2 10 − − − nA
VID ≥10 mV, VO= 35 V, TA = 25°C, Istrobe= 3.0 mA − − − − 0.2 50 nA
VID ≥5.0 mV, VO= 35 V, Tlow ≤ TA ≤ Thigh* − 0.1 0.5 − − − A
Input Voltage Range (Tlow ≤ TA ≤ Thigh*) VICR −14.5 −14.7
to
13.8
+13.0 −14.5 −14.7
to
13.8
+13.0 V
Positive Supply Current ICC − +2.4 +6.0 − +2.4 +7.5 mA
Negative Supply Current IEE − −1.3 −5.0 − −1.3 −5.0 mA
*LM211: Tlow = −25°C, Thigh = +85°C
LM311: Tlow = 0°C, Thigh = +70°C
1. Offset voltage, offset current and bias current specifications apply for a supply voltage range from a single 5.0 V supply up to ±15 V supplies.
2. This rating applies for ±15 V supplies. The positive input voltage limit is 30 V above the negative supply. The negative input voltage limit is
equal to the negative supply voltage or 30 V below the positive supply, whichever is less.
3. The of fset voltages and of fset currents given are the maximum values required to drive the output within a volt of either supply with a 1.0 mA
load. Thus, these parameters define an error band and take into account the “worst case” ef fects of voltage gain and input impedance.
4. The response time specified is for a 100 mV input step with 5.0 mV overdrive.
5. Do not short the strobe pin to ground; it should be current driven at 3.0 mA to 5.0 mA.
LM211, LM311
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3
Figure 2. Circuit Schematic
Figure 3. Input Bias Current
versus Temperature Figure 4. Input Offset Current
versus Temperature
Figure 5. Input Bias Current versus
Differential Input Voltage Figure 6. Common Mode Limits
versus Temperature
TA, TEMPERATURE (°C) TA, TEMPERATURE (°C)
DIFFERENTIAL INPUT VOLTAGE (V)
IIB , INPUT BIAS CURRENT (nA)
IIO , INPUT OFFSET CURRENT (nA)
COMMON MODE LIMITS (V)
140
120
100
80
40
0
140
120
100
80
40
0
60
20
−55 −25 0 25 50 75 100 125
−16 −12 −8.0 −4.0 0 4.0 8.0 12 16
5.0
4.0
3.0
2.0
1.0
0
−55 −25 0 25 50 75 100 125
−55 −25 0 25 50 75 100 125
VCC
−0.5
−1.0
−1.5
0.4
0.2
VEE
8
7
1
4
VEE
GND
Output
VCC
5.0k
200
600
3.0k
300
900
800
5.4k
1.3k
250
800800
100
3.7k
730 340
3.7k
3005
6300
2
3
Inputs 1.3k
1.3k
1.3k
Balance
Balance/Strobe
TA, TEMPERATURE (°C)
Normal
VCC = +15 V
VEE = −15 V
IIB , INPUT BIAS CURRENT (nA)
Referred to Supply Voltages
VCC = +15 V
VEE = −15 V
TA = +25°C
Normal
Pins 5 & 6 Tied
to VCC
VCC = +15 V
VEE = −15 V
Pins 5 & 6 Tied
to VCC
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Figure 7. Response Time for
Various Input Overdrives Figure 8. Response Time for
Various Input Overdrives
Figure 9. Response Time for
Various Input Overdrives Figure 10. Response Time for
Various Input Overdrives
Figure 11. Output Short Circuit Current
Characteristics and Power Dissipation Figure 12. Output Saturation Voltage
versus Output Current
tTLH, RESPONSE TIME (s) tTHL, RESPONSE TIME (s)
tTLH, RESPONSE TIME (s) tTHL, RESPONSE TIME (s)
VO, OUTPUT VOLTAGE (V) IO, OUTPUT CURRENT (mA)
Vin INPUT VOLTAGE (mV)
,VO, OUTPUT VOLTAGE (V)
Vin INPUT VOLTAGE (mV)
,VO, OUTPUT VOLTAGE (V)
Vin INPUT VOLTAGE (mV)
,VO, OUTPUT VOLTAGE (V)
Vin INPUT VOLTAGE (mV)
,VO, OUTPUT VOLTAGE (V)
OUTPUT SHORT CIRCUIT CURRENT (mA)
VOL, SATURATION VOLTAGE (V)
PD, POWER DISSIPATION (W)
5.0
4.0
3.0
2.0
1.0
0
0
50
100
0 0.1 0.2 0.3 0.4 0.5 0.6
5.0
4.0
3.0
2.0
1.0
0
−100
−50
0
0 0.1 0.2 0.3 0.4 0.5 0.6
15
10
5.0
0
−5.0
−10
−15
0
−50
−100
0 1.0 2.0 0 1.0 2.0
15
10
5.0
0
−5.0
−10
−15
0
50
100
150
125
100
75
50
25
00 5.0 10 15
0.90
0.75
0.60
0.45
0.30
0.15
0
0.90
0.75
0.60
0.45
0.30
0.15
0
0 8.0 16 24 32 40 48 56
TA = +25°C
TA = −55°C
TA = +25°C
TA = +125°C
5.0 mV
20 mV
2.0 mV
Vin
+5.0V
500
VO
+5.0V
500
VO
Vin
20 mV
5.0 mV
20 mV 5.0 mV
2.0 mV
Vin
VCC
VO
2.0k
VEE
20 mV
5.0 mV
2.0 mV
Vin
VCC
VO
2.0k
VEE
Power Dissipation
Short Circuit Current
2.0 mV
VCC = +15 V
VEE = −15 V
TA = +25°C
VCC = +15 V
VEE = −15 V
TA = +25°C
VCC = +15 V
VEE = −15 V
TA = +25°C
VCC = +15 V
VEE = −15 V
TA = +25°C
LM211, LM311
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5
8
8
Figure 13. Output Leakage Current
versus Temperature Figure 14. Power Supply Current
versus Supply Voltage
Figure 15. Power Supply Current
versus Temperature
APPLICATIONS INFORMATION
Figure 16. Improved Method of Adding
Hysteresis Without Applying Positive
Feedback to the Inputs
Figure 17. Conventional Technique
for Adding Hysteresis
OUTPUT LEAKAGE CURRENT (mA)
POWER SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
TA, TEMPERATURE (°C)
TA, TEMPERATURE (°C)
VCC−VEE, POWER SUPPLY VOLTAGE (V)
100
10
1.0
0.1
0.01
25 45 65 85 105 125
3.6
3.0
2.4
1.8
1.2
0.6
0
0 5.0 10 15 20 25 30
2.2
1.8
1.4
1.0
−55 −25 0 25 50 75 100 125
Positive and Negative Supply − Output High
Postive Supply − Output Low
+15 V
823.0 k
33 k
5.0 k
C1
0.002
F
6
2
R1
R2
C2
Input
34
17
−15 V
5
4.7 k
LM311
0.1 F
Output
+
−
0.1 F
+15 V
3.0 k
5.0 k
C1
6
3
R1
R2
C2
Input
24
17
−15 V
5
4.7 k
LM311
0.1 F
Output
+
−
0.1 F
510 k
1.0 M
100
100
3.0
2.6
VCC = +15 V
VEE = −15 V
TA = +25°C
Output VO = +50 V (LM211 only)
Positive Supply − Output Low
Positive and Negative Power Supply − Output H igh
VCC = +15 V
VEE = −15 V
LM211, LM311
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TECHNIQUES FOR AVOIDING OSCILLATIONS IN COMPARATOR APPLICATIONS
When a high speed comparator such as the LM211 is used
with high speed input signals and low source impedances,
the output response will normally be fast and stable,
providing the power supplies have been bypassed (with
0.1 F disc capacitors), and that the output signal is routed
well away from the inputs (Pins 2 and 3) and also away from
Pins 5 and 6.
However, when the input signal is a voltage ramp or a slow
sine wave, or if the signal source impedance is high (1.0 k
to 100 k), the comparator may burst into oscillation near
the crossing−point. This is due to the high gain and wide
bandwidth of comparators like the LM211 series. To avoid
oscillation or instability in such a usage, several precautions
are recommended, as shown in Figure 16.
The trim pins (Pins 5 and 6) act as unwanted auxiliary
inputs. If these pins are not connected to a trim−pot, they
should be shorted together. If they are connected to a
trim−pot, a 0.01 F capacitor (C1) between Pins 5 and 6 will
minimize the susceptibility to AC coupling. A smaller
capacitor is used if Pin 5 is used for positive feedback as in
Figure 16. For the fastest response time, tie both balance pins
to VCC.
Certain sources will produce a cleaner comparator output
waveform i f a 100 pF to 1000 pF capacitor (C2) is connected
directly across the input pins. When the signal source is
applied through a resistive network, R1, it is usually
advantageous to choose R2 of the same value, both for DC
and for dynamic (AC) considerations. Carbon, tin−oxide,
and metal−film resistors have all been used with good results
in comparator input circuitry, but inductive wirewound
resistors should be avoided.
When comparator circuits use input resistors (e.g.,
summing r esistors), t heir v alue a nd p lacement a re p articularly
important. I n a ll c ases t he b ody o f t he r esistor s hould b e c lose
to t he d evice o r s ocket. I n o ther w ords, t here should b e a v ery
short lead length or printed−circuit foil run between
comparator and resistor to radiate or pick up signals. The
same applies to capacitors, pots, etc. For example, if R1 =
10 k, as little as 5 inches of lead between the resistors and
the input pins can result in oscillations that are very hard to
dampen. Twisting these input leads tightly is the best
alternative to placing resistors close to the comparator.
Since feedback to almost any pin of a comparator can
result in oscillation, the printed−circuit layout should be
engineered thoughtfully. Preferably there should be a
groundplane under the LM211 circuitry (e.g., one side of a
double layer printed circuit board). Ground, positive supply
or negative supply foil should extend between the output and
the inputs to act as a guard. The foil connections for the
inputs should be as small and compact as possible, and
should be essentially surrounded by ground foil on all sides
to guard against capacitive coupling from any fast
high−level signals (such as the output). If Pins 5 and 6 are not
used, they should be shorted together. If they are connected
to a trim−pot, the trim−pot should be located no more than
a few inches away from the LM21 1, and a 0.01 F capacitor
should be installed across Pins 5 and 6. If this capacitor
cannot be used, a shielding printed−circuit foil may be
advisable between Pins 6 and 7. The power supply bypass
capacitors should be located within a couple inches of the
LM211.
A standard procedure is to add hysteresis to a comparator
to prevent oscillation, and to avoid excessive noise on the
output. In the circuit of Figure 17, the feedback resistor of
510 k from the output to the positive input will cause about
3.0 mV of hysteresis. However, if R2 is larger than 100 ,
such as 50 k, it would not be practical to simply increase
the value of the positive feedback resistor proportionally
above 510 k to maintain the same amount of hysteresis.
When both inputs of the LM211 are connected to active
signals, o r i f a high−impedance signal is driving the positive
input of the LM211 so that positive feedback would be
disruptive, the circuit of Figure 16 is ideal. The positive
feedback is applied to Pin 5 (one of the offset adjustment
pins). This will be sufficient to cause 1.0 mV to 2.0 mV
hysteresis and sharp transitions with input triangle waves
from a few Hz to hundreds of kHz. The positive−feedback
signal across the 82 resistor swings 240 mV below the
positive supply. This signal is centered around the nominal
voltage at Pin 5, so this feedback does not add to the offset
voltage of the comparator. As much as 8.0 mV of offset
voltage can be trimmed out, using the 5.0 k pot and 3.0 k
resistor as shown.
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7
Figure 18. Zero−Crossing Detector
Driving CMOS Logic Figure 19. Relay Driver with Strobe Capability
VCC = +15 V
3.0 k
10 k
VCC
5.0 k
LM311
Inputs
VEE
VEE = −15 V
Output
to CMOS Logic
Balance
Adjust
Balance
Input
GND
*D1
VCC2
VCC1
VEE
VEE VCC
Output
Inputs LM311
GND
1.0k
Q1
Balance/Strobe
2N2222 or
Equivalent
*Zener Diode D1
protects the comparator
from inductive kickback
and voltage transients
on the VCC2 supply line.
TTL
Strobe
+
+
ORDERING INFORMATION
Device Package Shipping†
LM211D SOIC−8
LM211DR2 SOIC−8
98 Units / Rail
LM211DR2G SOIC−8
(Pb−Free)
98
Units
/
Rail
LM311D SOIC−8 2500 Units / Reel
LM311DG SOIC−8
(Pb−Free) 98 Units / Rail
LM311DR2 SOIC−8
LM311DR2G SOIC−8
(Pb−Free) 2500 Units / Reel
LM311N PDIP−8
LM311NG PDIP−8
(Pb−Free) 50 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
PDIP−8
N SUFFIX
CASE 626
SOIC−8
D SUFFIX
CASE 751
AWL
LM311N
1
8
YYWW
x = 2 or 3
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
ALYW
LMx11
1
8
LM211, LM311
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8
PACKAGE DIMENSIONS
PDIP−8
N SUFFIX
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
58
F
NOTE 2 −A−
−B−
−T−
SEATING
PLANE
H
J
GDK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M−−− 10 −−− 10
N0.76 1.01 0.030 0.040

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9
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AC
1.52
0.060
7.0
0.275
0.6
0.024 1.270
0.050
4.0
0.155
mm
inches
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
SEATING
PLANE
1
4
58
N
J
X 45
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
AMIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) Z SXS
M

LM211, LM311
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to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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LM211/D
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