General Description
The MAX1516/MAX1517/MAX1518 include a high-perfor-
mance step-up regulator, two linear-regulator controllers,
and high-current operational amplifiers for active-matrix
thin-film transistor (TFT) liquid-crystal displays (LCDs).
Also included is a logic-controlled, high-voltage switch
with adjustable delay.
The step-up DC-DC converter provides the regulated
supply voltage for the panel source driver ICs. The con-
verter is a high-frequency (1.2MHz) current-mode regu-
lator with an integrated 14V n-channel MOSFET that
allows the use of ultra-small inductors and ceramic
capacitors. It provides fast transient response to pulsed
loads while achieving efficiencies over 85%.
The gate-on and gate-off linear-regulator controllers
provide regulated TFT gate-on and gate-off supplies
using external charge pumps attached to the switching
node. The MAX1518 includes five high-performance
operational amplifiers, the MAX1517 includes three,
and the MAX1516 includes one operational amplifier.
These amplifiers are designed to drive the LCD back-
plane (VCOM) and/or the gamma-correction divider
string. The devices feature high output current
(±150mA), fast slew rate (13V/µs), wide bandwidth
(12MHz), and rail-to-rail inputs and outputs.
The MAX1516/MAX1517/MAX1518 are available in 32-
pin thin QFN packages with a maximum thickness of
0.8mm for ultra-thin LCD panels. Applications
Notebook Computer Displays
LCD Monitor Panels
Automotive Displays
Features
♦2.6V to 5.5V Input Supply Range
♦1.2MHz Current-Mode Step-Up Regulator
Fast Transient Response to Pulsed Load
High-Accuracy Output Voltage (1.5%)
Built-In 14V, 2.4A, 0.16ΩN-Channel MOSFET
High Efficiency (90%)
♦Linear-Regulator Controllers for VGON and VGOFF
♦High-Performance Operational Amplifiers
±150mA Output Short-Circuit Current
13V/µs Slew Rate
12MHz, -3dB Bandwidth
Rail-to-Rail Inputs/Outputs
♦Logic-Controlled, High-Voltage Switch with
Adjustable Delay
♦Timer-Delay Fault Latch for All Regulator Outputs
♦Thermal-Overload Protection
♦0.6mA Quiescent Current
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
STEP-UP
CONTROLLER
GATE-ON
CONTROLLER
SWITCH
CONTROL
GATE-OFF
CONTROLLER
REF
VCN VCP
VMAIN
LX
FB
PGND
AGND
DRVP
FBP
VCP
VGON
VCN
VGOFF
DEL
CTL
DRVN
FBN
NEG4
REF
POS4
NEG5
POS5
OUT4
OUT5
BGND
NEG2
POS2
OP3
POS3
OUT2
OUT3
POS1
OUT1
NEG1
SUP
COM
DRN
SRC
COMP
IN
VIN
MAX1518
OP2
OP1
OP5
OP4
Minimal Operating Circuit
19-3244; Rev 0; 4/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART
TEMP RANGE
PIN-PACKAGE
MAX1516ETJ
-40°C to +100°C
32 Thin QFN 5mm x 5mm
MAX1517ETJ
-40°C to +100°C
32 Thin QFN 5mm x 5mm
MAX1518ETJ
-40°C to +100°C
32 Thin QFN 5mm x 5mm
Pin Configurations appear at end of data sheet.
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN, CTL to AGND......................................................-0.3V to +6V
COMP, FB, FBP, FBN, DEL, REF to AGND ....-0.3V to (VIN + 0.3V)
PGND, BGND to AGND......................................................±0.3V
LX to PGND ............................................................-0.3V to +14V
SUP to AGND .........................................................-0.3V to +14V
DRVP, SRC to AGND..............................................-0.3V to +30V
POS_, NEG_, OUT_ to AGND...................-0.3V to (VSUP + 0.3V)
POS1 to NEG1, POS2 to NEG2, POS3 to NEG3,
POS4 to NEG4, POS5 to NEG5...............................-6V to +6V
DRVN to AGND...................................(VIN - 30V) to (VIN + 0.3V)
COM, DRN to AGND ................................-0.3V to (VSRC + 0.3V)
DRN to COM............................................................-30V to +30V
OUT_ Maximum Continuous Output Current....................±75mA
LX Switch Maximum Continuous RMS Output Current.........1.6A
Continuous Power Dissipation (TA= +70°C)
32-Pin Thin QFN (derate 21.2mW/°C above +70°C) ..1702mW
Operating Temperature Range .........................-40°C to +100°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(VIN = 3V, VSUP = 8V, PGND = AGND = BGND = 0, IREF = 25µA, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless other-
wise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IN Supply Range VIN 2.6 5.5 V
IN Undervoltage-Lockout
Threshold VUVLO VIN rising, typical hysteresis = 150mV 2.3 2.5 2.7 V
VFB = VFBP = 1.4V, VFBN = 0,
LX not switching 0.6 0.8
IN Quiescent Current IIN VFB = 1.1V, VFBP = 1.4V, VFBN = 0,
LX switching 611
mA
Duration to Trigger Fault
Condition 55 ms
REF Output Voltage -2µA < IREF < 50µA, VIN = 2.6V to 5.5V
1.231 1.250 1.269
V
Temperature rising
+160
Thermal Shutdown Hysteresis 15 °C
MAIN STEP-UP REGULATOR
Output Voltage Range VMAIN VIN 13 V
Operating Frequency fOSC
1020 1200 1380
kHz
Oscillator Maximum Duty Cycle 84 87 90 %
TA = +25°C to +85°C1.221 1.233 1.245
FB Regulation Voltage VFB No load TA = 0°C to +85°C
1.218 1.233 1.247
V
FB Fault Trip Level VFB falling
0.96 1.00 1.04
V
FB Load Regulation 0 < IMAIN < full load, transient only
-1.6
%
FB Line Regulation VIN = 2.6V to 5.5V
+0.04 ±0.15
%/ V
FB Input Bias Current VFB = 1.4V -40
+40
nA
FB Transconductance ∆ICOMP = 5µA 75
150 280
µS
FB Voltage Gain FB to COMP
600
V/ V
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3V, VSUP = 8V, PGND = AGND = BGND = 0, IREF = 25µA, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless other-
wise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
LX On-Resistance
RLX
(
ON
)
160 250
mΩ
LX Leakage Current ILX VLX = 13V
0.02
40 µA
LX Current Limit ILIM VFB = 1V, duty cycle = 65% 2.5 3.0 3.5 A
Current-Sense
Transconductance 3.0 3.8 5 S
Soft-Start Period tSS 14 ms
Soft-Start Step Size
ILIM / 8
A
OPERATIONAL AMPLIFIERS
SUP Supply Range VSUP 4.5
13.0
V
MAX1518 3.2 4.8
MAX1517 2 3
SUP Supply Current ISUP Buffer configuration,
VPOS_ = 4V, no load
MAX1516 0.7 1.1
mA
Input Offset Voltage VOS (VNEG_, VPOS_, VOUT_) ≅ VSUP / 2,
TA = +25°C012mV
Input Bias Current IBIAS (VNEG_ , VPOS_, VOUT_) ≅ VSUP / 2 +1
±50
nA
Input Common-Mode Range VCM 0
VSUP
V
Common-Mode Rejection Ratio CMRR 0 ≤ (VNEG_, VPOS_) ≤ VSUP 45 dB
Open-Loop Gain
125
dB
IOUT_ = 100µA
VSUP -
15
VSUP -
3
Output Voltage Swing, High VOH
IOUT_ = 5mA
VSUP -
150
VSUP -
80
mV
IOUT_ = -100µA 2 15
Output Voltage Swing, Low VOL IOUT_ = -5mA 70
150
mV
Short-Circuit Current To VSUP / 2, source or sink 50
150
mA
Output Source and Sink Current (VNEG_ , VPOS_, VOUT_) ≅ VSUP / 2,
|∆VOS| < 10mV 40 mA
Power-Supply Rejection Ratio PSRR DC, 6V ≤ VSUP ≤ 13V,
(VNEG_, VPOS_) ≅ VSUP/2 60 dB
Slew Rate 13 V/µs
-3dB Bandwidth
RL = 10kΩ, CL = 10pF, buffer configuration
12
MHz
Gain-Bandwidth Product GBW Buffer configuration 8
MHz
GATE-ON LINEAR-REGULATOR CONTROLLER
FBP Regulation Voltage VFBP IDRVP = 100µA
1.231 1.250 1.269
V
FBP Fault Trip Level VFBP falling
0.96 1.00 1.04
V
FBP Input Bias Current IFBP VFBP = 1.4V -50
+50
nA
FBP Effective Load-Regulation
Error (Transconductance) VDRVP = 10V, IDRVP = 50µA to 1mA
-0.7 -1.5
%
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
4_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3V, VSUP = 8V, PGND = AGND = BGND = 0, IREF = 25µA, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless other-
wise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
FBP Line (IN) Regulation Error IDRVP = 100µA, 2.6V < VIN < 5.5V
±1.5
±5 mV
DRVP Sink Current IDRVP VFBP = 1.1V, VDRVP = 10V 1 5 mA
DRVP Off-Leakage Current VFBP = 1.4V, VDRVP = 28V
0.01
10 µA
Soft-Start Period tSS 14 ms
Soft-Start Step Size
VREF /
128
V
GATE-OFF LINEAR-REGUALTOR CONTROLLER
FBN Regulation Voltage VFBN IDRVN = 100µA
235 250 265
mV
FBN Fault Trip Level VFBN rising
370 420 470
mV
FBN Input Bias Current IFBN VFBN = 0 -50
+50
nA
FBN Effective Load-Regulation
Error (Transconductance) VDRVN = -10V, IDRVN = 50µA to 1mA 11 25 mV
FBN Line (IN) Regulation Error IDRVN = 0.1mA, 2.6V < VIN < 5.5V
+0.7
±5 mV
DRVN Source Current IDRVN VFBN = 500mV, VDRVN = -10V 1 4 mA
DRVN Off-Leakage Current VFBN = 0V, VDRVN = -25V
-0.01
-10 µA
Soft-Start Period tSS 14 ms
Soft-Start Step Size
VREF /
128
V
POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES
DEL Capacitor Charge Current During startup, VDEL = 1V 4 5 6 µA
DEL Turn-On Threshold
VTH
(
DEL
)
1.19 1.25 1.31
V
DEL Discharge Switch On-
Resistance During UVLO, VIN = 2.2V 20 Ω
CTL Input Low Voltage VIN = 2.6V to 5.5V 0.6 V
CTL Input High Voltage VIN = 2.6V to 5.5V 2 V
CTL Input Leakage Current CTL = AGND or IN -1 +1 µA
CTL-to-SRC Propagation Delay
100
ns
SRC Input Voltage Range 28 V
VDEL = 1.5V, CTL = IN 50
100
SRC Input Current ISRC VDEL = 1.5V, CTL = AGND 15 30 µA
SRC to COM Switch On-
Resistance
RSRC
(
ON
)
VDEL = 1.5V, CTL = IN 6 12 Ω
DRN to COM Switch On-
Resistance
RDRN
(
ON
)
VDEL = 1.5V, CTL = AGND 35 70 Ω
COM to PGND Switch On-
Resistance
RCOM
(
ON
)
VDEL = 1.1V
350 1000 1800
Ω
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS
(VIN = 3V, VSUP = 8V, PGND = AGND = BGND = 0, IREF = 25µA, TA= -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN MAX
UNITS
IN Supply Range VIN 2.6 5.5 V
IN Undervoltage-Lockout
Threshold VUVLO VIN rising, typical hysteresis = 150mV
2.265 2.715
V
VFB = VFBP = 1.4V, VFBN = 0,
LX not switching 0.8
IN Quiescent Current IIN VFB = 1.1V, VFBP = 1.4V, VFBN = 0,
LX switching 11
mA
REF Output Voltage -2µA < IREF < 50µA, VIN = 2.6V to 5.5V
1.222 1.269
V
MAIN STEP-UP REGULATOR
Output Voltage Range VMAIN VIN 13 V
Operating Frequency fOSC
1020 1380
kHz
FB Regulation Voltage VFB No load
1.212 1.250
V
FB Line Regulation VIN = 2.6V to 5.5V
±0.15
%/ V
FB Input Bias Current VFB = 1.4V -40
+40
nA
FB Transconductance ∆ICOMP = 5µA 75
300
µS
LX On-Resistance
RLX
(
ON
)
250
mΩ
LX Current Limit ILIM VFB = 1V, duty cycle = 65% 2.5 3.5 A
OPERATIONAL AMPLIFIERS
SUP Supply Range VSUP 4.5
13.0
V
MAX1518 4.8
MAX1517 3.0SUP Supply Current ISUP Buffer configuration,
VPOS_ = 4V, no load
MAX1516 1.1
mA
Input Offset Voltage VOS (VNEG_, VPOS_, VOUT_) ≅ VSUP / 2 12 mV
Input Common-Mode Range VCM 0
VSUP
V
IOUT_ = 100µA
VSUP -
15
Output Voltage Swing, High VOH
IOUT_ = 5mA
VSUP -
150
mV
IOUT_ = -100µA 15
Output Voltage Swing, Low VOL IOUT_ = -5mA
150
mV
Source 50
Short-Circuit Current To VSUP / 2 Sink 50 mA
Output Source and Sink Current (VNEG_ , VPOS_, VOUT_) ≅ VSUP / 2,
|∆VOS| < 10mV 40 mA
GATE-ON LINEAR-REGULATOR CONTROLLER
FBP Regulation Voltage VFBP IDRVP = 100µA
1.218
1.269
V
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
6_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3V, VSUP = 8V, PGND = AGND = BGND = 0, IREF = 25µA, TA= -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
FBP Effective Load-Regulation
Error (Transconductance) VDRVP = 10V, IDRVP = 50µA to 1mA -2 %
FBP Line (IN) Regulation Error IDRVP = 100µA, 2.6V < VIN < 5.5V 5 mV
DRVP Sink Current IDRVP VFBP = 1.1V, VDRVP = 10V 1 mA
GATE-OFF LINEAR-REGULATOR CONTROLLER
FBN Regulation Voltage VFBN IDRVN = 100µA
235
265
mV
FBN Effective Load-Regulation
Error (Transconductance) VDRVN = -10V, IDRVN = 50µA to 1mA 25 mV
FBN Line (IN) Regulation Error IDRVN = 0.1mA, 2.6V < VIN < 5.5V 5 mV
DRVN Source Current IDRVN VFBN = 500mV, VDRVN = -10V 1 mA
POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES
DEL Capacitor Charge Current During startup, VDEL = 1V 4 6 µA
DEL Turn-On Threshold
VTH
(
DEL
)
1.19 1.31
V
CTL Input Low Voltage VIN = 2.6V to 5.5V 0.6 V
CTL Input High Voltage VIN = 2.6V to 5.5V 2 V
SRC Input Voltage Range 28 V
VDEL = 1.5V, CTL = IN
100
SRC Input Current ISRC VDEL = 1.5V, CTL = AGND 30 µA
SRC to COM Switch On-
Resistance
RSRC
(
ON
)
VDEL = 1.5V, CTL = IN 12 Ω
DRN to COM Switch On-
Resistance
RDRN
(
ON
)
VDEL = 1.5V, CTL = AGND 70 Ω
COM to PGND Switch On-
Resistance
RCOM
(
ON
)
VDEL = 1.1V
350 1800
Ω
Note 1: Specifications to -40°C are guaranteed by design, not production tested.
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
_______________________________________________________________________________________ 7
STEP-UP EFFICIENCY
vs. LOAD CURRENT
MAX1516 toc01
LOAD CURRENT (mA)
EFFICIENCY (%)
10010
40
50
60
70
80
90
100
30
1 1000
VIN = 5.0V
VOUT = 13V
VIN = 3.3V
SWITCHING FREQUENCY
vs. INPUT VOLTAGE
MAX1516 toc02
INPUT VOLTAGE (V)
SWITCHING FREQUENCY (MHz)
5.04.54.03.53.0
1.1
1.2
1.3
1.4
1.0
2.5 5.5
STEP-UP SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1516 toc03
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
5.04.54.03.53.0
2
4
6
8
10
0
2.5 5.5
NO LOAD, SUP DISCONNECTED,
R1 = 95.3kΩ, R2 = 10.2kΩ
CURRENT INTO INDUCTOR
CURRENT INTO IN PIN
STEP-UP REGULATOR SOFT-START
(HEAVY LOAD)
MAX1516 toc04
2ms/div
A: VIN, 5V/div
B: VMAIN, 5V/div
C: INDUCTOR CURRENT, 1A/div
0V
A
B
0V
C
0A
10µs/div
STEP-UP REGULATOR PULSED
LOAD-TRANSIENT RESPONSE
13V
200mA
C
MAX1516 toc05
B
0A
A
A: LOAD CURRENT, 1A/div
B: VMAIN, 200mV/div, AC-COUPLED
C: INDUCTOR CURRENT, 1A/div
Typical Operating Characteristics
(Circuit of Figure 1. VIN = 5V, VMAIN = 13V, VGON = 24V, VGOFF = -8V, VOUT1 = VOUT2 = VOUT3 = VOUT4 = VOUT5 = 6.5V, TA= +25°C
unless otherwise noted.)
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
8_______________________________________________________________________________________
TIMER DELAY LATCH
RESPONSE TO OVERLOAD
MAX1516 toc06
10ms/div
A: VMAIN, 5V/div
B: INDUCTOR CURRENT, 1A/div
0V
A
B
0A
55ms
REF VOLTAGE LOAD REGULATION
MAX1516 toc07
LOAD CURRENT (µA)
REF VOLTAGE (V)
40302010
1.248
1.249
1.250
1.251
1.252
1.253
1.247
050
GATE-ON REGULATOR LINE REGULATION
MAX1516 toc08
INPUT VOLTAGE (V)
OUTPUT VOLTAGE ERROR (%)
292827262524
-0.8
-0.6
-0.4
-0.2
0
0.2
-1.0
23 30
VGON = 23.5V
IGON = 20mA
GATE-ON REGULATOR LOAD REGULATION
MAX1516 toc09
LOAD CURRENT (mA)
VOLTAGE ERROR (%)
15105
-0.25
-0.20
-0.15
-0.10
-0.05
0
-0.30
020
GATE-OFF REGULATOR LINE REGULATION
MAX1516 toc10
INPUT VOLTAGE (V)
OUTPUT VOLTAGE ERROR (%)
-10-12-14
0
0.25
0.50
0.75
1.00
-0.25
-16 -8
VGOFF = -8V
IGOFF = 50mA
GATE-OFF REGULATOR LOAD REGULATION
MAX1516 toc11
LOAD CURRENT (mA)
VOLTAGE ERROR (%)
40302010
-0.8
-0.6
-0.4
-0.2
0
-1.0
050
Typical Operating Characteristics (continued)
(Circuit of Figure 1. VIN = 5V, VMAIN = 13V, VGON = 24V, VGOFF = -8V, VOUT1 = VOUT2 = VOUT3 = VOUT4 = VOUT5 = 6.5V, TA= +25°C
unless otherwise noted.)
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
_______________________________________________________________________________________ 9
4ms/div
POWER-UP SEQUENCE
0V
0V
C
MAX1516 toc12
B
0V
A
A: VMAIN, 10V/div
B: VSRC, 20V/div
C: VGOFF, 10V/div
D: VGON, 20V/div
0V
D
MAX1518 OPERATIONAL-AMPLIFIER
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1516 toc13
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
8.07.57.06.56.0
1
2
3
4
5
6
0
4.5 8.5
NO-LOAD
BUFFER CONFIGURATION
VPOS1 TO VPOS5 = VSUP / 2
40µs/div
OPERATIONAL-AMPLIFIER
RAIL-TO-RAIL INPUT/OUTPUT
0V
MAX1516 toc14
B
0V
A
A: INPUT SIGNAL, 2V/div
B: OUTPUT SIGNAL, 2V/div
VSUP = 6V
Typical Operating Characteristics (continued)
(Circuit of Figure 1. VIN = 5V, VMAIN = 13V, VGON = 24V, VGOFF = -8V, VOUT1 = VOUT2 = VOUT3 = VOUT4 = VOUT5 = 6.5V, TA= +25°C
unless otherwise noted.)
400ns/div
OPERATIONAL-AMPLIFIER
LOAD-TRANSIENT RESPONSE
0V
MAX1516 toc15
B
-50mA
A
A: OUTPUT VOLTAGE, 1V/div, AC-COUPLED
B: OUTPUT CURRENT, 50mA/div
+50mA
0
1µs/div
OPERATIONAL-AMPLIFIER
LARGE-SIGNAL STEP RESPONSE
0V
MAX1516 toc16
B
A
A: INPUT SIGNAL, 2V/div
B: OUTPUT SIGNAL, 2V/div
0V
VSUP = 6V
400ns/div
OPERATIONAL-AMPLIFIER
SMALL-SIGNAL STEP RESPONSE
0V
MAX1516 toc17
B
A
A: INPUT SIGNAL, 100mV/div
B: OUTPUT SIGNAL, 100mV/div
0V
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
10 ______________________________________________________________________________________
Pin Description
NAME
PIN
MAX1516 MAX1517 MAX1518
FUNCTION
1SRC SRC SRC Switch Input. Source of the internal high-voltage p-channel MOSFET. Bypass SRC to
PGND with a minimum 0.1µF capacitor close to the pins.
2REF REF REF Reference Bypass Terminal. Bypass REF to AGND with a minimum of 0.22µF close to
the pins.
3AGND AGND AGND Analog Ground for Step-Up Regulator and Linear Regulators. Connect to power
ground (PGND) underneath the IC.
4PGND PGND PGND
Power Ground. PGND is the source of the main step-up n-channel power MOSFET.
Connect PGND to the input-capacitor ground terminals through a short, wide PC board
trace. Connect to analog ground (AGND) underneath the IC.
5OUT1 OUT1 OUT1 Operational-Amplifier 1 Output
6NEG1 NEG1 NEG1 Operational-Amplifier 1 Inverting Input
7POS1 POS1 POS1 Operational-Amplifier 1 Noninverting Input
8N.C. OUT2 OUT2 Operational-Amplifier 2 Output for the MAX1518 and MAX1517. Not Internally
Connected for the MAX1516.
9N.C. NEG2 NEG2 Operational-Amplifier 2 Inverting Input for the MAX1518 and MAX1517. Not Internally
Connected for the MAX1516.
10
I. C. POS2 POS2 Operational-Amplifier 2 Noninverting Input for the MAX1518 and MAX1517. Internally
Connected for the MAX1516. Connect this pin to GND for the MAX1516.
11
BGND BGND BGND Analog Ground for Operational Amplifiers. Connect to power ground (PGND)
underneath the IC.
12
N.C. N.C. POS3 Operational-Amplifier 3 Noninverting Input for the MAX1518. Not Internally Connected
for the MAX1517 and MAX1516.
13
N.C. N.C. OUT3 Operational-Amplifier 3 Output. Not Internally Connected for the MAX1517 and
MAX1516.
14
SUP SUP SUP Operational-Amplifier Power Input. Positive supply rail for the operational amplifiers.
Typically connected to VMAIN. Bypass SUP to BGND with a 0.1µF capacitor.
15
N.C. POS3 POS4 Operational-Amplifier 4 Noninverting Input for the MAX1518. Operational-Amplifier 3
Noninverting Input for the MAX1517. Not Internally Connected for the MAX1516.
16
N.C. NEG3 NEG4 Operational-Amplifier 4 Inverting Input for the MAX1518. Operational-Amplifier 3
Inverting Input for the MAX1517. Not Internally Connected for the MAX1516.
17
N.C. OUT3 OUT4 Operational-Amplifier 4 Output for the MAX1518. Operational-Amplifier 3 Output for the
MAX1517. Not Internally Connected for the MAX1516.
18
I. C. I. C. POS5 Operational-Amplifier 5 Noninverting Input for the MAX1518. Internally Connected for
the MAX1517 and MAX1516. Connect this pin to GND for the MAX1517 and MAX1516.
19
N.C. N.C. NEG5 Operational-Amplifier 5 Inverting Input. Not Internally Connected for the MAX1517 and
MAX1516.
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
______________________________________________________________________________________ 11
Pin Description (continued)
NAME
PIN
MAX1516 MAX1517 MAX1518
FUNCTION
20
N.C. N.C. OUT5 Operational-Amplifier 5 Output. Not Internally Connected for the MAX1517 and
MAX1516.
21
LX LX LX N-Channel Power MOSFET Drain and Switching Node. Connect the inductor and
Schottky diode to LX and minimize the trace area for lowest EMI.
22
IN IN IN Supply Voltage Input. IN can range from 2.6V to 5.5V.
23
FB FB FB
Step-Up Regulator Feedback Input. Regulates to 1.236V (nominal). Connect a resistive
voltage-divider from the output (VMAIN) to FB to analog ground (AGND). Place the
divider within 5mm of FB.
24
COMP
COMP COMP
Step-Up Regulator Error-Amplifier Compensation Point. Connect a series RC from
COMP to AGND. See the Loop Compensation section for component selection
guidelines.
25
FBP FBP FBP
Gate-On Linear-Regulator Feedback Input. FBP regulates to 1.25V (nominal). Connect
FBP to the center of a resistive voltage-divider between the regulator output and AGND
to set the gate-on linear-regulator output voltage. Place the resistive voltage-divider
close to the pin.
26
DRVP DRVP DRVP
Gate-On Linear-Regulator Base Drive. Open drain of an internal n-channel MOSFET.
Connect DRVP to the base of an external pnp pass transistor. See the Pass-Transistor
Selection section.
27
FBN FBN FBN
Gate-Off Linear-Regulator Feedback Input. FBN regulates to 250mV (nominal).
Connect FBN to the center of a resistive voltage-divider between the regulator output
and REF to set the gate-off linear-regulator output voltage. Place the resistive voltage-
divider close to the pin.
28
DRVN DRVN DRVN
Gate-Off Linear-Regulator Base Drive. Open drain of an internal p-channel MOSFET.
Connect DRVN to the base of an external npn pass transistor. See the Pass-Transistor
Selection section.
29
DEL DEL DEL High-Voltage Switch Delay Input. Connect a capacitor from DEL to AGND to set the
high-voltage switch startup delay.
30
CTL CTL CTL
High-Voltage Switch Control Input. When CTL is high, the high-voltage switch between
COM and SRC is on and the high-voltage switch between COM and DRN is off. When
CTL is low, the high-voltage switch between COM and SRC is off and the high-voltage
switch between COM and DRN is on. CTL is inhibited by the undervoltage lockout and
when the voltage on DEL is less than 1.25V.
31
DRN DRN DRN Switch Input. Drain of the internal high-voltage back-to-back p-channel MOSFETs
connected to COM.
32
COM COM COM Internal High-Voltage MOSFET Switch Common Terminal. Do not allow the voltage on
COM to exceed VSRC.
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
12 ______________________________________________________________________________________
Typical Operating Circuit
The MAX1518 Typical Operating Circuit (Figure 1) is a
complete power-supply system for TFT LCDs. The cir-
cuit generates a +13V source-driver supply and +24V
and -8V gate-driver supplies. The input voltage range
for the IC is from +2.6V to +5.5V. The listed load cur-
rents in Figure 1 are available from a +4.5V to +5.5V
supply. Table 1 lists some recommended components,
and Table 2 lists the contact information of component
suppliers.
Detailed Description
The MAX1516/MAX1517/MAX1518 contain a high-
performance step-up switching regulator, two low-cost
linear-regulator controllers, multiple high-current opera-
tional amplifiers, and startup timing and level-shifting
functionality useful for active-matrix TFT LCDs. Figure 2
shows the MAX1518 Functional Diagram.
Main Step-Up Regulator
The main step-up regulator employs a current-mode,
fixed-frequency PWM architecture to maximize loop
bandwidth and provide fast transient response to
pulsed loads typical of TFT-LCD panel source drivers.
The 1.2MHz switching frequency allows the use of low-
profile inductors and ceramic capacitors to minimize
the thickness of LCD panel designs. The integrated
high-efficiency MOSFET and the IC’s built-in digital
soft-start functions reduce the number of external com-
ponents required while controlling inrush currents. The
output voltage can be set from VIN to 13V with an exter-
nal resistive voltage-divider. To generate an output volt-
age greater than 13V, an external cascoded MOSFET
is needed. See the Generating Output Voltages > 13V
section in the Design Procedures.
The regulator controls the output voltage and the power
delivered to the output by modulating the duty cycle (D)
of the internal power MOSFET in each switching cycle.
The duty cycle of the MOSFET is approximated by:
Figure 3 shows the Functional Diagram of the step-up
regulator. An error amplifier compares the signal at FB
to 1.236V and changes the COMP output. The voltage
at COMP sets the peak inductor current. As the load
varies, the error amplifier sources or sinks current to the
COMP output accordingly to produce the inductor peak
current necessary to service the load. To maintain sta-
bility at high duty cycles, a slope-compensation signal
is summed with the current-sense signal.
On the rising edge of the internal clock, the controller
sets a flip-flop, turning on the n-channel MOSFET and
applying the input voltage across the inductor. The cur-
rent through the inductor ramps up linearly, storing
energy in its magnetic field. Once the sum of the cur-
rent-feedback signal and the slope compensation
exceeds the COMP voltage, the controller resets the
flip-flop and turns off the MOSFET. Since the inductor
current is continuous, a transverse potential develops
across the inductor that turns on the diode (D1). The
voltage across the inductor then becomes the differ-
ence between the output voltage and the input voltage.
DVV
V
MAIN IN
MAIN
≈−
DESIGNATION
DESCRIPTION
C1 22µF, 6.3V X5R ceramic capacitor (1210)
TDK C3225X5R0J227M
C2 22µF, 16V X5R ceramic capacitor (1812)
TDK C4532X5X1C226M
D1 3A, 30V Schottky diode (M-flat)
Toshiba CMS02
D2, D3
200mA, 100V, dual ultra-fast diodes (SOT23)
Fairchild MMBD4148SE
L1 3.0µH, 3A inductor
Sumida CDRH6D28-3R0
Q1 200mA, 40V pnp bipolar transistor (SOT23)
Fairchild MMBT3906
Q2 200mA, 40V npn bipolar transistor (SOT23)
Fairchild MMBT3904
Table 1. Component List
SUPPLIER PHONE FAX WEBSITE
Fairchild 408-822-2000 408-822-2102 www.fairchildsemi.com
Sumida 847-545-6700 847-545-6720 www.sumida.com
TDK 847-803-6100 847-390-4405 www.component.tdk.com
Toshiba 949-455-2000 949-859-3963 www.toshiba.com/taec
Table 2. Component Suppliers
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
______________________________________________________________________________________ 13
0.1µF
0.1µF
0.1µF
LX
D1
L1
3.0µH
LX
C2
22µF
D2
VMAIN
13V/500mA
R1
95.3kΩ
1%
R1
10.2kΩ
1%
6.8kΩ
R4
192kΩ
1%
R5
10.0kΩ
1%
Q1
0.47µF
VGON
24V/20mA
0.1µF
LX
VIN
4.5V TO 5.5V
D3
Q2
C1
22µF
220µF
C18
0.1µF
R10
10Ω
180kΩ
6.8kΩ
0.1µF
R7
332kΩ
1%
R8
40.2kΩ
1%
0.22µF
0.22µF
VGOFF
-8V/50mA
0.033µF
TO VCOM
BACKPLANE
IN
COMP
DRVN
FBN
REF
FB
AGND
PGND
DRVP
FBP
SRC
COM
LX
DEL
NEG1
NEG2
OUT2
OUT3
NEG4
OUT4
NEG5
OUT5
OUT1
DRN
CTL
SUP
BGND
POS1
POS2
POS3
POS4
POS5
MAX1518
Figure 1. Typical Operating Circuit
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
14 ______________________________________________________________________________________
STEP-UP
CONTROLLER
GATE-ON
CONTROLLER
SWITCH
CONTROL
GATE-OFF
CONTROLLER
REF
VCN VCP
VMAIN
LX
FB
PGND
AGND
DRVP
FBP
VCP
VGON
VCN
VGOFF
DEL
CTL
DRVN
FBN
NEG4
REF
POS4
NEG5
POS5
OUT4
OUT5
BGND
NEG2
POS2
OP3
POS3
OUT2
OUT3
POS1
OUT1
NEG1
SUP
COM
DRN
SRC
COMP
IN
VIN
MAX1518
OP2
OP1
OP5
OP4
Figure 2. MAX1518 Functional Diagram
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
______________________________________________________________________________________ 15
This discharge condition forces the current through the
inductor to ramp back down, transferring the energy
stored in the magnetic field to the output capacitor and
the load. The MOSFET remains off for the rest of the
clock cycle.
Gate-On Linear-Regulator Controller, REG P
The gate-on linear-regulator controller (REG P) is an
analog gain block with an open-drain n-channel output.
It drives an external pnp pass transistor with a 6.8kΩ
base-to-emitter resistor (Figure 1). Its guaranteed base-
drive sink current is at least 1mA. The regulator including
Q1 in Figure 1 uses a 0.47µF ceramic output capacitor
and is designed to deliver 20mA at 24V. Other output
voltages and currents are possible with the proper pass
transistor and output capacitor. See the Pass-Transistor
Selection and Stability Requirements sections.
REG P is typically used to provide the TFT-LCD gate
drivers’ gate-on voltage. Use a charge pump with as
many stages as necessary to obtain a voltage exceed-
ing the required gate-on voltage (see the Selecting the
Number of Charge-Pump Stages section). Note the
voltage rating of the DRVP is 28V. If the charge-pump
output voltage can exceed 28V, an external cascode
npn transistor should be added as shown in Figure 4.
Alternately, the linear regulator can control an interme-
diate charge-pump stage while regulating the final
charge-pump output (Figure 5).
REG P is enabled after the REF voltage exceeds 1.0V.
Each time it is enabled, the controller goes through a
soft-start routine that ramps up its internal reference
DAC in 128 steps.
QR
S
RESET DOMINANT
CURRENT
SENSE
Σ
OSCILLATOR
SLOPE COMP
CLOCK
LX
PGND
FB
COMP
1.236V
1.0V
SOFT-
START VLIMIT
PWM
COMPARATOR
FAULT
COMPARATOR
ILIM
COMPARATOR
TO FAULT LATCH
ERROR AMP
Figure 3. Step-Up Regulator Functional Diagram
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
16 ______________________________________________________________________________________
Gate-Off Linear-Regulator Controller, REG N
The gate-off linear-regulator controller (REG N) is an
analog gain block with an open-drain p-channel output.
It drives an external npn pass transistor with a 6.8kΩ
base-to-emitter resistor (Figure 1). Its guaranteed base-
drive source current is at least 1mA. The regulator
including Q2 in Figure 1 uses a 0.47µF ceramic output
capacitor and is designed to deliver 50mA at -8V. Other
output voltages and currents are possible with the proper
pass transistor and output capacitor (see the Pass-
Transistor Selection and Stability Requirements sections).
REG N is typically used to provide the TFT-LCD gate
drivers’ gate-off voltage. A negative voltage can be
produced using a charge-pump circuit as shown in
Figure 1. REG N is enabled after the voltage on REF
exceeds 1.0V. Each time it is enabled, the control goes
through a soft-start routine that ramps down its internal
reference DAC from VREF to 250mV in 128 steps.
Operational Amplifiers
The MAX1518 has five operational amplifiers, the
MAX1517 has three operational amplifiers, and the
MAX1516 has one operational amplifier. The operational
amplifiers are typically used to drive the LCD backplane
(VCOM) or the gamma-correction divider string. They
feature ±150mA output short-circuit current, 13V/µs slew
rate, and 12MHz bandwidth. The rail-to-rail input and
output capability maximizes system flexibility.
Short-Circuit Current Limit
The operational amplifiers limit short-circuit current to
approximately ±150mA if the output is directly shorted to
SUP or to BGND. If the short-circuit condition persists, the
junction temperature of the IC rises until it reaches the
thermal-shutdown threshold (+160°C typ). Once the junc-
tion temperature reaches the thermal-shutdown threshold,
an internal thermal sensor immediately sets the thermal
fault latch, shutting off all the IC’s outputs. The device
remains inactive until the input voltage is cycled.
Driving Pure Capacitive Load
The operational amplifiers are typically used to drive
the LCD backplane (VCOM) or the gamma-correction
divider string. The LCD backplane consists of a distrib-
uted series capacitance and resistance, a load that can
be easily driven by the operational amplifier. However,
if the operational amplifier is used in an application with
a pure capacitive load, steps must be taken to ensure
stable operation.
As the operational amplifier’s capacitive load increases,
the amplifier’s bandwidth decreases and gain peaking
increases. A 5Ωto 50Ωsmall resistor placed between
OUT_ and the capacitive load reduces peaking but also
reduces the gain. An alternative method of reducing
peaking is to place a series RC network (snubber) in par-
allel with the capacitive load. The RC network does not
continuously load the output or reduce the gain. Typical
values of the resistor are between 100Ωand 200Ω, and
the typical value of the capacitor is 10nF.
MAX1516
MAX1517
MAX1518
DRVP
FBP
VMAIN
FROM CHARGE-PUMP
OUTPUT
NPN CASCODE
TRANSISTOR
PNP PASS
TRANSISTOR
VGON
Figure 4. Using Cascoded npn for Charge-Pump Output
Voltages >28V
MAX1516
MAX1517
MAX1518
DRVP
FBP
VGON
35V
LX
VMAIN
13V
0.22µF
0.1µF
0.1µF
0.47µF
267kΩ
1%
10.0kΩ
1%
6.8kΩ
Q1
Figure 5. The linear regulator controls the intermediate charge-
pump stage.
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
______________________________________________________________________________________ 17
Undervoltage Lockout (UVLO)
The undervoltage-lockout (UVLO) circuit compares the
input voltage at IN with the UVLO threshold (2.5V rising,
2.35V falling, typ) to ensure the input voltage is high
enough for reliable operation. The 150mV (typ) hysteresis
prevents supply transients from causing a restart. Once
the input voltage exceeds the UVLO rising threshold,
startup begins. When the input voltage falls below the
UVLO falling threshold, the controller turns off the main
step-up regulator, turns off the linear-regulator outputs,
and disables the switch control block; the operational-
amplifier outputs are high impedance.
Reference Voltage (REF)
The reference output is nominally 1.25V and can
source at least 50µA (see the Typical Operating
Characteristics). Bypass REF with a 0.22µF ceramic
capacitor connected between REF and AGND.
Power-Up Sequence and Soft-Start
Once the voltage on IN exceeds approximately 1.7V,
the reference turns on. With a 0.22µF REF bypass
capacitor, the reference reaches its regulation voltage
of 1.25V in approximately 1ms. When the reference
voltage exceeds 1.0V, the ICs enable the main step-up
regulator, the gate-on linear-regulator controller, and
the gate-off linear-regulator controller simultaneously.
The IC employs soft-start for each regulator to minimize
inrush current and voltage overshoot and to ensure a
well-defined startup behavior. During the soft-start, the
main step-up regulator directly limits the peak inductor
current. The current-limit level is increased through the
soft-start period from 0 up to the full current-limit value
in eight equal current steps (ILIM / 8). The maximum
load current is available after the output voltage reach-
es regulation (which terminates soft-start), or after the
soft-start timer expires. Both linear-regulator controllers
use a 7-bit soft-start DAC. For the gate-on linear regula-
tor, the DAC output is stepped in 128 steps from zero
up to the reference voltage. For the gate-off linear regu-
lator, the DAC output steps from the reference down to
250mV in 128 steps. The soft-start duration is 14ms
(typ) for all three regulators.
A capacitor (CDEL) from DEL to AGND determines the
switch-control-block startup delay. After the input volt-
age exceeds the UVLO threshold (2.5V typ) and the
soft-start routine for each regulator is complete and
there is no fault detected, a 5µA current source starts
charging CDEL. Once the capacitor voltage exceeds
1.25V (typ), the switch-control block is enabled as
shown in Figure 6. After the switch-control block is
enabled, COM can be connected to SRC or DRN
through the internal p-channel switches, depending
upon the state of CTL. Before startup and when IN is
less than VUVLO, DEL is internally connected to AGND
to discharge CDEL. Select CDEL to set the delay time
using the following equation:
Switch-Control Block
The switch-control input (CTL) is not activated until all
four of the following conditions are satisfied: the input
voltage exceeds VUVLO, the soft-start routine of all the
regulators is complete, there is no fault condition
detected, and VDEL exceeds its turn-on threshold. As
shown in Figure 7, COM is pulled down to PGND
through a 1kΩresistor when the switch control is not
activated. Once activated and if CTL is high, the 5Ω
internal p-channel switch (Q1) between COM and SRC
turns on and the 30Ωp-channel switch (Q2) between
DRN and COM turns off. If CTL is low, Q1 turns off and
Q2 turns on.
C DELAY TIME A
V
DEL =×
µ
_.
5
125
12ms
2.5V
1.05V
1.25V
VIN
VREF
VMAIN
VGON
VGOFF
VDEL
SWITCH
CONTROL
ENABLED
SOFT-
START
ENDS
SOFT-
START
BEGINS
INPUT
VOLTAGE
OK
Figure 6. Power-Up Sequence
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
18 ______________________________________________________________________________________
Fault Protection
During steady-state operation, if the output of the main
regulator or any of the linear-regulator outputs does not
exceed its respective fault-detection threshold, the
MAX1516/MAX1517/MAX1518 activate an internal fault
timer. If any condition or combination of conditions indi-
cates a continuous fault for the fault-timer duration
(55ms typ), the MAX1516/MAX1517/MAX1518 set the
fault latch to shut down all the outputs except the refer-
ence. Once the fault condition is removed, cycle the
input voltage (below the UVLO falling threshold) to
clear the fault latch and reactivate the device. The fault-
detection circuit is disabled during the soft-start time.
Thermal-Overload Protection
Thermal-overload protection prevents excessive power
dissipation from overheating the MAX1516/MAX1517/
MAX1518. When the junction temperature exceeds TJ=
+160°C, a thermal sensor immediately activates the
fault protection, which shuts down all outputs except
the reference, allowing the device to cool down. Once
the device cools down by approximately 15°C, cycle
the input voltage (below the UVLO falling threshold) to
clear the fault latch and reactivate the device.
The thermal-overload protection protects the controller
in the event of fault conditions. For continuous opera-
tion, do not exceed the absolute maximum junction
temperature rating of TJ= +150°C.
MAX1516
MAX1517
MAX1518
FB OK
FBP OK
FBN OK
2.5V
5µA
REF
DRN
COM
SRC
Q1
Q2
Q3
1kΩ
CTL
DEL
IN
Figure 7. Switch-Control Block
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
______________________________________________________________________________________ 19
Design Procedure
Main Step-Up Regulator
Inductor Selection
The minimum inductance value, peak current rating,
and series resistance are factors to consider when
selecting the inductor. These factors influence the con-
verter’s efficiency, maximum output load capability,
transient-response time, and output voltage ripple. Size
and cost are also important factors to consider.
The maximum output current, input voltage, output volt-
age, and switching frequency determine the inductor
value. Very high inductance values minimize the cur-
rent ripple and therefore reduce the peak current,
which decreases core losses in the inductor and I2R®
losses in the entire power path. However, large induc-
tor values also require more energy storage and more
turns of wire, which increases size and can increase
I2R losses in the inductor. Low inductance values
decrease the size but increase the current ripple and
peak current. Finding the best inductor involves choos-
ing the best compromise between circuit efficiency,
inductor size, and cost.
The equations used here include a constant LIR, which
is the ratio of the inductor peak-to-peak ripple current
to the average DC inductor current at the full load cur-
rent. The best trade-off between inductor size and cir-
cuit efficiency for step-up regulators generally has an
LIR between 0.3 and 0.5. However, depending on the
AC characteristics of the inductor core material and
ratio of inductor resistance to other power-path resis-
tances, the best LIR can shift up or down. If the induc-
tor resistance is relatively high, more ripple can be
accepted to reduce the number of turns required and
increase the wire diameter. If the inductor resistance is
relatively low, increasing inductance to lower the peak
current can decrease losses throughout the power
path. If extremely thin high-resistance inductors are
used, as is common for LCD-panel applications, the
best LIR can increase to between 0.5 and 1.0.
Once a physical inductor is chosen, higher and lower
values of the inductor should be evaluated for efficien-
cy improvements in typical operating regions.
Calculate the approximate inductor value using the typ-
ical input voltage (VIN), the maximum output current
(IMAIN(MAX)), the expected efficiency (ηTYP) taken from
an appropriate curve in the Typical Operating
Characteristics section, and an estimate of LIR based
on the above discussion:
Choose an available inductor value from an appropriate
inductor family. Calculate the maximum DC input cur-
rent at the minimum input voltage (VIN(MIN)) using con-
servation of energy and the expected efficiency at that
operating point (ηMIN) taken from the appropriate curve
in the Typical Operating Characteristics:
Calculate the ripple current at that operating point and
the peak current required for the inductor:
The inductor’s saturation current rating and the
MAX1516/MAX1517/MAX1518s’ LX current limit (ILIM)
should exceed IPEAK, and the inductor’s DC current
rating should exceed IIN(DC,MAX). For good efficiency,
choose an inductor with less than 0.1Ωseries resistance.
Considering the Typical Operating Circuit, the maximum
load current (IMAIN(MAX)) is 500mA with a 13V output and
a typical input voltage of 5V. Choosing an LIR of 0.5 and
estimating efficiency of 85% at this operating point:
Using the circuit’s minimum input voltage (4.5V) and
estimating efficiency of 80% at that operating point:
The ripple current and the peak current are:
IVVV
HV MHz A
IA
AA
RIPPLE
PEAK
=×−
µ× × ≈
=+ ≈
45 13 45
33 13 12 074
18 074
222
.( .)
..
.
...
IAV
VA
IN DCMAX(, ) .
..
.=×
×≈
05 13
45 08 18
LV
V
VV
A MHz H=
−
×
≈µ
5
13
13 5
05 12
085
05 33
2
..
.
..
IVVV
LV f
II I
RIPPLE IN MIN MAIN IN MIN
MAIN OSC
PEAK IN DCMAX RIPPLE
=×−
××
=+
() ()
(, )
()
2
IIV
V
IN DCMAX MAIN MAX MAIN
IN MIN MIN
(, ) ()
()
=×
×η
LV
V
VV
IfLIR
IN
MAIN
MAIN IN
MAIN MAX OSC
TYP
=
−
×
2
()
η
I2R is a registered trademark of Instruments for Research and
Industry, Inc.
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
20 ______________________________________________________________________________________
Output-Capacitor Selection
The total output voltage ripple has two components: the
capacitive ripple caused by the charging and discharg-
ing of the output capacitance, and the ohmic ripple due
to the capacitor’s equivalent series resistance (ESR).
where IPEAK is the peak inductor current (see the
Inductor Selection section). For ceramic capacitors, the
output voltage ripple is typically dominated by
VRIPPLE(C). The voltage rating and temperature charac-
teristics of the output capacitor must also be considered.
Input-Capacitor Selection
The input capacitor (CIN) reduces the current peaks
drawn from the input supply and reduces noise injec-
tion into the IC. A 22µF ceramic capacitor is used in the
Typical Applications Circuit (Figure 1) because of the
high source impedance seen in typical lab setups.
Actual applications usually have much lower source
impedance since the step-up regulator often runs
directly from the output of another regulated supply.
Typically, CIN can be reduced below the values used in
the Typical Applications Circuit. Ensure a low-noise
supply at IN by using adequate CIN. Alternately,
greater voltage variation can be tolerated on CIN if IN is
decoupled from CIN using an RC lowpass filter (see
R10 and C18 in Figure 1).
Rectifier Diode
The MAX1516/MAX1517/MAX1518s’ high switching fre-
quency demands a high-speed rectifier. Schottky
diodes are recommended for most applications
because of their fast recovery time and low forward
voltage. In general, a 2A Schottky diode complements
the internal MOSFET well.
Output-Voltage Selection
The output voltage of the main step-up regulator can be
adjusted by connecting a resistive voltage-divider from
the output (VMAIN) to AGND with the center tap connect-
ed to FB (see Figure 1). Select R2 in the 10kΩto 50kΩ
range. Calculate R1 with the following equation:
where VFB, the step-up regulator’s feedback set point,
is 1.236V. Place R1 and R2 close to the IC.
Generating Output Voltages >13V
The maximum output voltage of the step-up regulator is
13V, which is limited by the absolute maximum rating of
the internal power MOSFET. To achieve higher output
voltages, an external n-channel MOSFET can be cascod-
ed with the internal FET (Figure 8). Since the gate of the
external FET is biased from the input supply, use a logic-
level FET to ensure that the FET is fully enhanced at the
minimum input voltage. The current rating of the FET
needs to be higher than the IC’s internal current limit.
Loop Compensation
Choose RCOMP to set the high-frequency integrator
gain for fast transient response. Choose CCOMP to set
the integrator zero to maintain loop stability.
For low-ESR output capacitors, use the following equa-
tions to obtain stable performance and good transient
response:
To further optimize transient response, vary RCOMP in
20% steps and CCOMP in 50% steps while observing
transient-response waveforms.
Charge Pumps
Selecting the Number of Charge-Pump Stages
For highest efficiency, always choose the lowest num-
ber of charge-pump stages that meet the output
requirement. Figures 9 and 10 show the positive and
negative charge-pump output voltages for a given
VMAIN for one-, two-, and three-stage charge pumps.
The number of positive charge-pump stages is given by:
where nPOS is the number of positive charge-pump
stages, VGON is the gate-on linear-regulator REG P out-
put, VMAIN is the main step-up regulator output, VDis
the forward-voltage drop of the charge-pump diode,
and VDROPOUT is the dropout margin for the linear reg-
ulator. Use VDROPOUT = 0.3V.
nVV V
VV
POS GON DROPOUT MAIN
MAIN D
=+−
−×2
RVV C
LI
CVC
IR
COMP IN OUT OUT
MAIN MAX
COMP OUT OUT
MAIN MAX COMP
≈×× ×
×
≈×
××
315
10
()
()
RR V
V
MAIN
FB
12 1=× −
VV V
VI
C
VV
Vf and
VIR
RIPPLE RIPPLE C RIPPLE ESR
RIPPLE C MAIN
OUT
MAIN IN
MAIN OSC
RIPPLE ESR PEAK ESR COUT
=+
≈−
≈
() ( )
()
() ( )
,
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
______________________________________________________________________________________ 21
The number of negative charge-pump stages is given by:
where nNEG is the number of negative charge-pump
stages, VGOFF is the gate-off linear-regulator REG N
output, VMAIN is the main step-up regulator output, VD
is the forward-voltage drop of the charge-pump diode,
and VDROPOUT is the dropout margin for the linear reg-
ulator. Use VDROPOUT = 0.3V.
The above equations are derived based on the
assumption that the first stage of the positive charge
pump is connected to VMAIN and the first stage of the
negative charge pump is connected to ground.
Sometimes fractional stages are more desirable for bet-
ter efficiency. This can be done by connecting the first
stage to VIN or another available supply. If the first
charge-pump stage is powered from VIN, then the
above equations become:
Flying Capacitors
Increasing the flying-capacitor (CX) value lowers the
effective source impedance and increases the output-
current capability. Increasing the capacitance indefi-
nitely has a negligible effect on output-current capabili-
ty because the internal switch resistance and the diode
impedance place a lower limit on the source imped-
ance. A 0.1µF ceramic capacitor works well in most
low-current applications. The flying capacitor’s voltage
rating must exceed the following:
where n is the stage number in which the flying capaci-
tor appears, and VMAIN is the output voltage of the
main step-up regulator.
Charge-Pump Output Capacitor
Increasing the output capacitance or decreasing the
ESR reduces the output ripple voltage and the peak-to-
peak transient voltage. With ceramic capacitors, the
output voltage ripple is dominated by the capacitance
value. Use the following equation to approximate the
required capacitor value:
where COUT_CP is the output capacitor of the charge
pump, ILOAD_CP is the load current of the charge
pump, and VRIPPLE_CP is the peak-to-peak value of the
output ripple.
Charge-Pump Rectifier Diodes
Use low-cost silicon switching diodes with a current rat-
ing equal to or greater than two times the average
charge-pump input current. If it helps avoid an extra
stage, some or all of the diodes can be replaced with
Schottky diodes with an equivalent current rating.
Linear-Regulator Controllers
Output-Voltage Selection
Adjust the gate-on linear-regulator (REG P) output volt-
age by connecting a resistive voltage-divider from the
REG P output to AGND with the center tap connected
to FBP (Figure 1). Select the lower resistor of the divider
R5 in the range of 10kΩto 30kΩ. Calculate the upper
resistor R4 with the following equation:
where VFBP = 1.25V (typ).
RR V
V
GON
FBP
45 1=× −
CI
fV
OUT CP LOAD CP
OSC RIPPLE CP
__
_
≥2
VnV
CX MAIN
>×
nVV V
VV
nVV V
VV
POS GON DROPOUT IN
MAIN D
NEG GOFF DROPOUT IN
MAIN D
=++
−×
=−++
−×
2
2
nVV
VV
NEG GOFF DROPOUT
MAIN D
=−+
−×2
STEP-UP
CONTROLLER
MAX1516
MAX1517
MAX1518
PGND
FB
LX
VMAIN
>13V
VIN
Figure 8. Operation with Output Voltages >13V Using
Cascoded MOSFET
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
22 ______________________________________________________________________________________
Adjust the gate-off linear-regulator REG N output volt-
age by connecting a resistive voltage-divider from
VGOFF to REF with the center tap connected to FBN
(Figure 1). Select R8 in the range of 20kΩto 50kΩ.
Calculate R7 with the following equation:
where VFBN = 250mV, VREF = 1.25V. Note that REF can
only source up to 50µA; using a resistor less than 20kΩ
for R8 results in higher bias current than REF can supply.
Pass-Transistor Selection
The pass transistor must meet specifications for current
gain (hFE), input capacitance, collector-emitter saturation
voltage and power dissipation. The transistor’s current
gain limits the guaranteed maximum output current to:
where IDRV is the minimum guaranteed base-drive cur-
rent, VBE is the transistor’s base-to-emitter forward volt-
age drop, and RBE is the pullup resistor connected
between the transistor’s base and emitter. Furthermore,
the transistor’s current gain increases the linear regula-
tor’s DC loop gain (see the Stability Requirements sec-
tion), so excessive gain destabilizes the output.
Therefore, transistors with current gain over 100 at the
maximum output current can be difficult to stabilize and
are not recommended unless the high gain is needed to
meet the load-current requirements.
The transistor’s saturation voltage at the maximum out-
put current determines the minimum input-to-output
voltage differential that the linear regulator can support.
Also, the package’s power dissipation limits the usable
maximum input-to-output voltage differential. The maxi-
mum power-dissipation capability of the transistor’s
package and mounting must exceed the actual power
dissipated in the device. The power dissipated equals
the maximum load current (ILOAD(MAX)_LR) multiplied
by the maximum input-to-output voltage differential:
where VIN(MAX)_LR is the maximum input voltage of the
linear regulator, and VOUT_LR is the output voltage of
the linear regulator.
Stability Requirements
The MAX1516/MAX1517/MAX1518 linear-regulator con-
trollers use an internal transconductance amplifier to
drive an external pass transistor. The transconductance
amplifier, the pass transistor, the base-emitter resistor,
and the output capacitor determine the loop stability.
The following applies to both linear-regulator controllers
in the MAX1516/MAX1517/MAX1518.
PI V V
LOAD MAX LR IN MAX LR OUT LR
=×−
()_ ()_ _
()
II
V
Rh
LOAD MAX DRV BE
BE FE MIN() ()
=−
×
RRVV
VV
FBN GOFF
REF FBN
78=× −
−
POSITIVE CHARGE-PUMP
OUTPUT VOLTAGE vs. VMAIN
VMAIN (V)
G_ON (V)
1210864
10
20
30
40
50
60
0
214
2-STAGE CHARGE PUMP
3-STAGE CHARGE PUMP
VD = 0.3V TO 1V
1-STAGE CHARGE PUMP
Figure 9. Positive Charge-Pump Output Voltage vs. VMAIN
NEGATIVE CHARGE-PUMP
OUTPUT VOLTAGE vs. VMAIN
VMAIN (V)
G_OFF (V)
1210864
-40
-35
-30
-25
-20
-15
-10
-5
-0
-45
214
1-STAGE
CHARGE PUMP
2-STAGE
CHARGE PUMP
3-STAGE
CHARGE PUMP
VD = 0.3V TO 1V
Figure 10. Negative Charge-Pump Output Voltage vs. VMAIN
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
______________________________________________________________________________________ 23
The transconductance amplifier regulates the output
voltage by controlling the pass transistor’s base cur-
rent. The total DC loop gain is approximately:
where VTis 26mV at room temperature, and IBIAS is the
current through the base-to-emitter resistor (RBE). For
the MAX1516/MAX1517/MAX1518, the bias currents for
both the gate-on and gate-off linear-regulator controllers
are 0.1mA. Therefore, the base-to-emitter resistor for
both linear regulators should be chosen to set 0.1mA
bias current:
The output capacitor and the load resistance create the
dominant pole in the system. However, the internal
amplifier delay, pass transistor’s input capacitance,
and the stray capacitance at the feedback node create
additional poles in the system, and the output capaci-
tor’s ESR generates a zero. For proper operation, use
the following equations to verify the linear regulator is
properly compensated:
1) First, determine the dominant pole set by the linear
regulator’s output capacitor and the load resistor:
The unity-gain crossover of the linear regulator is:
fCROSSOVER = AV_LR ✕fPOLE_LR
2) The pole created by the internal amplifier delay is
approximately 1MHz:
fPOLE_AMP = 1MHz
3) Next, calculate the pole set by the transistor’s
input capacitance, the transistor’s input resistance,
and the base-to-emitter pullup resistor:
gmis the transconductance of the pass transistor,
and fTis the transition frequency. Both parameters
can be found in the transistor’s data sheet. Because
RBE is much greater than RIN, the above equation
can be simplified:
Substituting for CIN and RIN yields:
4) Next, calculate the pole set by the linear regula-
tor’s feedback resistance and the capacitance
between FB_ and AGND (including stray capaci-
tance):
where CFB is the capacitance between FB_ and
AGND, RUPPER is the upper resistor of the linear
regulator’s feedback divider, and RLOWER is the
lower resistor of the divider.
5) Next, calculate the zero caused by the output
capacitor’s ESR:
where RESR is the equivalent series resistance of
COUT_LR.
To ensure stability, choose COUT_LR large enough so
the crossover occurs well before the poles and zero
calculated in steps 2 to 5. The poles in steps 3 and 4
generally occur at several megahertz, and using
ceramic capacitors ensures the ESR zero occurs at
several megahertz as well. Placing the crossover below
500kHz is sufficient to avoid the amplifier-delay pole
and generally works well, unless unusual component
choices or extra capacitances move one of the other
poles or the zero below 1MHz.
fCR
POLE ESR OUT LR ESR
__
=××
1
2π
fCR R
POLE FB FB UPPER LOWER
_(|| )
=××
1
2π
ff
h
POLE IN T
FE
_=
fCR
POLE IN IN IN
_=××
1
2π
where C g
fRh
g
IN m
TIN FE
m
==
2π,,
fCRR
POLE IN IN BE IN
_(||)
=××
1
2π
fI
CV
POLE LR LOAD MAX LR
OUT LR OUT LR
_()_
__
=××2π
RV
mA
V
mA k
BE BE
==≈
01
07
01 68
.
.
..Ω
AV
Ih
IV
VLR T
BIAS FE
LOAD LR REF_ _
≅
×+ ×
×
10 1
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
24 ______________________________________________________________________________________
Applications Information
Power Dissipation
An IC’s maximum power dissipation depends on the
thermal resistance from the die to the ambient environ-
ment and the ambient temperature. The thermal resis-
tance depends on the IC package, PC board copper
area, other thermal mass, and airflow.
The MAX1516/MAX1517/MAX1518, with their exposed
backside pad soldered to 1in2of PC board copper,
can dissipate about 1.7W into +70°C still air. More PC
board copper, cooler ambient air, and more airflow
increase the possible dissipation, while less copper or
warmer air decreases the IC’s dissipation capability.
The major components of power dissipation are the
power dissipated in the step-up regulator and the
power dissipated by the operational amplifiers.
Step-Up Regulator
The largest portions of power dissipation in the step-up
regulator are the internal MOSFET, the inductor, and the
output diode. If the step-up regulator has 90% efficiency,
about 3% to 5% of the power is lost in the internal
MOSFET, about 3% to 4% in the inductor, and about 1%
in the output diode. The remaining 1% to 3% is distrib-
uted among the input and output capacitors and the PC
board traces. If the input power is about 5W, the power
lost in the internal MOSFET is about 150mW to 250mW.
Operational Amplifier
The power dissipated in the operational amplifiers
depends on their output current, the output voltage,
and the supply voltage:
where IOUT_(SOURCE) is the output current sourced by
the operational amplifier, and IOUT_(SINK) is the output
current that the operational amplifier sinks.
In a typical case where the supply voltage is 13V and
the output voltage is 6V with an output source current
of 30mA, the power dissipated is 180mV.
PC Board Layout and Grounding
Careful PC board layout is important for proper opera-
tion. Use the following guidelines for good PC board
layout:
•Minimize the area of high-current loops by placing
the inductor, the output diode, and the output
capacitors near the input capacitors and near the
LX and PGND pins. The high-current input loop
goes from the positive terminal of the input capacitor
to the inductor, to the IC’s LX pin, out of PGND, and
to the input capacitor’s negative terminal. The high-
current output loop is from the positive terminal of
the input capacitor to the inductor, to the output
diode (D1), and to the positive terminal of the output
capacitors, reconnecting between the output capac-
itor and input capacitor ground terminals. Connect
these loop components with short, wide connec-
tions. Avoid using vias in the high-current paths. If
vias are unavoidable, use many vias in parallel to
reduce resistance and inductance.
•Create a power-ground island (PGND) consisting of
the input and output capacitor grounds, PGND pin,
and any charge-pump components. Connect all of
these together with short, wide traces or a small
ground plane. Maximizing the width of the power-
ground traces improves efficiency and reduces out-
put voltage ripple and noise spikes. Create an
analog ground plane (AGND) consisting of the
AGND pin, all the feedback-divider ground connec-
tions, the operational-amplifier divider ground con-
nections, the COMP and DEL capacitor ground
connections, and the device’s exposed backside
pad. Connect the AGND and PGND islands by con-
necting the PGND pin directly to the exposed back-
side pad. Make no other connections between these
separate ground planes.
•Place all feedback voltage-divider resistors as close
to their respective feedback pins as possible. The
divider’s center trace should be kept short. Placing
the resistors far away causes their FB traces to
become antennas that can pick up switching noise.
Take care to avoid running any feedback trace near
LX or the switching nodes in the charge pumps.
•Place the IN pin and REF pin bypass capacitors as
close to the device as possible. The ground connec-
tion of the IN bypass capacitor should be connected
directly to the AGND pin with a wide trace.
•Minimize the length and maximize the width of the
traces between the output capacitors and the load
for best transient responses.
•Minimize the size of the LX node while keeping it
wide and short. Keep the LX node away from feed-
back nodes (FB, FBP, and FBN) and analog ground.
Use DC traces to shield if necessary.
Refer to the MAX1518 evaluation kit for an example of
proper PC board layout.
Chip Information
TRANSISTOR COUNT: 4608
PROCESS: BiCMOS
PD I V V
PD I V
SOURCE OUT SOURCE SUP OUT
SINK OUT SINK OUT
=×−
=×
_( ) _
_( ) _
()
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
______________________________________________________________________________________ 25
8OUT2
MAX1517
THIN QFN
5mm x 5mm
4PGND
3AGND
2REF
1SRC
5OUT1
6NEG1
7POS1
28
DRVN
27
FBN
26
DRVP
25
FBP
29
DEL
30
CTL
31
DRN
32
COM
20 N.C.
19 N.C.
18 I.C.
17 OUT3
21 LX
22 IN
23 FB
24 COMP
13
N.C.
14
SUP
15
POS3
16
NEG3
12
N.C.
11
BGND
10
POS2
9
NEG2
TOP VIEW
N.C. = NOT INTERNALLY CONNECTED
I.C. = INTERNALLY CONNECTED
Pin Configurations
8N.C.
MAX1516
THIN QFN
5mm x 5mm
4PGND
3AGND
2REF
1SRC
5OUT1
6NEG1
7POS1
28
DRVN
27
FBN
26
DRVP
25
FBP
29
DEL
30
CTL
31
DRN
32
COM
20 N.C.
19 N.C.
18 I.C.
17 N.C.
21 LX
22 IN
23 FB
24 COMP
13
N.C.
14
SUP
15
N.C.
16
N.C.
12
N.C.
11
BGND
10
I.C.
9
N.C.
TOP VIEW
N.C. = NOT INTERNALLY CONNECTED
I.C. = INTERNALLY CONNECTED
8OUT2
MAX1518
THIN QFN
5mm x 5mm
4PGND
3AGND
2REF
1SRC
5OUT1
6NEG1
7POS1
28
DRVN
27
FBN
26
DRVP
25
FBP
29
DEL
30
CTL
31
DRN
32
COM
20 OUT5
19 NEG5
18 POS5
17 OUT4
21 LX
22 IN
23 FB
24 COMP
13
OUT3
14
SUP
15
POS4
16
NEG4
12
POS3
11
BGND
10
POS2
9
NEG2
TOP VIEW
MAX1516/MAX1517/MAX1518
TFT-LCD DC-DC Converters with
Operational Amplifiers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
©2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QFN THIN.EPS
D2
(ND-1) X e
e
D
C
PIN # 1
I.D.
(NE-1) X e
E/2
E
0.08 C
0.10 C
A
A1 A3
DETAIL A
0.15 C B
0.15 C A
E2/2
E2
0.10 M C A B
PIN # 1 I.D.
b
0.35x45∞
L
D/2 D2/2
L
C
L
C
e e
L
CC
L
k
k
LL
E1
2
21-0140
PACKAGE OUTLINE
16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm
DETAIL B
L
L1
e
COMMON DIMENSIONS
3.353.15
T2855-1 3.25 3.353.15 3.25
MAX.
3.20
EXPOSED PAD VARIATIONS
3.00T2055-2 3.10
D2
NOM.MIN.
3.203.00 3.10
MIN.
E2
NOM. MAX.
NE
ND
PKG.
CODES
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1,
T2855-3 AND T2855-6.
NOTES:
SYMBOL
PKG.
N
L1
e
E
D
b
A3
A
A1
k
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
JEDEC
T1655-1 3.203.00 3.10 3.00 3.10 3.20
0.70 0.800.75
4.90
4.90
0.25
0.25
0
--
4
WHHB
4
16
0.350.30
5.10
5.105.00
0.80 BSC.
5.00
0.05
0.20 REF.
0.02
MIN. MAX.NOM.
16L 5x5
3.10
T3255-2 3.00 3.20 3.00 3.10 3.20
2.70
T2855-2 2.60 2.602.80 2.70 2.80
E
2
2
21-0140
PACKAGE OUTLINE
16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm
L0.30 0.500.40
------
WHHC
20
5
5
5.00
5.00
0.30
0.55
0.65 BSC.
0.45
0.25
4.90
4.90
0.25
0.65
--
5.10
5.10
0.35
20L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
---
WHHD-1
28
7
7
5.00
5.00
0.25
0.55
0.50 BSC.
0.45
0.25
4.90
4.90
0.20
0.65
--
5.10
5.10
0.30
28L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
---
WHHD-2
32
8
8
5.00
5.00
0.40
0.50 BSC.
0.30
0.25
4.90
4.90
0.50
--
5.10
5.10
32L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
-
40
10
10
5.00
5.00
0.20
0.50
0.40 BSC.
0.40
0.25
4.90
4.90
0.15
0.60
5.10
5.10
0.25
40L 5x5
0.20 REF.
0.75
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
0.20 0.25 0.30
-
0.35 0.45
0.30 0.40 0.50
DOWN
BONDS
ALLOWED
NO
YES3.103.00 3.203.103.00 3.20T2055-3
3.103.00 3.203.103.00 3.20T2055-4
T2855-3 3.15 3.25 3.35 3.15 3.25 3.35
T2855-6 3.15 3.25 3.35 3.15 3.25 3.35
T2855-4 2.60 2.70 2.80 2.60 2.70 2.80
T2855-5 2.60 2.70 2.80 2.60 2.70 2.80
T2855-7 2.60 2.70 2.80 2.60 2.70 2.80
3.20
3.00 3.10T3255-3 3.203.00 3.10
3.203.00 3.10T3255-4 3.203.00 3.10
3.403.20 3.30T4055-1 3.20 3.30 3.40
NO
NO
NO
NO
NO
NO
NO
NO
YES
YES
YES
YES
YES
3.203.00T1655-2 3.10 3.00 3.10 3.20 YES
