CS5343/4 98 dB, 96 kHz, Multi-Bit Audio A/D Converter Features General Description ! Advanced Multi-Bit Architecture The CS5343/4 is a complete analog-to-digital converter for digital audio systems. It performs sampling, analogto-digital conversion, and anti-alias filtering, generating 24-bit values for both left and right inputs in serial form at sample rates up to 108 kHz per channel. ! 24-bit Conversion ! Supports Audio Sample Rates Up to 108 kHz ! 98 dB Dynamic Range at 5 V The CS5343/4 uses a 3rd-order, multi-bit Delta-Sigma modulator followed by a digital filter, which removes the need for an external anti-alias filter. ! -90 dB THD+N ! Low-Latency Digital Filter The CS5343/4 also features a high-impedance sampling network which eliminates costly external components such as op-amps. ! High-Pass Filter to Remove DC Offsets ! Single +3.3 V or +5 V Power Supply ! Power Consumption Less Than 50 mW The CS5343/4 is available in a 10-pin TSSOP package for both Commercial (-10 to +70 C) and Automotive grades (-40 to +85 C). The CDB5343 Customer Demonstration Board is also available for device evaluation and implementation suggestions. Please refer to the "Ordering Information" on page 21 for complete details. ! Master or Slave Operation ! Slave Mode Speed Auto-Detect ! Master Mode Default Settings ! 256x or 384x MCLK/LRCK Ratio ! CS5343 Supports IS Audio Format ! CS5344 Supports Left-Justified Audio Format The CS5343/4 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as set-top boxes, DVD-karaoke players, DVD recorders, A/V receivers, and automotive applications. VA 3.3 V to 5 V AINL High-Z Sampling Network FILT+ AINR Low-Latency Digital Filters Internal Reference Voltages VQ Single-Ended Analog Input High-Pass Filter High-Z Sampling Network Advance Product Information http://www.cirrus.com High-Pass Filter Master Clock Auto-detect MCLK Divider Serial Port Single-Ended Analog Input SCLK Slave Mode Auto-detect LRCK Low-Latency Digital Filters SDOUT This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright (c) Cirrus Logic, Inc. 2006 (All Rights Reserved) AUGUST '06 DS687A4 CS5343/4 TABLE OF CONTENTS 1. PIN DESCRIPTIONS .............................................................................................................................. 4 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 5 SPECIFIED OPERATING CONDITIONS ............................................................................................... 5 ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 5 ANALOG CHARACTERISTICS - COMMERCIAL GRADE .................................................................... 6 ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE ..................................................................... 7 DIGITAL FILTER CHARACTERISTICS ................................................................................................ 8 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 8 DIGITAL CHARACTERISTICS .............................................................................................................. 9 SYSTEM CLOCKING AND SERIAL AUDIO INTERFACE ................................................................... 10 3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 12 4. APPLICATIONS ................................................................................................................................... 13 4.1 Operation as Clock Master or Slave ............................................................................................... 13 4.1.1 Slave Mode Operation ........................................................................................................... 13 4.1.2 Master Mode Operation ......................................................................................................... 14 4.1.2.1 Master Mode Speed Selection ................................................................................... 14 4.1.3 Master Clock ......................................................................................................................... 14 4.2 Serial Audio Interface ..................................................................................................................... 15 4.3 Digital Interface ............................................................................................................................... 15 4.4 Analog Connections ....................................................................................................................... 15 4.4.1 Component Values ................................................................................................................ 16 4.5 Grounding and Power Supply Decoupling ...................................................................................... 16 4.6 Synchronization of Multiple Devices ............................................................................................... 17 5. FILTER PLOTS ................................................................................................................................... 17 6. PARAMETER DEFINITIONS ................................................................................................................ 19 7. PACKAGE DIMENSIONS .................................................................................................................... 20 THERMAL CHARACTERISTICS .......................................................................................................... 20 8. ORDERING INFORMATION ................................................................................................................ 21 9. REVISION HISTORY ............................................................................................................................ 21 LIST OF FIGURES Figure 1. CS5343 IS Serial Audio Interface .............................................................................................. 11 Figure 2. CS5344 Left-Justified Serial Audio Interface .............................................................................. 11 Figure 3. Typical Connection Diagram....................................................................................................... 12 Figure 4. IS Serial Audio Interface ............................................................................................................ 15 Figure 5. Left-Justified Serial Audio Interface ............................................................................................ 15 Figure 6. CS5343/4 Analog Input Network................................................................................................. 15 Figure 7. CS5343/4 Example Analog Input Network.................................................................................. 16 Figure 8. Single-Speed Mode Stopband Rejection .................................................................................... 17 Figure 9. Single-Speed Mode Transition Band .......................................................................................... 17 Figure 10. Single-Speed Mode Transition Band (Detail)............................................................................ 17 Figure 11. Single-Speed Mode Passband Ripple ...................................................................................... 17 Figure 12. Double-Speed Mode Stopband Rejection................................................................................. 18 Figure 13. Double-Speed Mode Transition Band....................................................................................... 18 Figure 14. Double-Speed Mode Transition Band (Detail) .......................................................................... 18 Figure 15. Double-Speed Mode Passband Ripple..................................................................................... 18 2 DS687A4 CS5343/4 LIST OF TABLES Table 1. Master/Slave Mode Selection ...................................................................................................... 13 Table 2. Speed Modes and the Associated Sample Rates (Fs) in Slave Mode......................................... 13 Table 3. Speed Modes and the Associated Sample Rates (Fs) in Master Mode....................................... 14 Table 4. Speed Mode Selection in Master Mode ....................................................................................... 14 Table 5. Common MCLK Frequencies in Master and Slave Modes .......................................................... 14 Table 6. Analog Input Design Parameters ................................................................................................. 16 DS687A4 3 CS5343/4 1. PIN DESCRIPTIONS Pin Name Pin # SDOUT 1 10 SCLK 2 9 GND LRCK 3 8 AINR MCLK 4 7 VQ FILT+ 5 6 AINL VA Pin Description SDOUT 1 Serial Audio Data Output (Output) - Output for two's complement serial audio data. Also selects Master or Slave Mode. SCLK 2 Serial Clock (Input/Output) - Serial clock for the serial audio interface. LRCK 3 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. MCLK 4 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. FILT+ 5 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. AINL AINR 6 8 Analog Input (Input) - The full-scale analog input level is specified in the Analog Characteristics specification table. VQ 7 Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage. GND 9 Ground (Input) - Ground reference. Must be connected to analog ground. VA 10 Power (Input) - Positive power supply for the digital and analog sections. 4 DS687A4 CS5343/4 2. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at typical supply voltages and TA = 25C.) SPECIFIED OPERATING CONDITIONS (GND = 0 V, all voltages with respect to GND.) Parameter Power Supplies Ambient Operating Temperature Commercial Automotive Symbol Min Typ Max Unit VA 3.1 4.75 3.3 5.0 3.5 5.25 V V TAC TAD -10 -40 - 70 85 C C ABSOLUTE MAXIMUM RATINGS (GND = 0 V, all voltages with respect to GND.) (Note 1) Parameter DC Power Supplies Symbol Min Max Unit VA -0.3 +6.0 V Input Current (Note 2) Iin -10 +10 mA Input Voltage (Note 3) VIN -0.7 VA+0.7 V Ambient Operating Temperature (Power Applied) TA -50 +115 C Storage Temperature Tstg -65 +150 C Notes: 1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 2. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 3. The maximum over/under voltage is limited by the input current. DS687A4 5 CS5343/4 ANALOG CHARACTERISTICS - COMMERCIAL GRADE Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz; source impedance less than or equal to 2.5 k. Dynamic Performance for Commercial Grade Single-Speed Mode Fs = 48 kHz Dynamic Range A-weighted unweighted Total Harmonic Distortion + Noise Double-Speed Mode Dynamic Range Total Harmonic Distortion + Noise VA = 3.3 V Min Typ Max Min Typ Max Unit 89 86 95 92 - 92 89 98 95 - dB dB - -86 -75 -35 -80 - - -90 -78 -38 -84 - dB dB dB Fs = 96 kHz Min Typ Max Min Typ Max Unit A-weighted unweighted 89 86 95 92 - 92 89 98 95 - dB dB - -86 -75 -35 -80 - - -90 -78 -38 -84 - dB dB dB (Note 4) -1 dB -20 dB -60 dB (Note 4) -1 dB -20 dB -60 dB Symbol VA = 5.0 V THD+N THD+N Dynamic Performance for Commercial Grade - All Modes Min Typ Max Unit - 90 - dB Interchannel Gain Mismatch - - 0.1 dB Gain Error -3 - +3 % Gain Drift - 100 - ppm/C 0.51*VA 0.56*VA 0.57*VA Vpp - 7.5 - M Interchannel Isolation DC Accuracy Analog Input Characteristics Full-scale Input Voltage Input Impedance Notes: 4. Referred to the typical full-scale input voltage 6 DS687A4 CS5343/4 ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz; source impedance less than or equal to 2.5 k. Dynamic Performance for Automotive Grade Single-Speed Mode Dynamic Range Total Harmonic Distortion + Noise Double-Speed Mode Dynamic Range Total Harmonic Distortion + Noise Fs = 48 kHz VA = 3.3 V Symbol VA = 5.0 V Min Typ Max Min Typ Max Unit 87 84 95 92 - 90 87 98 95 - dB dB - -86 -75 -35 -78 - - -90 -78 -38 -82 - dB dB dB Fs = 96 kHz Min Typ Max Min Typ Max Unit A-weighted unweighted 87 84 95 92 - 90 87 98 95 - dB dB - -86 -75 -35 -78 - - -90 -78 -38 -82 - dB dB dB A-weighted unweighted (Note 5) -1 dB -20 dB -60 dB (Note 5) -1 dB -20 dB -60 dB THD+N THD+N Dynamic Performance for Automotive Grade - All Modes Min Typ Max Unit - 90 - dB Interchannel Gain Mismatch - - 0.1 dB Gain Error -3 - +3 % Gain Drift - 100 - ppm/C 0.51*VA 0.56*VA 0.57*VA Vpp - 7.5 - M Interchannel Isolation DC Accuracy Analog Input Characteristics Full-scale Input Voltage Input Impedance Notes: 5. Referred to the typical full-scale input voltage DS687A4 7 CS5343/4 DIGITAL FILTER CHARACTERISTICS Parameter Single-Speed Mode Passband Symbol Min Typ Max Unit Fs = 4 - 54 kHz 0 - 0.489 Fs Passband Ripple (-0.1 dB) -0.025 - 0.025 dB Stopband 0.560 - - Fs 69 - - dB - 12/Fs - s 0 - 0.489 Fs Passband Ripple -0.025 - 0.025 dB Stopband 0.560 - - Fs 69 - - dB - 9/Fs - s - 1 20 - Hz Hz - 10 - Deg - - 0 dB Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Double-Speed Mode Passband tgd Fs = 86 - 108 kHz (-0.1 dB) Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) tgd High-Pass Filter Characteristics Frequency Response Phase Deviation -3.0 dB -0.13 dB (Note 6) @ 20 Hz (Note 6) Passband Ripple Notes: 6. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs. DC ELECTRICAL CHARACTERISTICS (GND = 0 V, all voltages with respect to 0 V. MCLK=12.288 MHz; Master Mode) VA = 3.3 V Parameter Symbol Min DC Power Supplies: Typ VA = 5.0 V Max Min Typ Max Unit VA 3.1 3.3 - - 5 5.25 V Power Supply Current (Normal Operation) IA - 15 - - 15 - mA Power Supply Current (Power-Down Mode) (Note 7) IA - 1.1 - - 1.1 - mA Power Consumption (Normal Operation) (Power-Down Mode) (Note 7) - - 50 3.6 - - 75 5.5 - mW mW Parameter Symbol Min Typ Max Unit PSRR - 65 - dB VQ Nominal Voltage Output Impedance - 0.44xVA 25 - V k Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink - VA 220 2.5 - V k uA Power Supply Rejection Ratio (1 kHz) (Note 8) Notes: 7. Device enters power-down mode when MCLK is held static. 8. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram. 8 DS687A4 CS5343/4 DIGITAL CHARACTERISTICS Symbol Min Typ Max Units High-Level Input Voltage Parameter (% of VA) VIH 70 - - % Low-Level Input Voltage (% of VA) VIL - - 30 % High-Level Output Voltage at Io = 500 A (% of VA) VOH 70 - - % Low-Level Output Voltage at Io =500 A (% of VA) VOL - - 15 % Iin -10 - 10 A Input Leakage Current DS687A4 9 CS5343/4 SYSTEM CLOCKING AND SERIAL AUDIO INTERFACE (Logic "0" = GND = 0 V; Logic "1" = VA, CL = 20 pF) Parameter Symbol Min Typ Max Unit tclkw 24 - 30 ns (Double-Speed, 192x Mode) 48 - 60 ns (Double-Speed, 256x Mode) 36 - 45 ns (Double-Speed, 128x Mode) 72 - 90 ns (Single-Speed, 768x Mode) 24 - 325 ns (Single-Speed, 384x Mode) 48 - 651 ns (Single-Speed, 512x Mode) 36 - 488 ns (Single-Speed, 256x Mode) 72 - 976 ns 40 50 60 % 4 86 - 54 108 kHz kHz LRCK Duty Cycle - 50 - % SCLK Duty Cycle - 50 - % Master Mode MCLK Period (Double-Speed, 384x Mode) MCLK Duty Cycle Output Sample Rate (Single-Speed) (Double-Speed) Fs SDOUT valid before SCLK rising tstp 10 - - ns SDOUT valid after SCLK rising thld 40 - - ns SCLK falling to LRCK edge tslrd -20 - 20 ns tclkw 24 - 30 ns (Double-Speed, 192x Mode) 48 - 60 ns (Double-Speed, 256x Mode) 36 - 45 ns (Double-Speed, 128x Mode) 72 - 90 ns (Single-Speed, 768x Mode) 24 - 325 ns (Single-Speed, 384x Mode) 48 - 651 ns (Single-Speed, 512x Mode) 36 - 488 ns (Single-Speed, 256x Mode) 72 - 976 ns 40 50 60 % 4 86 - 54 108 kHz kHz 40 50 60 % 1 ----------------64 x Fs - - ns 45 50 55 % Slave Mode MCLK Period (Double-Speed, 384x Mode) MCLK Duty Cycle Input Sample Rate (Single-Speed) (Double-Speed) Fs LRCK Duty Cycle SCLK Period tsclkw SCLK Duty Cycle SDOUT valid before SCLK rising tstp 10 - - ns SDOUT valid after SCLK rising thld 10 - - ns SCLK falling to LRCK edge tslrd -20 - 20 ns 10 DS687A4 CS5343/4 t slrd LRCK t sclkw SCLK SDOUT MSB t stp MSB-1 t hld Figure 1. CS5343 IS Serial Audio Interface t slrd LRCK t sclkw SCLK SDOUT MSB t stp MSB-1 t hld Figure 2. CS5344 Left-Justified Serial Audio Interface DS687A4 11 CS5343/4 3. TYPICAL CONNECTION DIAGRAM 3.3 V to 5 V 0.1 F 1 F VA or GND 10 VA 1 F CS5343/4 0.1 F 9 GND 7 VQ 0.1 F 6 AINL Analog Input Conditioning SDOUT 1 SCLK 2 LRCK 3 MCLK 4 See Figure 6 on page 15 Audio Processor/ System Clocks 1 8 10 k2 FILT+ 10 k2 1 F VA 10 k1 5 Pull-up to VA for Master Mode Pull-down to GND for Slave Mode AINR 2 Optional pull-up resistor for configuring clocks in Master Mode as desribed in the "Master Mode Speed Selection" section on page 14 Figure 3. Typical Connection Diagram 12 DS687A4 CS5343/4 4. APPLICATIONS 4.1 Operation as Clock Master or Slave The CS5343/4 supports operation as either a clock master or slave. As a clock master, the left/right and serial clocks are synchronously generated on-chip and output on the LRCK and SCLK pins, respectively. As a clock slave, the LRCK and SCLK pins are always inputs and require external generation of the left/right and serial clocks. The selection of clock master or slave is made via a 10 k pull-up resistor from SDOUT to VA for Master Mode selection or via a 10 k pull-down resistor from SDOUT to GND for Slave Mode selection, as shown in Table 1. Mode Selection Master Mode 10 k pull-up resistor from SDOUT to VA Slave Mode 10 k pull-down resistor from SDOUT to GND Table 1. Master/Slave Mode Selection 4.1.1 Slave Mode Operation A unique feature of the CS5343/4 is the automatic selection of either Single- or Double-Speed Mode when acting as a clock slave. The auto-mode selection feature supports all standard audio sample rates from 4 to 108 kHz. Please refer to Table 2 for supported sample rate ranges in Slave Mode. Speed Mode Single-Speed Mode Double-Speed Mode MCLK/LRCK Ratio SCLK/LRCK Ratio Input Sample Rate Range (kHz) 256x 64 4 - 54 512x 64 4 - 54 384x 48, 64 4 - 54 768x 48, 64 4 - 54 128x 64 86 - 108 256x 64 86 - 108 192x 48, 64 86 - 108 384x 48, 64 86 - 108 Table 2. Speed Modes and the Associated Sample Rates (Fs) in Slave Mode DS687A4 13 CS5343/4 4.1.2 Master Mode Operation As clock Master, the CS5343/4 generates LRCK and SCLK synchronously on-chip. Table 3 shows the available sample rates and associated clock ratios in Master Mode. Speed Mode Single-Speed Mode Double-Speed Mode MCLK/LRCK Ratio SCLK/LRCK Ratio Input Sample Rate Range (kHz) 256x 64 4 - 54 512x 64 4 - 54 384x 64 4 - 54 768x 64 4 - 54 128x 64 86 - 108 256x 64 86 - 108 192x 64 86 - 108 384x 64 86 - 108 Table 3. Speed Modes and the Associated Sample Rates (Fs) in Master Mode 4.1.2.1 Master Mode Speed Selection During power-up in Master Mode, the LRCK and SCLK pins are inputs to configure speed mode and the output clock ratio. The LRCK pin is pulled low internally to select Single-Speed Mode by default, but Double-Speed Mode is accessed with a 10 k pull-up resistor from LRCK to VA as shown in Table 4. Similarly, the SCLK pin is internally pulled-low by default to select a 256x MCLK/LRCK ratio, but a MCLK/LRCK ratio of 348x is accessed with a 10 k pull-up resistor from SCLK to VA as shown in Table 4. Following the power-up routine, the LRCK and SCLK pins become clock outputs. Pin LRCK SCLK Resistor Option Clock Configuration Internal Pull-Down to GND (100 k) Single-Speed Mode (default) External Pull-Up to VA (10 k) Double-Speed Mode Internal Pull-Down to GND (100 k) 256x MCLK/LRCK (default) External Pull-Up to VA (10 k) 384x MCLK/LRCK Table 4. Speed Mode Selection in Master Mode 4.1.3 Master Clock The CS5343/4 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters. There is also an internal MCLK divider which is automatically activated based on the frequency of the MCLK. Table 4 lists some common audio output sample rates and the required MCLK frequency. Sample Rate (kHz) Master and Slave Mode MCLK(MHz) Speed Mode 32 44.1 48 SSM SSM SSM Sample Rate (kHz) Speed Mode 88.2 96 DSM DSM 256x 8.912 11.289 12.288 512x 16.384 22.579 24.576 MCLK (MHz) 384x 12.288 16.934 18.432 MCLK(MHz) 128x 11.289 12.288 256x 22.579 24.576 768x 24.576 33.868 36.864 MCLK (MHz) 192x 16.934 18.432 384x 33.868 36.864 Table 5. Common MCLK Frequencies in Master and Slave Modes 14 DS687A4 CS5343/4 4.2 Serial Audio Interface The CS5343 output is serial data in IS audio format and the CS5344 output is serial data in Left-Justified audio format. Figures 4 and 5 show the IS and Left-Justified data relative to SCLK and LRCK. Additionally, Figures 1 and 2 display more information on the required timing for the serial audio interface format. For an overview of serial audio interface formats, please refer to Cirrus Application Note AN282. Left Channel LRCK Right Channel SCLK SDATA 23 22 9 8 7 6 5 4 3 2 1 0 23 22 9 8 7 6 5 4 3 2 1 0 23 22 Figure 4. IS Serial Audio Interface Left Channel LRCK Right Channel SCLK SDATA 23 22 9 8 7 6 5 4 3 2 1 0 23 22 9 8 7 6 5 4 3 2 1 0 23 22 Figure 5. Left-Justified Serial Audio Interface 4.3 Digital Interface VA supplies power to both the analog and digital sections of the ADC, and also powers the serial port. Consequently, the digital interface logic level must equal VA to within the limits specified under "Digital Characteristics" on page 9. 4.4 Analog Connections The analog modulator samples the input signal at half of the internal master clock rate, or 6.144 MHz when MCLK = 12.288 MHz. The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are multiples of the input sampling frequency (n x 6.144 MHz), where n=0,1,2,... Refer to Figure 6 which shows the recommended topology of the analog input network. The external shunt capacitor and internal input impedance form a single-pole RC filter to provide the appropriate filtering of noise at the modulator sampling frequency. Additionally, the 180 pF capacitor acts as a charge source for the internal sampling circuits. Capacitors of NPO or other high-quality dielectric will produce the best results while capacitors with a large voltage coefficient (such as general-purpose ceramics) can degrade signal linearity. R1 1 F Input CS5343/4 AIN R2 180pF C0G Figure 6. CS5343/4 Analog Input Network DS687A4 15 CS5343/4 4.4.1 Component Values Three parameters determine the values of resistors R1 and R2 as shown in Figure 6: source impedance, attenuation, and input impedance. Table 6 shows the design equation used to determine these values. * Source Impedance: Source impedance is defined as the impedance as seen from the ADC looking back into the signal network. The ADC achieves optimal THD+N performance with a source impedance less than or equal to 2.5 k. * Attenuation: The required attenuation factor depends on the magnitude of the input signal. The fullscale input voltage is specified under "Analog Characteristics - Commercial Grade" on page 6. The user should select values for R1 and R2 such that the magnitude of the incoming signal multiplied by the attenuation factor is less than or equal to the full-scale input voltage of the device. * Input Impedance: Input impedance is the impedance from the signal source to the ADC analog input pins. Table 6 shows the input parameters and the associated design equations. Source Impedance (-----------------------R1 x R2 )R1 + R2 Attenuation Factor ( R2 ) ------------------------( R1 + R2 ) Input Impedance ( R1 + R2 ) Table 6. Analog Input Design Parameters Figure 7 illustrates an example configuration using two 4.99 k resistors in place of R1 and R2. Based on the discussion above, this circuit provides an optimal interface for both the ADC and the signal source. First, consumer equipment frequently requires an input impedance of 10 k, which the 4.99 k resistors provide. Second, this circuit will attenuate a typical line level voltage, 2 Vrms, to the full-scale input of the ADC, 1 Vrms when VA = 5 V. Finally, at 2.5 k, the source impedance optimizes analog performance of the ADC. 4.99 k 1 F Input CS5343/4 AIN 4.99 k 180pF C0G Figure 7. CS5343/4 Example Analog Input Network 4.5 Grounding and Power Supply Decoupling As with any high-resolution converter, designing with the CS5343/4 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 3 shows the recommended power arrangements, with VA connected to a clean supply. Decoupling capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.01 F, must be positioned to minimize the electrical path from FILT+ to GND. The CDB5343 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs. 16 DS687A4 CS5343/4 4.6 Synchronization of Multiple Devices In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the MCLK, SCLK, and LRCK must be the same for all of the CS5343 and CS5344 devices in the system. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 Amplitude (dB) Amplitude (dB) 5. FILTER PLOTS 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.42 0.44 Frequency (norm alized to Fs) 0 0.10 -1 0.08 -2 0.06 -3 -4 -5 -6 -7 0.51 0.52 Frequency (norm alized to Fs) Figure 10. Single-Speed Mode Transition Band (Detail) DS687A4 0.60 0.00 -0.04 -0.08 0.50 0.58 -0.02 -0.06 0.49 0.56 0.02 -9 0.48 0.54 0.04 -8 0.47 0.52 Figure 9. Single-Speed Mode Transition Band Amplitude (dB) Amplitude (dB) Figure 8. Single-Speed Mode Stopband Rejection -10 0.46 0.46 0.48 0.50 Frequency (norm alized to Fs) -0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (norm alized to Fs) Figure 11. Single-Speed Mode Passband Ripple 17 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.42 0.44 Amplitude (dB) Amplitude (dB) CS5343/4 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (norm alized to Fs) 0.10 0.08 -2 0.06 Amplitude (dB) Amplitude (dB) 0 -3 -4 -5 -6 -7 0.52 Frequency (norm alized to Fs) Figure 14. Double-Speed Mode Transition Band (Detail) 18 0.00 -0.04 -0.08 0.51 0.60 -0.02 -0.06 0.50 0.58 0.02 -9 0.49 0.56 0.04 -8 0.48 0.54 Figure 13. Double-Speed Mode Transition Band -1 0.47 0.52 Frequency (norm alized to Fs) Figure 12. Double-Speed Mode Stopband Rejection -10 0.46 0.46 0.48 0.50 -0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (norm alized to Fs) Figure 15. Double-Speed Mode Passband Ripple DS687A4 CS5343/4 6. PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog input for a full-scale digital output. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. DS687A4 19 CS5343/4 7. PACKAGE DIMENSIONS 10LD TSSOP (3 mm BODY) PACKAGE DRAWING (Note 1) N D E11 c E A2 A e b A1 SIDE VIEW 1 2 3 END VIEW L SEATING PLANE L1 TOP VIEW INCHES DIM MIN A A1 A2 b c D E E1 e L L1 -0 0.0295 0.0059 0.0031 ----0.0157 -0 MILLIMETERS NOM MAX MIN -0.0433 --0.0059 0 -0.0374 0.75 -0.0118 0.15 -0.0091 0.08 0.1181 BSC --0.1929 BSC --0.1181 BSC --0.0197 BSC --0.0236 0.0315 0.40 0.0374 REF ---8 0 Controlling Dimension is Millimeters NOTE NOM MAX -----3.00 BSC 4.90 BSC 3.00 BSC 0.50 BSC 0.60 0.95 REF -- 1.10 0.15 0.95 0.30 0.23 ----0.80 -8 4, 5 2 3 Notes: 1. Reference document: JEDEC MO-187 2. D does not include mold flash or protrusions which is 0.15 mm max. per side. 3. E1 does not include inter-lead flash or protrusions which is 0.15 mm max per side. 4. Dimension b does not include a total allowable dambar protrusion of 0.08 mm max. 5. Exceptions to JEDEC dimension. THERMAL CHARACTERISTICS Parameter Allowable Junction Temperature Junction to Ambient Thermal Impedance (4-layer PCB) (2-layer PCB) 20 Symbol Min Typ Max Unit TJ - - 135 C JA-4 JA-2 - 100 170 - C/W C/W DS687A4 CS5343/4 8. ORDERING INFORMATION Product Description 98 dB, Multi-Bit Audio CS5343 A/D Converter, IS Audio Format 98 dB, Multi-Bit Audio CS5343 A/D Converter, IS Audio Format 98 dB, Multi-Bit Audio CS5344 A/D Converter, Left-Justified Audio Format 98 dB, Multi-Bit Audio CS5344 A/D Converter, Left-Justified Audio Format CDB5343 CS5343 Evaluation Board Package Pb-Free Grade Temp Range 10-TSSOP Yes Commercial -10 to +70 C 10-TSSOP Yes Automotive 10-TSSOP Yes Commercial -10 to +70 C 10-TSSOP Yes Automotive -40 to +85 C - No - - -40 to +85 C Container Rail Order # CS5343-CZZ Tape & Reel CS5343-CZZR Rail CS5343-DZZ Tape & Reel CS5343-DZZR Rail CS5344-CZZ Tape & Reel CS5344-CZZR Rail CS5344-DZZ Tape & Reel CS5344-DZZR - CDB5343 9. REVISION HISTORY Release Changes A2 Changes made to Serial Port diagrams. See Figure 1 and Figure 2 on page 11. A3 Replaced block diagram on cover page. Increased minimum hold time (Thld) specification on page 10. Updated Table 4, "Speed Mode Selection in Master Mode," on page 14. A4 Corrected MCLK timing specifications on page 10 Corrected "Typical Connection Diagram" on page 12 Corrected Table 3, "Speed Modes and the Associated Sample Rates (Fs) in Master Mode," on page 14 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. DS687A4 21