CS5343 - Cirrus Logic, Inc.

http://www.cirrus.com

Advance Product Information This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

98 dB, 96 kHz, Multi-Bit Audio A/D Converter

Features

!Advanced Multi-Bit ∆Σ Architecture

!24-bit Conversion

!Supports Audio Sample Rates Up to 108 kHz

!98 dB Dynamic Range at 5 V

!-90 dB THD+N

!Low-Latency Digital Filter

!High-Pass Filter to Remove DC Offsets

!Single +3.3 V or +5 V Power Supply

!Power Consumption Less Than 50 mW

!Master or Slave Operation

!Slave Mode Speed Auto-Detect

!Master Mode Default Settings

!256x or 384x MCLK/LRCK Ratio

!CS5343 Supports I²S Audio Format

!CS5344 Supports Left-Justified Audio Format

General Description

The CS5343/4 is a complete analog- to-digital converter

for digital au dio sy stem s. It pe rfor ms sa mpling, analo g-

to-digital conversion, and anti-alias filtering, generating

24-bit values for both left and right inputs in serial form

at sample rates up to 108 kHz per channel.

The CS5343/4 uses a 3rd-order, multi-bit Delta-Sigma

modulator followed by a digital filter, which removes the

need for an external anti-alias filter.

The CS5343/4 also features a high-impedance sam-

pling network which eliminates costly external

components such as op-amps.

The CS5343/4 is available in a 10-p in TSSOP package

for both Commercial (-10° to +70° C) and Automotive

grades (-40° to +85° C). Th e CDB5343 Customer Dem-

onstration Board is also available for device ev aluation

and implementation suggestions. Please refer to the

“Ordering Informatio n” on p age 21 for complete details.

The CS5343/4 is ideal for audio systems requiring wide

dynamic range, negligible distortion and low noise, such

as set-top boxes, DVD-karaoke players, DVD record-

ers, A/V receivers, and automotive applications.

High-Pass

Filter

High-Pass

Filter

Low-Latency

Digital Filte r s

3.3 V to 5 V

Inte rn al

Reference

Voltages

High-Z

Sampling

Network

Auto-dete ct

MCLK Divider Master

Clock

Single-Ended

Analog Input

Low-Latency

Digital Filte r s

High-Z

Sampling

Network

Single-Ended

Analog Input

SCLK

LRCK

SDOUT

FILT+

AINR

AINL

Serial Port

Slave Mode

Auto-detect

High-Pass

Filter

AUGUST '06

DS687A4

CS5343/4

2 DS687A4
CS5343/4
TABLE OF CONTENTS
1. PIN DESCRIPTIONS .............................................................................................................................. 4
2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 5
SPECIFIED OPERATING CONDITIONS ............................................................................................... 5
ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 5
ANALOG CHARACTERISTICS - COMMERCIAL GRADE  .................................................................... 6
ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE ..................................................................... 7
DIGITAL FILTER CHARACTERISTICS   ................................................................................................8
DC ELECTRICAL CHARA CTERISTIC S  .... ... .... ... ... ... .... ... ... ... .... ................................................... ........ 8
DIGITAL CHARACTERISTICS  .............................................................................................................. 9
SYSTEM CLOCKING AND SERIAL AUDIO INTERFACE ................................................................... 10
3. TYPICAL CONNECTION DIAGRAM  ................................................................................................... 12
4. APPLICATIONS  ................................................................................................................................... 13
4.1 Operation as Clock Master or Slave ............................................................................................... 13
4.1.1 Slave Mode Operat ion . ... ................ .... ... ... ... .... ... ... ................ ... .... ... ... ... .... ... ... ...................... 13
4.1.2 Master Mode Operation ......................................................................................................... 14
4.1.2.1 Master Mode Speed Selection ................................................................................... 14
4.1.3 Master Clock  ............ ... ... ................ .... ... ... ... .... ... ... ................ ... .... ... ... ... .... ... ... ...................... 14
4.2 Serial Audio Interface ..................................................................................................................... 15
4.3 Digital Interface ............................................................................................................................... 15
4.4 Analog Connections  ....................................................................................................................... 15
4.4.1 Component Values ...................... ... .... ... ... ... .... ... ... ... ................ .... ... ... ... .... ... ... ... ... .... ............ 16
4.5 Grounding and Power Supply Decoupling ................ ... ................... ... .................... ... ................... ...16
4.6 Synchronization of Multiple Devices ............................................................................................... 17
5. FILTER PLOTS   ................................................................................................................................... 17
6. PARAMETER DEFINITIONS ................................................................................................................ 19
7. PACKAGE DIMENSIONS  .................................................................................................................... 20
THERMAL CHARACTERISTICS .......................................................................................................... 20
8. ORDERING INFORMATION  ................................................................................................................ 21
9. REVISION HISTORY ............................................................................................................................ 21
LIST OF FIGURES
Figure 1. CS5343 I²S Serial Audio Interface.............................................................................................. 11
Figure 2. CS5344 Left-Justified Serial Audio Interface.... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ...... 11
Figure 3. Typical Connection Diagram................ .................... ... ................... .... ................... ... ................... 12
Figure 4. I²S Serial Audio Interface............................................................................................................ 15
Figure 5. Left-Justified Serial Audio Interface..... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ...................... 15
Figure 6. CS5343/4 Analog Input Network................................................................................................. 15
Figure 7. CS5343/4 Example Analog Input Network.................................................................................. 16
Figure 8. Single-Speed Mode Stopband Rejection.................... ... .... ... ... ... ... .... ... ... ................ ... .... ... ... ...... 17
Figure 9. Single-Speed Mode Transition Band.......................................................................................... 17
Figure 10. Single-Speed Mode Transition Band (Detail).. .... ... ... ... .... ... ... ... ... .... ... ... ... .... ................... ... ...... 17
Figure 11. Single-Speed Mode Passband Ripple............ .... ... ... ... .... ... ... ... ... .... ... ... ................... .... ... ... ... ... 17
Figure 12. Double-Speed Mode Stopband Rejection....... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .. .18
Figure 13. Double-Speed Mode Transition Band....................................................................................... 18
Figure 14. Double-Speed Mode Transition Band (Detail).......................................................................... 18
Figure 15. Double-Speed Mode Passband Ripple.................. ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 18

DS687A4 3

CS5343/4

LIST OF TABLES

Table 1. Master/Slave Mode Selection ...................................................................................................... 13

Table 2. Speed Modes and the Associated Sample Rates (Fs) in Slave Mode...... ... .................... ... ......... 13

Table 3. Speed Modes and the Associated Sample Rates (Fs) in Master Mode....... .................... ... ......... 14

Table 4. Speed Mode Selection in Master Mode....................................................................................... 14

Table 5. Common MCLK Frequencies in Master and Slave Modes.......................................................... 14

Table 6. Analog Input Design Parameters................................................................................................. 16

4 DS687A4

CS5343/4

1. PIN DESCRIPTIONS

Pin Name Pin # Pin Description

SDOUT 1 Serial Audio Data Output (Output) - Output for two’s complement serial audio data. Also selects Master

or Slave Mode.

SCLK 2 Serial Clock (Input/Output) - Serial clock for the serial audio interface.

LRCK 3 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line.

MCLK 4 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

FILT+ 5 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

AINL

AINR 6

8Analog Input (Input) - The full-scale analog inpu t level is specified in the Analog Characteristics specifi-

cation table.

VQ 7 Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.

GND 9 Ground (Input) - Ground reference. Must be connected to analog ground.

VA 10 Power (Input) - Positive power supply for the digital and analog sections.

SDOUT

SCLK

LRCK

MCLK

FILT+

GND

AINR

AINL

DS687A4 5

CS5343/4

2. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical

performance characteristics and specifications are derived from measurements taken at typical supply voltages

and TA = 25°C.)

SPECIFIED OPERATING CONDITIONS

(GND = 0 V, all voltages with respect to GND.)

ABSOLUTE MAXIMUM RATINGS

(GND = 0 V, all voltages with respect to GND.) (Note 1)

Notes: 1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not

guaranteed at these extremes.

2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause

SCR latch-up.

3. The maximum over/under voltage is limited by the input current.

Parameter Symbol Min Typ Max Unit

Power Supplies VA 3.1

4.75 3.3

5.0 3.5

5.25 V

Ambient Operating Temperature Commercial

Automotive TAC

TAD

-10

-40 -

-70

85 °C

°C

Parameter Symbol Min Max Unit

DC Power Supplies VA -0.3 +6.0 V

Input Current (Note 2) Iin -10 +10 mA

Input Voltage (Note 3) VIN -0.7 VA+0.7 V

Ambient Operating Temperature (Power Applied) TA-50 +115 °C

Storage Tempera ture Tstg -65 +150 °C

6 DS687A4

CS5343/4

ANALOG CHARACTERISTICS - COMMERCIAL GRADE

Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is

10 Hz to 20 kHz; source impedance less than or equal to 2.5 kΩ.

Notes: 4. Referred to the typical full-scale input voltage

Dynamic Performance for Commercial Grade VA = 3.3 V VA = 5.0 V

Single-Speed Mode Fs = 48 kHz Symbol Min Typ Max Min Typ Max Unit

Dynamic Range A-weighted

unweighted 89

86 95

92 -

-92

89 98

95 -

-dB

Total Harmonic Distortion + Noise (Note 4)

-1 dB

-20 dB

-60 dB

THD+N -

-86

-75

-35

-80

-90

-78

-38

-84

Double-Speed Mode Fs = 96 kHz Min Typ Max Min Typ Max Unit

Dynamic Range A-weighted

unweighted 89

86 95

92 -

-92

89 98

95 -

-dB

Total Harmonic Distortion + Noise (Note 4)

-1 dB

-20 dB

-60 dB

THD+N -

-86

-75

-35

-80

-90

-78

-38

-84

Dynamic Performance for Commercial Grade - All Modes

Min Typ Max Unit

Interchannel Isolation - 90 - dB

DC Accuracy

Interchannel Gain Mismatch - - 0.1 dB

Gain Error -3 - +3 %

Gain Drift - ±100 - ppm/°C

Analog Input Characteristics

Full-scale Input Voltage 0.51*VA 0.56*VA 0.57*VA Vpp

Input Impedance - 7.5 - MΩ

DS687A4 7

CS5343/4

ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE

Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is

10 Hz to 20 kHz; source impedance less than or equal to 2.5 kΩ.

Notes: 5. Referred to the typical full-scale input voltage

Dynamic Performance for Automotive Grade VA = 3.3 V VA = 5.0 V

Single-Speed Mode Fs = 48 kHz Symbol Min Typ Max Min Typ Max Unit

Dynamic Range A-weighted

unweighted 87

84 95

92 -

-90

87 98

95 -

-dB

Total Harmonic Distortion + Noise (Note 5)

-1 dB

-20 dB

-60 dB

THD+N -

-86

-75

-35

-78

-90

-78

-38

-82

Double-Speed Mode Fs = 96 kHz Min Typ Max Min Typ Max Unit

Dynamic Range A-weighted

unweighted 87

84 95

92 -

-90

87 98

95 -

-dB

Total Harmonic Distortion + Noise (Note 5)

-1 dB

-20 dB

-60 dB

THD+N -

-86

-75

-35

-78

-90

-78

-38

-82

Dynamic Performance for Automotive Grade - All Modes

Min Typ Max Unit

Interchannel Isolation - 90 - dB

DC Accuracy

Interchannel Gain Mismatch - - 0.1 dB

Gain Error -3 - +3 %

Gain Drift - ±100 - ppm/°C

Analog Input Characteristics

Full-scale Input Vo ltage 0.51*VA 0.56*VA 0.57*VA Vpp

Input Impedance - 7.5 - MΩ

8 DS687A4

CS5343/4

DIGITAL FILTER CHARACTERISTICS

Notes: 6. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.

DC ELECTRICAL CHARACTERISTICS

(GND = 0 V, all voltages with respect to 0 V. MCLK=12.288 MHz; Master Mode)

Notes: 7. Device enters power-down mode when MCLK is held static.

8. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection

Diagram.

Parameter Symbol Min Typ Max Unit

Single-Speed Mode Fs = 4 - 54 kHz

Passband (-0.1 dB) 0 - 0.489 Fs

Passband Ripple -0.025 - 0.025 dB

Stopband 0.560 - - Fs

Stopband Attenuation 69 - - dB

Total Group Delay (Fs = Output Sample Rate) tgd - 12/Fs - s

Double-Speed Mode Fs = 86 - 108 kHz

Passband (-0.1 dB) 0 - 0.489 Fs

Passband Ripple -0.025 - 0.025 dB

Stopband 0.560 - - Fs

Stopband Attenuation 69 - - dB

Total Group Delay (Fs = Output Sample Rate) tgd -9/Fs- s

High-Pass Filter Characteristics

Frequency Response -3.0 dB

-0.13 dB (Note 6) -1

20 -

-Hz

Phase Deviation @ 20 Hz (Note 6) -10-Deg

Passband Ripple - - 0 dB

Parameter Symbol

VA = 3.3 V VA = 5.0 V

Min Typ Max Min Typ Max Unit

DC Power Supplies: VA 3.1 3.3 - - 5 5.25 V

Power Supply Current (Normal Operation) IA-15--15 -mA

Power Supply Current (Power-Down Mode) (Note 7) IA-1.1--1.1 - mA

Power Consumption (Normal Operation)

(Power-Down Mode) (Note 7) -

-50

3.6 -

-75

5.5 -

-mW

Parameter Symbol Min Typ Max Unit

Power Supply Rejection Ratio (1 kHz) (Note 8) PSRR - 65 - dB

VQ Nominal Voltage

Output Impedance -

-0.44xVA

25 -

-V

kΩ

Filt+ Nominal Voltage

Output Impedance

Maximum allowable DC current source/sink

220

2.5

kΩ

DS687A4 9

CS5343/4

DIGITAL CHARACTERISTICS

Parameter Symbol Min Typ Max Units

High-Level Input Voltage (% of VA ) VIH 70 - - %

Low-Level Input Voltage (% of VA) VIL --30%

High-Level Output Voltage at Io = 500 µA(% of VA)

VOH 70 - - %

Low-Level Output Voltage at Io =500 µA(% of VA)

VOL --15%

Input Leakage Current Iin -10 - 10 µA

10 DS687A4

CS5343/4

SYSTEM CLOCKING AND SERIAL AUDIO INTERFACE

(Logic “0” = GND = 0 V; Logi c “1” = VA, CL = 20 pF)

Parameter Symbol Min Typ Max Unit

Master Mode

MCLK Period (Double-Speed, 384x Mode) tclkw 24 - 30 ns

(Double-Speed, 192x Mode) 48 - 60 ns

(Double-Speed, 256x Mode) 36 - 45 ns

(Double-Speed, 128x Mode) 72 - 90 ns

(Single-Speed, 768x Mode) 24 - 325 ns

(Single-Speed, 384x Mode) 48 - 651 ns

(Single-Speed, 512x Mode) 36 - 488 ns

(Single-Speed, 256x Mode) 72 - 976 ns

MCLK Duty Cycle 40 50 60 %

Output Sample Rate (Single-Sp eed)

(Double-Speed) Fs 4

86 -

-54

108 kHz

kHz

LRCK Duty Cycle - 50 - %

SCLK Duty Cycle - 50 - %

SDOUT valid before SCLK rising tstp 10 - - ns

SDOUT valid after SCLK rising thld 40 - - ns

SCLK falling to LRCK edge tslrd -20 - 20 ns

Slave Mode

MCLK Period (Double-Speed, 384x Mode) tclkw 24 - 30 ns

(Double-Speed, 192x Mode) 48 - 60 ns

(Double-Speed, 256x Mode) 36 - 45 ns

(Double-Speed, 128x Mode) 72 - 90 ns

(Single-Speed, 768x Mode) 24 - 325 ns

(Single-Speed, 384x Mode) 48 - 651 ns

(Single-Speed, 512x Mode) 36 - 488 ns

(Single-Speed, 256x Mode) 72 - 976 ns

MCLK Duty Cycle 40 50 60 %

Input Sample Rate (Single-Speed)

(Double-Speed) Fs 4

86 -

-54

108 kHz

kHz

LRCK Duty Cycle 405060%

SCLK Period tsclkw --ns

SCLK Duty Cycle 455055%

SDOUT valid before SCLK rising tstp 10 - - ns

SDOUT valid after SCLK rising thld 10 - - ns

SCLK falling to LRCK edge tslrd -20 - 20 ns

64 Fs×

------------------

DS687A4 11

CS5343/4

Figure 1. CS5343 I²S Serial Audio Interface

stp hld

MSB MSB-1

LRCK

SCLK

SDOUT

tslrd

tsclkw

Figure 2. CS5344 Left-Justified Serial Audio Interface

stp hld

MSB MSB-1

LRCK

SCLK

SDOUT

tslrd

tsclkw

12 DS687A4

CS5343/4

3. TYPICAL CONNECTION DIAGRAM

Figure 3. Typical Connection Diagram

AINL

AINR

SDOUT

9GND

7VQ

5FILT+

SCLK

LRCK

MCLK

Audio

Processor/

System

Clocks

VA or

GND VA

3.3 V to 5 V

CS5343/4

10 kΩ1

10 kΩ2

Analog Input

Conditioning

10 kΩ2

1 µF 0.1 µF

1 µF0.1 µF

See Figure 6 on

page 15 1 Pull-up to VA for Master Mode

Pull-down to GND for Slave Mode

2 Optional pull-up resistor for configur-

ing clocks in Master Mode as desribed

in the “Master Mode Speed Selection”

section on page 14

DS687A4 13

CS5343/4

4. APPLICATIONS

4.1 Operation as Clock Master or Slave

The CS5343/4 supports operation as either a clock master or slave. As a clock master, the left/right and

serial clocks are synchronously generated on-chip and output on the LRCK and SCLK pins , respectively.

As a clock slave, the LRCK and SCLK pins are always inputs and require e xternal generation of the left/right

and serial clocks. The selection of clock master or slave is made via a 10 kΩ pull-up resistor from SDOUT

to VA for Master Mode selecti on or via a 10 kΩ pull-down resistor from SDOUT to GND for Slave Mode se-

lection, as shown in Table 1.

4.1.1 Slave Mode Operation

A unique feature of the CS5343/4 is the automatic selection of either Single- or Double-Speed Mode when

acting as a clock slave. The auto-mode selection feature supports all standard audio sample rates from

4 to 108 kHz. Please refer to Table 2 for supported sample rate ranges in Slave Mode.

Table 2. Speed Modes and the Associated Sample Rates (Fs) in Slave Mode

Mode Selection

Master Mode 10 kΩ pull-up resistor from SDOUT to VA

Slave Mode 10 kΩ pull-down resistor from SDOUT to GND

Table 1. Master/Slave Mode Selection

Speed Mode MCLK/LRCK

Ratio SCLK/LRCK

Ratio Input Sample Rate Range (kHz)

Single-Speed Mode

256x 64 4 - 54

512x 64 4 - 54

384x 48, 64 4 - 54

768x 48, 64 4 - 54

Double-Speed Mode

128x 64 86 - 108

256x 64 86 - 108

192x 48, 64 86 - 108

384x 48, 64 86 - 108

14 DS687A4

CS5343/4

4.1.2 Master Mode Operation

As clock Master, the CS5343/4 generates LRCK and SCLK synchronously on-chip. Table 3 shows the

available sample rates and asso ciated clock ratios in Master Mode.

4.1.2.1 Master Mode Speed Selection

During power-up in Master Mode, the LRCK and SCLK pins are inputs to configure speed mode and the

output clock ratio. The LRCK pin is pulled low intern ally to select Single-Speed M ode by default, but Dou-

ble-Speed Mode is accessed with a 10 kΩ pull-up resistor from LRCK to VA as shown in Table 4. Simi-

larly, the SCLK pin is internally pulled-low by default to select a 256x MCLK/LRCK ratio, but a

MCLK/LRCK ratio of 348x is accessed with a 10 kΩ pull-up resistor from SCLK to VA as shown in Table 4.

Following the power-up routine, the LRCK and SCLK pins become clock outputs.

4.1.3 Master Clock

The CS5343/4 requir es a Master clock (MCLK) which run s the internal sampling circuits and digital filters.

There is also an internal MCLK divider which is automatically activated based on the frequency of the

MCLK. Table 4 lists some common audio output sample rates and the required MCLK frequency.

Speed Mode MCLK/LRCK

Ratio SCLK/LRCK

Ratio Input Sample Rate Range (kHz)

Single-Speed Mode

256x 64 4 - 54

512x 64 4 - 54

384x 64 4 - 54

768x 64 4 - 54

Double-Speed Mode

128x 64 86 - 108

256x 64 86 - 108

192x 64 86 - 108

384x 64 86 - 108

Table 3. Speed Modes and the Associated Sample Rates (Fs) in Master Mode

Pin Resistor Option Clock Configuration

LRCK Internal Pull-Down to GND (100 kΩ) Single-Speed Mode (default)

External Pull-Up to VA (10 kΩ) Double-Speed Mode

SCLK Internal Pull-Down to GND (100 kΩ) 256x MCLK/LRC K (d efault)

External Pull-Up to VA (10 kΩ) 384x MCLK/LRCK

Table 4. Speed Mode Selection in Master Mode

Master and Slave Mode

Sample Rate (kHz) Speed Mode MCLK(MHz) MCLK (MHz)

256x 512x 384x 768x

32 SSM 8.912 16.384 12.288 24.576

44.1 SSM 11.289 22.579 16.934 33.868

48 SSM 12.288 24.576 18.432 36.864

Sample Rate (kHz) Speed Mode MCLK(MHz) MCLK (MHz)

128x 256x 192x 384x

88.2 DSM 11.289 22.579 16.934 33.868

96 DSM 12.288 24.576 18.432 36.864

Table 5. Common MCLK Frequencies in Master and Slave Modes

DS687A4 15

CS5343/4

4.2 Serial Audio Interface

The CS5343 output is serial data in I²S audio format and the CS5344 output is serial data in Left-Justified

audio format. Figures 4 and 5 show th e I²S and Left-Justified data relative to SCLK and LRCK. Additionally,

Figures 1 and 2 display more information on the required timing for the serial audio interface format. For an

overview of serial audio interf ace formats, please refer to Cirrus Application Note AN282.

4.3 Digital Interface

VA supplies power to both the analog an d digital sections of the ADC, and also po wers the serial port. Con-

sequently, the digital interface logic level mu st equal VA to within the limits specified u nder “Digital Charac-

teristics” on page 9.

4.4 Analog Connections

The analog modulator samples the input signal at half of the internal master clock rate, or 6.144 MHz when

MCLK = 12.288 MHz. The digital filter will reject signals within the stopband of the filter. However, there is

no rejection for input signals which are multiples of the input sampling frequency (n ×6.144 MHz), where

n=0,1,2,... Refer to Figure 6 which shows the recommended topology of the analog input networ k. The ex-

ternal shunt capacitor and internal input impedance form a single-pole RC filter to provide the appropriate

filtering of noise at the modulator sampling frequency. Additionally, the 180 pF capa citor acts as a char ge

source for the internal sampling circuits. Capacitors of NPO or other high-quality dielectric will produce the

best results while capacitors with a large voltage coefficient (such as general-purpose ceramics) can de-

grade signal linearity.

Figure 4. I²S Serial Audio Interface

SDATA 23 22 8 723 22

SCLK

LRCK

23 2265432108765432109 9

Left Channel Right Channel

Figure 5. Left-Justified Serial Audio Interface

SDATA 23 22 7 623 22

SCLK

LRCK

23 2254321087654321089 9

Left Channel Right Channel

Figure 6. CS5343/4 Analog Input Network

CS5343/4

AIN

Input R1

1 µF

180pF

C0G

16 DS687A4

CS5343/4

4.4.1 Component Values

Three parame ters determ ine the values of re sistors R1 and R2 as shown in Figure 6: source impe dance,

attenuation, and input impedance. Table 6 shows the design equati on use d to de te rm in e th es e valu e s.

•Source Impedance: Source impedance is defined as the impedance as seen from the ADC looking

back into the signal network. The ADC achieves optimal THD+N performance with a source imped-

ance less than or equal to 2.5 kΩ.

•Attenuation: The required attenuation factor depends on the magnitude of the input signal. The full-

scale input voltage is specified under “Analog Characteristics - Commercial Grade” on page 6. The

user should select values for R1 and R2 such that the m agn itude o f the incom ing signa l multiplied by

the attenuation factor is less than or equal to the full-scale input voltage of the device.

•Input Impedance: Inp ut impedance is the impeda nce from the signa l source to the ADC analog inpu t

pins. Table 6 shows the input paramete rs and the associated design equations.

Figure 7 illustrates an example configuration using two 4.99 kΩ resistors in place of R1 and R2. Based on

the discussion above, this circuit provides an optimal interface for both the ADC and the signal source.

First, consumer equipment frequently requires an input impedance of 10 kΩ, which the 4.99 kΩ resistors

provide. Second, this circuit will attenuate a typical line level voltage, 2 Vrms, to the full-scale input of the

ADC, 1 Vrms when VA = 5 V. Finally, at 2.5 kΩ, the source impedance optimizes analog performance of

the ADC.

4.5 Grounding and Power Supply Decoupling

As with any high-resolu tion converter, designing with the CS5343/4 re quires careful attention to power sup-

ply and grounding arrangements if its potential performance is to be realized . Figure 3 shows the recom-

mended power arrangements, with VA connected to a clean supply. Decoupling capacitors should be as

near to the ADC as possible, with the low value ceramic ca pacitor b eing the ne arest. All sign als, espe cially

clocks, should be kept away from the FILT+ an d VQ pins in order to a void unwanted coupling into the mod-

ulators. The FI LT + an d VQ de co up lin g cap ac ito rs , par ticularly the 0.01 µF, must be positioned to minimize

the electrical path from FILT+ to GND. The CDB5343 evaluation board demonstrates the optimum layout

and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS

inputs.

Source Impedance

Attenuation Factor

Input Impedance

Table 6. Analog Input Design Parameters

R1R2×()

R1R2+

-------------------------

R2()

R1R2+()

-------------------------

R1R2+()

Figure 7. CS5343/4 Example Analog Input Network

CS5343/4

AIN

Input 4.99 kΩ

4.99 kΩ

1 µF

180pF

C0G

DS687A4 17

CS5343/4

4.6 Synchronization of Multiple Devices

In systems where multiple ADCs ar e required, care must be taken to achieve simultaneous sampling. To

ensure synchronous sampling, the MCLK, SCLK, and LRCK must be the same for all of the CS5343 and

CS5344 devices in the system.

5. FILTER PLOTS

Figure 8. Single-Speed Mode Stopband Rejection Figure 9. Single-Speed Mode Transiti on Band

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Frequency (normal ized to Fs)

Amplitude (dB)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60

Frequency (normalized to Fs)

Amplitude (dB)

Figure 10. Single-Speed Mode Transition Band (Detail) Figure 11. Single-Speed Mode Passband Ripple

-0.10

-0.08

-0.06

-0.04

-0.02

0.00

0.02

0.04

0.06

0.08

0.10

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency (normalized to Fs)

Amplitude (dB)

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.46 0.47 0.48 0.49 0.50 0.51 0.52

Frequenc y (norma li zed to Fs)

Amplitude (dB)

18 DS687A4

CS5343/4

Figure 12. Double-Speed Mode Stopband Rejection Figure 13. Double-Speed Mode Tran sition Band

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60

Frequency (normalized to Fs)

Amplitude (dB)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Frequenc y (norma li zed to Fs)

Amplitude (dB)

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.46 0.47 0.48 0.49 0.50 0.51 0.52

Frequenc y (norma li zed to Fs)

Amplitude (dB)

-0.10

-0.08

-0.06

-0.04

-0.02

0.00

0.02

0.04

0.06

0.08

0.10

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency (normalized to Fs)

Amplitude (dB)

Figure 14. Double-Speed Mode Transition Band (Detail) Figure 15. Double-Speed Mode Passband Ripple

DS687A4 19

CS5343/4

6. PARAMETER DEFINITIONS

Dynamic Range

The ratio of the rms value of the signal to the rms sum of all other spectral comp onents ove r the specif ied

bandwidth. Dynamic Range is a signal-to- noise ratio measurement over th e specified bandwidth made with

a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This

technique ensu res tha t the distortion co mpone nts are below the noise level and do n ot affect the m easure-

ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,

and the Electronic Industries Association of Japan, EIAJ CP-307 . Exp resse d in de cib els .

Total Harmonic Distortion + Noise

The ratio of the rms value of the signal to the rms sum of all other spectral comp onents ove r the specif ied

bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured

at -1 and -20 dBFS as suggested in AES17-1991 Annex A.

Frequency Response

A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at

1 kHz. Units in decibels.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel a t the conver ter's

output with no signal to the input under test and a full-scale signal applied to the other channel. Units in deci-

bels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full-scale analog input for a full-scale digital output.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Offset Error

The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.

20 DS687A4

CS5343/4

7. PACKAGE DIMENSIONS

Notes: 1. Reference document: JEDEC MO-187

2. D does not include mold flash or protrusions which is 0.15 mm max. per side.

3. E1 does not inclu de inter-lead flash or protrusions which is 0.15 mm max per side.

4. Dimensio n b do es not inc l ud e a to ta l allowa b le da m ba r pr ot ru sio n of 0. 08 mm max .

5. Exceptions to JEDEC dimension.

THERMAL CHARACTERISTICS

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.0433 -- -- 1.10

A1 0 -- 0.0059 0 -- 0.15

A2 0.0295 -- 0.0374 0.75 -- 0.95

b 0.0059 -- 0.0118 0.15 -- 0.30 4, 5

c 0.0031 -- 0.0091 0.08 -- 0.23

D -- 0.1181 BSC -- -- 3.00 BSC -- 2

E -- 0.1929 BSC -- -- 4.90 BSC --

E1 -- 0.1181 BSC -- -- 3.00 BSC -- 3

e -- 0.0197 BSC -- -- 0.50 BSC --

L 0.0157 0.0236 0.0315 0.40 0.60 0.80

L1 -- 0.0374 REF -- -- 0.95 REF --

µ0°--8°0°--8°

Controlling Dimension is Millimeters

Parameter Symbol Min Typ Max Unit

Allowable Junction Temperature TJ--135

°C

Junction to Ambient Thermal Impedance (4-layer PCB)

(2-layer PCB) θJA-4

θJA-2

-100

170 -

-°C/W

°C/W

10LD TSSOP (3 mm BODY) PACKAGE DRAWING (Note 1)

123

ebA1

A2 A

SEATING

PLANE

E11

SIDE VIEW

END VIEW

TOP VIEW

∝

DS687A4 21
CS5343/4
8. ORDERING INFORMATION
9. REVISION HISTORY
Product Description Package Pb-Free Grade Temp Range Container Order #
CS5343 98 dB, Multi-Bit Au dio 
A/D Converter, 
I²S Audio Format 10-TSSOP Yes Commercial -10° to +70° C Rail CS5343-CZZ 
Tape & Reel CS5343-CZZR
CS5343 98 dB, Multi-Bit Au dio 
A/D Converter, 
I²S Audio Format 10-TSSOP Yes Automotive -40° to +85° C Rail CS5343-DZZ 
Tape & Reel CS5343-DZZR
CS5344 98 dB, Multi-Bit Au dio 
A/D Converter, 
Left -Ju sti fi e d Au di o  Form at 10-TSSOP Yes Commercial -10° to +70° C Rail CS5344-CZZ 
Tape & Reel CS5344-CZZR
CS5344 98 dB, Multi-Bit Au dio 
A/D Converter, 
Left -Ju sti fi e d Au di o  Form at 10-TSSOP Yes Automotive -40° to +85° C Rail CS5344-DZZ 
Tape & Reel CS5344-DZZR
CDB5343 CS5343 Evaluation Board - No - - - CDB5343
Release Changes
A2 Changes made to Serial Port diagrams. See Figure 1 and Figure 2 on page 11.
A3 Replaced block diagram on cover page.
Increased minimum hold time (Thld) specification on page 10.
Updated Table 4, “Speed Mode Selection in Master Mode,” on page 14.
A4 Corrected MCLK timing specifications on  page 10
Corrected “Typical Connection Diagram” on page 12
Corrected Table 3, “Speed Modes and the Associated Sample Rates (Fs) in Master Mode,” on pa ge 14
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative. 
To find one nearest you, go to www.cirrus.com.
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believe that the  inform ation co ntained in  this docu ment  is accura te and  reliable. Ho wever, the  informa tion is subje ct to chan ge without notice an d is provided "AS  IS"
without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that
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