Data Sheet
July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Features
■
+5 V only
■
Two independent channels
■
Pin-selectable receive gain control
■
Pin-selectable
µ
-law or A-law companding
■
Automatic powerdown mode
■
Low-power, latch-up-free CMOS technology
— 40 mW/channel typical operating power
dissipation
— 12.5 mW/channel typical standby power
dissipation
■
Automatic master clock frequency selection
— 2.048 MHz or 4.096 MHz
■
Independent transmit and receive frame strobes
■
2.048 MHz or 4.096 MHz data rate
■
On-chip sample and hold, autozero, and precision
voltage reference
■
Differential architecture for high noise immunity
and power supply rejection
■
Meets or exceeds ITU-T G.711—G.714 require-
ments and VF characteristics of D3/D4 (as per
Bellcore PUB43801)
■
Operating temperature range: –40
°
C to +85
°
C
Description
The T8502 and T8503 devices are single-chip, two-
channel,
µ
-law/A-law PCM codecs with filters. These
integrated circuits provide analog-to-digital and
digital-to-analog conversion. They provide the
transmit and receiv e filtering necessary to interf ace a
voice telephone circuit to a time-division multiplexed
system. These devices are packaged in both 20-pin
SOJs and 20-pin SOGs.
The T8502 differs from the T8503 in its timing mode.
The T8502 operates in the delayed timing mode
(digital data is valid one clock cycle after frame sync
goes high), and the T8503 operates in the
nondelayed timing mode (digital data valid when
frame sync goes high) (see Figures 5 and 6).
5-3579.b
Figure 1. Block Diagram
FS
X
0
FS
R
0
FS
X
1
FS
R
1
GNDD
GS
X
0
VF
X
IN0
VF
R
O0
GS
X
1
VF
X
IN1
VF
R
O1
–
+
FILTER
NETWORK ENCODER
CHANNEL 0
+2.4 V
DECODER
PCM
INTERFACE
GAIN
CONTROL
INTERNAL TIMING
& CONTROL
BIAS
CIRCUITRY
&
REFERENCE
CHANNEL 1
FILTER
NETWORK
D
X
D
R
MCLK
ASEL
V
DD
GNDA (2)
GS0
GS1
22 Lucent Technologies Inc.
Data Sheet
July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Functional Description
Two channels of PCM data input and output are passed
through only two ports, D
X
and D
R
, so some type of
time-slot assignment is necessary. The scheme used
here is to utilize a fix ed-data rate mode of 32 or 64 time
slots corresponding to master clock frequencies of
either 2.048 MHz or 4.096 MHz, respectively. Each
device has four frame sync (FS
X
and FS
R
) inputs, one
pair for each channel. During a single 125
µ
s frame,
each frame sync input is supplied a single pulse. The
timing of the respective frame sync pulse indicates the
beginning of the time slot during which the data for that
channel is clocked in or out of the de vice . FS
X
and FS
R
must be high for a minimum of one master clock cycle.
They can be operated independently, or they can be
tied together for coincident transmit and receive data
transfer. During a frame, channel 0 and 1 transmit
frame sync pulses must be separated from each other
by one or more time slots. Likewise, channel 0 and 1
receive frame sync pulses must be separated from
each other by one or more time slots . Both transmit and
receive frame strobes must be derived from master
clock, but they do not need to be byte aligned.
A channel is placed in standby mode b y remo ving both
FS
X
and FS
R
for 500
µ
s. Note, if any one of those
pulses (per channel) is removed, operation is indeter-
minate. Standby mode reduces overall device power
consumption by turning off nonessential circuitry. Criti-
cal circuits that ensure a fast, quiet powerup are kept
active. Master clock need not be active when both
channels are in standby mode.
The frequency of the master clock must be either
2.048 MHz or 4.096 MHz. Internal circuitry determines
the master clock frequency during the powerup reset
interval.
The analog input section in Figure 2 includes an on-
chip op amp that is used in conjunction with external,
user-supplied resistors to vary encoder passband gain.
The f eedback resistance (RF) should range from 10 k
Ω
to 200 k
Ω
, and capacitance from GS
X
to ground should
be kept to less than 50 pF. The input signal at VF
X
IN
should be ac coupled. For best performance, the maxi-
mum gain of this op amp should be limited to 20 dB or
less. Gain in the receive path is selectable via the GS
pins as either 0 dB or –3.5 dB.
5-3786.a
Figure 2. Typical Analog Input Section
Pin Information
5-3788.b
Figure 3. Pin Diagram
VF
X
IN TO
CODEC
FILTERS
2.4 V
GAIN = R
F
R
I
GS
X
R
F
C
I
R
I
–
+
VFXIN0
GSX0
GS0
FSR0
MCLK
GNDD
DR
DX
VFXIN1
GSX1
ASEL
FSR1
FSX1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
FSX0
T-8502
T-8503
VFRO0
GNDA0
VDD
VFRO1
GNDA1
GS1
Lucent Technologies Inc. 3
Data Sheet
July 1998 T8502 and T8503 Dual PCM Codecs with Filters
Pin Information
(continued)
* I
d
indicates
a pull-down device is included on this lead. I
u
indicates a pull-up device is included on this lead.
Table 1. Pin Descriptions
Symbol Pin Type
*
Name/Function
VF
X
IN1
VF
X
IN0 20
1I
Voice Frequency Transmitter Input.
Analog inverting input to the uncommitted oper-
ational amplifier at the transmit filter input. Connect the signal to be digitized to this pin
through a resistor R
I
(see Figure 2).
GS
X
1
GS
X
019
2O
Gain Set for Transmitter.
Output of the transmit uncommitted operational amplifier.
The pin is the input to the transmit differential filters. Connect the pin to its
corresponding VF
X
IN through a resistor R
F
(see Figure 2).
VF
R
O1
VF
R
O0 17
4O
Voice Frequency Receiver Output.
This pin can drive 2000
Ω
(or greater) loads.
V
DD
6 —
+5 V Power Supply
. This pin should be bypassed to ground with at least 0.1
µ
F of
capacitance as close to the device as possible.
GNDA1
GNDA0 18
3—
Analog Grounds
. All ground pins must be connected on the circuit board.
D
R
12 I
Receive PCM Data Input
. The data on this pin is shifted into the device on the falling
edges of MCLK. Data is only entered for valid time slots as defined by the FS
R
inputs.
D
X
11 O
Transmit PCM Data Output
. This pin remains in the high-impedance state except
during active transmit time slots. An active transmit time slot is defined as one in which
a pulse is present on one of the FS
X
inputs. Data is shifted out on the rising edge of
MCLK.
MCLK 9 I
Master Clock Input
. The frequency must be 2.048 MHz or 4.096 MHz. This clock
serves as the bit clock for all PCM data transfer.
GNDD 10 —
Digital Ground
. Ground connection for the digital circuitry. All ground pins must be
connected on the circuit board.
FS
X
1
FS
X
013
8I
d
Transmit Frame Sync
. This signal is an edge trigger and must be high for a minimum
of one MCLK cycle. This signal must be derived from MCLK. The division ratio is 1:256
or 1:512 (FS
X
:MCLK). Each FS
X
input must have a pulse present at the start of the
desired active output time slot. Pulses on FS
X
inputs must be separated by one or more
integer multiples of time slots. If the device is to be used as an A/D converter only, FS
X
must be tied to FS
R
. An internal pull-down device is included on each FS
X
.
FS
R
1
FS
R
014
7I
d
Receive Frame Sync
. This signal is an edge trigger and must be high for a minimum
of one MCLK cycle. This signal must be derived from MCLK. The division ratio is 1:256
or 1:512 (FS
R
:MCLK). Each FS
R
input must have a pulse present at the start of the
desired active input time slot. Pulses on FS
R
inputs must be separated by one or more
integer multiples of time slots. If the device is to be used as a D/A converter only, FS
R
must be tied to FS
X
. An internal pull-down device is included on each FS
R
.
GS1
GS0 16
5I
u
Gain Selection
. A high or floating state sets the receive path gain at 0 dB; a logic low
sets the gain to –3.5 dB. A pull-up device is included.
ASEL 15 I
d
A-Law/
µ
-Law Select
. A logic low selects
µ
-law coding. A logic high selects A-law
coding. A pull-down device is included.
4 Lucent Technologies Inc.
Data Sheet
July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operational sections of this data sheet. Exposure to absolute maximum ratings for
extended periods can adversely affect device reliability.
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid
exposure to electrostatic discharge (ESD) during handling and mounting. Lucent Technologies Microelectronics
Group emplo ys a human-body model (HBM) and a charged-de vice model (CDM) f or ESD-susceptibility testing and
protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the
model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance = 1500
Ω
,
capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD
threshold presented here was obtained by using these circuit parameters:
Electrical Characteristics
Specifications apply for T
A
= –40
°
C to +85
°
C, V
DD
= 5 V
±
5%, MCLK = either 2.048 MHz or 4.096 MHz, and
GND = 0 V, unless otherwise noted.
dc Characteristics
Table 2. Digital Interface
Parameter Symbol Min Max Unit
Storage Temperature Range T
stg
–55 150
°
C
Power Supply Voltage V
DD
— 6.5 V
Voltage on Any Pin with Respect to Ground — –0.5 0.5 + V
DD
V
Maximum Power Dissipation (package limit) P
D
— 600 mW
HBM ESD Threshold Voltage
Device Rating
T8502 >2000
T8503 >2000
Parameter Symbol Test Conditions Min Typ Max Unit
Input Low Voltage V
IL
All digital inputs — — 0.8 V
Input High Voltage V
IH
All digital inputs 2.0 — — V
Output Low Voltage V
OL
D
X
, IL = 3.2 mA — — 0.4 V
Output High Voltage VOH DX, IL = –3.2 mA 2.4 — — V
DX, IL = –320 µA 3.5 — — V
Input Current, Pins 9, 12 IIGNDD < VIN < VDD –10 — 10 µA
Input Current, Pins 7, 8, 13, 14, 15 IIGNDD < VIN < VDD 2 — 150 µA
Input Current, Pins 5, 16 IIGNDD < VIN < VDD –120 — –2 µA
Output Current in High-impedance State IOZ DX–30 <±2 30 µA
Input Capacitance CI— — — 5 pF
Lucent Technologies Inc. 5
Data Sheet
July 1998 T8502 and T8503 Dual PCM Codecs with Filters
Electrical Characteristics (continued)
dc Characteristics (continued)
Table 3. Power Dissipation
Power measurements are made at MCLK = 4.096 MHz with outputs unloaded and ASEL and GS[1:0] not
connected. Clock and frame sync levels are +5 V and 0 V.
Transmission Characteristics
Table 4. Analog Interface
Channels
Operational Parameter Symbol Test Conditions Min Typ Max Unit
0 Standby Current IDDS MCLK present;
FSX[1:0] = FSR[1:0] = 0 V — 5 8 mA
1 Partial Standby Current IDDP MCLK present;
FS pulses present for
one channel,
FSX = FSR = 0 V for other
channel
— 10 16 mA
2 Powerup Current IDD1 MCLK, FS pulses present — 16 23 mA
Parameter Symbol Test Conditions Min Typ Max Unit
Input Resistance, VFXIN RVFXI0.25 V < VFXI < 4.75 V 1.0 60 — MΩ
Input Leakage Current, VFXIN IBVFXI0.25 V < VFXI < 4.75 V — 0.04 2.4 µA
dc Open-loop Voltage Gain, GSXAVOL —5000 — — —
Open-loop Unity Gain Bandwidth, GSXfO— 1 3 — MHz
Load Capacitance, GSXCLX1 — — — 50 pF
Load Resistance, GSXRLX1 — 10 — — kΩ
Input Voltage, VFXIN VIX Relative to ground 2.25 2.35 2.5 V
Load Resistance, VFRO RLVFRO— 2000 — — Ω
Load Capacitance, VFRO CLVFRO— — — 100 pF
Output Resistance, VFRO ROVFRO0 dBm0, 1020 Hz PCM code
applied to DR— — 20 Ω
Standby mode FSX = FSR = 0 V for
channel under test 3000 — 10000 Ω
Output Voltage, VFRO VOR Alternating ± zero µ-law PCM
code applied to DR2.25 2.38 2.5 V
Output Voltage, VFRO, Standby VORPD Standby mode FSX = FSR = 0 V for
channel under test, no load 2.0 2.35 2.65 V
Output Voltage Swing, VFRO VSWR RL = 2000 Ω3.2 — — Vp-p
6 Lucent Technologies Inc.
Data Sheet
July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Transmission Characteristics (continued)
ac T ransmission Characteristics
Unless otherwise noted, the analog input is a 0 dBm0, 1020 Hz sine wave; the input amplifier is set for unity gain.
The digital input is a PCM bit stream equivalent to that obtained by passing a 0 dBm0, 1020 Hz sine wave through
an ideal encoder. The output level is sin(x)/x-corrected.
Table 5. Absolute Gain
Table 6. Gain Tracking
Table 7. Distortion
Parameter Symbol Test Conditions Min Typ Max Unit
Encoder Milliwatt
Response (transmit
gain tolerance)
EmW Signal input of 0.775 Vrms,
µ-law or A-law 0 °C to 85 °C –0.20 — 0.20 dBm0
–40 °C to +85 °C –0.25 — 0.25 dBm0
Decoder Milliwatt
Response (receive
gain tolerance)
DmW Measured relative to
0.775 Vrms µ-law or A-law,
PCM input of 0 dBm0
1020 Hz, RL = 10 kΩ
0 °C to 85 °C –0.20 — 0.20 dBm0
–40 °C to +85 °C –0.25 — 0.25 dBm0
Relative Decoder Gain
Variation Referenced
to DmW
RGR Decoder gain at –3.5 dB
(GS = 0) –40 °C to +85 °C –0.15 — 0.15 dB
Parameter Symbol Test Conditions Min Typ Max Unit
Transmit Gain Tracking Error
Sinusoidal Input µ-Law/A-Law GTX+3 dBm0 to –37 dBm0
–37 dBm0 to –50 dBm0 –0.25
–0.50 —
—0.25
0.50 dB
dB
Receive Gain Tracking Error
Sinusoidal Input µ-Law/A-Law GTR+3 dBm0 to –37 dBm0
–37 dBm0 to –50 dBm0 –0.25
–0.50 —
—0.25
0.50 dB
dB
Parameter Symbol Test Conditions Min Typ Max Unit
Transmit Signal to Distortion SDXµ-law 3 dBm0 ≤ VFXI ≤ –30 dBm0
A-law 3 dBm0 ≤ VFXI ≤ –30 dBm0 36
35 —
——
—dB
dB
µ-law –30 dBm0 ≤ VFXI ≤ –40 dBm0
A-law –30 dBm0 ≤ VFXI ≤ –40 dBm0 30
29 —
——
—dB
dB
µ-law –40 dBm0 ≤ VFXI ≤ –45 dBm0
A-law –40 dBm0 ≤ VFXI ≤ –45 dBm0 25
25 —
——
—dB
dB
Receive Signal to Distortion SDRµ-law 3 dBm0 ≤ VFRO ≤ –30 dBm0
A-law 3 dBm0 ≤ VFRO ≤ –30 dBm0 36
35 —
——
—dB
dB
µ-law –30 dBm0 ≤ VFRO ≤ –40 dBm0
A-law –30 dBm0 ≤ VFRO ≤ –40 dBm0 30
29 —
——
—dB
dB
µ-law –40 dBm0 ≤ VFRO ≤ –45 dBm0
A-law –40 dBm0 ≤ VFRO ≤ –45 dBm0 25
25 —
——
—dB
dB
Single Frequency Distortion,
Transmit SFDX200 Hz—3400 Hz, 0 dBm0 input,
output any other single
frequency ≤ 3400 Hz
— — –38 dBm0
Single Frequency Distortion,
Receive SFDR200 Hz—3400 Hz, 0 dBm0 input,
output any other single
frequency ≤ 3400 Hz
— — –40 dBm0
Intermodulation Distortion IMD Transmit or receive, two frequencies
in the range (300 Hz—3400 Hz)
at –6 dBm0
— — –42 dBm0
Lucent Technologies Inc. 7
Data Sheet
July 1998 T8502 and T8503 Dual PCM Codecs with Filters
Transmission Characteristics (continued)
ac T ransmission Characteristics (continued)
Overload Compression
Figure 4 shows the region of operation for encoder signal levels above the reference input power (0 dBm0).
5-3586C
Figure 4. Overload Compression
Table 8. Envelope Delay Distortion
Parameter Symbol Test Conditions Min Typ Max Unit
TX Delay, Absolute DXA f = 1600 Hz — 280 300 µs
TX Delay, Relative to 1600 Hz DXR f = 500 Hz—600 Hz
f = 600 Hz—800 Hz
f = 800 Hz—1000 Hz
f = 1000 Hz—1600 Hz
f = 1600 Hz—2600 Hz
f = 2600 Hz—2800 Hz
f = 2800 Hz—3000 Hz
—
—
—
—
—
—
—
—
—
—
—
—
—
—
220
145
75
40
75
105
155
µs
µs
µs
µs
µs
µs
µs
RX Delay, Absolute DRA f = 1600 Hz — 190 200 µs
RX Delay, Relative to 1600 Hz DRR f = 500 Hz—1000 Hz
f = 1000 Hz—1600 Hz
f = 1600 Hz—2600 Hz
f = 2600 Hz—2800 Hz
f = 2800 Hz—3000 Hz
–40
–30
—
—
—
—
—
—
—
—
—
—
90
125
175
µs
µs
µs
µs
µs
Round-trip Delay, Absolute DRTA Any time slot/channel to
any time slot/channel
f = 1600 Hz
— 470 600 µs
1
2
3
4
5
6
7
8
9
123456789
ACCEPTABLE
REGION
FUNDAMENTAL INPUT POWER (dBm)
FUNDAMENTAL OUTPUT POWER (dBm)
8 Lucent Technologies Inc.
Data Sheet
July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Transmission Characteristics (continued)
ac T ransmission Characteristics (continued)
Table 9. Noise
Table 10. Receive Gain Relative to Gain at 1.02 kHz
Table 11. Transmit Gain Relative to Gain at 1.02 kHz
Parameter Symbol Test Conditions Min Typ Max Unit
Transmit Noise,
µ-Law NXC — — — 18 dBrnC0
Input amplifier gain = 20 dB — — 19 dBrnC0
Transmit Noise,
A-Law NXP — — — –68 dBm0p
Receive Noise,
µ-Law NRC PCM code is alternating positive
and negative zero — — 13 dBrnC0
Receive Noise,
A-Law NRP PCM code is A-law positive one — — –75 dBm0p
Noise, Single Frequency,
f = 0 kHz—100 kHz NRS VFXIN = 0 Vrms, measurement at
VFRO, DR = DX— — –53 dBm0
Power Supply Rejection Transmit PSRXVDD = 5.0 Vdc + 100 mVrms:
f = 0 kHz—4 kHz
f = 4 kHz—50 kHz 36
30 —
——
—dB
dB
Power Supply Rejection Receive PSRXPCM code is positive one LSB
VDD = 5.0 Vdc + 100 mVrms:
f = 0 kHz—4 kHz
f = 4 kHz—25 kHz
f = 25 kHz—50 kHz
36
40
30
—
—
—
—
—
—
dB
dB
dB
Spurious Out-of-band Signals at
VFRO Relative to Input SOS 0 dBm0, 300 Hz—3400 Hz input
PCM code applied:
4600 Hz—7600 Hz
7600 Hz—8400 Hz
8400 Hz—50 kHz
—
—
—
—
—
—
–30
–40
–30
dB
dB
dB
Frequency (Hz) Min Typ Max Unit
Below 3000 –0.150 ±0.04 0.150 dB
3140 –0.570 ±0.04 0.150 dB
3380 –0.735 –0.58 0.010 dB
3860 — –10.7 –9.4 dB
4600 and above — — –28 dB
Frequency (Hz) Min Typ Max Unit
16.67 — –35 –30 dB
40 — –34 –26 dB
50 — –36 –30 dB
60 — –50 –30 dB
200 –1.8 –0.5 0 dB
300 to 3000 –0.150 ±0.04 0.150 dB
3140 –0.570 ±0.04 0.150 dB
3380 –0.735 –0.58 0.010 dB
3860 — –10.7 –9.4 dB
4600 and above — — –32 dB
Lucent Technologies Inc. 9
Data Sheet
July 1998 T8502 and T8503 Dual PCM Codecs with Filters
Transmission Characteristics (continued)
ac T ransmission Characteristics (continued)
Table 12. Interchannel Crosstalk (Between Channels) RF = ≤ 200 kΩ (See Note.)
Table 13. Intrachannel Crosstalk (Within Channels) RF = ≤ 200 kΩ (See Note.)
Note: F or Tables 12 and 13, crosstalk into the tr ansmit channels (VFXIN) can be significantly affected by par asitic
capacitive feeds from GSX and VFRO outputs. PWB layouts should be arranged to keep these parasitics
low. The resistor value of RF (from GSX to VFXIN) should also be kept as lo w as possib le (while maintaining
the load on GSX above 10 kΩ, per Table 4) to minimize crosstalk.
Parameter Symbol Test Conditions Min Typ Max Unit
Transmit to Receive
Crosstalk 0 dBm0
Transmit Levels
CTXX-RY f = 300 Hz—3400 Hz
idle PCM code for channel under test;
0 dBm0 into other channel VFXIN
— –100 –77 dB
Receive to Transmit
Crosstalk 0 dBm0
Receive Levels
CTRX-XY f = 300 Hz—3400 Hz
VFXIN = 0 Vrms for channel under test;
0 dBm0 code level on other channel DR
— –92 –77 dB
Transmit to Trans-
mit Crosstalk
0 dBm0 Transmit
Levels
CTXX-XY f = 300 Hz—3400 Hz
VFXIN = 0 Vrms for channel under test;
0 dBm0 into other channel VFXIN
— –90 –77 dB
Receive to Receive
Crosstalk 0 dBm0
Receive Levels
CTRX-RY f = 300 Hz—3400 Hz
idle PCM code for channel under test;
0 dBm0 code level on other channel DR
— –102 –77 dB
Parameter Symbol Test Conditions Min Typ Max Unit
Transmit to Receive
Crosstalk 0 dBm0
Transmit Levels
CTXX-RX f = 300 Hz—3400 Hz
idle PCM code for channel under test;
0 dBm0 into VFXIN
— –80 –70 dB
Receive to Transmit
Crosstalk 0 dBm0
Receive Levels
CTRX-XX f = 300 Hz—3400 Hz
VFXIN = 0 Vrms for channel under test;
0 dBm0 code level on DR
— –88 –70 dB
10 Lucent Technologies Inc.
Data Sheet
July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Timing Characteristics
Table 14. Clock Section (See Figures 5 and 6.)
T able 15. T8502 T ransmit Section (See Figure 5.)
* Timing parameter tMCLDZ is referenced to a high-impedance state.
T able 16. T8503 T ransmit Section (See Figure 6.)
* Timing parameter tMCHDZ is referenced to a high-impedance state.
Table 17. T8502 and T8503 Receive Section (See Figures 5 and 6.)
Symbol Parameter Test Conditions Min Typ Max Unit
tMCHMCL1 Clock Pulse Width — 97 — — ns
tMCH1MCH2
tMCL2MCL1 Clock Rise and
Fall Time — 0 — 15 ns
Symbol Parameter Test Conditions Min Typ Max Unit
tMCHDV Data Enabled on TS Entry 0 < CLOAD < 100 pF 0 — 60 ns
tMCHDV1 Data Delay from MC 0 < CLOAD < 100 pF 0 — 60 ns
tMCLDZ* Data Float on TS Exit CLOAD = 0 10 — 100 ns
tFSHMCL Frame-sync Hold Time — 50 — — ns
tMCLFSH Frame-sync High Setup — 50 — — ns
tFSLMCL Frame-sync Low Setup — 50 — — ns
tFSHFSL Frame-sync Pulse Width — 0.1 — 125 – tMCHMCH µs
Symbol Parameter Test Conditions Min Typ Max Unit
tFSHDV Data Enabled on TS Entry 0 < CLOAD < 100 pF 0 — 80 ns
tMCHDV1 Data Delay from FSX0 < CLOAD < 100 pF 0 — 60 ns
tMCHDZ* Data Float on TS Exit CLOAD = 0 0 — 30 ns
tFSHMCL Frame-sync Hold Time — 50 — — ns
tMCLFSH Frame-sync High Setup — 50 — — ns
tFSLMCL Frame-sync Low Setup — 50 — — ns
tFSHFSL Frame-sync Pulse Width — 0.1 — 125 – tMCHMCH µs
Symbol Parameter Test Conditions Min Typ Max Unit
tDVMCL Receive Data Setup — 30 — — ns
tMCLDV Receive Data Hold — 15 — — ns
Lucent Technologies Inc. 11
Data Sheet
July 1998 T8502 and T8503 Dual PCM Codecs with Filters
Timing Characteristics (continued)
5-3581.I(C)
Note: FSX and FSR do not need to be coincident.
Figure 5. T8502 Transmit and Receive Timing
5-3581.R(C)
Note: FSX and FSR do not need to be coincident.
Figure 6. T8503 Transmit and Receive Timing
MCLK
FS
X
N
Dx
FS
R
N
TIME SLOT
12345678 1
tFSLMCL
tMCH1MCH2
tFSLMCL
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
tMCHDV tMCLDZ
D
R
tDVMCL
BIT
1BIT
2BIT
3BIT
4BIT
5BIT
6BIT
7BIT
8
tMCLDV
D
R
STABLE
tMCHMCL1
tMCHDV1
tMCL2MCL1
tFSHMCL
tMCLFSH
tFSHFSL
MCLK
FSXN
DX
FSRN
tFSHMCL
TIME SLOT
1234567 8 1
tFSLMCL
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
tFSHDV tMCHDZ
DR
tDVMCL
BIT
1BIT
2BIT
3BIT
4BIT
5BIT
6BIT
7BIT
8
tMCLDV
DR
STABLE
tMCHMCL1
tMCHDV1
tMCL2MCL1
tMCH1MCH2
tFSLMCL
tFSHFSL
tMCLFSH
12 Lucent Technologies Inc.
Data Sheet
July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Applications
5-3584.d
Figure 7. T ypical T8502 and T8503/SLIC Interconnection
VTR
ACIN
SLIC
0.1 µF
0.1 µF
RG
RF
ZHBZT1
ZT2
ZRCV
GSXn
VFXINn
VFROn
T8502
T8503
Lucent Technologies Inc. 13
Data Sheet
July 1998 T8502 and T8503 Dual PCM Codecs with Filters
Outline Diagrams
20-Pin SOJ
Dimensions are in millimeters.
5-4413 (C)r4
Number
of Pins
(N)
Maximum Length
(L)
Maximum Width
Without Leads
(B)
Maximum Width
Including Leads
(W)
Maximum Height
Above Board
(H)
20 12.95 7.62 8.81 3.18
N
1
PIN #1 IDENTIFIER ZONE
0.51 MAX 0.79 MAX
0.10
SEATING PLANE
1.27 TYP
H
W
B
L
14 Lucent Technologies Inc.
Data Sheet
July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Outline Diagrams (continued)
20-Pin SOG
Dimensions are in millimeters.
5-4414 (C)r.4
Number
of Pins
(N)
Maximum Length
(L)
Maximum Width
Without Leads
(B)
Maximum Width
Including Leads
(W)
Maximum Height
Above Board
(H)
20 13.00 7.62 10.64 2.67
W
0.61
0.51 MAX
H
0.28 MAX
0.10
SEATING PLANE
1.27 TYP
N
L
B
1
PIN #1 IDENTIFIER ZONE
Lucent Technologies Inc. 15
Data Sheet
July 1998 T8502 and T8503 Dual PCM Codecs with Filters
Ordering Information
Note: All parts are shipped in dry bag.
Device Part No. Package Temperature Comcode
T-8502 - - EL2-D 20-Pin SOJ –40 °C to +85 °C 108295908
T-8502 - - EL2-DT 20-Pin SOJ Tape & Reel –40 °C to +85 °C 108295916
T-8502 - - GL2-D 20-Pin SOG –40 °C to +85 °C 108295924
T-8502 - - GL2-DT 20-Pin SOG Tape & Reel –40 °C to +85 °C 108295932
T-8503 - - EL2-D 20-Pin SOJ –40 °C to +85 °C 108295940
T-8503 - - EL2-DT 20-Pin SOJ Tape & Reel –40 °C to +85 °C 108295957
T-8503 - - GL2-D 20-Pin SOG –40 °C to +85 °C 108295965
T-8503 - - GL2-DT 20-Pin SOG Tape & Reel –40 °C to +85 °C 108295973
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information.
Copyright © 1998 Lucent Technologies Inc.
All Rights Reserved
July 1998
DS98-342ALC (Replaces DS97-205ALC)
For additional information, contact your Microelectronics Group Account Manager or the following:
INTERNET: http://www.lucent.com/micro
E-MAIL: docmaster@micro.lucent.com
N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA PACIFIC:Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
Tel. (65) 778 8833, FAX (65) 777 7495
CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road,
Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652
JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148
Technical Inquiries:GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Bracknell),
FRANCE: (33) 1 48 83 68 00 (Paris), SWEDEN: (46) 8 600 7070 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki),
ITALY: (39) 2 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
