MM74HC74AMX_NL - Fairchild Semiconductor

September 1983

Revised January 2005

MM74HC74A Dual D-Type Flip-Flop wit h Preset and Clear

MM74HC74A

Dual D-Type Flip-Fl op wit h Preset and Clear

General Description

The MM74HC74A utilizes advanced silicon-gate CMOS

technology to achieve operating speeds similar to the

equivalen t LS-T TL par t. It possesse s the high no ise imm u-

nity and low power consumption of standard CMOS inte-

grated circuits, along with the ability to drive 10 LS-TTL

loads.

This flip-flop has independent data, preset, clear, and clock

inputs and Q and Q outputs. The logic level present at the

data input is transferred to the output during the positive-

going transition of the clock pulse. Preset and clear are

indepen dent of the clock a nd accomplished b y a low level

at the appropriate input.

The 74HC logic family is functionally and pinout compatible

with the standard 74LS logic family . All inputs are protected

from damage due to static discharge by internal diode

clamps to VCC and ground.

Features

■Typical propagation delay: 20 ns

■Wide power supply range: 2–6V

■Low quiescent current: 40 µA maximum ( 74HC S erie s)

■Low input current: 1 µA maximum

■Fanout of 10 LS-TTL loads

Ordering Code:

Devices also available in Tape and R eel. Speci fy by append ing the suffix let t er “X” to the ordering code.

Pb-F ree packag e per JEDE C J- ST D -020 B.

Connection Diagram

Pin Assignments for DIP, SOIC, SOP and TSSOP

Truth Table

Note: Q0 = the level of Q before the indicated input conditions were estab-

lished.

Note 1: This configuration is nonstable; that is, it will not persist when pre-

set and clear inputs return to their inactive (HIGH) level.

Order Number Package Package Description

Number

MM74HC74AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

MM74HC74AMX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

MM74HC74ASJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC74AMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HC74AMTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

MM74HC74AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Inputs Outputs

PR CLR CLK D Q Q

LHXX H L

HL XX L H

L L X X H (Note 1) H (Note 1)

HH ↑HH L

HH ↑LL H

HH LX Q0 Q

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MM74HC74A

Logic Diagram

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MM74HC74A

Absolute Maximum Ratings(Note 2)

(Note 3) Recommended Operating

Conditions

Note 2: Absolute Maximum Ratings are those values beyond which dam-

age to the device may occur.

Note 3: Unless otherwise specified all voltages are referenced to ground.

Note 4: Power Dis sipation te mperature d erating — plas tic “N” package: −

12 mW/°C from 65°C to 85°C.

DC Electrical Characteristics (Note 5)

Note 5: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occ ur for HC at 4.5V. Thus the 4. 5V valu es shou ld be u sed when

designi ng with t his s upply. Worst c as e VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-

rent (IIN, ICC, and IOZ) occur fo r C M OS at the h igher vol ta ge and so th e 6. 0V values s hould be used.

Supply Voltage (VCC)−0.5 to +7.0V

DC Input Voltage (VIN)−1.5 to VCC +1.5V

DC Output Voltage (VOUT)−0 .5 to VCC +0.5V

Clamp Diode Current (IIK, IOK)±20 mA

DC Output Current, per pin (IOUT)±25 mA

DC VCC or GND Current, per pin

(ICC)±50 mA

Storage Temperature Range (TSTG)−65°C to +150°C

Power Dissipation (PD)

(Note 4) 600 mW

S.O. Package onl y 500 mW

Lead Temperature (TL)

(Solder i ng 10 seco nds) 260°C

Min Max Units

Supply Voltage (VCC)26V

DC Input or Output Voltage 0 VCC V

(VIN, OUT)

Operating Temperature Range (TA)−40 +85 °C

Input Rise or Fall Times

(tr, tf) VCC = 2.0V 1000 ns

CC = 4.5V 500 ns

VCC = 6.0V 400 ns

Symbol Parameter Conditions VCC TA = 25°CT

A = −40 to 85°CT

A = −55 to 125°CUnits

Typ Guaranteed Limits

VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 V

Input Voltage 4.5V 3.15 3.15 3.15 V

6.0V 4.2 4.2 4.2 V

VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 V

Input Voltage 4.5V 1.35 1.35 1.35 V

6.0V 1.8 1.8 1.8 V

VOH Minimum HIGH Level VIN = VIH or VIL

Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V

4.5V 4.5 4.4 4.4 4.4 V

6.0V 6.0 5.9 5.9 5.9 V

VIN = VIH or VIL

|IOUT| ≤ 4.0 mA 4.5V 4.3 3.98 3.84 3.7 V

|IOUT| ≤ 5.2 mA 6.0V 5.2 5.48 5.34 5.2 V

VOL Maximum LOW Level VIN = VIH or VIL

Output Voltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V

4.5V 0 0.1 0.1 0.1 V

6.0V 0 0.1 0.1 0.1 V

VIN = VIH or VIL

|IOUT| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V

|IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V

IIN Maximum Input VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA

Current

ICC Maximum Quiescent VI N =VCC or GND 6.0V 4.0 40 80 µA

Supply Curre nt IOUT = 0 µA

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MM74HC74A

AC Electrical Characteristics

VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns

AC Electrical Characteristics

CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)

Note 6: CPD determines the no load dynam ic pow er cons um ption, PD = CPD VCC2 f + ICC VCC, and the no load dynam ic c urrent consump t ion,

IS = CPD VCC f + ICC.

Symbol Parameter Conditions Typ Guaranteed Units

Limit

fMAX Maximum Operating Frequency 72 30 MHz

tPHL, tPLH Maximum Propagation 10 30 ns

Delay Clock to Q or Q

tPHL, tPLH Maximum Propagation 17 40 ns

Delay Preset or Clear to Q or Q

tREM Minimum Removal Time, 6 5 ns

Preset or Clear to Clock

tsMinimum Setup Time 10 20 ns

Data to Clock

tHMinimum Hold Time 0 0 ns

Clock to Data

tWMinimum Pulse Width 8 16 ns

Clock, Preset or Clear

Symbol Parameter Conditions VCC TA = 25°CT

A = −40 to 85°CT

A = −55 to 125°CUnits

Typ Guaranteed Limits

fMAX Maximum Operating 2.0V 22 6 5 4 MHz

Frequency 4.5V 72 30 24 20 MHz

6.0V 94 35 28 24 MHz

tPHL, tPLH Maximum Propagation 2.0V 34 110 140 165 ns

Delay Clock to Q or Q 4.5V 12 22 28 33 ns

6.0V 10 19 24 28 ns

tPHL, tPLH Maximum Propagation 2.0V 66 150 190 225 ns

Delay Preset or Clear 4.5V 20 30 38 45 ns

To Q or Q 6.0V 16 26 33 38 ns

tREM Minimum Removal Time 2.0V 20 50 65 75 ns

Preset or Clear 4.5V 6 10 13 15 ns

To Clock 6.0V 5 9 11 13 ns

tsMinimum Setup Time 2.0V 35 80 100 120 ns

Data to Clock 4.5V 10 16 20 24 ns

6.0V 8 14 17 20 ns

tHMini mum Hold Time 2.0V 0 0 0 ns

Clock to Data 4.5V 0 0 0 ns

6.0V 0 0 0 ns

tWMinimum, Pulse Width 2.0V 30 80 101 119 ns

Clock, Preset or Clear 4.5V 9 16 20 24 ns

6.0V 8 14 17 20 ns

tTLH, tTHL Maximum Output 2.0V 25 75 95 110 ns

Rise and Fall Time 4.5V 7 15 19 22 ns

6.0V 6 13 16 19 ns

tr, tfMaximum Input Rise 2.0V 1000 1000 1000 ns

and Fall Time 4.5V 500 500 500 ns

6.0V 400 400 400 ns

CPD Power Dissipation (per flip-flop) 80 pF

Capacitance (Note 6)

CIN Maximum Input 5 10 10 10 pF

Capacitance

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MM74HC74A

Physical Dim ensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M14A

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MM74HC74A

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

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MM74HC74A

Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)

14-Lea d Th in S hri n k Small Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC14

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MM74HC74A Dual D-Type Flip-Flop wit h Preset and Clear

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N14A

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

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to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

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user.

2. A critical compon ent i n any compon ent of a lif e support

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device or system, or to affect its safety or effectiveness.