PF1227-01 S1X50000 Series S1X50000 Series High Speed/Low Power Embedded Array 1P SRAM/2P SRAM/Mask ROM mounted Two types available: High-speed type and the low-power-consumption cell type Eight models available with different sizes of SRAM/MaskROM DESCRIPTION S1X50000 is an embedded array product series with a high-speed/high-density SRAM/MaskROM mounted adopting the CMOS 0.35m process. Having a high-speed/high-density SRAM/MaskROM, it will realize the same development time as you need to develop gate arrays after you have finished designing circuits. The Series is available in eight models, which can meet a wide range of application requiring a large-capacity SRAM/MaskROM mounted. The internal gates are rated at 2.0V/3.3V and I/O cell is rated at 2.0V/3.3V/5.0V, respectively, to be compatible with a wider range of power source, so you can use the product with a singlevoltage or two-voltage power source. On top of that, the Series has the output cell with a low noise at a A order. Two types of internal cells are available, that is, the low-power-consumption and high-speed types. You can also utilize the assets of your S1L50000 Series for the high-speed type. FEATURES SRAM/MaskROM mounted (Highly-integrated Sync. 1P SRAM, high-speed Sync. 1P SRAM, high-speed Sync. 2P SRAM, MaskROM) High-speed type (Internal gates' delay: 0.14ns standard at 3.3V. Power consumption: 0.70W/MHz/BC) Low-power-consumption type (Internal gates' delay: 0.14ns standard at 3.3V. Power consumption: 0.39W/MHz/BC) Selectable power voltage (2.0V/3.3V single, or mixed 2.0V/3.3V or 3.3V/5.5V) High driving capacity (IOL=1, 2, 6, 12mA at 3.3V) Various soft macros mountable (USB 1.1, IrDA, PLL, Peripheral, etc.) LINE-UP Series name S1X50000Series Model name S1X55033 S1X55053 S1X55083 S1X55103 S1X55163 S1X55173 S1X55214 S1X55343 Number of gates mounted 62K 80K 87K 162K 47K 29K 132K 66K Number of gates available 24K 32K 70K 114K 18K 24K 80K 26K AL layer 3 3 3 3 3 3 4 3 Cell type Low power consumption Low power consumption High speed High speed Low power consumption High speed Low power consumption Low power consumption Number of pads 128 128 188 144 128 144 128 128 Built-in 1P SRAM's capacity 640Kbit - 64Kbit 1Mbit 256Kbit 256Kbit 640Kbit 644Kbit macro 2P SRAM's capacity - 32Kbit - - - - - - MaskROM's capacity - - - - 128Kbit - - - The libraries for the high-speed type and the low-power-consumption type cells are different. If you want them, please tell which type you want to our sales. Rev. 0.8 1 S1X50000 Series CONFIGURATION OF THE MEMORY MOUNTED The configuration of the SRAM/MaksROMs mounted on each model is as follows (words x bit width x chips): S1X55033 S1X55053 S1X55083 S1X55103 S1X55163 S1X55173 S1X55214 S1X55343 High-density Sync. 1P SRAM 16Kword x 8bit x 4pcs 8Kword x 8bit x 2pcs - - 4Kword x 16bit x 12pcs 4Kword x 8bit x 8pcs 32Kword x 8bit x 1pcs 16Kword x 8bit x 2pcs 8Kword x 8bit x 2pcs 16Kword x 8bit x 4pcs 16Kword x 8bit x 4pcs 4Kword x 8bit x 4pcs High-speed Sync. 1P SRAM High-speed Sync. 2P SRAM Sync.MaskROM - - - - 2Kword x 8bit x 4pcs - - - - - - 256word x 18bit x 1pcs - 512word x 32bit x 2pcs - - - - - - - - - - - - - 16Kword x 8bit x 1pcs - - - - - Comparison of the High-density Sync. 1P SRAM and the High-speed Sync. 1P SRAM (-40 to 85C, 3.3V0.3V, memory configuration: 8Kword x 8bit) High-speed Sync. 1P SRAM High-density Sync. 1P SRAM Rate of integration *1 1 0.8 Operating frequency 90MHz(Max.) 76MHz(Max.) Power consumption 100A/MHz(Typ.) 160A/MHz(Typ.) *1: The rate calculated assuming that that the area occupied by the high-speed Sync. 1P SRAM is 1. PACKAGE LINE-UP The table below shows the line-up of the packages the S1X50000 Series supports. For other packages, please contact our Sales. Model S1X55033 S1X55053 S1X55083 S1X55103 S1X55163 S1X55173 S1X55214 S1X55343 Compatible package QFP14-80 QFP15-128 QFP5-80,100,128/QFP8-128,160,208/QFP14-80 QFP15-100,128/QFP20-144/QFP21-176 TQFP15-100,128 - (QFP17-144) - QFP5-80,100,128/QFP8-128,208/QFP14-80 QFP15-100,128/QFP20-144/QFP21-176 TQFP15-100,128 QFP20-184 TQFP15-100 As of May 31, 2001 More packages will be added as they become ready. 2 Rev. 0.8 S1X50000 Series SOFT MACRO CELLS Like S1L50000 Series, the S1X50000 Series allows you to mount a soft macro on it. The soft macro is mounted on the usable BCs of the Series. However, you can not mount the soft macro for the low-power-consumptiontype cell on the embedded array which uses a cell with the usable gates of the high-speed type, and vice versa. Please use the soft macro which uses the same type of the cell as the internal cell. I/O buffer Peripheral * DMA (EIF37) Interface/LCDC Variable output/Low noise/High speed/PCI/Proof voltage: 5V/Gated control * USB1.1FC * RTC (EIF42) * IrDA1.1 * USART (EIF51) * SS * Programable general-purpose timer (EIF54) * S1D13501(LCDC) * I/O port (EIF55) * Interruption controller (EIF59) * UART + FIFO (EIF65) I/O cell * S1D13502(LCDC) Internal cell (available gates) PLL G/A SRAM Connected SRAM * PLL for multiplication (*1) * Asynchronous 1-port SRAM or * Asynchronous 2-port SRAM mounted FlashROM * PLL for phase adjestment (*1) (*2) (*1) Under consideration (*2) Under development The PLL has some difference in the way to secure the mounting area from other soft macros. If you want it built-in, please contact our Sales. Rev. 0.8 3 S1X50000 Series NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. (c) Seiko Epson Corporation 2001, All rights reserved. All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. ELECTRONIC DEVICES MARKETING DIVISION IC Marketing & Engineering Group ED International Marketing Department Europe & U.S.A 421-8 Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: 042-587-5812 FAX: 042-587-5564 EPSON Electronic Devices Website http://www.epson.co.jp/device/ ED International Marketing Department Asia 421-8 Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: 042-587-5814 FAX: 042-587-5110 This manual was made with recycle paper, and printed using soy-based inks. 4 First issue July, 2001 Printed in Japan H Rev. 0.8