19-0030, Rev 0; 9/92 MA AAIM 500ksps, 12-Bit ADCs with Track/Hold and Reference General Description The MAX120 and MAX122 complete, BICMOS, sampling 12-bit analog-to-digital converters (ADCs) combine an on- chip track/nold (T/H) and a low-drift voltage reference with fast conversion speeds and low power consumption. The T/H's 350ns acquisition time combined with the MAX120's 1.618 conversion time results in throughput rates as high as 500k samples per second (ksps). Throughput rates of 333ksps are possible with the 2.6us conversion time of the MAX1 22. The MAX120/MAX122 accept analog input voltages from -5V to +5V. The only external components needed are decoupling capacitors for the power-supply and refer- ence voltages. The MAX120 operates with clocks in the 0.1MHz to 8MHz frequency range. The MAX122 accepts 0.1MHz to 5MHz clock frequencies The MAX120/MAX122 employ a standard microproces- sor (uP) interface. Three-state data outputs are config- ured to operate with 12-bit data buses. Data-access and bus-release timing specifications are compatible with most popular pPs without resorting to wait states. In addition, the MAX120/MAX122 can interface directly to a first in, first out (FIFO) buffer, virtually eliminating pP interrupt overhead. All logic inputs and outputs are TTLICMOS compatible. For applications requiring a serial interface, refer to the new MAx121. Applications Digital-Signal Processing Audio and Telecom Processing Speech Recognition and Synthesis High-Speed Data Acquisition Spectrum Analysis Data Logging Systems Pin Configuration Features @ 12-Bit Resolution @ No Missing Codes Over Temperature @ 20ppm/C -5V Internal Reference # 1.6us Conversion Time/S00ksps Throughput (MAX120) @ 2.6us Conversion Time/333ksps Throughput (MAX122) @ Low Noise and Distortion: 70 dB Min SINAD; -77 dB Max THD (MAX122) @ Low Power Dissipation: 210mW @ Separate Track/Hold Control Input @ Continuous-Conversion Mode Available @ +5V Input Range, Overvoltage Tolerant to +15V @ 24-Pin Narrow DIP, Wide SO and SSOP Packages Ordering Information | PART TEMP.RANGE F \CKAGE (LSBs) MAXI20CNG O0Cto+70C 24Narrow Plasic DIP #1 MAX120CWG OC t0+70C 24Wide SO + MAX120CAG OC to+70C 24SSO0P +4 MAX1200C/D. OC lo +70C. Dice +4 MAX420ENG -A0 Cto +85 C 24 Narrow Plastic DIP 44 | MAX120EWG -40. C10 +85 C24 Wide SO HH Ordering Information continued on last page. Contact factory for dice specifications Functional Diagram A + . Vu: | 3% SAMPLING AIN + 4K + BUFFER COMPARATOR nen TRACKHOLD [oO . me | UGND | 3k > 5 fob! | 4 | : Mes, bv S AnaAximn VREF | * CAC > MAN'120 | MAX 122 | s ' | san ft | \, REI ERENCE un S LATCH AND J | - I THREE STATE BUSY OUTPUT BUFFERS , INTBUSY contROI 1ocie | \ | - bb I. TOP VIEW St. _ MODE L 2a] RO vss [2] Eames Von 3 [22] INI/BUSY AIN pa) MAAXIAATS) cin 4 MAX120 a VREF Ls] jyayyo2 feo. CONVST AGND 6 19) 00 Dit | ee] D1 p10 fe] iz 02 D9 sg fie] 03 D8 10 fis] D4 D? fs fa D5 UGND 72 | 13] D6 DIP/SO/SSOP MAXIM Maxim Integrated Products 1 Call toll free 1-800-998-8800 for free samples or literature. 2oLXVIN/OCLXVINMAX120/MAX1 22 500ksps,12-Bit ADCs with Track/Hold and Reference ABSOLUTE MAXIMUM RATINGS Yop to DGND .., -0.3V to +6V Operating Temperature Ranges Vss to DGND Le ne +0.3V to-17V MAX12_C__ OC la+70C AINtoAGND ...... . Lee +15V MAX12_E__ -40 C to +85 C AGNDtoDGND ......... +0.3V MAX12_MRG : +55 Cto4+125C Digital Inputs/Outputs to DGND . . 0 3V to (Vpn + 0.3V} Storage Temperature Range -65 C to +160 C Continuous Power Dissipation (Ta = +70C) Lead Temperature (soldering, 10 sec) +300 C Narrow Plastic DIP (derate 13.33mW/'C above +70C) 1067mMW SO (derate 11.76mMW/'C above +70C) woe... 941mW SSOP (derate 8.00mW/'C above +70C) 640mw Narrow CERDIP (derate 12.50W/"C above +70C) 1000mW Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only. and luncte operation of the device at these or any other condilions beyond those indicated in the operational sections of the specifications is nol implied f xpos: absolute maximum rating conditions for extended periods may aflect device reliability ELECTRICAL CHARACTERISTICS (VoD = +4.75V to +5.25V. Vss = -10.8V to -15.75V, feLk = 8MHz for MAX120 and S5MHz for MAX122, TA TMIN lo T MAX, unless otherwise noted. cd) |. PARAMETER s|[SYMBOL|_SCCONDDITIONS__ | MIN TYP MAX | UNITS [ACCURACY ee / _ Resolution _ RES | a a a 12 Bits | "Maxi22aciae | +3/4 | 12-bit no missing : ' | codes over temp. range | MAX120C/E, ; | Differential Nonlinearity (Note 1) DNL | MAX 122BC/BE/BM | ~ LSB 11-bit no missing , re | _Codes over temp. range MAX 120M te | | MAX122AC/AE | 43/4 Integral Nonlinearity (Note 1) | INL MAX 120C/E, +1 | | SB MAX 122BC/BE/BM | | MAX120M +2 | | Code 00 00.00 to 00..01 transition, near AIN = OV +3 LSB Bipolar Zero Error (Note 1) _ { . | Temperature drift +0005 LSB/C | Including reference: adjusted sd for bipolar zero Full-Scale Error (Notes 1. 2) [ error Ta = 425C | +8 LSB [Full Scale ale Temperature Drift eDritt Excluding reference +i | ppm/ C | Vob only. 5V +5% +1/4 3/4 (Change in FS, Note 3) | Fower-Supply Rejection Ratio PSRR_ | Vss only, -12V 410% +14 #1 LSB YL jVssonly.-15V45% | +1/4 +1 | ANALOG INPUT | Input Range {| To | 5 5 Vv Input Current | ain: AIN = +5 (ap (approximately 6k to REF) 25 mA rer Capacitance ( (Note 4 4) | ~ 10 | pk | Full-Power Input Bandwidth | BO - 15 MHe | REFERENCE [OutputVoliage sd Noexternal load, AIN = SV. Ta = +25 C | 5.02 a9! ov | lEwernait Load Regulation _ | OmA <IsiNK < SMA, AIN = OV_ OO 5 | mo + oT MAXI2.C/E , 25 Temperature Drift (Note 5) _ : pony Cc | |" Be |MAX12M _ 4 +30 | 2 MAXIM500ksps, 12-Bit ADCs with Track/Hold and Reference ELECTRICAL CHARACTERISTICS (continued) (VDD = +4.75V to +5.25V, Vss = -10.8V to -15.75V, fcoLk = 8MHz for MAX120 and 5MHz for MAX122, Ta = TMIN to TMAx, unless otherwise noted.) _ PARAMETER [SYMBOL CONDITIONS | MIN TYP MAX] UNITS DYNAMIC PERFORMANCE (MAX120: fs = 500kHz, AIN = +5Vp-p, 100kHz; MAX122: fg = 333kHz, AIN = +5Vp-p, SOkHz Ta = 425C MAX120. MAX122 70 72 ' Signal-to-Noise Plus Distortion SINAD MAX122AC/AE 70 dB MAX122BC/BE/BM 69 MAX120 -82 77 TA = +25C me : Total Harmonic Distortion _ MAX122 __ 85 78 : THD Te dB (First Five Harmonics) MAX122AC/AE 77 _ MAX122BC/BE/BM 75 MAX120 77 82 TA = +25C - ____. MAX122 78 85 Spurious-Free Dynamic Range SFDR me dB MAX 122AC/AE 77 MAX122BC/BE/BM 15 CONVERSION TIME ; MAX120 1.63 Synchronous tCONV 13tCLK - us | MAX122 2.60 MAX120 0.1 8 Clock Frequency fCLK MH? _ | MAX122 0.1 5 DIGITAL INPUTS (CLKIN, CONVST, RD, CS) _ Input High Voltage VIH _ - 2.4 Vv Input Low Voltage VIL ; - 08 Vv Input Capacitance (Note 4) 10 pF nn SS : * Input Current : VIN = OV or VoD ee | +5 WA DIGITAL OUTPUTS (INT/BUSY, D11-Do) ee Output Low Voltage VOL ISINK = 1.6mA a 0.4 Vv Output High Voltage VOH ISOURCE = IMA ee Vob - 0.5 Vv | Leakage Current ILKG | VIN = OV oF Vp. D11-D0 +o WA Output Capacitance (Note 4) ; __ 10 pF POWER REQUIREMENTS a Positive Supply Voltage VoD Guaranteed by supply rejection test 475 5.25 Vv Negative Supply Voltage Vss Guaranteed by supply rejection test -10.80 -15.75 V Positive Supply Current (Note 6) iDD Vopb = 5.25V, Vss = -15.75V, AIN = OV / 9 15 mA Negative Supply Current (Note 6) Iss Vpp = 5.25V, Vss = -15.75V. AIN = OV 14 20 mA - { Power Dissipation (Note 6) Vpb = 5V. Vssg = -12V, AIN = OV 210 315 mw Note 1: These tests are performed at VoD = 5V, Vss = -15V. Operation over supply is guaranteed by supply rejection tests Note 2: ideal full-scale transition is at +5V - 3/2LSB = +4.9963V. adjusted for offset error Note 3: Supply rejection defined as change in full-scale transition voltage with the specified change in supply voltage - (FS at nominal supply) - (FS at nominal supply + tolerance), expressed in LSBs. Note 4: For design guidance only, not tested. Note 5: Temperature drift is defined as the change in output voltage from +25C to Twin or Tmax. It is calculated as TC = (AVREE/VREF)(AT) Note 6: CS = RD = CONVST = OV, MODE = 5V MMAAIMI 3 coLXVIN/OC LXVINMAX1 20/MAX 122 500ksps, 12-Bit ADCs with Track/Hold and Reference TIMING CHARACTERISTICS (Vpp = +5V. Vss = -12V to -15V, 100% tested, TA = Tun to TMAX, unless otherwise noted.) (Note 7) ee a a |. | Ta=+25C | MAX12_ C/E MAX12_M PARAMETER SYMBOL | CONDITIONS | | UNITS | | MIN TYP MAX | MIN TYP MAX | MIN TYP MAX CS to RD Setup Time tcs lo 0 | 0 Ions CS to RD Hold Time | ton [? 0 | 0 ions | | CONVST Pulse Width of ew 30 | 30 | ns | RD Pulse Width tRW tba | {DA tba ns - - | Data-Access Time 7 OP {DA {* = 100pF i 40 75 100 120 ns | Bus- Relinguish Time | tbH | 30 50 t 65 | 80 | ons RD or CONVST lo BUSY | tBo Cy = 50pF 30 75 100 | 120 ns CLKIN to BUSY or INT {B14 CL = 500F 70 110 | mee 180 ns __ : . CLKIN to BUSY Low | tB2 | In mode 5 | 45 90 120 150 | ons | RD to INT High | ti | CL = 50pF | 30 50 75 | 90 | ns CL (Data) = | | 100pF. ; | BUSY or INT to Data Valid | BD Gg (Nt BUSY) | 20 | 30 35 ons = 50pF | | Acquisition Time (Note 8) | taQ 350 | 350 400 | ns Aperture Delay (Note 8) | LAP | | 10 ns _ | | A t Jitter (Note 8 30 S perture Jitter (Note y iL _ | _ L ; p Note 7: Control inputs specified with tr = tf = 5ns (10% to 90% of +5V) and timed from a 1.6V voltage level. Output delays are measured to +0.8V if going low. or +2.4V if going high. For bus- relinquish time. a change of 0.5V is measured. See figures 1 and 2 for load circuits. Note 8: For design guidance only. not tested. Pin Description PN NAME jo FUNCTION Mode Input - hard-wire to seLoperational mode. Vop: Single conversion, INT Output OPEN: Single conversion, BUSY Output DGND: Continuous conversions, BUSY Output Negative Power Supply. -12V or -15V i { | MODE _ ae L HS Vpb [Postive Power Supply +5V ola AIN [Serine Analog Input. +5V 5V bipolar input range 5 VREF | -5V Reference Output byp bypass to AGND with 2our NO Wr 4 MAXIM500ksps, 12-Bit ADCs with Track/Hold and Reference Pin Description (continued) Clock Input. Drive with TTL-compatible clock from 0. 1IMHz to 8MHz (MAX120), 0.1MHz to SMH2 (MAX 122) Interrupt or Busy Output indicates converter status. If MODE is connected to Vb. configure for an INT output lf MODE is open or connected to DGND, configure for a BUSY output. See operational diagrams Chip Select [nput - active low. When RD is low, enables the three-state outputs. Hf CONVST and RD are low, a Read Input - active low. When CS is low, RD enables the three-state outputs. If CONVST and CS are low, a | _ __ _ PIN NAME | FUNCTION 6 AGND | Analog Ground | {aitg | 011-00 | Three-State Data Outputs D1 1 (MSB) to D0 (LSB) 12 DGND | Digital Ground 20 CONVST | Convert Start Input initiates conversions on its falling edge | 21 | - | | 22 | INT/BUSY 23 L cS conversion 's initiated on the falling edge of CS | 24 | RD ! Detailed Description ADC Operation The MAX120/MAX 122 use successive approximation and input T/H circuitry to convert an analog signal to a series of 12-bit digital-outout codes. The control logic interfaces easily to most uPs, requiring only a few passive compo- nents for most applications. The T/H does not require an external capacitor. Figure 3 snows the MAX120/MAX 122 in the simplest operational configuration. Analog Input Track/Hold Figure 4 shows the equivalent input circuit, illustrating the sampling architecture of the ADC's analog comparator. An internal buffer charges the hold capacitor to minimize the required acquisition time between conversions. The analog input appears as a 6kQ resistor in parallel with a 1OpF capacitor. Between conversions, the buffer input is connected to AIN through the input resistance. When a conversion starts. the buffer input disconnects from AIN, thus sampling the input. At the end of the conversion, the buffer input reconnects to AIN, and the hold capacitor once again charges to the input voltage. The T/His in tracking mode whenever a conversion is NOT in progress. Hold mode starts approximately 10ns after a conversion is initiated. Variation in this delay from one conversion to the next (aperture jitter) is typically 30ps Figures 7 through 11 detail the T/H mode and interface timing for the various interface modes. MAXI convsersion is initiated on the falling edge of RD ON 4 C : Cl ON * | I | DGND DONT a High-Zto Vou (toaj are Ver to Von (lac ob High @ to Ver (had and Vie ta Vi Gea coLXVIN/OCLXVIN Figure 1. Load Circuits for Access Time DN Tt Tt NN ry 3k ~10pt 1 sop s = DGND DGND a. You io Higa-dZ (is) b Vor to High 7 tani Figure 2. Load Circuits for Bus-Relinquish TimeMAX 1 20/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference MAXIAN MAX120 MAX 122 | MODE iD sayeisy 88 SF By Yoo INT/BUSY STATUS OUTPUT ANALOG INPUT | ain CLKIN | CLK INPUT" VREF CONVST 22uF== 0 IRE aye ole AGND bo Td ny 1} ; _. p10 b2 p9 03 - 08 04 | / DF DSF _} veno 06 ) (O.1MHz 6MH? MAX120} 12-BIT DIGITAL OUPUTS (O.1MHe - SMHz MAX122} SAMPLING COMPARATOR Ooo | | _L. ept [0 | . . Crit ; 3k TRACK BUT FER ot AIN @ AAA ~, ms | 6 . | j CPncKaGr 2 HOLD og | Jr Sa 7 | CswiibH VREF + ] VREE (5V) po \ pA SS Z aN. s SAR 7 EL HO Figure 3. MAX120/MAX 122 in the Simplest Operational Mode (Continuous Conversion) Internal Reference The MAX120/MAX122 -5.00V buried-zener reference biases the internal DAC. The reference output is avail- able at the VREF pin and must be bypassed to the AGND pin with a 0.1uF ceramic capacitor in parallel with a 22uF or greater electrolytic capacitor. The elec- trolytic capacitors equivalent series resistance (ESR) must be 100mQ or less to properly compensate the reference output buffer. Sanyos organic semiconduc- tor works well. Sanyo Video Components (USA) Phone: (619) 661-6835 FAX: (619) 661-1055 Sanyo Electric Company, LTD. (Japan) Phone: 0720-70-1005 FAX: 0720-70-1174 Sanyo Fisher Vertrieos GmbH (Germany) Phone: 06102-27041, ext. 44 FAX: 06102-27045 Proper bypassing minimizes reference noise and main- tains a low impedance at high frequencies. The internal reference output buffer can sink up to a 5mA external load. An external reference voltage can be used to overdrive the MAX120/MAX122's internal reference if it ranges from -5.05V to -5.10V and is capable of sinking a minimum of omA. The external VREF bypass capacitors are still re- quired Figure 4. Equivalent input Circuit Digital Interface External Clock The MAX120/MAX1 22 require a TTL-compatible clock for proper operation. The MAX120 accepts clocks in the O.1MHz to 8MHz frequency range when operating in modes 1-4 (see Operating Modes section). The maxi- mum clock frequency is limited to 6MHz when operating in mode 5. The MAX122 requires a 0.1MHz to 5MHz clock for operation in all five modes. The minimum clock frequency for both the MAX120 and MAX122 is limited to 0.1MHz, due to the T/Hs droop rate Clock and Control Synchronization If the clock and convert start inputs (CONVST or RD and CS - see Operating Modes section) are not synchronized, the conversion time can vary from 13 to 14 clock cycles The successive approximation register (SAR) always changes state on the CLKIN input's rising edge. To ensure a fixed conversion time, refer to Figure 5 and the following guidelines. For a conversion time of 13 clock cycles, the convert start input(s) should go low at least 50ns before CLKINs next rising edge. For a conversion time of 14 clock cycles. the convert start input(s) should go low within 10ns_ of CLKIN's next rising edge. If the convert start input(s) go low from 10ns to 50ns before CLKINs next rising edge. the number of clock cycles required is undefined and can be either 13 or 14. For best analog performance, syn- chronize the convert start inputs with the clock input. MAXIM500ksps, 12-Bit ADCs with Track/Hold and Reference CONVST or CS \ Loe CLKIN| | THE TIMING RFI ATIONSHIP BETWEEN CLKIN AND CONVST OR RD DETERMINES IF A CLOCK CYCLE SLIPS OR NOT. USE THE FOLLOWING RULES IF cx < 10ns, CONVERSION TIME - 147 CLOCK EDGES IF tok > 50ns, CONVERSION TIME - 137 CLOCK LDGES IF 10ns tek < 50ns, CONVERSION TIME IS INDETERMINATE {13 OR 14) CLKIN RD -CS INT/BUSY MODE - Von INT/BUSY MODE - OPFN Ten oe thea CNIW LATA) iAP DA bo HOLD! TRACK TRACK HOLD 'Bo HIGH IMPEDANCE DATA OUT - | HOLD iA) bea Figure 5. Clock and Control Synchronization DATA QUT HIGH IMPEDANCE x DATA VALID HIGH IMPEDANCE 011-D0 Figure 6. Data-Access and Bus-Relinquish Timing Output Data Format The conversion result is output on a 12-bit data bus with a 75ns data-access time. The output data format is twos-complement. The three input control signals (CS, RD, and CONVST), the INT/BUSY converter status output, and the 12 bits of output data can interface directly to a 16-bit data bus. See Figure 6 for data-access timing Timing and Control The MAX120/MAX122 have five operational modes as outlined in Figures 7-11 and discussed in the Operating Modes section Full-control mode (mode 1) provides maximum control to the user for convert start and data-read operations. MAAAIMI Figure 7. Full-Control Mode (Mode 1) Full-control mode is for wPs with or without wait-state capability. Stand-alone mode (mode 2) and continu- ous-conversion mode (mode 5) are for systems without uPs, or for uP-based systems where tne ADC and the uP are linked through first in, first out (FIFO) buffers or direct memory access (DMA) ports. Slow-memory mode (mode 3) is intended for uPs that can be forced into a wait state during the ADC's conversion time ROM mode (mode 4) is for uPs that cannot be forced into a wait state. In all five operating modes, the start of a conversion is controlled by one of three digital inputs: CONVST, RD, or CS. Figure 12 shows the logic equivalent for the conversion circuitry. In any operating mode, CONVST must be low for a conversion to occur. Once the conver- sion is in progress, it cannot be restarted. Read operations are controlled by RD and CS. Both of these digital inputs must be low to read output data. The INT/BUSY output indicates the converter's status and determines when the data from the most recent conver- sion is available. The MODE input configures the INT/BUSY output as follows If MODE = Vpp, INT/BUSY functions as an INTER- RUPT output. In this configuration, INT/BUSY goes low when the conversion is complete and returns high after the conversion data has been read If MODE is left open or tied to DGND, INT/BUSY functions as a BUSY output. In this case, INT/BUSY goes low at the start of a conversion and remains low until the conversion is complete and the data is available at DO-D114 Z2oLXVW/OCLXVINMAX 120/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference CONVST VL low CLKIN mee 180 > tet INT/BUSY .- i ;_ igo BL DATA OUT OLD DATA X NEW DATA 011-00 D11-00 am IAP HOLD TRACK __| HOLD Track _| nt tag -- CLKIN \ \ sa aN ef PN fs RD+CS >*~ t _ ~a {ho te ; INT/BUSY oy \. ~ tet : e0 PAL me {Am 1 ee HIGH , HICH PATA OUT rPEDANGE ip \ OLU DATA ANEW DATA yt Sed DW ha D1 DO HOLD , TRACK Track TRACK HOLD Figure 8. Stand-Alone Mode (Mode 2) Initialization After Power-Up On power-up, the first MAX120/MAX122 conversion is valid if the following conditions are met: 1) Allow 14 clock cycles for the internal T/H to enter the track mode, plus a minimum of 350ns in the track mode for the data-acquisition time. 2) Make sure the reference voltage has settled. Allow 0.5ms for each 1nF of reference bypass capaci- tance (11ms for a 22uF capacitor). Operating Modes Mode 1: (Full-Control Mode) Figure 7 shows the timing diagram for full-control mode (mode 1). In this mode, the uP controls the conversion- start and data-read operations independently. A falling edge on CONVST places the T/H into hold mode and starts a conversion in the SAR. The conversion is complete in 13 or 14 clock cycles as discussed in the Clock and Control Synchronization section. A change in the INT/BUSY output state signals the end of a conversion as follows If MODE = Vpp, the end of conversion is signaled by the INT/BUSY output falling edge lf MODE = OPEN or DGND, the INT/BUSY output goes low while the conversion is in progress and returns high when the conversion is complete Figure 9. Slow-Memory Mode (Mode 3) When the conversion is complete, the data can be read without initiating anew conversion by pulling RD and CS low and leaving CONVST high. To start anew conversion without reading data, RD and CS should remain high while CONVST is driven low. To simultaneously read data and initiate a new conversion, CONVST, RD, and CS should all be pulled low. Note: Allow at least 350ns for T/H acquisition time between the end of one conversion and the beginning of the next. Mode 2: Stand-Alone Operation (MODE = OPEN, RD = CS = DGND) For systems that do not use or require full-bus interfacing, the MAX120/MAX122 can be operated in stand-alone mode directly linked to memory through DMA ports or a FIFO buffer. In stand-alone mode. a conversion is initi- ated by a falling edge on CONVST. The data outputs are always enabled; data changes at the end of a conversion as indicated by a rising edge on INT/BUSY. See Figure 8 for stand-alone mode timing. Mode 3: Slow-Memory Mode (CONVST = GND, MODE = OPEN) Taking RD and CS low places the T/H into hold mode and starts a conversion. INT/BUSY remains low while the con- version is in progress and can be used as a wait input to the pP. Data from the previous conversion appears on the data bus until the conversion end is indicated by INT/BUSY See Figure 9 for slow-memory mode timing MAXIM500ksps, 12-Bit ADCs with Track/Hold and Reference CLKIN \ vat . fi 2\./ 12\ iB / \ f- RD CS \ \ | tei INT/BUSY \ tha (DH HIGH i DATA OUT } {OU DATA IMPEDANCE ( NEW DATA 011-D0 HOLD | track [ TRACK so HOLD tar be tag N = BLE DIGIAl x} ~ Joe UIPHIS cs IL. ~ CONVERSION am ,* 7 4 f a Ne SINGLE SHOI | |? ZOMET . / 0 | ADC 4 BUSY SINGLE SHOT Figure 10. ROM Mode (Made 4) oan ov" Ja/1\ MAS fa /1 Ip? | (81 INT/BUSY _ a _ d \ - 180 DATA OUT OLD DATA r NEW DATA ~ HOLD _ __ TRACK HOLD | __TRRR | ouo he - TAG Figure 11. Continuous-Conversion Mode (Mode 5) Mode 4: ROM Mode (MODE = OPEN, CONVST = GND) In ROM mode, the MAX120/MAX122 behave like a fast- access memory location and avoid placing the pP into a wait state. Pulling RD and CS low places the T/H in hold mode, starts a conversion, and reads data from the previous conversion. Data from the first read in a se- quence is often disregarded when this interface mode is used. A second read operation accesses the first conversions result and also starts anew conversion. The time between successive read operations must be longer than the sum of the T/H acquisition time and the MAX120/MAX122 conversion time. See Figure 10 for ROM-mode timing. Mode 5: Continuous-Conversion Mode (CONVST = RD = CS = MODE = GND) For systems that do not use or require full-bus interfacing, the MAX120/MAX122 can operate in continuous-conver- MAXIM Figure 12. Conversion-Control Logic sion mode, directly linked to memory through DMA ports or a FIFO buffer. In this mode, conversions are per- formed continuously at the rate of one conversion for every 14 clock cycles, which includes 2 clock cycles for the T/H acquisition time. To satisfy the 350ns minimum acquisition time requirement within 2 clock cycles, the MAX120's maximum clock frequency is GMHz when op- erating in mode 5. The data outputs are always enabled and "new' data appears on the output bus at the end of a conversion as indicated by the INT/BUSY output rising edge. The MODE input should be hard-wired to GND. Pulling CS, RD, or CONVST high stops conversions. See Figure 11 for continuous-conver- sion mode timing. Applications Information Using FIFO Buffers Using FIFO memory to buffer blocks of data from the MAX120 reduces uP interrupt overhead time by enabling the uP to process data while the MAX120, unassisted, writes conversion results to the FIFO. To retrieve a block of data. the uP reads from the FIFO via a read-interrupt cycle. Read and write oper- ations for the FIFO are completely asynchronous. Figure 13 shows the MAX120 operating in continuous-conversion mode (mode 5), writing data directly into the two |DT7200 256 x 9 FIFO buffers at the rate of 428ksps. The IP is interrupted to read the accumulated data by the FIFOs half-full (HF) flag approxi mately three times per millisecond. For operation at 500ksps, use an 8MHz clock, and pulse CONVST at 500kHz. The full flag (FF) indicates that the FIFO is full. If this flag is ignored, data may be lost. If necessary, conversions can be inhibited by pull- ing CS. RD, or CONVST high. The FIFO's read cycle times are as fast as 15ns, satisfying most system speed requirements. The RESET input resets ail data in the FIFO to zero COLXVIN/OCLXVINMAX120/MAX122 500ksps,12-Bit ADCs with Track/Hold and Reference fo 25 15V vce fuRT = FF > FULL FLAG * 10utF - LOU O4uF Frou XO/HF wm HALF FULL HLAG id = s tt | sm FMPTYILAG Von Vss NS _ _ wmausy}- | i As SI MODE & ea oF _|es MAXUM 1077200 ~~ MAX120 | RO ote. | \ bo go. = RUN/STOP l const bs /loe 08 [>] | | | oo Xi GND | p . 6MHzCLOCK = CLKIN bo }- - | | | *S DATAOUT TO Cp | vier | > rf PROCESSOR 22uk 22 OF | Veco FLIRT i AGND ao, | | | | DGND | ow wl L_ N bo Rm ep RIAD / be #5 le "| RESEI | IDT7200 - | pg7ope | | x) GND | | "iy | Figure 13. Using MAX 120 with FIFO Memory For synchronous operation, the CONVST pin may be used to initiate conversions, as described in the Operat- ing Modes section (Mode 2: Stand-Alone Operation). Digital-Bus Noise if the ADCs data bus is active during a conversion, coupling from the data pins to the AOC comparator can cause errors. Using slow-memory mode (mode 3) avoids this problem by placing the wP in a wait state during the conversion. If the data bus is active during the conver- sion in either mode 1 or 4, use three-state drivers to isolate the bus from the ADC. In ROM mode (mode 4), considerable digital noise is generated in the ADC when RD or CS go high, disabling the output buffers after a conversion is started. This noise can cause errors if it occurs at the same instant the SAR latches a comparator decision. To avoid this problem, RD and CS should be active for less than 1 clock cycle. If this is not possible, RD or CS should go high coinciding with CLKIN's falling edge, since the comparator output is always latched at CLKiN's rising edge 10 Layout, Grounding, and Bypassing For best system performance, use printed circuil boards with separate analog and digital ground planes. Wire- wrap boards are not recommended. The two ground planes should be tied together at the low-impedance power-supply source, as shown in Figure 14 The board layout should ensure that digital and analog signal lines are kept separate from each other as much as possible. Do not run analog and digital (especially clock) lines parallel to one another. The ADC's high-speed comparator is sensitive to high- frequency noise in the VoD and Vss power supplies Bypass these supplies to the analog ground plane with O.1uF and 10uF bypass capacitors. Minimize capacitor lead lengths for best noise rejection. If the +5V power supply is very noisy, connect a 5Q resistor. as shown in Figure 14. Figure 15 shows the negative power-supply (Vgs) rejection vs. frequency. Figure 16 shows the pos- itive power-supply (VDD) rejection vs. frequency, with and without the optional 5Q resistor. MAAIM500ksps, 12-Bit ADCs with Track/Hold and Reference [ DIGITAL | ANALOG SUPPLY SUPPLY i W15V 15V AGND | | +8V DGND | | Aw NN we | ra tele OPTIONAL @*. Le aid | BSE) Sl mig | mee did 15V AGND +5V veh [\5V DGN MANOA? plea CIRCUITRY L | a m T M | PLFILUER bad uo MAX120 te Vin PIN 1 fou) [0 tpt eet tl | | | NO PLFILIER ery 20 t 10k 100k IM FREQUENCY (Hi WITH PI FILTER 50 + sone 40 |_ Va REJECTION (dB) Figure 14. Power-Supply Grounding 60 N 50 Viss REJECTION (dB) 40 | 1 TA- +25 C ol 10k 100k 1M FREQUENCY (He) Figure 15. Vss Power-Supply Rejection vs. Frequency Gain and Offset Adjustment Figure 17 plots the bipolar input/output transfer function for the MAX120/MAX122. Code transitions occur halfway between successive integer LSB values. Output coding is twos-complement binary with 1LSB = 2.44mvV (10V/4096). In applications where gain (full-scale range) adjustment is required, Figure 18s circuit can be used. If both offset and gain (full-scale range) need adjustment, either of the circuits in Figures 19 and 20 can be used. Offset should be adjusted before gain for either of these circuits MAXIWI Figure 16. Von Power-Supply Rejection vs. Frequency To adjust bipolar offset with Figure 19's circuit, apply +1/2LSB (0.61mV) to the noninverting amplifier input and adjust R4 for output-code flicker between 0000 0000 0000 and 0000 0000 0001. For full scale, apply FS - 1/2LSB (2.4988V) to the amplifier input and adjust R2 so the output code flickers between 0111 1111 1110 and 0111 1111 1111. There may be some interaction be- tween these adjustments. The MAX120/MAX122 trans- fer function used in conjunction with Figure 19's circuit is the same as Figure 17, except the full-scale range Is reduced to 2.5V. To adjust bipolar offset with Figure 20's circuit. apply -1/2LSB (-1.22mV) at VIN and adjust R5 for output-code flicker between 0000 0000 0000 and 0000 0000 0001. For gain adjustment, apply -FS + 1/2LSB (-4.9951V) at Vin and adjust R1 so the output code flickers between 0111 11114 1110 and 0111 11111111. As with Figure 20's circuit, the offset and gain adjustments may interact. Figure 21 plots the transfer function for Figure 20's circuit. Dynamic Performance High-speed sampling capability and 500ksps throughput (333ksps for the MAX122) make the MAX120/MAX122 ideal for wideband-signal processing. To support these and other related applications, fast fourier transform (FFT) test techniques are used to guarantee the ADC's dynamic frequency response, distortion, and noise at the rated throughput. Specifically, this involves applying a low-dis- tortion sine wave to the ADC input and recording the digital conversion results for a specified time. The data is then analyzed using an FFT algorithm, which deter- mines its spectral content. 11 coLXVIN/OCLXVINMAX120/MAX122 500ksps,12-Bit ADCs with Track/Hold and Reference 6 oi MN oN O14 nf | 4 (+2.5V 0-2 BV) se, ds = # | : oF 10 An Le eo Rt 000.010 a 150k 000... 001 : 000... 000+ - --- _ -- | Rca AD, NI re | po Sk. (AINADJUSIMA NT it.. 110 LT RB 441... 101 . | Vv 150k sd we , RAS RS 1 ae AN ANA 100... 001 ont YN 100. . 000 51k _ 1802 | (OFFSET ADJUSTMENT} 1S SH TO Vite CAV) -5V ov 4.9975V Figure 17. Bipolar Transfer Function Figure 19. Offset and Gain Adjustment (Noninverting) ' > vk VIN AAA oN NAVI 7 10 OA 5os2 a MAX 120/ Re ve | Ro 10k a MAKI22 1, 2 18x y _ a IN VIN aa y, \ e 1 | a (- Vy to 15V) RL 104 5082 . . O Ain shea (GAINADJUSTMENT) pg: Af iv 680k > S . LOVREL | SY BY ha, ad RS = 20k (OFF ADJUSIMENT} Figure 18. Trim Circuit for Gain Only ADCs have traditionally been evaluated by specifications such as zero and full-scale error, integral nonlinearity (INL), and differential nonlinearity (DNL). Such parame- ters are widely accepted for specifying performance with DC and slowly varying signals, but are less useful in signal processing applications where the ADC's impact on the system transfer function is the main concern. The sig- nificance of various DC errors does not translate well to the dynamic case, so different tests are required. Signal-to-Noise Ratio and Effective Number of Bits The signal-to-noise plus distortion ratio (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to the RMS amplitude of all other ADC output signals. The output bandis limited to frequencies above DC and below one-half the ADC sample rate. 12 Figure 20. Offset and Gain Adjustment (Inverting) The theoretical minimum ADC noise is caused by quan- tization error and is a direct result of the ADC's resolution SNR = (6.02N + 1.76)dB, where N is the number of bits of resolution. A perfect 12-bit ADC can, therefore, do no better than 74dB. An FFT plot snows the output level in various spectral bands. Figure 22 shows the result of sampling a pure 100kHz sinusoid at a S50Q0ksps rate with the MAX120 By transposing the equation that converts resolution to SNR, we can, from the measured SINAD, determine the effective resolution (or effective number of bits) the ADC provides: N = (SINAD - 1.76)/6.02. Figure 22 shows the effective number of bits as a function of the input frequency for the MAX120. The MAX122 performs similarly MAXIM500ksps, 12-Bit ADCs with Track/Hold and Reference S- < oO... 1 ont ne ) | 000. 010 000... 001 l 000... 000 +- - | - oe | W1...1nt id. 110 111 of - | S- wf 100 oo | - 100 000 | CL L_ | Ss s; | -4.9975V ov 15V Figure 21. Inverting Bipolar Transfer Function 0 | T fs - S00kHz 99 K- } fiy- 100kKHe SINAD - 72dB Ta- 125 C | } 4 ae r SIGNAL AMPLITUDE (dB) -80 100 Mev owen 0 50 100 150 = 200.250 . i o~ | Ne a I | | Hh 10M Li ig EFFECTIVE BITS 10k 100 INPUT FREQUENCY (He) FREQUENCY (kH7) Figure 22. MAX120 FFT Plot Total Harmonic Distortion Ifa pure sine wave is sampled by an ADC at greater than the Nyquist frequency, the nonlinearities in the ADC's transfer function create harmonics of the input frequency in the sampled output data Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics (in the frequency band above DC and below one-half the sample rate, but not including the DC component) to the RMS amplitude of the fundamental frequency. This is expressed as follows: 22 a? Wo? + _ THD = 2010g ee +VNT MM AAIMI Figure 23. Effective Bits vs. Input Frequency where V1 is the fundamental RMS amplitude, and V2 to VN are the amplitudes of the 2nd through Nth harmonics. The THD specification in the Electrical Characteristics table includes the 2nd through Sth harmonics. intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function non- linearities produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency If two pure sine waves of frequency fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function create distortion products at sum and difference frequencies of mfa + nfo. where m and n = 0, 1, 2,3, etc. THD includes those distortion products with m orn equal to zero. Intermodulation distortion consists of all distortion products for which neither m nor n equal zero. For example, the 2nd-order IMD terms include (fa + fb) and (fa - fb) while the Srd-order IMD terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb). If the two input sine waves are equal in magnitude. the value (in decibels) of the 2nd-order IMD products can be expressed by the following formula amplitude at (fa + fb) IMD (fa + tb) = 20log amplitude at fa 13 2Z2KXVIN/OCEXVINMAX 120/MAX1 22 500ksps, 1 2-Bit ADCs with Track/Hold and Reference Spurious-Free Dynamic Range Spurious-free dynamic range ts the ratio of the fundamen- tal RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually the next largest spectral component occurs at some harmonic of the input frequency. However, if the ADC is exceptionally linear, it may occur only at a random peak in the ADCs noise floor Chip Topography MAX120/MAX122 TRANSISTOR COUNT 1920; SUBSTRATE CONNECTED TO Vop. _ Ordering information (continued) FO a ~ t INL | PART __ TEMP. RANGE PIN-PACKAGE (LSBs)! +4! |MAX120EAG -40 Cto +86. C_ 24 SSOP | MAX120MRG_ -55 C to +125 C 24 Narrow CERDIP fe | MAX122ACNG OCto+70C 24Narrow Plastic DIP 43/4 | MAX122BCNG QOCto+70C 24 Narrow Plastic DIP 41 r MAX122ACWG OC to70C 24Wide SO 43/4 |Max122BCWG OC 10+70C 24 Wide SO Hy |MAX122ACAG OC to +70 C24 SSOP 43/4 | |MAX122BCAG OC to +70 24 SSOP + MAX122BC/D __ Oo Cto +70 Co Dice + MAX122AENG -40.C to +85 C24 Narrow Plastic DIP -+3/4 | MAX122BENG -40Cto +85 C24 Narrow Plastic DIP #1 MAX122AEWG -40 C10 +85C 24 Wide SO 43/4 , | MAX122BEWG -40C to +85'C 24 Wide SO | [NIDA Tee EW OEY 10 FOOD eB WIGE OD | [|MAX122AEAG -40C to +85 C24 SSOP +3/4 [MAX122BEAG 40 Cto+85C 24SS0P #1 MAX122BMRG_ -55'C to +125 C 24 Narrow CFRDIP +1 _MAXI20EVKI-DP" OC to+70C Plastic DIP - Through Hole * Contact factory for dice specifications MAX 120 EV kit can be used to evaluate the MAX 122) when ordering the EV kit, ask for a free sample of the MAX 122 MAAKIM500ksps,12-Bit ADCs with Track/Hold and Reference Package Information pina |__INCHES MILLIMETERS MIN | MAX | MIN | MAX A | - | o0200 | - 5.08 | [DI ai {0.015 | - | 0.38 = moo a i a eo no a on on ~ A2 | 0.125 | 0.150 | 3.18 | 3.81 A3 | 0.055 [| 0.080 | 1.40 | 2.03 B | 0.016 | 0.022 | o41 | 0.56 Bi | 0.050 | 0.065 | 1.27 | 1.65 SSS c | 0008 | 0.012 | 0.20 | 0.30 D | 1.235 | 1.265 [ 31.37 | 32.13 |~a- 01 0.050 0.080 1.27 2.03 E | 0.300 | 0.325 | 7.62 | 8.26 I~ E1 7 E1 0.240 0.280 6.10 7.11 A a2 l= D | e 0.100 BSC 2.54 BSC i vw laa I @, | __0.300 BSC 7.62 BSC ep | - | 0400 | - | 10.16 Y Ww tL | o1i5 | o150 | 292 | 3.81 Th | | i Lo oO 15 o 15" a ny Ms 21-337A yA ~~ i 24-PIN PLASTIC L ele =I=-c DUAL-IN-LINE BI t 2, | (NARROW) B 3 PACKAGE pint |___INCHES MILLIMETERS MIN [| MAX [ MIN | MAX A 0.093 0.104 2.35 2.65 Al 0.004 0.012 0.10 0.30 B 0.014 0.019 0.35 0.49 c [0.009 | 0.013 | 0.23 | 0.32 b | os9s | o614 | 15.20 | 15.60 E | 0291 | 0299 | 7.40 | 7.60 e 0.050 BSC 1.27 BSC H_ | 0.394 [ 0.419 | 10.00 | 10.65 h | 0.010 | 0.030 | 0.25 | 0.75 i_|oot6 | 0.050 | 040 | 1.27 o Qo" 8" 0 8" 21-338A <p __| j hx 45 7 ; 1 | yA a 1 | Ah Stee a 24-PIN PLASTIC | |-~a- | | e B Al c Le ae SMALL-OUTLINE PACKAGE MAXIM 16 cokLXVIW/OCLXUVINMAX120/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference Package Information (continued) DIM INCHES MILLIMETERS MIN MAX MIN MAX A | 0.068 | 0.078 1.73 1.99 _ Al _| 0.002 0.008 0.05 0.21 ee ee B [ooo [001s | 025 | 0.98 4 c | 0.005 | 0.009 | 0.13 | 0.22 D | 0.317 | 0.328 .807 8.33 EH E | 0.205 | 0212 | 520 | 5.38 1 e 0.0256 BSC 0.65 BSC St H | 0.301 | 0.311 | 7.65 | 7.90 ARR RR BORE HG L | 0.022 | 0.037 | 0.55 | 0.95 a O 8 0" 8 21-0002A <a$ D _- a mY. Lo n._1 0.127mm - Ti T TF 24-PIN PLASTIC rn ar \ SHRINK Lt. SMALL-OUTLINE PACKAGE Maxim cannot assume responsibility for use of any circuitry other tnan circuitry entirely embodied in a Maxim proauct. No circuit patent tCenses are implied. Maxim reserves the right to change the circuttry and specifications wiinuut nauce at ary time 16 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 1994 Maxim Integrated Products Printed USA MAXIMA js a registered trademark of Maxim Integrated Products