LP5907UVE-1.8/NOPB - NATIONAL SEMICONDUCTOR

IN OUT

GND

INPUT

ENABLE

GND

OUTPUT

LP5907

1 F 1 F

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LP5907

SNVS798O –APRIL 2012–REVISED JUNE 2020

LP5907 250-mA, Ultra-Low-Noise, Low-I

LDO

1 Features

1• Input voltage range: 2.2 V to 5.5 V

• Output voltage range: 1.2 V to 4.5 V

• Stable with 1-µF ceramic input and output

capacitors

• No noise bypass capacitor required

• Remote output capacitor placement

• Thermal-overload and short-circuit protection

• –40°C to 125°C operating junction temperature

• Low output voltage noise: < 6.5 µVRMS

• PSRR: 82 dB at 1 kHz

• Output voltage tolerance: ±2%

• Very low IQ(enabled): 12 µA

• Low dropout: 120 mV (typical)

• Create a custom design using the LP5907 with

the WEBENCH®Power Designer

2 Applications

•Smartphones

•Tablets

•Communications equipment

•Digital still cameras

•Factory automation

3 Description

The LP5907 is a low-noise LDO that can supply up to

250 mA output current. Designed to meet the

requirements of RF and analog circuits, the LP5907

device provides low noise, high PSRR, low quiescent

current, and low line or load transient response

figures. Using new innovative design techniques, the

LP5907 offers class-leading noise performance

without a noise bypass capacitor and the ability for

remote output capacitor placement.

The device is designed to work with a 1-µF input and

a 1-µF output ceramic capacitor (no separate noise

bypass capacitor is required).

This device is available with fixed output voltages

from 1.2 V to 4.5 V in 25-mV steps. Contact Texas

Instruments Sales for specific voltage option needs.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE

LP5907 DSBGA (4) 0.645 mm × 0.645 mm (NOM)

SOT-23 (5) 2.90 mm × 1.60 mm (NOM)

X2SON (4) 1.00 mm × 1.00 mm (NOM)

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

space

Simplified Schematic

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 4

6 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

6.6 Output and Input Capacitors..................................... 7

6.7 Typical Characteristics.............................................. 8

7 Detailed Description............................................ 12

7.1 Overview................................................................. 12

7.2 Functional Block Diagram....................................... 12

7.3 Feature Description................................................. 12

7.4 Device Functional Modes........................................ 13

8 Application and Implementation ........................ 14

8.1 Application Information............................................ 14

8.2 Typical Application.................................................. 14

9 Power Supply Recommendations...................... 17

10 Layout................................................................... 18

10.1 Layout Guidelines ................................................. 18

10.2 Layout Examples................................................... 18

11 Device and Documentation Support................. 20

11.1 Documentation Support ........................................ 20

11.2 Receiving Notification of Documentation Updates 20

11.3 Support Resources ............................................... 20

11.4 Trademarks........................................................... 20

11.5 Electrostatic Discharge Caution............................ 20

11.6 Glossary................................................................ 20

12 Mechanical, Packaging, and Orderable

Information........................................................... 21

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision N (April 2018) to Revision O Page

• Changed Applications section................................................................................................................................................ 1

• Changed DSBGA body size in Device Information table ...................................................................................................... 1

• Added YKG to pinout caption of Pin Configuration and Functions section............................................................................ 4

• Added YKG column to Thermal Information table.................................................................................................................. 6

Changes from Revision M (January 2018) to Revision N Page

• Added Overshoot on start-up with EN row to Electrical Characteristics table ...................................................................... 7

Changes from Revision L (August 2016) to Revision M Page

• Added links for WEBENCH ................................................................................................................................................... 1

• Added information about YKM package option ..................................................................................................................... 1

• Added minor editorial changes .............................................................................................................................................. 1

Changes from Revision K (May 2016) to Revision L Page

• Changed title of data sheet and updated list of Applications and wording of 1st sentence in Description............................ 1

• Changed "10 µVRMS" to "6.5 µVRMS"....................................................................................................................................... 1

Changes from Revision J (March 2016) to Revision K Page

• Changed "Linear Regulator" to "LDO" in title and first sentence of Description .................................................................... 1

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Changes from Revision I (August 2015) to Revision J Page

• Changed VOUT min and max values and VEN min value in Abs Max table and VEN row of ROC table to correct format

errors; replace text of footnote 2 of Abs Max table ............................................................................................................... 5

Changes from Revision H (November 2014) to Revision I Page

• Added icon for reference design to Top Navs and "ΔVOUT vs Temperature" graph to Typical Characteristics ..................... 1

• Changed Storage Temperature to Abs Max table; replace Handling Ratings with ESD Ratings ......................................... 5

• Deleted "VOUT ≥1.8 V" from first row of ΔVout spec ............................................................................................................. 6

• Added "SOT-23, X2SON packages" to second row of ΔVout spec ...................................................................................... 6

Changes from Revision G (October 2013) to Revision H Page

• Added Device Information and Handling Rating tables, Feature Description,Device Functional Modes,Application

and Implementation,Power Supply Recommendations,Layout,Device and Documentation Support, and

Mechanical, Packaging, and Orderable Information sections; moved some curves to Application Curves section ............. 1

OUT

GND

IN EN

N/C

GND

IN OUT

B2B1

A2A1

OUT

GND

B2 B1

A2 A1

OUT

GND

TOP VIEW BOTTOM VIEW

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SNVS798O –APRIL 2012–REVISED JUNE 2020

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5 Pin Configuration and Functions

YKE, YKG, and YKM Packages

4-Pin DSBGA

Pin Functions: DSBGA

PIN I/O DESCRIPTION

DSBGA

NUMBER NAME

A1 IN I Input voltage supply. Connect a 1-µF capacitor at this input.

A2 OUT O Regulated output voltage. Connect a minimum 1-µF low-ESR capacitor to this pin. Connect

this output to the load circuit. An internal 230-Ω(typical) pulldown resistor prevents a charge

remaining on VOUT when the regulator is in the shutdown mode (VEN low).

B1 EN I Enable input. A low voltage (< VIL) on this pin turns the regulator off and discharges the

output pin to GND through an internal 230-Ωpulldown resistor. A high voltage (> VIH) on this

pin enables the regulator output. This pin has an internal 1-MΩpulldown resistor to hold the

regulator off by default.

B2 GND — Common ground

DQN Package

4-Pin X2SON

Bottom View

DBV Package

5-Pin SOT-23

Top View

Pin Functions: X2SON, SOT-23

PIN I/O DESCRIPTION

NAME X2SON

NUMBER SOT-23

NUMBER

IN 4 1 I Input voltage supply. Connect a 1-µF capacitor at this input.

OUT 1 5 O Regulated output voltage. Connect a minimum 1-µF low-ESR capacitor to this

pin. Connect this output to the load circuit. An internal 230-Ω(typical) pulldown

resistor prevents a charge remaining on VOUT when the regulator is in the

shutdown mode (VEN low).

EN 3 3 I Enable input. A low voltage (< VIL) on this pin turns the regulator off and

discharges the output pin to GND through an internal 230-Ωpulldown resistor. A

high voltage (> VIH) on this pin enables the regulator output. This pin has an

internal 1-MΩpulldown resistor to hold the regulator off by default.

GND 2 2 — Common ground

N/C — 4 — No internal electrical connection.

Thermal Pad 5 — — Thermal pad for X2SON package, connect to GND or leave floating. Do not

connect to any potential other than GND.

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the GND pin.

(3) Abs Max VOUT is the lessor of VIN + 0.3 V, or 6 V.

(4) Internal thermal shutdown circuitry protects the device from permanent damage.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)

MIN MAX UNIT

VIN Input voltage –0.3 6 VVOUT Output voltage –0.3 See(3)

VEN Enable input voltage –0.3 6

Continuous power dissipation(4) Internally Limited W

TJMAX Junction temperature 150 °C

Tstg Storage temperature –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the GND pin.

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =

125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the

part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX). See Application and

Implementation.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)(2)

MIN MAX UNIT

VIN Input supply voltage 2.2 5.5 V

VEN Enable input voltage 0 5.5

IOUT Output current 0 250 mA

TJJunction temperature –40 125 °C

TAAmbient temperature(3) –40 85 °C

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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.4 Thermal Information

THERMAL METRIC(1)

LP5907

UNIT

DBV

(SOT-23) DQN

(X2SON) YKE

(DSBGA) YKG

(DSBGA) YKM

(DSBGA)

5 PINS 4 PINS 4 PINS 4 PINS 4 PINS

RθJA Junction-to-ambient thermal resistance 193.4 216.1 206.1 191.6 194.1 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 102.1 161.7 1.5 2.4 3.0 °C/W

RθJB Junction-to-board thermal resistance 45.8 162.1 37.0 58.9 62.7 °C/W

ψJT Junction-to-top characterization parameter 8.4 5.1 15.0 1.1 1.1 °C/W

ψJB Junction-to-board characterization parameter 45.3 161.7 36.8 58.9 62.7 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 123.0 n/a n/a n/a °C/W

(1) All voltages are with respect to the device GND terminal, unless otherwise stated.

(2) Minimum and maximum limits are ensured through test, design, or statistical correlation over the junction temperature (TJ) range of

–40°C to 125°C, unless otherwise stated. Typical values represent the most likely parametric norm at TA= 25°C, and are provided for

reference purposes only.

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =

125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the

part/package in the application RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX). See Application and

Implementation.

(4) The device maintains a stable, regulated output voltage without a load current.

(5) Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT.

(6) Ground current is defined here as the total current flowing to ground as a result of all input voltages applied to the device.

(7) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its

nominal value.

(8) Short-circuit current (ISC) for the LP5907 is equivalent to current limit. To minimize thermal effects during testing, ISC is measured with

VOUT pulled to 100 mV below its nominal voltage.

6.5 Electrical Characteristics

VIN = VOUT(NOM) + 1 V, VEN = 1.2 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF (unless otherwise noted)(1)(2)(3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIN Input voltage TA= 25°C 2.2 5.5 V

ΔVOUT

Output voltage tolerance

VIN = (VOUT(NOM) + 1 V) to 5.5 V,

IOUT = 1 mA to 250 mA –2 2

%VOUT

VIN = (VOUT(NOM) + 1 V) to 5.5 V,

IOUT = 1 mA to 250 mA

(VOUT < 1.8 V, SOT-23, X2SON packages) –3 3

Line regulation VIN = (VOUT(NOM) + 1 V) to 5.5 V,

IOUT = 1 mA 0.02 %/V

Load regulation IOUT = 1 mA to 250 mA 0.001 %/mA

ILOAD Load current See(4) 0 250 mA

Maximum output current 250

IQQuiescent current(5) VEN = 1.2 V, IOUT = 0 mA 12 25 µAVEN = 1.2 V, IOUT = 250 mA 250 425

VEN = 0.3 V (disabled) 0.2 1

IGGround current(6) VEN = 1.2 V, IOUT = 0 mA 14 µA

VDO Dropout voltage(7) IOUT = 100 mA 50 mVIOUT = 250 mA (DSBGA package) 120 200

IOUT = 250 mA (SOT-23, X2SON packages) 250

ISC Short-circuit current limit TA= 25°C(8) 250 500 mA

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Electrical Characteristics (continued)

VIN = VOUT(NOM) + 1 V, VEN = 1.2 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF (unless otherwise noted)(1)(2)(3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(9) This specification is verified by design.

(10) There is a 1-MΩresistor between EN and ground on the device.

PSRR Power-supply rejection ratio(9)

f = 100 Hz, IOUT = 20 mA 90

f = 1 kHz, IOUT = 20 mA 82

f = 10 kHz, IOUT = 20 mA 65

f = 100 kHz, IOUT = 20 mA 60

eNOutput noise voltage(9) BW = 10 Hz to 100 kHz IOUT = 1 mA 10 µVRMS

IOUT = 250 mA 6.5

RAD Output automatic discharge

pulldown resistance VEN < VIL (output disabled) 230 Ω

TSD Thermal shutdown TJrising 160 °C

Thermal hysteresis TJfalling from shutdown 15

LOGIC INPUT THRESHOLDS

VIL Low input threshold VIN = 2.2 V to 5.5 V,

VEN falling until the output is disabled 0.4 V

VIH High input threshold VIN = 2.2 V to 5.5 V

VEN rising until the output is enabled 1.2 V

IEN Input current at EN pin(10) VEN = 5.5 V and VIN = 5.5 V 5.5 µA

VEN = 0 V and VIN = 5.5 V 0.001

TRANSIENT CHARACTERISTICS

ΔVOUT

Line transient(9)

VIN = (VOUT(NOM) + 1 V) to

(VOUT(NOM) + 1.6 V) in 30 µs –1

VIN = (VOUT(NOM) + 1.6 V) to

(VOUT(NOM) + 1.6 V) in 30 µs 1

Load transient(9) IOUT = 1 mA to 250 mA in 10 µs –40

IOUT = 250 mA to 1 mA in 10 µs 40

Overshoot on start-up(9) Stated as a percentage of VOUT(NOM) 5%

Overshoot on start-up with EN(9) Stated as a percentage of VOUT(NOM), VIN =

VOUT + 1 V to 5.5 V, 0.7 µF < COUT < 10 µF,

0 mA < IOUT < 250 mA, EN rising until the

output is enabled 1%

tON Turnon time From VEN > VIH to VOUT = 95% of VOUT(NOM),

TA= 25°C 80 150 µs

(1) The minimum capacitance should be greater than 0.5 µF over the full range of operating conditions. The capacitor tolerance should be

30% or better over the full temperature range. The full range of operating conditions for the capacitor in the application must be

considered during device selection to ensure this minimum capacitance specification is met. X7R capacitors are recommended however

capacitor types X5R, Y5V and Z5U may be used with consideration of the application and conditions.

(2) This specification is verified by design.

6.6 Output and Input Capacitors

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN(1) TYP MAX UNIT

CIN Input capacitance(2) Capacitance for stability 0.7 1 µF

COUT Output capacitance(2) 0.7 1 10 µF

ESR Output/Input capacitance(2) 5 500 mΩ

0 50 100 150 200 250 300

100

150

200

250

300

350

GROUND CURRENT (A)

IOUT(mA)

VIN = 3.0V

VIN = 3.8V

VIN = 4.2V

VIN = 5.5V

SVA-30180571

0 50 100 150 200 250

2.700

2.725

2.750

2.775

2.800

2.825

2.850

2.875

2.900

VOUT(V)

LOAD (mA)

VIN= 3.6V

-40°C

90°C

25°C

SVA-30180567

VIN (V)

VOUT (V)

0 0.5 1 1.5 2 2.5

0.2

0.4

0.6

0.8

1.2

1.4

D002

RLOAD = 1.2 k:

RLOAD = 4.8 :

VIN (V)

VOUT (V)

0 1 2 3 4 5 6

0.5

1.5

2.5

3.5

4.5

D003

RLOAD = 4.5 k:

RLOAD = 18 :

2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8

IQ(A)

VIN(V) SVA-30180569

VIN (V)

VEN (V)

2 2.5 3 3.5 4 4.5 5 5.5 6

0.5

0.6

0.7

0.8

0.9

D001

VIH Rising

VIL Falling

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6.7 Typical Characteristics

VIN = 3.7 V, VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA= 25°C (unless otherwise noted)

Figure 1. Quiescent Current vs Input Voltage Figure 2. VEN Thresholds vs VIN

VOUT = 1.2 V, VEN = VIN

Figure 3. VOUT vs VIN

VOUT = 4.5 V, VEN = VIN

Figure 4. VOUT vs VIN

Figure 5. Ground Current vs Output Current Figure 6. Load Regulation

100 s/DIV

VOUT 100 mV/DIV

LOAD 200 mA/DIV

SVA-30180512

10 s/DIV

10 mV/

DIV

1V/DIV

VIN

VOUT

(AC Coupled)

SVA-30180511

10 s/DIV

VOUT

(AC Coupled)

10 mV/

DIV

1V/DIV

VIN

SVA-30180510

2 ms/DIV

VOUT

2V/DIV

1A/DIV

VIN = VEN

IIN

SVA-30180509

Junction Temperature (qC)

'VOUT (%)

-50 -25 0 25 50 75 100 125

-0.4

-0.3

-0.2

-0.1

0.1

0.2

D010

3.0 3.5 4.0 4.5 5.0 5.5

2.700

2.725

2.750

2.775

2.800

2.825

2.850

2.875

2.900

VOUT(V)

VIN(V)

Load = 10 mA

-40°C

90°C

25°C

SVA-30180568

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Typical Characteristics (continued)

VIN = 3.7 V, VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA= 25°C (unless otherwise noted)

Figure 7. ΔVOUT vs Temperature Figure 8. Line Regulation

Figure 9. Inrush Current

VIN = 3.2 V ↔4.2 V, load = 1 mA

Figure 10. Line Transient

VIN = 3.2 V ↔4.2 V, load = 250 mA

Figure 11. Line Transient

Load = 0 mA ↔250 mA, –40°C

Figure 12. Load Transient

0 50 100 150 200 250

100

120

140

DROPOUT VOLTAGE (mV)

LOAD CURRENT (mA)

Dropout Voltage

SVA-30180573

20 s/DIV

VOUT

1V/DIV

SVA-30180515

20 s/DIV

VOUT

1V/DIV

SVA-30180516

100 s/DIV

VOUT 100 mV/DIV

LOAD 200 mA/DIV

SVA-30180514

100 s/DIV

VOUT 100 mV/DIV

LOAD 200 mA/DIV

SVA-30180513

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Typical Characteristics (continued)

VIN = 3.7 V, VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA= 25°C (unless otherwise noted)

Load = 0 mA ↔250 mA, 90°C

Figure 13. Load Transient

Load = 0 mA ↔250 mA, 25°C

Figure 14. Load Transient

Load = 0 mA

Figure 15. Start-Up

Load = 250 mA

Figure 16. Start-Up

Figure 17. Noise Density Test Figure 18. Dropout Voltage vs Load Current

FREQUENCY (kHz)

PSRR (dB)

0.1 1 10 100

-120

-100

-80

-60

-40

-20

D004

250 mA

200 mA

150 mA

100 mA

50 mA

20 mA

FREQUENCY (kHz)

PSRR (dB)

0.01 0.1 1 10 100 1000 10000

-120

-100

-80

-60

-40

-20

D005

250 mA

200 mA

150 mA

100 mA

50 mA

20 mA

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Typical Characteristics (continued)

VIN = 3.7 V, VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA= 25°C (unless otherwise noted)

Figure 19. PSRR Loads Averaged 100 Hz to 100 kHz Figure 20. PSRR Loads Averaged 10 Hz to 10 MHz

VBG

1.20V

+EN

GND

POR

OUT

1 M

VIH

RAD

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7 Detailed Description

7.1 Overview

Designed to meet the needs of sensitive RF and analog circuits, the LP5907 provides low noise, high PSRR, low

quiescent current, as well as low line and load transient response figures. Using new innovative design

techniques, the LP5907 offers class leading noise performance without the need for a separate noise filter

capacitor.

The LP5907 is designed to perform with a single 1-µF input capacitor and a single 1-µF ceramic output

capacitor. With a reasonable PCB layout, the single 1-µF ceramic output capacitor can be placed up to 10 cm

away from the LP5907 device.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Enable (EN)

The LP5907 EN pin is internally held low by a 1-MΩresistor to GND. The EN pin voltage must be higher than the

VIH threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage must

be lower than the VIL threshold to ensure that the device is fully disabled and the automatic output discharge is

activated.

7.3.2 Low Output Noise

Any internal noise at the LP5907 reference voltage is reduced by a first order low-pass RC filter before it is

passed to the output buffer stage. The low-pass RC filter has a –3 dB cut-off frequency of approximately 0.1 Hz.

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Feature Description (continued)

7.3.3 Output Automatic Discharge

The LP5907 output employs an internal 230-Ω(typical) pulldown resistance to discharge the output when the EN

pin is low, and the device is disabled.

7.3.4 Remote Output Capacitor Placement

The LP5907 requires at least a 1-µF capacitor at the OUT pin, but there are no strict requirements about the

location of the capacitor in regards the OUT pin. In practical designs, the output capacitor may be located up to

10 cm away from the LDO.

7.3.5 Thermal Overload Protection (TSD)

Thermal shutdown disables the output when the junction temperature rises to approximately 160°C which allows

the device to cool. When the junction temperature cools to approximately 145°C, the output circuitry enables.

Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may

cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a

result of overheating.

The thermal shutdown circuitry of the LP5907 has been designed to protect against temporary thermal overload

conditions. The TSD circuitry was not intended to replace proper heat-sinking. Continuously running the LP5907

device into thermal shutdown may degrade device reliability.

7.4 Device Functional Modes

7.4.1 Enable (EN)

The LP5907 Enable (EN) pin is internally held low by a 1-MΩresistor to GND. The EN pin voltage must be

higher than the VIH threshold to ensure that the device is fully enabled under all operating conditions.

When the EN pin is pulled low, and the output is disabled, the output automatic discharge circuitry is activated.

Any charge on the OUT pin is discharged to GND through the internal 230-Ω(typical) pulldown resistance.

7.4.2 Minimum Operating Input Voltage (VIN)

The LP5907 does not include any dedicated UVLO circuitry. The LP5907 internal circuitry is not fully functional

until VIN is at least 2.2 V. The output voltage is not regulated until VIN has reached at least the greater of 2.2 V or

(VOUT + VDO).

IN OUT

GND

INPUT

ENABLE

GND

OUTPUT

LP5907

1 F 1 F

LP5907

SNVS798O –APRIL 2012–REVISED JUNE 2020

www.ti.com

Product Folder Links: LP5907

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LP5907 is designed to meet the requirements of RF and analog circuits, by providing low noise, high PSRR,

low quiescent current, and low line or load transient response figures. The device offers excellent noise

performance without the need for a noise bypass capacitor and is stable with input and output capacitors with a

value of 1 µF. The LP5907 delivers this performance in industry standard packages such as DSBGA, X2SON,

and SOT-23 which, for this device, are specified with an operating junction temperature (TJ) of –40°C to 125°C.

8.2 Typical Application

Figure 21 shows the typical application circuit for the LP5907. Input and output capacitances may need to be

increased above the 1 µF minimum for some applications.

Figure 21. LP5907 Typical Application

8.2.1 Design Requirements

DESIGN PARAMETER EXAMPLE VALUE

Input voltage range 2.2 V to 5.5 V

Output voltage 1.8 V

Output current 200 mA

Output capacitor range 0.7 µF to 10 µF

Input/Output capacitor ESR range 5 to 500 mΩ

LP5907

www.ti.com

SNVS798O –APRIL 2012–REVISED JUNE 2020

Product Folder Links: LP5907

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LP5907 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Power Dissipation and Device Operation

The permissible power dissipation for any package is a measure of the capability of the device to pass heat from

the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus, the power

dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces

between the die junction and ambient air.

The maximum allowable power dissipation for the device in a given package can be calculated using Equation 1:

PD-MAX = ((TJ-MAX – TA) / RθJA) (1)

The actual power being dissipated in the device can be represented by Equation 2:

PD= (VIN – VOUT)×IOUT (2)

These two equations establish the relationship between the maximum power dissipation allowed due to thermal

consideration, the voltage drop across the device, and the continuous current capability of the device. These two

equations should be used to determine the optimum operating conditions for the device in the application.

In applications where lower power dissipation (PD) and/or excellent package thermal resistance (RθJA) is present,

the maximum ambient temperature (TA-MAX) may be increased.

In applications where high power dissipation and/or poor package thermal resistance is present, the maximum

ambient temperature (TA-MAX) may have to be derated. TA-MAX is dependent on the maximum operating junction

temperature (TJ-MAX-OP = 125°C), the maximum allowable power dissipation in the device package in the

application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA),

as given by Equation 3:

TA-MAX = (TJ-MAX-OP – (RθJA × PD-MAX)) (3)

Alternately, if TA-MAX can not be derated, the PDvalue must be reduced. This can be accomplished by reducing

VIN in the VIN–VOUT term as long as the minimum VIN is met, or by reducing the IOUT term, or by some

combination of the two.

8.2.2.3 External Capacitors

Like most low-dropout regulators, the LP5907 requires external capacitors for regulator stability. The device is

specifically designed for portable applications requiring minimum board space and smallest components. These

capacitors must be correctly selected for good performance.

8.2.2.4 Input Capacitor

An input capacitor is required for stability. The input capacitor should be at least equal to, or greater than, the

output capacitor for good load transient performance. At least a 1 µF capacitor has to be connected between the

LP5907 input pin and ground for stable operation over full load current range. Basically, it is ok to have more

output capacitance than input, as long as the input is at least 1 µF.

LP5907

SNVS798O –APRIL 2012–REVISED JUNE 2020

www.ti.com

Product Folder Links: LP5907

The input capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean

analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.

NOTE

To ensure stable operation it is essential that good PCB practices are employed to

minimize ground impedance and keep input inductance low. If these conditions cannot be

met, or if long leads are to be used to connect the battery or other power source to the

LP5907, TI recommends increasing the input capacitor to at least 10 µF. Also, tantalum

capacitors can suffer catastrophic failures due to surge current when connected to a low-

impedance source of power (like a battery or a very large capacitor). If a tantalum

capacitor is used at the input, it should be verified by the manufacturer to have a surge

current rating sufficient for the application. The initial tolerance, applied voltage de-rating,

and temperature coefficient must all be considered when selecting the input capacitor to

ensure the actual capacitance is never less than 0.7 µF over the entire operating range.

8.2.2.5 Output Capacitor

The LP5907 is designed specifically to work with a very small ceramic output capacitor, typically 1 µF. A ceramic

capacitor (dielectric types X5R or X7R) in the 1 µF to 10 µF range, and with ESR between 5 mΩto 500 mΩ, is

suitable in the LP5907 application circuit. For this device the output capacitor should be connected between the

OUT pin and a good connection back to the GND pin.

It may also be possible to use tantalum or film capacitors at the device output, VOUT, but these are not as

attractive for reasons of size and cost (see Capacitor Characteristics).

The output capacitor must meet the requirement for the minimum value of capacitance and have an ESR value

that is within the range 5 mΩto 500 mΩfor stability. Like the input capacitor, the initial tolerance, applied voltage

de-rating, and temperature coefficient must all be considered when selecting the input capacitor to ensure the

actual capacitance is never less than 0.7 µF over the entire operating range.

8.2.2.6 Capacitor Characteristics

The LP5907 is designed to work with ceramic capacitors on the input and output to take advantage of the

benefits they offer. For capacitance values in the range of 1 µF to 10 µF, ceramic capacitors are the smallest,

least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise.

The ESR of a typical 1 µF ceramic capacitor is in the range of 20 mΩto 40 mΩ, which easily meets the ESR

requirement for stability for the LP5907.

A better choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the most stable

and holds the capacitance within ±15% over the temperature range. Tantalum capacitors are less desirable than

ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance

and voltage ratings in the 1 µF to 10 µF range.

Another important consideration is that tantalum capacitors have higher ESR values than equivalent size

ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the

stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic

capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum increases about

2:1 as the temperature goes from 25°C down to –40°C, so some guard band must be allowed.

8.2.2.7 Remote Capacitor Operation

The LP5907 requires at least a 1-µF capacitor at the OUT pin, but there is no strict requirements about the

location of the capacitor in regards to the pin. In practical designs the output capacitor may be located up to 10

cm away from the LDO. This means that there is no need to have a special capacitor close to the output pin if

there is already respective capacitors in the system (like a capacitor at the input of supplied part). The remote

capacitor feature helps user to minimize the number of capacitors in the system.

20 s/DIV

VOUT

1V/DIV

SVA-30180515

100 s/DIV

VOUT 100 mV/DIV

LOAD 200 mA/DIV

SVA-30180514

LP5907

www.ti.com

SNVS798O –APRIL 2012–REVISED JUNE 2020

Product Folder Links: LP5907

As a good design practice, keep the wiring parasitic inductance at a minimum, which means to use as wide as

possible traces from the LDO output to the capacitors, keeping the LDO output trace layer as close to ground

layer as possible and avoiding vias on the path. If there is a need to use vias, implement as many as possible

vias between the connection layers. The recommendation is to keep parasitic wiring inductance less than 35 nH.

For the applications with fast load transients, it is recommended to use an input capacitor equal to or larger to

the sum of the capacitance at the output node for the best load transient performance.

8.2.2.8 No-Load Stability

The LP5907 remains stable, and in regulation, with no external load.

8.2.2.9 Enable Control

The LP5907 may be switched ON or OFF by a logic input at the EN pin. A voltage on this pin greater than VIH

turns the device on, while a voltage less than VIL turns the device off.

When the EN pin is low, the regulator output is off and the device typically consumes less than 1 µA.

Additionally, an output pulldown circuit is activated which ensures that any charge stored on COUT is discharged

to ground.

If the application does not require the use of the shutdown feature, the EN pin can be tied directly to the IN pin to

keep the regulator output permanently on.

An internal 1-MΩpulldown resistor ties the EN input to ground, ensuring that the device remains off if the EN pin

is left open circuit. To ensure proper operation, the signal source used to drive the EN pin must be able to swing

above and below the specified turnon or turnoff voltage thresholds listed in the Electrical Characteristics under

VIL and VIH.

8.2.3 Application Curves

Figure 22. Start-Up Figure 23. Load Transient Response

9 Power Supply Recommendations

This device is designed to operate from an input supply voltage range of 2.2 V to 5.5 V. The input supply must

be well regulated and free of spurious noise. To ensure that the LP5907 output voltage is well regulated and

dynamic performance is optimum, the input supply must be at least VOUT + 1 V. A minimum capacitor value of 1

µF is required to be within 1 cm of the IN pin.

GND

OUT

N/C

CIN COUT

VIN

GND

Enable

VOUT

GND

LP5907

SNVS798O –APRIL 2012–REVISED JUNE 2020

www.ti.com

Product Folder Links: LP5907

10 Layout

10.1 Layout Guidelines

The dynamic performance of the LP5907 is dependant on the layout of the PCB. PCB layout practices that are

adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5907.

Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5907, and as

close to the package as is practical. The ground connections for CIN and COUT must be back to the LP5907

ground pin using as wide and short a copper trace as is practical.

Connections using long trace lengths, narrow trace widths, and/or connections through vias must be avoided.

These add parasitic inductances and resistance that results in inferior performance especially during transient

conditions

10.1.1 X2SON Mounting

The X2SON package thermal pad must be soldered to the printed circuit board for proper thermal and

mechanical performance. For more information, see the QFN/SON PCB Attachment application report.

10.1.2 DSBGA Mounting

The DSBGA package requires specific mounting techniques, which are detailed in AN-1112 DSBGA Wafer Level

Chip Scale Package. For best results during assembly, alignment ordinals on the PC board may be used to

facilitate placement of the DSBGA device.

10.1.3 DSBGA Light Sensitivity

Exposing the DSBGA device to direct light may cause incorrect operation of the device. Light sources such as

halogen lamps can affect electrical performance if they are situated in proximity to the device. Light with

wavelengths in the red and infrared part of the spectrum have the most detrimental effect; thus, the fluorescent

lighting used inside most buildings has very little effect on performance.

10.2 Layout Examples

Figure 24. LP5907MF-x.x (SOT-23) Typical Layout

A1 A2

VIN VOUT

Power Ground

VEN

CIN COUT

LP5907UV

VIN

VOUT

Power Ground

VEN

CIN

COUT

LP5907SN

LP5907

www.ti.com

SNVS798O –APRIL 2012–REVISED JUNE 2020

Product Folder Links: LP5907

Layout Examples (continued)

Figure 25. LP5907SN-xx (X2SON) Typical Layout

Figure 26. LP5907A/UV-x.x (DSBGA) Typical Layout

LP5907

SNVS798O –APRIL 2012–REVISED JUNE 2020

www.ti.com

Product Folder Links: LP5907

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LP5907 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.1.2 Related Documentation

For related documentation, see the following:

• Texas Instruments, AN-1112 DSBGA Wafer Level Chip Scale Package application note

• Texas Instruments, QFN/SON PCB Attachment application report

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.4 Trademarks

E2E is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

LP5907

www.ti.com

SNVS798O –APRIL 2012–REVISED JUNE 2020

Product Folder Links: LP5907

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 23-Sep-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP5907A28YKMR ACTIVE DSBGA YKM 4 3000 Green (RoHS

& no Sb/Br) SAC396 Level-1-260C-UNLIM -40 to 125 Q

LP5907A29YKMR ACTIVE DSBGA YKM 4 3000 Green (RoHS

& no Sb/Br) SAC396 Level-1-260C-UNLIM -40 to 125 Y

LP5907A33YKMR ACTIVE DSBGA YKM 4 3000 Green (RoHS

& no Sb/Br) SAC396 Level-1-260C-UNLIM -40 to 125 N

LP5907MFX-1.2/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LLTB

LP5907MFX-1.5/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LN8B

LP5907MFX-1.8/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LLUB

LP5907MFX-2.5/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LN7B

LP5907MFX-2.8/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LLYB

LP5907MFX-2.85/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LN4B

LP5907MFX-2.9/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 1E5X

LP5907MFX-3.0/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LLZB

LP5907MFX-3.1/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LN5B

LP5907MFX-3.2/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LN6B

LP5907MFX-3.3/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LLVB

LP5907MFX-4.5/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LLXB

LP5907SNX-1.2/NOPB ACTIVE X2SON DQN 4 3000 Green (RoHS

& no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 125 CF

PACKAGE OPTION ADDENDUM

www.ti.com 23-Sep-2020

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP5907SNX-1.8/NOPB ACTIVE X2SON DQN 4 3000 Green (RoHS

& no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 125 CG

LP5907SNX-1.9 ACTIVE X2SON DQN 4 3000 Green (RoHS

& no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 125 3Z

LP5907SNX-2.2/NOPB ACTIVE X2SON DQN 4 3000 Green (RoHS

& no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 125 EP

LP5907SNX-2.5/NOPB ACTIVE X2SON DQN 4 3000 Green (RoHS

& no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 125 F9

LP5907SNX-2.7/NOPB ACTIVE X2SON DQN 4 3000 Green (RoHS

& no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 125 CH

LP5907SNX-2.75 ACTIVE X2SON DQN 4 3000 Green (RoHS

& no Sb/Br) NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 HI

LP5907SNX-2.8/NOPB ACTIVE X2SON DQN 4 3000 Green (RoHS

& no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 125 CI

LP5907SNX-2.85/NOPB ACTIVE X2SON DQN 4 3000 Green (RoHS

& no Sb/Br) NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CJ

LP5907SNX-2.9/NOPB ACTIVE X2SON DQN 4 3000 Green (RoHS

& no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 125 GV

LP5907SNX-3.0/NOPB ACTIVE X2SON DQN 4 3000 Green (RoHS

& no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 125 CK

LP5907SNX-3.1/NOPB ACTIVE X2SON DQN 4 3000 Green (RoHS

& no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 125 CL

LP5907SNX-3.2/NOPB ACTIVE X2SON DQN 4 3000 Green (RoHS

& no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 125 CM

LP5907SNX-3.3/NOPB ACTIVE X2SON DQN 4 3000 Green (RoHS

& no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 125 CN

LP5907SNX-4.0/NOPB ACTIVE X2SON DQN 4 3000 Green (RoHS

& no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 125 GU

LP5907SNX-4.5/NOPB ACTIVE X2SON DQN 4 3000 Green (RoHS

& no Sb/Br) NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CO

LP5907UVE-1.2/NOPB ACTIVE DSBGA YKE 4 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 R

LP5907UVE-1.8/NOPB ACTIVE DSBGA YKE 4 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 S

PACKAGE OPTION ADDENDUM

www.ti.com 23-Sep-2020

Addendum-Page 3

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP5907UVE-2.8/NOPB ACTIVE DSBGA YKE 4 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 U

LP5907UVE-2.85/NOPB ACTIVE DSBGA YKE 4 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 V

LP5907UVE-3.0/NOPB ACTIVE DSBGA YKE 4 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 B

LP5907UVE-3.1/NOPB ACTIVE DSBGA YKE 4 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 X

LP5907UVE-3.2/NOPB ACTIVE DSBGA YKE 4 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 C

LP5907UVE-3.3/NOPB ACTIVE DSBGA YKE 4 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 D

LP5907UVE-4.5/NOPB ACTIVE DSBGA YKE 4 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 Z

LP5907UVX-1.2/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 R

LP5907UVX-1.6/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS

& no Sb/Br) SAC396 Level-1-260C-UNLIM -40 to 125 J

LP5907UVX-1.8/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 S

LP5907UVX-2.2/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS

& no Sb/Br) SAC396 Level-1-260C-UNLIM -40 to 125 5

LP5907UVX-2.5/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 E

LP5907UVX-2.8/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 U

LP5907UVX-2.85/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 V

LP5907UVX-3.0/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 B

LP5907UVX-3.1/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 X

LP5907UVX-3.2/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 C

PACKAGE OPTION ADDENDUM

www.ti.com 23-Sep-2020

Addendum-Page 4

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP5907UVX-3.3/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 D

LP5907UVX-4.5/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 Z

LP5907UVX19/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 8

LP5907UVX37/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 9

LP5907YKGR-2.0 PREVIEW DSBGA YKG 4 3000 Green (RoHS

& no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 W

LP5907YKGR-2.8 ACTIVE DSBGA YKG 4 3000 Green (RoHS

& no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 3

LP5907YKGR-2.825 ACTIVE DSBGA YKG 4 3000 Green (RoHS

& no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 5

LP5907YKGR-2.85 ACTIVE DSBGA YKG 4 3000 Green (RoHS

& no Sb/Br) SAC396 Level-1-260C-UNLIM -40 to 125 P

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

PACKAGE OPTION ADDENDUM

www.ti.com 23-Sep-2020

Addendum-Page 5

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LP5907 :

•Automotive: LP5907-Q1

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LP5907A28YKMR DSBGA YKM 4 3000 178.0 8.4 0.74 0.74 0.54 4.0 8.0 Q1

LP5907A29YKMR DSBGA YKM 4 3000 178.0 8.4 0.74 0.74 0.54 4.0 8.0 Q1

LP5907A33YKMR DSBGA YKM 4 3000 178.0 8.4 0.74 0.74 0.54 4.0 8.0 Q1

LP5907MFX-1.2/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LP5907MFX-1.5/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LP5907MFX-1.8/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LP5907MFX-2.5/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LP5907MFX-2.8/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LP5907MFX-2.85/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LP5907MFX-2.9/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LP5907MFX-3.0/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LP5907MFX-3.1/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LP5907MFX-3.2/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LP5907MFX-3.3/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LP5907MFX-4.5/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LP5907SNX-1.2/NOPB X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2

LP5907SNX-1.8/NOPB X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2

LP5907SNX-1.9 X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Jul-2020

Pack Materials-Page 1

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LP5907SNX-2.2/NOPB X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2

LP5907SNX-2.5/NOPB X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2

LP5907SNX-2.7/NOPB X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2

LP5907SNX-2.75 X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2

LP5907SNX-2.8/NOPB X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2

LP5907SNX-2.85/NOPB X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2

LP5907SNX-2.9/NOPB X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2

LP5907SNX-3.0/NOPB X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2

LP5907SNX-3.1/NOPB X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2

LP5907SNX-3.2/NOPB X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2

LP5907SNX-3.3/NOPB X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2

LP5907SNX-4.0/NOPB X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2

LP5907SNX-4.5/NOPB X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2

LP5907UVE-1.2/NOPB DSBGA YKE 4 250 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907UVE-1.2/NOPB DSBGA YKE 4 250 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVE-1.8/NOPB DSBGA YKE 4 250 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVE-1.8/NOPB DSBGA YKE 4 250 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907UVE-2.8/NOPB DSBGA YKE 4 250 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907UVE-2.8/NOPB DSBGA YKE 4 250 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVE-2.85/NOPB DSBGA YKE 4 250 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVE-2.85/NOPB DSBGA YKE 4 250 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907UVE-3.0/NOPB DSBGA YKE 4 250 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907UVE-3.0/NOPB DSBGA YKE 4 250 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVE-3.1/NOPB DSBGA YKE 4 250 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVE-3.1/NOPB DSBGA YKE 4 250 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907UVE-3.2/NOPB DSBGA YKE 4 250 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907UVE-3.2/NOPB DSBGA YKE 4 250 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVE-3.3/NOPB DSBGA YKE 4 250 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVE-3.3/NOPB DSBGA YKE 4 250 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907UVE-4.5/NOPB DSBGA YKE 4 250 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907UVE-4.5/NOPB DSBGA YKE 4 250 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVX-1.2/NOPB DSBGA YKE 4 3000 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907UVX-1.2/NOPB DSBGA YKE 4 3000 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVX-1.6/NOPB DSBGA YKE 4 3000 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907UVX-1.8/NOPB DSBGA YKE 4 3000 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVX-1.8/NOPB DSBGA YKE 4 3000 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907UVX-2.2/NOPB DSBGA YKE 4 3000 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907UVX-2.5/NOPB DSBGA YKE 4 3000 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVX-2.8/NOPB DSBGA YKE 4 3000 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVX-2.8/NOPB DSBGA YKE 4 3000 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907UVX-2.85/NOPB DSBGA YKE 4 3000 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVX-2.85/NOPB DSBGA YKE 4 3000 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907UVX-3.0/NOPB DSBGA YKE 4 3000 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Jul-2020

Pack Materials-Page 2

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LP5907UVX-3.0/NOPB DSBGA YKE 4 3000 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVX-3.1/NOPB DSBGA YKE 4 3000 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907UVX-3.1/NOPB DSBGA YKE 4 3000 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVX-3.2/NOPB DSBGA YKE 4 3000 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907UVX-3.2/NOPB DSBGA YKE 4 3000 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVX-3.3/NOPB DSBGA YKE 4 3000 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVX-3.3/NOPB DSBGA YKE 4 3000 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907UVX-4.5/NOPB DSBGA YKE 4 3000 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907UVX-4.5/NOPB DSBGA YKE 4 3000 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVX19/NOPB DSBGA YKE 4 3000 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVX19/NOPB DSBGA YKE 4 3000 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907UVX37/NOPB DSBGA YKE 4 3000 178.0 8.4 0.71 0.71 0.51 2.0 8.0 Q1

LP5907UVX37/NOPB DSBGA YKE 4 3000 178.0 8.4 0.74 0.74 0.5 2.0 8.0 Q1

LP5907YKGR-2.8 DSBGA YKG 4 3000 178.0 9.2 0.72 0.72 0.39 4.0 8.0 Q1

LP5907YKGR-2.825 DSBGA YKG 4 3000 178.0 9.2 0.72 0.72 0.39 4.0 8.0 Q1

LP5907YKGR-2.85 DSBGA YKG 4 3000 178.0 9.2 0.72 0.72 0.39 4.0 8.0 Q1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP5907A28YKMR DSBGA YKM 4 3000 220.0 220.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Jul-2020

Pack Materials-Page 3

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP5907A29YKMR DSBGA YKM 4 3000 220.0 220.0 35.0

LP5907A33YKMR DSBGA YKM 4 3000 220.0 220.0 35.0

LP5907MFX-1.2/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LP5907MFX-1.5/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LP5907MFX-1.8/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LP5907MFX-2.5/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LP5907MFX-2.8/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LP5907MFX-2.85/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LP5907MFX-2.9/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LP5907MFX-3.0/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LP5907MFX-3.1/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LP5907MFX-3.2/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LP5907MFX-3.3/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LP5907MFX-4.5/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LP5907SNX-1.2/NOPB X2SON DQN 4 3000 184.0 184.0 19.0

LP5907SNX-1.8/NOPB X2SON DQN 4 3000 184.0 184.0 19.0

LP5907SNX-1.9 X2SON DQN 4 3000 184.0 184.0 19.0

LP5907SNX-2.2/NOPB X2SON DQN 4 3000 184.0 184.0 19.0

LP5907SNX-2.5/NOPB X2SON DQN 4 3000 184.0 184.0 19.0

LP5907SNX-2.7/NOPB X2SON DQN 4 3000 184.0 184.0 19.0

LP5907SNX-2.75 X2SON DQN 4 3000 184.0 184.0 19.0

LP5907SNX-2.8/NOPB X2SON DQN 4 3000 184.0 184.0 19.0

LP5907SNX-2.85/NOPB X2SON DQN 4 3000 184.0 184.0 19.0

LP5907SNX-2.9/NOPB X2SON DQN 4 3000 184.0 184.0 19.0

LP5907SNX-3.0/NOPB X2SON DQN 4 3000 184.0 184.0 19.0

LP5907SNX-3.1/NOPB X2SON DQN 4 3000 184.0 184.0 19.0

LP5907SNX-3.2/NOPB X2SON DQN 4 3000 184.0 184.0 19.0

LP5907SNX-3.3/NOPB X2SON DQN 4 3000 184.0 184.0 19.0

LP5907SNX-4.0/NOPB X2SON DQN 4 3000 184.0 184.0 19.0

LP5907SNX-4.5/NOPB X2SON DQN 4 3000 184.0 184.0 19.0

LP5907UVE-1.2/NOPB DSBGA YKE 4 250 220.0 220.0 35.0

LP5907UVE-1.2/NOPB DSBGA YKE 4 250 210.0 185.0 35.0

LP5907UVE-1.8/NOPB DSBGA YKE 4 250 210.0 185.0 35.0

LP5907UVE-1.8/NOPB DSBGA YKE 4 250 220.0 220.0 35.0

LP5907UVE-2.8/NOPB DSBGA YKE 4 250 220.0 220.0 35.0

LP5907UVE-2.8/NOPB DSBGA YKE 4 250 210.0 185.0 35.0

LP5907UVE-2.85/NOPB DSBGA YKE 4 250 210.0 185.0 35.0

LP5907UVE-2.85/NOPB DSBGA YKE 4 250 220.0 220.0 35.0

LP5907UVE-3.0/NOPB DSBGA YKE 4 250 220.0 220.0 35.0

LP5907UVE-3.0/NOPB DSBGA YKE 4 250 210.0 185.0 35.0

LP5907UVE-3.1/NOPB DSBGA YKE 4 250 210.0 185.0 35.0

LP5907UVE-3.1/NOPB DSBGA YKE 4 250 220.0 220.0 35.0

LP5907UVE-3.2/NOPB DSBGA YKE 4 250 220.0 220.0 35.0

LP5907UVE-3.2/NOPB DSBGA YKE 4 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Jul-2020

Pack Materials-Page 4

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP5907UVE-3.3/NOPB DSBGA YKE 4 250 210.0 185.0 35.0

LP5907UVE-3.3/NOPB DSBGA YKE 4 250 220.0 220.0 35.0

LP5907UVE-4.5/NOPB DSBGA YKE 4 250 220.0 220.0 35.0

LP5907UVE-4.5/NOPB DSBGA YKE 4 250 210.0 185.0 35.0

LP5907UVX-1.2/NOPB DSBGA YKE 4 3000 220.0 220.0 35.0

LP5907UVX-1.2/NOPB DSBGA YKE 4 3000 210.0 185.0 35.0

LP5907UVX-1.6/NOPB DSBGA YKE 4 3000 220.0 220.0 35.0

LP5907UVX-1.8/NOPB DSBGA YKE 4 3000 210.0 185.0 35.0

LP5907UVX-1.8/NOPB DSBGA YKE 4 3000 220.0 220.0 35.0

LP5907UVX-2.2/NOPB DSBGA YKE 4 3000 220.0 220.0 35.0

LP5907UVX-2.5/NOPB DSBGA YKE 4 3000 210.0 185.0 35.0

LP5907UVX-2.8/NOPB DSBGA YKE 4 3000 210.0 185.0 35.0

LP5907UVX-2.8/NOPB DSBGA YKE 4 3000 220.0 220.0 35.0

LP5907UVX-2.85/NOPB DSBGA YKE 4 3000 210.0 185.0 35.0

LP5907UVX-2.85/NOPB DSBGA YKE 4 3000 220.0 220.0 35.0

LP5907UVX-3.0/NOPB DSBGA YKE 4 3000 220.0 220.0 35.0

LP5907UVX-3.0/NOPB DSBGA YKE 4 3000 210.0 185.0 35.0

LP5907UVX-3.1/NOPB DSBGA YKE 4 3000 220.0 220.0 35.0

LP5907UVX-3.1/NOPB DSBGA YKE 4 3000 210.0 185.0 35.0

LP5907UVX-3.2/NOPB DSBGA YKE 4 3000 220.0 220.0 35.0

LP5907UVX-3.2/NOPB DSBGA YKE 4 3000 210.0 185.0 35.0

LP5907UVX-3.3/NOPB DSBGA YKE 4 3000 210.0 185.0 35.0

LP5907UVX-3.3/NOPB DSBGA YKE 4 3000 220.0 220.0 35.0

LP5907UVX-4.5/NOPB DSBGA YKE 4 3000 220.0 220.0 35.0

LP5907UVX-4.5/NOPB DSBGA YKE 4 3000 210.0 185.0 35.0

LP5907UVX19/NOPB DSBGA YKE 4 3000 210.0 185.0 35.0

LP5907UVX19/NOPB DSBGA YKE 4 3000 220.0 220.0 35.0

LP5907UVX37/NOPB DSBGA YKE 4 3000 210.0 185.0 35.0

LP5907UVX37/NOPB DSBGA YKE 4 3000 220.0 220.0 35.0

LP5907YKGR-2.8 DSBGA YKG 4 3000 220.0 220.0 35.0

LP5907YKGR-2.825 DSBGA YKG 4 3000 220.0 220.0 35.0

LP5907YKGR-2.85 DSBGA YKG 4 3000 220.0 220.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Jul-2020

Pack Materials-Page 5

www.ti.com

PACKAGE OUTLINE

0.35

4X 0.20

0.16

0.33 MAX

0.12

0.09

0.175

B E A

DSBGA - 0.33mm MAX HEIGHTYKG0004

DIE SIZE BALL GRID ARRAY

4218366/E 05/2020

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per

ASME Y14.5M.

2. This drawing is subject to change without notice.

0.05 C

0.015 C A B

BUMP

SEATING PLANE

SCALE 15.000

BUMP A1 CORNER

D: Max =

E: Max =

0.675 mm, Min =

0.615 mm

www.ti.com

EXAMPLE BOARD LAYOUT

(0.35)

0.0375 MAX 0.0375 MIN

(0.175)

4X ( 0.18)

SOLDERMASK

OPENING

( 0.18)

METAL

( 0.18)

SOLDERMASK

OPENING

METAL UNDER

SOLDER MASK

DSBGA - 0.33mm MAX HEIGHTYKG0004

DIE SIZE BALL GRID ARRAY

4218366/E 05/2020

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:60X

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

Refer to Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).

SOLDERMASK DETAILS

NOT TO SCALE

NON SOLDERMASK

DEFINED

EXPOSED

METAL

SOLDERMASK

DEFINED

(PREFERRED)

EXPOSED

METAL

www.ti.com

EXAMPLE STENCIL DESIGN

METAL

TYP

(0.21)

(R0.05)

TYP

(0.175)

(0.35)

(0.175)

DSBGA - 0.33mm MAX HEIGHTYKG0004

DIE SIZE BALL GRID ARRAY

4218366/E 05/2020

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

SYMM

SOLDERPASTE EXAMPLE

BASED ON 0.075 mm THICK STENCIL

SCALE:80X

www.ti.com

PACKAGE OUTLINE

0.22

0.08 TYP

0.25

3.0

2.6

2X 0.95

1.9

1.45

0.90

0.15

0.00 TYP

5X 0.5

0.3

0.6

0.3 TYP

0 TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/E 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/E 09/2019

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/E 09/2019

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

www.ti.com

PACKAGE OUTLINE

0.495 MAX

0.18

0.14

0.35

TYP

0.35

TYP

4X 0.225

0.195

B E A

4223494/A 11/2014

DSBGA - 0.495 mm max heightYKM0004

DIE SIZE BALL GRID ARRAY

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

BALL A1

CORNER

SEATING PLANE

BALL TYP

BACK COATING

0.015 C A B

SCALE 12.000

D: Max =

E: Max =

0.675 mm, Min =

0.615 mm

www.ti.com

EXAMPLE BOARD LAYOUT

4X ( 0.18) (0.35) TYP

(0.35) TYP

( 0.18)

METAL 0.04 MAX

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

( 0.18)

SOLDER MASK

OPENING

0.04 MIN

4223494/A 11/2014

DSBGA - 0.495 mm max heightYKM0004

DIE SIZE BALL GRID ARRAY

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

Refer to Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).

SOLDER MASK DETAILS

NOT TO SCALE

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:40X

NON-SOLDER MASK

DEFINED

EXPOSED

METAL

SOLDER MASK

DEFINED

(PREFERRED)

EXPOSED

METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(0.35)

TYP

(0.35) TYP

4X ( 0.21) (R0.05) TYP

METAL

TYP

4223494/A 11/2014

DSBGA - 0.495 mm max heightYKM0004

DIE SIZE BALL GRID ARRAY

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.075 - 0.1mm THICK STENCIL

SCALE:40X

www.ti.com

PACKAGE OUTLINE

0.445 MAX

0.18

0.14

0.35

TYP

0.35

TYP

4X 0.225

0.195

B E A

4220102/A 11/2014

DSBGA - 0.445mm max heightYKE0004

DIE SIZE BALL GRID ARRAY

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

BALL A1

CORNER

SEATING PLANE

BALL TYP

0.005 C A B

SCALE 12.000

D: Max =

E: Max =

0.675 mm, Min =

0.615 mm

www.ti.com

EXAMPLE BOARD LAYOUT

4X 0.18 0.02 (0.35) TYP

(0.35) TYP

( )

METAL

0.18 0.04 MAX

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

( )

SOLDER MASK

OPENING

0.18

0.04 MIN

4220102/A 11/2014

DSBGA - 0.445mm max heightYKE0004

DIE SIZE BALL GRID ARRAY

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

Refer to Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).

SOLDER MASK DETAILS

NOT TO SCALE

SYMM

LAND PATTERN EXAMPLE

SCALE:40X

NON-SOLDER MASK

DEFINED

(PREFERRED) SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

(0.35)

TYP

(0.35) TYP

4X ( 0.21) (R ) TYP0.05

METAL

TYP

4220102/A 11/2014

DSBGA - 0.445mm max heightYKE0004

DIE SIZE BALL GRID ARRAY

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.075 - 0.1mm THICK STENCIL

SCALE:40X

PACKAGE OUTLINE

DQN0004A X2SON - 0.4 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

4215302/E 12/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.

5. Shape of exposed side leads may differ.

6. Number and location of exposed tie bars may vary.

www.ti.com

SEATING PLANE

0.08

PIN 1

INDEX AREA

0.1 C A B

0.05 C

PIN 1 ID

(OPTIONAL)

NOTE 4

EXPOSED

THERMAL PAD

1.05

0.95

1.05

0.95

0.4 MAX

2X 0.65

0.48+0.12

-0.1

3X 0.30

0.15

0.3

0.2

4X 0.28

0.15

0.05

0.00

(0.11)

NOTE 5

NOTE 6

(0.07) TYP

(0.05) TYP

EXAMPLE BOARD LAYOUT

DQN0004A X2SON - 0.4 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

4215302/E 12/2016

NOTES: (continued)

7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

8. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.

www.ti.com

SOLDER MASK

DEFINED

SOLDER MASK DETAIL

0.05 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

LAND PATTERN EXAMPLE

SCALE: 40X

SYMM

4X (0.21)

4X (0.36)

(0.65)

(0.86)

( 0.48)

SEE DETAIL

4X (0.18)

(0.22) TYP

EXPOSED METAL

CLEARANCE

(0.03)

EXPOSED METAL

EXAMPLE STENCIL DESIGN

DQN0004A X2SON - 0.4 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

4215302/E 12/2016

NOTES: (continued)

9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

SOLDER PASTE EXAMPLE

BASED ON 0.075 - 0.1mm THICK STENCIL

EXPOSED PAD

88% PRINTED SOLDER COVERAGE BY AREA

SCALE: 60X

SYMM

SOLDER MASK

EDGE

4X (0.21)

4X (0.4)

(0.65)

(0.9)

( 0.45)

4X (0.03)

4X (0.235)

4X (0.22)

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