Evaluation Board Document
NE5550234-EV09-A
Evaluation Board
o Circuit Description
o Typical Performance Data
o Circuit Schematic and Assembly Drawing
2
Circuit Description
The NE5550234-EV09-A is an evaluation circuit board for Renesas’ LDMOS power FET,
NE5550234 optimized for the performance at 915MHz. The circuit board is RoHS compliant.
Matching and Bias Circuits
Refer to the schematic and assembly drawing in the two last pages for the component designation
and location.
The input matching circuit consists of two sections of low pass network. An inductor, L1 and a
section of transmission line, TL4 are the serial components in the network. At output, three
sections of transmission line, TL1, TL2 and TL3 provide the required serial components for the
impedance transformation. The performance is most sensitive to the length of TL1 and not very
sensitive to TL3. The electrical lengths of the transmission lines labeled on the schematic are
estimated and for reference only. Some bench tuning on the actual circuit board is usually
required to achieve an optimal performance. For applications where there is a constraint on the
board space, serial inductors, instead of transmission lines, can be used for the matching circuits.
Low loss inductors should be selected to maintain good efficiency of the PA circuit. The resistor,
R3(=2.4ohm) at input is used to improve the stability margin. The gain is reduced by about 1-
2dB when R3 is used.
LDMOSFETs essentially draw no gate current under normal operation conditions. Therefore a
large value resistor, in the order of kΩ, can be used for the bias at gate so that the RF path is
completely isolated from the DC line. At the drain an inductor is used as the RF choke. The
current rating for this inductor should be high enough to provide the required current at the
operation conditions.
Bias Conditions
This evaluation board was optimized at a specific drain voltage, 7.5V. For different supply
voltages, the matching circuits should be adjusted to fully utilize the device capability. The
quiescent current is 40mA for the data shown below. The gain is higher at higher quiescent
currents, particularly when the device is not completely saturated. For many communication
systems, where the PA is never at idle state, a high quiescent current might be used.
PCB Material:
The PCB is Getek 28mil two layer board. The dielectric constant of Getek is 4.2.
3
Typical Performance Data
Test Conditions:
f=915MHz
Vd=7.5V, Idsq=40mA
Pout, Gain, PAE and Current vs Pin are shown in the following plot.
