PC107AVZFU100LD - Atmel Corporation

2137C–HIREL–03/04

Features

•Processor Bus Frequency up to 100 MHz

•64- or 32-bit Data Bus and 32-bit Address Bus

•Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst

SRAM

•Compliant with PCI Specification, Revision 2.1

•PCI Interface Operates up to 66 MHz/5.0V Compa t ible

•IEEE 1149.1 Compliant, JTAG Boundary-scan Interface

•PD Max = 1W (66 MHz), Full Opera t ing Conditions

•Nap, Doze and Sleep Modes for Power Savings

•Two-channel Integrated DMA Contr oller

•Message Unit

– Intelligent Input/Output (Tw o- wire Interface) Message Controller

– Two Door Bell Registers

– Inbound and Outbound Messaging Registers

•Inter-integrated Circuit (Two-wire Interface) Controller, Full Master/Slave Support

•Embedded Programmable Interrupt Controller (EPIC)

– Five Hardware Interrupts (IRQs) or 16 Serial Interrupts

– Four Programmable Timers

Description

The PC107A PCI Bridge/Integrated Memory Controller provides a bridge between th e

Peripheral Component Interconnect, (PCI) bus and PowerPC 603e™, PowerPC 740™,

PowerPC 750™ or PC7400 microprocessors.

PCI suppor t allows system designers to design systems quickly using peripherals

already designed for PCI and other standard interfaces available in the personal com-

puter hardware environment. The PC107A provides many other necessities for

embedded application s including a high-performance memory controller and dual pro-

cessor support, 2-channel flexible DMA controller, an interrupt controller, an I2O-ready

message unit , an inter-integrated circuit controller (Two-wire Interface), and low skew

clock drivers. The PC107A contains an Embedded Programmable Interrupt Controller

(EPIC) featuring five hardware interrupts (IRQ’s) as well as sixteen serial interrupts

along with four timers. The PC10 7A uses a n advanced, 2.5V HiP3 process te chnol ogy

and is fully compatible with TTL devices.

Screening

This product is manufactured in full compliance with:

• PBGA upscreenings based upon Atmel standards

• Full military temperature range (Tj = -55°C, +125°C)

• Industrial temperature range (Tj = -40°C, +110°C)

• HiTCE (TBC)

PBGA 503

Flip-chip Plastic Ball Grid Array

GH suffix

HITCE 503

Ceramic Ball Grid Array

PCI Bridge

Memory

Controller

PC107A

Preliminary

Specification

β-site

Rev. 2137C–HIREL–03/04

2PC107A [Preliminary] 2137C–HIREL–03/04

General Description

Simplified Block Diagram The PC107A integra tes a PCI bri dge , memor y controller, DM A controlle r, EPIC inter rupt

controller/timers, a message unit with an Intelligent Input/Output (I2O) message control-

ler, and an Inter-integrated Circuit (two-wire interface) controller. The integration

reduces the overall packaging requirements and the number of discrete devices

required for an embedded system.

Figure 1 shows the major functional units within the PC107A. Note that this is a concep-

tual block diagram intended to show the basic features rather than an attemp t to show

how these featu r es ar e ph ys ica lly imple m en te d .

Figure 1. PC107A Block Diagram

Data (64-Bit)

60x Bus Interface (64- or 32-Bit Data Bus)

Address

(32-Bit)

DLL

PLL

Fanout

Buffers

Additional features:

• Programmable I/O

• with Watchpoint

• JTAG/COP Interface

• Power Management

SDRAM_SYNC_IN

SDRAM Clocks

CPU Clocks

PCI_SYNC_IN

PCI Bus Clocks

Memory/ROM/

Port X Control/

Address

Data Bus

(64- or 32-bit)

with 8-bit Parity

or ECC

OSC_INFive

Request/Grant

Pairs

32-Bit

PCI Interface

I2C

5 IRQs/

16 Serial

Interrupts

EPIC

Interrupt

Controller

/Timers

Address

Translator PCI

Arbiter

MPC107

I2C

Controller

DMA

Controller

Message

Unit

(with I2O)

Peripheral Logic Block

Central

Control

Unit

Data Path

ECC Controller

Memory

Controller

Configuration

Registers

PCI Bus

Interface Unit

PC107A [Preliminary]

2137C–HIREL–03/04

General Parameters The following list provides a su mmary of the general parameters of the PC107A:

Technology 0.29 µm CMOS, five-layer metal

Die size 50 mm2

Transistor count 0.96 million

Logic design Fully-static

Package Surface mount 50 3 Plastic Ball Grid Array (C4/PBGA)

Core power supply 2.5 ±5% V DC (nominal; see Table 3 on page 12 for

recommended operating conditions)

I/O power supply 3.0 to 3.6V DC

Features The PC107A provides an integrated high-bandwidth, high-performance interface

between up to two 60x processors, the PCI bus, and main memory. This section sum-

marizes the featur es of the PC107A. Major features of the PC107A ar e as follows:

• Memory Interface

– 64-/32-bit 10 0 MHz bus

– Progr ammab le ti ming supporting either FPM DRAM, EDO DRAM or SDRAM

– High-bandwidth bus (32-/64-bit data bus) to DRAM

– Supports one to eight banks of 4-, 16-, 64-, or 128-Mbit memory devices,

and up to four banks of 256 Mbit SDRAM devices

– Supports 1M byte to 1 Gbyte DRAM memory

– 144M byt es of ROM space

– 8-, 32-, or 64-bit ROM

– Write buffering for PCI and processor accesses

– Supports normal parity, read- modify-write (RMW), or ECC

– Data-path buffering between memory interface and processor

– Low-voltage TTL logic (LVTTL) interfaces

– Port X: 8-, 32-, or 64-bit general-purpose I/O port using ROM controller

interface with programmable address strobe timing

• 32-bit PCI Interface Operating up to 6 6 MHz

– PCI 2.1-compliant

– PCI 5.0V tolerance

– Support for PCI locked accesses to memory

– Support for accesses to PCI memory, I/O, and configuration spaces

– Selectable big- or little-endian operat ion

– Store gathering of processor-to-PCI write and PCI-to-memory write

accesses

– Memory prefet ching of PCI read accesses

– Selectable hardw are-enforced coherency

– PCI bus arbitration unit (five request/grant pairs)

– PCI agent mode capability

– Address translation unit

– Some internal configuration registers accessible from PCI

• Two -channel Integrated DMA Controller (Writes to RO M/Port × Not Supported)

4PC107A [Preliminary] 2137C–HIREL–03/04

– Supports direct mode or chaining mode (automatic linking of DMA transfers)

– Supports scatter gathering-read or write discontinuous memory

– Interrupt on completed segmen t, chain, and error

– Local-to-local memory

– PCI-to-PCI memory

– PCI-to-local memory

– PCI memory-to-local memory

• Message Unit

– Two doorbell regist er s

– An extended doorbell register mechanism that facilitates interprocessor

communication through interrupts in a dual-local-processor system

– Two inbound and two ou tb ou n d me ssaging regist er s

–I

2O message controller

• Two-wire Interface Controller with Full Master/Slave Support (Except Broadcast All)

• Embedded Programmable Inter rupt Contr oller (EPIC)

– Five hardware interrupts (IRQs) or 16 serial interrupts

– Four programmable timers

• Integrated PCI Bus, CPU, and SDRAM Clock Generation

• Programmable PCI Bus, 60x, and Memory Interface Output Drive rs

• Dynamic Power Management – Supports 60x Nap, Do ze, and Sleep Modes

• Programmable Input and Output Signals with Watchpoint Capability

• Built-in PCI Bus Performance Monitor Facility

• Debug Features

– Error injection/capture on data path

– IEEE 1149.1 (JTAG)/test interface

• Processor Interface

– Supports up to two PowerPCTM microprocessors with 60x bus inte rface

– Supports various operating frequencies and bus divider r atios

– 32-bit address bus, 64/32-bit data bus supported at 100 MHz

– Supports full memory coherency

– Supports optional local bus slave

– Decoupled address and data buses for pipelining of 60x accesses

– Store gathering on 60x-to-PCI writes

– Concurrent transactions on 60x and PCI buses supported

PC107A [Preliminary]

2137C–HIREL–03/04

Pin Assignments

Pinout Listings Table 1 provides the pinout listing for the PC107A, 503 PBGA package.

Table 1. PC107A Pinout Listing

Signal Name Package Pin Number Pin Type Supply

Voltage Output Driver Type Notes

60x Processor Interface Signals

A[0–31]

AE22, AE16, AA14, AE17, AD21,

AD14, AD20, AB16, AB20, AB15,

AA20, AD13, Y15, AE12, AD15, AB9,

AB14, AA8, AC13, Y12, Y11, AE15,

AE13, AA16, Y13, AB8, AD12, AE10,

AB13, Y9, Y8, AD9

I/O BVDD DRV_CPU (4)

AACK AC7 Output BVDD DRV_CPU

ARTRY Y7 I/O BVDD DRV_CPU (15)

BG0 AE11 Output BVDD DRV_CPU

BG1 AD11 Output BVDD DRV_CPU

BR0 AB17 Input BVDD –

BR1 Y14 Input BVDD –(10)

CI AD16 I/O BVDD DRV_CPU

DBG0 AC10 Output BVDD DRV_MEM_ADDR

DBG1 AD10 Output BVDD DRV_MEM_ADDR

DBGLB AB10 Output BVDD DRV_MEM_ADDR

DH[0–31]

P1, R1, P2, T4, T1, T3, R4, P6, U6,

V5, V2, T5, U1, R6, W1, V4, W2, U4,

T2, V6, W3, W5, Y1, Y2, Y4, Y5, AA1,

AA2, AA4, AB1, AB3, AB4

I/O BVDD DRV_CPU (4)

DL[0–31]

AA7, W6, AB6, AA6, AB5, AC4, AD3,

AB7, AE1, W4, N6, M1, N3, N4, N5,

N1, M2, R2, V1, P5, P4, N2, U2, AE4,

AE6, AE2, AE3, AE7, AD5, AB2, A C2,

AC1

I/O BVDD DRV_CPU (4)

DP[0–7] AE9, AD6, AD8, AD1, AE8, AD7, AD4,

AE5 I/O BVDD DRV_CPU (4)

GBL AD17 I/O BVDD DRV_CPU

LBCLAIM Y17 Input BVDD

TA AE14 I/O BVDD DRV_CPU (15)

TBST AE21 I/O BVDD DRV_CPU

TEA AB11 Output BVDD DRV_CPU

TS AA10 I/O BVDD DRV_CPU (15)

TSIZ[0–2] AE19, AD18, AB18 I/O BVDD DRV_CPU (4)

TT[0–4] AD19, AC19, AB19, AA19, AA18 I/O BVDD DRV_CPU (4)

6PC107A [Preliminary] 2137C–HIREL–03/04

WT AC16 I/O BVDD DRV_CPU

PCI Interf ace Signals

AD[31–0]

N23, N21, M20, M21, M22, M24, M25,

L20, L22, K25, K24, K23, K21, J20,

J24, J25, H20, F24, E25, F21, E24,

E22, D25, A25, B25, A23, B23, B22,

C22, C25, D23, D21

I/O OVDD DRV_PCI (4)(11)

C/BE[3–0] L24, J22, G22, A24, I/O OVDD DRV_PCI (4)(11)

DEVSEL G23 I/O OVDD DRV_PCI (6)(11)

FRAME G20 I/O OVDD DRV_PCI (6)(11)

GNT[4–0] T24, P22, P21, R22, N20 Output OVDD DRV_PCI (4)(11)

IDSEL L25 Input OVDD –

INTA V21 Output OVDD DRV_PCI (6)(11)(12)

IRDY H24 I/O OVDD DRV_PCI (6)(11)

LOCK G21 Input OVDD –(6)

PAR G24 I/O OVDD DRV_PCI (11)

PERR G25 I/O OVDD DRV_PCI (6)(11)(13)

REQ[4–0] W25, V25, U25, T25, T23 Input OVDD –(10)

SERR F25 I/O OVDD DRV_PCI (6)(11)(12)

STOP H21 I/O OVDD DRV_PCI (6)(11)

TRDY H25 I/O OVDD DRV_PCI (6)(11)

Memory Interf ace Signals

AS A4 Output GVDD DRV_MEM_ADDR

CAS/DQM[0–7] A2, B1, A11, A10, B3, C2, F12, D11 Output GVDD DRV_MEM_ADDR (4)

CKE A12 Output GVDD DRV_MEM_ADDR (1)

FOE A13 I/O GVDD DRV_MEM_ADDR (1)(2)

MDH[0–31]

M6, L4, L6, K2, K4, K5, J4, J6, H4, H5,

G3, G5, G6, F5, F1, E1, B14, D15,

B15, E16, D16, C16, D18, D17, B17,

F18, E19, E20, B19, B20, B21, A22

I/O GVDD DRV_MEM_DATA (4)

MDL[0–31]

M5, L1, L2, K1, K3, J1, J2, H1, H2,

H6, G2, G4, F4, G1, F2, E2, F14, F1 5,

A16, F17, B16, A17, A18, A19, B18,

E18, D19, F19, A20, C19, D20, A21

I/O GVDD DRV_MEM_DATA (3)(4)

PAR/AR[0–7] D2, C1, A15, A14, D1, D3, F13, C13 I/O GVDD DRV_MEM_DATA (4)

RAS/CS[0–7] E6, C4, D5, E4, C10, F11, B10, B11 Output GVDD DRV_MEM_ADDR (4)

RCS0 D10 I/O GVDD DRV_MEM_ADDR (1)(2)

RCS1 B9 Output GVDD DRV_MEM_DATA

RCS2 B5 Output GVDD DRV_MEM_ADDR

Table 1. PC107A Pinout Listing (Continued)

Signal Name Package Pin Number Pin Type Supply

Voltage Output Driver Type Notes

PC107A [Preliminary]

2137C–HIREL–03/04

RCS3 D7 Output GVDD DRV_MEM_ADDR

SDBA0 A9 Output GVDD DRV_MEM_ADDR (1)(2)

SDBA1 A8 Output GVDD DRV_MEM_ADDR

SDCAS D4 Output GVDD DRV_MEM_ADDR (1)

SDMA[13–0] E10, F9, D9, F8, E8, D8, B8, E7, C7,

B7, A7, B6, A6, A5 Output GVDD DRV_MEM_ADDR (4)(5)

SDRAS B4 Output GVDD DRV_MEM_ADDR (1)

WE A3 Output GVDD DRV_MEM_ADDR

EPIC Control Signals

INT Y22 Output OVDD DRV_CPU (16)

IRQ_0 / S_INT U24 Input OVDD –

IRQ_1 / S_CLK C24 I/O OVDD DRV_PCI

IRQ_2 / S_RST T21 I/O OVDD DRV_PCI

IRQ_3 / S_FRAME U20 I/O OVDD DRV_PCI

IRQ_4/ L_INT V22 I/O OVDD DRV_PCI

Two-wire Interface Control Signals

SCL AB25 I/O OVDD DRV_CPU (8)(12)

SDA AB24 I/O OVDD DRV_CPU (8)(12)

Clock Signals

CKO V20 Output OVDD DRV_PCI

CPU_CLK[0–2] AA12, AA13, AB12 Output BVDD DRV_MEM_ADDR (4)

OSC_IN U22 Input OVDD –

PCI_CLK[0–4] R25, P24, R24, N24, N25 Output OVDD DRV_MEM_ADDR (4)

PCI_SYNC_IN P20 Input OVDD –

PCI_SYNC_OUT P25 Output OVDD DRV_MEM_ADDR

SDRAM_CLK[0–3] D14, D13, E12, E14 Output GVDD DRV_MEM_ADDR (4)

SDRAM_SYNC_IN E13 Input GVDD –

SDRAM_SYNC_OUT D12 Output GVDD DRV_MEM_ADDR

Miscellaneous Signals

HRESET AA23 Input OVDD –

HRESET_CPU AB21 Output BVDD DRV_CPU (10)(12)

MCP AE20 Output OVDD DRV_CPU (12)(16)

NMI AC25 Input OVDD –

QACK AE18 Output BVDD DRV_CPU (10)

QREQ M4 Input BVDD –

SRESET Y18 Output BVDD DRV_CPU (10)

Table 1. PC107A Pinout Listing (Continued)

Signal Name Package Pin Number Pin Type Supply

Voltage Output Driver Type Notes

8PC107A [Preliminary] 2137C–HIREL–03/04

Test/Configuration Signals

PLL_CFG[0–3] AC22, AD23, AD22, AE23 Input OVDD –(2)(4)

TCK W24 Input OVDD –(7)(10)

TDI Y25 Input OVDD –(7)(10)

TDO W23 Output OVDD DRV_PCI

TEST AA25 Input OVDD –(7)(10)

TEST1 V24 Input OVDD –(8)

TEST2 D6 Input GVDD –(9)

TMS Y24 Input OVDD –(7)(10)

TRIG_IN W22 Input OVDD –

TRIG_OUT W21 Output OVDD DRV_CPU (10)

TRST AA24 Input OVDD –(7)(10)(14)

Power and Ground Signals

AVDD AE24 Input – –

GND

AA21, AB22, AC11, AC14, AC17,

AC20, AC23, AC3 , AC5, AC8, AD24,

AE25, C12, C15, C18, C21, C23, C3,

C6, C9, E3, F10, F16, F20, F23, F6,

G11, G13, G15, G18, G8, H19, H3,

H7, J23, K20, K6, L19, L3, L7, M23,

N19, N7, P3, R19, R23, R7, T20, T6,

U3, V19, V23, V7, W11, W13, W15,

W18, W8, Y10, Y16, Y19, Y20, Y3, Y6

Input – –

GVDD

B2, C5, C8, C11, C14, C17, C20, E5,

E9, E11, E15, E17, F3, G7 , G9, G12,

G14, G17, G19, J3, J5, J7, L5, M3, M7 Input – –

LAVDD F7 Input – –

LVDD D22, F22, H22, K22, N22, T22 Input – –

OVDD

B24, E21, E23, H23, J19, J21, L21,

L23, M19, P19, P23, R21, U19, U21,

U23, Y23 Input – –

BVDD

P7, R3, R5, U5, U7, V3, W7, W9,

W12, W14, W17, AA3, AA5, AA9,

AA11, AA15, AA17, AC6, AC9, A C 12,

A C15, AC18, AC21, AD2

Input – –

VDD

K19, W16, T19, G10, G16, K7, T7,

W10, W19, W20, Y21, AA22, AB23,

A C24, AD25 Input – –

Manufacturing Pins

FTP[2–3] R20, D24 I/O OVDD DRV_PCI (4)(8)

MTP[1–2] B12, B13 I/O GVDD DRV_MEM_ADDR (4)(9)

Table 1. PC107A Pinout Listing (Continued)

Signal Name Package Pin Number Pin Type Supply

Voltage Output Driver Type Notes

PC107A [Preliminary]

2137C–HIREL–03/04

Notes: 1. This pin has an inter nal pull-up resistor which is enabled only when th e PC107A is in the reset state. The value of the inter-

nal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic "1" is read into configuration bits during reset.

2. This pin is a reset configuration pin.

3. MDL[0] is a reset configuration pin and has an internal pull-up resistor which is enabled only when the MPC107 is in the

reset state.The value of the inter nal pull-up resistor is not guaranteed, but is sufficient to insure that a logic '1' is read into

configuration bits during reset.

4. Multi-pin signals such as AD[0–31] or DL[0–31] have their ph ysical pac kage pin numbers listed in order corresponding to the

signal names. Ex: AD0 is on pin D21, AD1 is on pin D23,... AD31 is on pin N23.

5. SDMA[10–1] are reset confi guration pins and h ave internal pul l-up resi sto rs which a re en abled only when the MPC1 07 i s in

the reset state.The values of the internal pull-up resisto rs is not guaranteed, but are sufficient to ensure that logic "1"s are

read into the configuration bits during reset.

6. Recommend a weak pull-up resistor (2 kΩ– 10 kΩ) be placed on this PCI control pin to LVDD.

7. VIH and VIL for these signals are the same as the PCI VIH and VIL entries in Table 7, “DC Electrical Specifications.”

8. Recommend a weak pull-up resistor (2 kΩ – 10 kΩ) be placed on this pin to OVDD.

9. Recommend a weak pull-up resistor (2 kΩ – 10 kΩ) be placed on this pin to GVDD.

10.This pin has an internal pull-up resistor; the v alue of the internal pull-up resistor is not guaranteed, but is sufficient to pre v ent

unused inputs from floating.

11.This pin is affected by programmable PCI_HOLD_DEL parameter, see “PCI Signal Output Hold Timing” on page 29.”

12.This pin is an open drain signal.

13.This pin is a sustained tri-state pin as defined by the PCI Local Bus Specification.

14.See “Connection Recommendations” on page 43 for additional information on this pin.

15.A weak pull-up resistor is recommend (2 kΩ – 10 kΩ) to be placed on this pin to BVDD.

16.If BVDD = 2.5V ±5%, this microprocessor interface pin needs to be DC voltage level shifted from OVDD (3.3 ±0.3V) to 2.5V

±5%; this can typically be accomplished with a two resistor voltage divider circuit since the signal is an output only signal.

10 PC107A [Preliminary] 2137C–HIREL–03/04

Signal Description

Figure 2. PC107A Microprocessor Signal Groups

32 A[0-31]

1AACK

1ARTRY

1BG0

1BG1

1BR0

1BR1

1CI

1DBG0

1DBG1

1DBGLB

32 DLL[0-31] 60x

Processor Interface Signals

32 DL[0-31]

1GBL

1LBCLAIM

1TA

1TBST

1TEA

1TS

3TSIZ[0-2]

5TT[0-4]

1WT

32 AD[0-31]

4C/BE[0-3]

1DEVSEL

1FRAME

5GNT[0-4]

1IDSEL

1INTA

IRDY

1PAR

1PERR

6REQ[0-4]

1SERR

PCI Interface Signals

STOP

1TRDY

1LOCK

Memory Interface Signals

CAS/DQM[0-7]

CKE

FOE

SDRAS

SDMA[13-0]

SDcAS

SDBA1

SDBA0

MDH[0-31]

MDL[0-31]

PAR/AR[0-7]

RAS/CS[0-7]

RCS0

RCS1

RCS2

RCS3

EPIC Control Signals

INT

IRQ_0/S_INT

IRQ_1/S_CLK

IRQ2_2/S_RST

IRQ_3/S_FRAME

IRQ_4/L_INT

SCL

SDA

Two-wire Interface Control Signals

CPUCLK[0-2]

CKO 1

OSC_IN 1

PCI_CLK[0-4] 5

Clock Signals PCI_SYNC_IN 1

PCI_SYNC_OUT 1

SDRAM_CLK[0-3]

SDRAM_SYNC_IN 1

SDRAM_SYNC_OUT 1

HRESET

HRESET_CPU

MCP

NMI

QACK

QREQ

SRESET Test/Configuration Signals

PLL_CFG[0-3]

TCK

TDI

TDO

TEST

TEST1

TEST2

TMS

TRIG_IN

TRIG_OUT

TRST

AVdd

GND

GVdd

LAVdd

LVdd

OVdd

BVdd

Vdd

FTP[2-3]

2MTP[1-2]

Miscellaneous Signals

Power and Ground Signals

Manufacturing Pins

8DL[0-7]

PC107A [Preliminary]

2137C–HIREL–03/04

Detailed Specification

Scope This drawing describes the specific requirements for the PC107A, in compliance with

Atmel standard screening.

Applicable

Documents 1. MIL-STD-883: Test methods and procedures for electronics.

2. SQ32S0100.0: Quality levels for supplied components.

Requirements

General The microcircuits are in accordance with the applicable documents and as specified

herein.

Design and Construction

Terminal Connections The terminal connections are shown in Ta ble 1, “PC107A Pinout Listing,” on page 5.

Absolute Maximum Ratings The tables in this section describe the PC107A DC electrical characteristics. Table 2

provides the ab so lut e ma xim u m ra tin gs .

Notes: 1. Functional and tested operating conditi ons are given in Table 3. Absolute maximum

ratings are stress ratings only and fun ctional operation at the maximums is not guar-

anteed. Stresses bey ond those listed may aff ect de vice reliability or cause permanent

damage to the device.

2. PCI inputs with LVDD = 5V ± 5% V DC may be correspondingly stressed at voltages

exceeding LVDD + 0.5V DC.

Table 2. Absolute Maximum Ratings

Symbol Characteristic(1) Value Unit

VDD Supply Voltage – Core -0.3 to 2.75 V

GVDD Supply Voltage – Memory Bus Drivers -0.3 to 3.6 V

BVDD Supply Voltage – Processor Bus Drivers -0.3 to 3.6 V

OVDD Supply Voltage – PCI and Standard I/O Buffers -0.3 to 3.6 V

AVDD/LAVDD Supply Voltage – PLLs and DLL -0.3 to 2.75 V

LVDD Supply Voltage – PCI Reference -0.3 to 5.4 V

VIN Input Voltage(2) -0.3 to 3.6 V

TJOperational Die-Junction Temperature Range -55 to 125 °C

TSTG Storage Temperature Range -55 to 150 °C

12 PC107A [Preliminary] 2137C–HIREL–03/04

Recommended

Operating Conditions Table 3 provides the recommended operating conditions for the PC107A.

Notes: 1. PCI pins are designed to withstand LVDD + 0.5V DC when LVDD is connected to a 5.0V DC power supply.

2. PCI pins are designed to withstand LVDD + 0.5V DC when LVDD is connected to a 3.3 V DC power supply.

Cautions:

3. Input voltage (VIN) must not be greater than the supply voltage (VDD/AVDD/LAVDD) by more than 2.5V at all times, including

during power-on reset.

4. OVDD must not exceed VDD/AVDD/LAVDD by more than 1.8V at any time, including during power-on reset. This limit may be

exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

5. VDD/AVDD/LAVDD must not exceed OVDD by more than 0.6V at any time, including during power-on reset. This limit may be

exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

6. BVDD/GVDD must not e xceed VDD/AVDD/LAVDD b y more than 1.8V at an y time, including during power-on reset. This limit may

be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

7. LVDD must not exceed VDD/AVDD/LAVDD by more than 5.4V at any time including during power-on reset. This limit may be

exceeded for a maximum of 20 ms during power-on reset and power-down sequences

8. LVDD must not exceed OVDD by more than 3.6V at any time, including during power-on reset. This limit may be exceeded for

a maximum of 20 ms during power-on reset and power-down sequences.

Table 3. Recommended Operating Conditions

Symbol Characteristic Recommended Value Unit Notes

VDD Supply Voltage 2.5 ±5% V (4)

GVDD Supply Voltages for Memory Bus Drivers 3.3 ±5% V (6)

BVDD Supply Voltages for Processor Bus Drivers 3.3 ±5% V(6)

2.5 ±5%

OVDD I/O Buffer supply for PCI and Standard 3.3 ±0.3 V (4)

AVDD PLL Supply Voltage 2.5 ±5% V (5)

LAVDD DLL Supply Voltage 2.5 ±5% V (5)

LVDD PCI Reference 5.0 ±5% V (7)(8)

3.3 ±0.3 V (7)(8)

VIN Input Voltage PCI Inputs 0 to 3.6 or 5.75 V (1)(2)

All Other Inputs 0 to 3.6 V (3)

TJDie-Junction Temperature -55°C to 125°C°C

PC107A [Preliminary]

2137C–HIREL–03/04

Figure 3 shows the supply voltage sequencing and separation cautions.

Figure 3. Supply Voltage Sequencing and Separation Cautions

Notes: 1. Numbers associated with wa v eform separations correspond to caution numbers listed in Table 3, “Recommended Operating

Conditions,” on page 12.

2. Refer to “Power Supply Voltage Sequencing” on page 42 for additional information.

3. Refer to Table 10 on page 25 for additional information on PLL Relock and reset signal assertion timing requirements.

4. Refer to Table 11 on page 26 for additional inf ormation on reset configu ration pin setup timing requirements.

5. HRESET must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN clock cycle f or the device to be in the

non-reset state.

6. HRESET_CPU negates 217 memory clock cycles after HRESET negates.

OVDD/BVDD/GVDD(LVDD at 3.3V ----)

VDD/AVDD/LAVDD

LVDD at 5V

Time

3.3V

2.5V

5.7

DC Power Supply Voltage

Voltage

Regulator

Delay(2)

Reset

Configuration Pins

HRESET

asserted 255

external memory

Clock cycles

(3)

9 external memory

clock cycles setup time

(4)

HRESET_CPU

HRESET

Vdd Stable

See Note 1 below.

VM = 1.4V

Maximum rise time must be less than

one external memory clock cycle

(5)

100

PLL

Relock

Time

(3)

Power Supply Ramp Up

(2)

14 PC107A [Preliminary] 2137C–HIREL–03/04

Figure 4 shows the undershoot and overshoot voltage of the memory interface of the

PC107A.

Figure 4. Overshoot/Undershoot Voltage

Figure 5 and Figure 6 show the undershoot/overshoot voltage of the PCI interface for

3.3 and 5V signals, respecti vely.

Figure 5. Maximum AC Waveforms for 3.3V Signaling

Gnd

Gnd - 0.3V

Gnd - 1.0V Not to exceed 10%

GVdd

of tSDRAM_CLK

VIH

VIL

GVdd +5%

+3.6V

11 ns

(Min) +7.1V

4 ns

(Max)

4 ns

(Max)

-3.5V

Overvoltage

Waveform

Undervoltage

Waveform

62.5 ns

7.1V p-to-p

(Min)

7.1V p-to-p

(Min)

PC107A [Preliminary]

2137C–HIREL–03/04

Figure 6. Maximum AC Waveforms for 3.3V Signaling

Thermal Information

Package Characteristics Table 4 provides the package thermal characteristics for the PC107A.

Notes: 1. Junction temperature is a function of on-chip power dissipation, package

thermal resistance, mounting site (board) temperature, ambient tempera-

ture, airflow, po we r dissipation of ot her com ponent s o n the bo ard, a nd boa rd

thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed-circuit board per JEDEC

JESD51-8. Board temperature is measured on th e top surface of the board near the

package.

5. Thermal resistance between the die and the case top surf ace without thermal grease.

–

7.1V p-to-p

(Min)

7.1V p-to-p

(Min)

+3.6V

11 ns

(Min) +7.1V

4 ns

(Max)

4 ns

(Max)

-3.5V

Overvoltage

Waveform

Undervoltage

Waveform

62.5 ns

Table 4. FC-PBGA Package Thermal Characteristics

Symbol Characteristic(1) Value Unit

RθJA Junction-to-ambient natural convection(1)(2)

(Single-layer board-1s) 30 °C/W

RθJMA J unction-to-ambient natural convection(1)(3)

(F our-layer board-2s2p) 26 °C/W

RθJMA J unction-to-ambient (at 200 ft/min)(1)(3)

(Single-layer board-1s) 25 °C/W

RθJMA J unction-to-ambient (at 200 ft/min)(1)(3)

(F our-layer board-2s2p) 22 °C/W

RθJB Junction-to-board(4) 20 °C/W

RθJC Junction-to-case(5) < 0.1 °C/W

16 PC107A [Preliminary] 2137C–HIREL–03/04

Package Thermal

Characteristics for HiTCE Table 5 provides the package thermal characteristics for the PC107 HiTCE.

Notes: 1. Nominal values: means computed with nominal geometry and nominal thermal conductivities of materials as given in legend

of each simulation results.

2. In this case thermal resistance junction to case is thermal resistance junction to top of Silicon die, and value almost not

depend from substrate used for land grid array. Value depends strongly on heatin g zone size in Silicon chip assumption. In

present simulations heating zone is 5.8 mm × 3.65 mm that is 42% of die size. Assuming the full die size as unif ormly power

dissipating is not realistic.

Assuming 8.3 mm × 5.15 mm heating zone (85% of die surface) leads to 0.15°C/watt instead of 0.29°C/watt.

Table 5. Package Thermal Characteristics for HiTCE Package(1)

Characteristic

Value

UnitPC107 HiTCE

Ther mal resistance junction to case(2) 0.295 °C/Watt

Thermal resistance junction to bottom of balls 15.8 °C/Watt

Thermal resistance junc tion to board, Jedec JESD51-8 (2s2p board) 18.4 °C/Watt

Thermal resistance junction to ambient, Jedec JESD51-2

(2s2p board = 2 signals + 2 power planes in board) 26.3 °C/Watt

PC107A [Preliminary]

2137C–HIREL–03/04

Thermal Management

Information An estimation of the chip junction temperature, TJ, can be obt ained from the equation:

TJ = TA + (RθJA × PD)

where

TA = ambient temperature for the package (°C)

RθJA = junction-to-ambient thermal resistance (°C/W)

PD = power dissipation in the package (W)

The junction-to- ambien t the rmal resist ance is an indu stry-st andard value tha t provides a

quick and easy estimation of thermal performance. Table 4 has four junction-to-ambient

thermal resistances (RθJA or RθJMA). Two test boards are used: single-signal-layer (1s)

and four-layer boards with two internal planes (2s2p). Which value is closer to the appli-

cation depends on the system board thermal resistance and the density of other high-

power dissipation components.

To illustrate the p rocess, determine the jun ction temperature based on the values pro-

vided in Table 4 for an PC107 that is mounted on a board with many internal planes

using arbitrary values. If the PC107 is doing most of the power dissipation, use RθJMA of

26°C/W given in Table 4. The ambient temperature near the device is 45°C. Suppose

the total typical power dissipation at 100 MHz core frequen cy is 2.1W (see Tabl e 6). The

junction temperature is:

TJ = 45 + (2.1 × 26) = 100°C.

If this value is less than the maximum junction temperature noted in Table 2, th e PC107

will not need a heat sink. If the ambient temperature is higher or the power dissipation is

higher because of faster bus speed, the device will probably need a heat sink.

The PC107 may need a heat sink depending on the system. This section provides ther-

mal management information for the flip chip plastic ball grid array (FC-PBGA) package

for air-cooled applications. Proper thermal control design is primarily dependent on the

system-level desig n–the heat sink, airflow, and thermal in terface mat erial. To r educe the

die-junction temp erature, heat sin ks may be attached to the package by several meth -

ods–spring c lip to holes in the prin ted-circuit board or package, and m ounting clip and

screw assembly (see Figure 7); however, due to the potential large mass of the heat

sink, attachment through the printed-circuit board is suggested. The force of the heat

sink on the die should not exceed 6 lb.

The heat sink surface must be flat without protrusions and must be parallel with the die

as the heat sink is brought into contact to avoid chipping the edges of the die and the

heat sink. Because of the small contact area of the heat sink, it is suggested that the

mounting force be centered over the die.

18 PC107A [Preliminary] 2137C–HIREL–03/04

Figure 7. Package Exploded Cross-Se ctional View with Several Heat Sink Options

The board designer can choose be tween several types of heat sinks to place on the

PC107. There are several commercially available heat sinks for the PC107 provided by

the listvendors:

Aavid Thermalloy 603-224-9988

80 Commercial St.

Concord, NH 03301

Internet: www.aavidthermalloy.com

Alpha Novatech 408-749-7601

473 Sapena Ct. #15

Santa Clara, CA 95054

Internet: www.alphanovatech.com

International Electronic Research Corporation (IERC) 818-842-7277

413 North Moss St.

Burbank, CA 91502

Internet: www.ctscorp.com

Tyco Electronics 800-522-6752

Chip Coolers™

P.O. Box 3668

Harrisburg, PA 17105-3668

Internet: www.chipcoolers.com

Wakefield Engineering 603-635-5102

33 Bridge St.

Pelham, NH 03076

Internet: www.wakefield.com

Ultimately, the final selection of an appropriat e heat sink depe nds on many factors, such

as thermal performance at a given air velocity, spatial volume, mass, attachment

method, assembly, and cost.

FC-PBGA Package

Heat Sink

Clip

Thermal Interface Material

Printed-Circuit Board

PC107A [Preliminary]

2137C–HIREL–03/04

Internal Package Conduction

Resistance For the PBGA packaging technology, the in trinsic conduction thermal resistance paths

are as follows:

• The die junction-to-case thermal resistance,

• The die junction-to-ball thermal resistance.

Figure 8 depicts the primary heat transfer path for a package with an attached heat sink

mounted to a printed-circuit board.

Figure 8. C4 Package with Heat Sink Mounted to a Printed-Circuit Boar d

Note: The internal versus external package resistance

For this PBGA package, he at is dissipated from the component via sev eral concurrent

paths. Heat is conducted through the silicon and may be removed to the ambient air by

convection and/or radiation. In addition, a second, parallel heat flow path exists by con-

duction in parallel through the C4 bumps and the epoxy under-fill, to the plastic

substrate f or further con vection coolin g off the edges. Then from the plastic substrate,

heat is conduct ed via t he lea ds/balls to the ne xt-level interco nnect (p rinted- circuit boar d)

whereupon the primary mode of heat transfer is by convecti on and/or radiation.

External Resistance

External Re sistance

Internal Resistance

Radiation Convection

Heat Sink

Printed-Circuit Board

Thermal Interface Material

Package/Leads

Die Junction

Die/Package

20 PC107A [Preliminary] 2137C–HIREL–03/04

Power Characteristics Table 6 provides the preliminary power consumption estimates for the PC107A. Power

consumption on the PLL supply pin (AVDD) and the DLL supply pin (LAVDD) < 15 mW.

This information is based on characterization data.

Notes: 1. Power is measured with VDD = 2.625V, GVDD = OVDD = BVDD = 3.45V at 0°C and one DIMM populated in test system.

2. All clock drivers enabled.

Table 6. Power Consumption

Mode

PCI_SYNC_IN/Core Frequency (MHz)

Unit Notes

25/50 33/33 33/66 66/100

VDD

Power I/O

Power VDD

Power I/O

Power VDD

Power I/O

Power VDD

Power I/O

Power

Typical 468 923 351 759 644 1087 933 1122 mW (1)(2)

Doze 176 697 118 636 235 800 350 915 mW (1)(2)

Nap 139 744 93 693 185 420 276 970 mW (1)(2)

Sleep 79 718 45 677 102 841 138 939 mW (1)(2)

PC107A [Preliminary]

2137C–HIREL–03/04

Electrical

Characteristics This section provides the AC and DC electrical specifications and thermal characteris-

tics for the PC107A.

Static Characteristics

DC Electrical Specification Table 7 provides the DC electrical characteristics for the PC107A.

At recommended operating condition s (see Table 3 on page 12)

Notes: 1. These specifications are for the default driver strengths indicated in Table 8 on page 22.

2. See Figure 23 on page 35 for pins with internal pull-up resistors.

3. The minimum Input high voltage is not compliant with the PCI Local Bus Specification (Re v 2.1) which specifies 0.5*O VDD for

minimum input high voltage.

4. Leakage current is measured on input pins and on output pins in the high impedance state. The leakage current is mea-

sured for nominal OVDD/LVDD and VDD or both OvDD/LVDD and VDD must vary in the same direction.

5. See Table 8 on page 22 for the typical drive capability of a spec ific signal pin based upon the type of output driver associ-

ated with that pin as listed in Table 1 on page 5.

6. Capacitance is periodically sampled rather than 100% tested.

Table 7. DC Electrical Specifications

Characteristics Conditions(1) Symbol

Value

UnitMin Max

Input High Voltage(2)(3) PCI only VIH 0.65*OVDD(3) LVDD V

Input Low Voltage PCI only VIL –0.3*OV

DD V

Input High Voltage(2) All other pins (GVDD = 3.3V) VIH 2.0 – V

Input High Voltage(2) All other pins (BVDD = 2.5V) VIH 1.7 – V

Input Low Voltage All inputs except PCI_SYNC_IN VIL GND 0.8 V

PCI_SYNC_IN Input High Voltage CVIH 2.4 – V

PCI_SYNC_IN Input Low Voltage CVIL GND 0.4 V

Input Leakage Current for pins

using DRV_PCI driver(4) 0.5V ≤ VIN ≤ 2.7V

at LVDD = 4.75 IL–± 70 µA

Input Leakage Current all others(4) LVDD = 3.6V (GVDD ≤ 3.465) IL–± 10 µA

Output High Voltage(5) IOH = Driver Dependent(5) (GVDD = 3.3V) VOH 2.4 – V

Output Low Voltage(5) IOL = Driver Dependent(5) (GVDD = 3.3V) VOL –0.4V

Output High Voltage(5)

IOH = Driver Dependent(5) (BVDD = 2.5V)

All outputs except CPU_CLKS[0-2] VOH 1.85 – V

IOH = Driver Dependent(5) (BVDD = 2.5V)

CPUCLKS[0-2] Only VOH 2.0 – V

Output Low Voltage(5)

IOL = Driver Dependent(5) (BVDD = 2.5V)

All outputs except CPU_CLK[0-2] VOL –0.4V

IOL = Driver Dependent(5) (BVDD = 2.5V)

CPU_CLK[0-2] Only VOL –0.3V

Capacitance(6) VIN = 0V, f = 1 MHz CIN –7.0

22 PC107A [Preliminary] 2137C–HIREL–03/04

Output Driver Characteristics Table 8 provides information on the characteristics of the output drivers referenced in

Table 1 on page 5. The values are from the PC107A IBIS model (v1.1) and are not

tested, for additional detailed information see the complete IBIS model listing at

http://www.motorola.com/semiconductor.

Notes: 1. For DRV_PCI, IOH read from the IBIS listing in the pull-up mode, I(Min) column, at the 0.33V la bel by inter polating between

the 0.3V and 0.4V table entries’ curre nt values which corresponds to the PCI VOH = 2.97 = 0.9*OVDD (OVDD = 3.3V) where

Table Entry Voltage = OVDD - PCI VOH.

2. For all others with GVDD or BVDD = 3.3V, IOH read from the IBIS listing in the p ull-up mode, I(Min) column, at the 0.9V table

entr y which corresponds to the VOH = 2.4V where Table Entry Voltage = G/BVDD - VOH.

3. For all others with BV DD = 2.5V, IOH read from the IBIS listing in the pull-up m ode, I(Min) column, at the 0.65V ta ble entr y by

interpolating between the 0.6V and 0.7V table entries’ current values which corresponds to the VOH = 1.85V where Table

Entry Voltage = BVDD - VOH.

4. For DRV_PCI, IOL read from the IBIS listing in the pull-down mode, I(Min) column, at 0.33V = PCI VOL = 0.1*OVDD (OVDD =

3.3V) by interpolating between the 0.3V and 0.4V table entries.

5. F or all others with GVDD or BVDD = 3.3V, IOL read from the IBIS listing in the pull-down mode, I(Min) column, at the 0.4V table

entry.

6. For all others with BVDD = 2.5V, IOL read from the IBIS listi ng in the pull-down mode, I(Min) column, at the 0.4V table entry.

7. For BVDD = 2.5V, the IOH and IOL values are estima ted from the io_mem_da ta_XX_2.5 and io_mem_addr_XX_2.5 sections

of the IBIS model where XX = driver output impedance (20 or 40 Ω).

Table 8. Drive Capability of PC107A Output Pins

Driver Type Programmable Output

Impedance (Ohms) Supply

Voltage IOH IOL Unit Notes

DRV_CPU

20 BVDD = 3.3V 36.6 18.1 mA (2)(5)

BVDD = 2.5V 21.4 15.6 mA (3)(6)(7)

40 (default) BVDD = 3.3V 18.6 9.2 mA (2)(5)

BVDD = 2.5V 10.8 7.9 mA (3)(6)(7)

DRV_PCI 25 OVDD = 3.3V 12.0 12.4 mA (1)(4)

50 (default) OVDD = 3.3V 6.1 6.3 mA (1)(4)

DRV_MEM_ADDR

DRV_PCI_CLK

8 (default) GVDD = 3.3V 89.0 42.3 mA (2)(5)

13.3 GVDD = 3.3V 55.8 26.4 mA (2)(5)

20 GVDD = 3.3V 36.6 18.1 mA (2)(5)

40 GVDD = 3.3V 18.6 9.2 mA (2)(5)

DRV_MEM_DATA 20 (default) GVDD = 3.3V 36.6 18.1 mA (2)(5)

40 GVDD = 3.3V 18.6 9.2 mA (2)(5)

PC107A [Preliminary]

2137C–HIREL–03/04

Dynamic Electrical

Characteristics

Clock AC Specifications Table 9 provides the clock AC timing specifications as defined in Section.

At recommended operating conditions (see Table 3 on page 12) with GVDD = 3.3V ± 5%

and LVDD = 3.3 ±0.3V

Notes: 1. These specifications are for the default driver strengths indicated in Table 8 on page 22.

2. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4V to 2.4V.

3. Specification value at maximum frequency of operation.

4. Relock time is guaranteed by design and characterization. Relock time is not tested.

5. Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input r ise a nd fall times are

not tested.

6. Relock timing is guaranteed by design. PLL-relock time is the ma ximum amount of time required for PLL lock after a stable

VDD and PCI_SYNC_IN are reached dur ing th e reset sequen ce. This specification also applies when the PLL has been dis-

abled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a mini mu m of 255

bus clocks after the PLL-relock time during the reset sequence.

7. DLL_STANDARD is bit 7 of the PMC2 register <72>. N is a non-zero integer (1 or 2). Tclk is the period of one

SDRAM_SYNC_OUT clock cycle in ns. tloop is the propagation delay of the DLL synchronization feedback loop (PC board

runner) from SDRAM_SYNC_OUT to SD RAM_ SYNC_IN in ns; 6.25 inches of loop length (unloaded PC board runner) cor-

responds to approximately 1 ns of delay. See Figure 12 on page 25 for DLL locking ranges.

8. See Table 19 on page 41 for PCI_SYNC_IN input frequency range for specific PLL_CFG[0–3] settings.

Table 9. Clock AC Timing Specifications

Num Characteristics and Condition s (1) Min Max Unit Notes

1a Frequency of Operation (PCI_SYNC_IN) 12.5 66 MHz (8)

1b PCI_SYNC_IN Cycle Time 80 15 ns (8)

2, 3 PCI_SYNC_IN Rise and Fall Times – 2.0 ns (2)

4 PCI_SYNC_IN Duty Cycle Measured at 1.4V 40 60 %

5a PCI_SYNC_IN Pulse Width High Measured at 1.4V 6 9 ns (3)

5b PCI_SYNC_IN Pulse Width Low Measured at 1.4V 6 9 ns (3)

7 PCI_SYNC_IN Jitter – < 150 ps

9a PCI_CLK[0–4] Skew (Pin to Pin) – 500 ps

9b SDRAM_CLK[0–3] Ske w (Pin to Pin) – 350 ps

9c CPU_CLK[0–2] Skew (Pin to Pin) – 350 ps

9d SDRAM_CLK[0–3]/CPU_CLK[0–2] Jitter – 150 ps

10 Internal PLL Relock Time – 100 µs (3)(4)(6)

15 DLL lock range with DLL_STANDARD = 1 (default) See Figure 11 on page 24 ns (7)

16 DLL lock range with DLL_STANDARD = 0 See Figure 12 on page 25 ns (7)

17 Frequency of Operation (OSC_IN) 12.5 66 MHz (8)

18 OSC_IN Cycle Time 80 15 ns (8)

19 OSC_IN Rise and Fall Times – 5 ns (5)

20 OSC_IN Duty Cycle Measured at 1.4V 40 60 %

21 OSC_IN Frequency Stability – 100 ppm

24 PC107A [Preliminary] 2137C–HIREL–03/04

Figure 9 shows the PCI_SYNC_IN Input Clock Timing Diagra m, Figure 10 illustrates

how Table 9 clock specifications relate to the PC107A Clocking diagram, and Figure

shows the DLL Locking Range Loop Delay vs. Frequency of Operation.

Figure 9. PCI_SYNC-IN Inpu t Clock Timing Diagram

Figure 10. Clock Subsystem Block Diagram

Note: Specification numbers are from Table 9.

Figure 11. DLL Locking Range Loop Delay (DLL_Standard = 0)

5a 5b

VMPCI_SYNC_IN VM VM CVIH

CVIL

VM = Midpoint Voltage (1.4V)

DLL

PLL

Core Logic

sys_logic_clk

PCI_CLK[0:4]

PCI_SYNC_OUT

PCI_SYNC_IN

SDRAM_CLK[0:3]

SDRAM_SYNC_OUT

SDRAM_SYNC_IN

OSC_IN

CPU_CLK[0:2]

MPC107 Specs. 9c,9d

Specs. 9b,9d

Specs. 1 - 7

Spec. 9a

Specs. 17 - 23

Spec. 10

Specs. 15,16

0 5 10 15

Tloop Propagation Delay Time (ns)

Tclk SDRAM_SYNC_OUT Period (ns)

Tclk = 0.7 x Tloop + 3.96 ns

Tclk = 0.6 x Tloop + 9.27 ns

Tclk = 2.2 x Tloop + 11.88 ns

Tclk = 1.8 x Tloop + 27.9 ns

PC107A [Preliminary]

2137C–HIREL–03/04

Figure 12. DLL Locking Range Loop Delay (DLL_Standard = 1)

Operating Frequency This section prov ides the AC ele ctrical ch aracter istics for th e PC107A. Af ter fabricat ion,

functional parts are sorted by maximum core frequency as shown in Figure 10 and

“Clock AC Specifications” on page 23 and tested for conformance to the AC specifica-

tions for that fr equency. The core frequency is determine d by the bus (PCI_SYNC_IN)

clock frequency and the settings of the PLL_CFG[0–3] signals. Parts are sold by maxi-

mum processor core frequency; see “Ordering Information” on page 46.

Table 10 provides the operating frequency information for the PC107A.

At recommended oper ating condition s (see Table 3 on page 12) with LVDD = 3.3 ±0.3V.

Note: 1. Caution: The PCI_SYNC_IN frequency and PLL_CFG[0– 3] settings must be chosen

such that the resulting peripheral logic/memory bus frequency, CPU (core) frequency,

and PLL (VCO) frequencies do not exceed their respective maximum or minimum

operating frequencies. Refer to the PLL_CFG[0–3] signal description in “Clock Rela-

tionships Choice” on page 41 for valid PLL_CFG[0–3] settings and PCI_SYNC_IN

frequencies.

0 5 10 15

Tloop Propagation Delay Time (ns)

Tclk = 0.9 x Tloop + 13.95 ns

Tclk SDRAM_SYNC_OUT Period (ns)

Tclk = 0.45 x Tloop + 6.98 ns

Tclk = 0.55 x Tloop + 2.97 ns

Tclk = 1.1 x Tloop + 5.94 ns

Table 10. Operating Frequency

Characteristic(1)

66 MHz 100 MHz

UnitMinMaxMinMax

Core (memory bus/processor bus) frequency 25 66 25 100 MHz

PCI input frequency (PCI_SYNC_IN) 12.5 – 66 MHz

26 PC107A [Preliminary] 2137C–HIREL–03/04

Input AC Timing

Specifications Table 11 provides the input AC timing specification s. See Figure 13 on page 27 a nd Fig-

ure 14 on page 27.

At recommended operating conditions (see Table 3 on page 12) with GVDD = 3.3V ±5%

and LVDD = 3.3 ±0.3V

Notes: 1. All memory, processor and related interface input signal specifications are measured from the TTL level (0.8 or 2.0V) of the

signal in question to the V M = 1.4V of the rising edge of the memor y bus clock, SDRAM_SYNC_IN. SDRAM_SYNC_IN is

the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memor y bus clock rising edges

occur on every rising and falling edge of PCI_SYNC_IN). See Figure 13.

2. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4*O VDD of the signal in question for 3.3 V

PCI signaling levels. See Figure 14.

3. Input timings are measured at the pin.

4. tCLK is the time of one SDRAM_SYNC_IN clock cycle.

5. All mode select input signals specifications are measured from the TTL level (0.8 or 2.0V) of the signal in question to the

VM = 1.4V of the rising edge of the HRESET signal. See Figure 15 on page 27.

Table 11. Input AC Timing Specifications

Num Characteristics Min Max Unit Notes

10a PCI Input Signals

Valid to PCI_SYNC_IN (Input Setup) 3.0 – ns (2)(3)

10b Memory Interface Signals

Valid to SDRAM_SYNC_IN (Input Setup) 2.0 – ns (1)(3)

10c Epic, Misc. Debug Input Signals

Valid to SDRAM_SYNC_IN (Input Setup) 2.0 – ns (1)(3)

10d Two-wire interface Input Signals

Valid to SDRAM_SYNC_IN (Input Setup) 2.0 – ns (1)(3)

10e Mode select Inputs

Valid to HRESET (Input Setup) 9*tCLK –ns

(1)(3)(5)

10f 60x Processor Inte rface Signals

Valid to SDRAM_SYNC_IN (Input Setup) 2.0 – ns (1)(3)

11a1 PCI_SYNC_IN (SDRAM_SYNC_IN) to Inputs Invalid (Input Hold) 1.0 – ns (2)(3)

11a2 Memory Interface Signals

SDRAM_SYNC_IN to Inputs Invalid (Input Hold) 0.5 – ns (1)(3)

11a3 60x Processor Interface Signals

SDRAM_SYNC_IN to Inputs Invalid (Input Hold) 0–ns

(1)(3)

11b HRESET to Mode select Inputs Invalid (Input Hold) 0 – ns (1)(3)(5)

PC107A [Preliminary]

2137C–HIREL–03/04

Figure 13. Input – Output Timing Diagram Referenced to SDRAM_SYNC_IN

Figure 14. Input – Output Timing Diagram Referenced to PCI_SYNC_IN

Figure 15. Input Timing Diagram for Mode Select Signals

11a

VM = Midpoint Voltage (1.4V)

MEMORY

PCI_SYNC_IN

INPUTS/OUTPUTS

13b

14b

SDRAM_SYNC_IN

shown in 2:1 mode

Input Timing Output Timing

2.0V

0.8V

2.0V

10b-d

12b-d

OVdd/2

10a

11a

PCI_SYNC_IN

PCI

12a 13a

14a

OVdd/2

0.4*OVdd 0.615*OVdd

0.285*OVdd

Input Timing Output Timing

INPUTS/OUTPUTS

VM = Midpoint Voltage (1.4V)

11b

MODE PINS

10e

HRESET

2.0V

0.8V

28 PC107A [Preliminary] 2137C–HIREL–03/04

Output AC Timing

Specification Table 12 provides the processor bus AC timing specifications for the PC107A. See Fig-

ure 13 on page 27 and Figure 14 on pa ge 27.

At recommended oper ating condition s (see Table 3 on page 12) with LVDD = 3.3 ±0.3V

Notes: 1. All memory and related interface output signal specifications are specified from the VM = 1.4V of the rising edge of the mem-

or y bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0V) of the signal in question. SDRAM_SYNC_IN is the same as

PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on

every rising and falling edge of PCI_SYNC_IN). See Figure 13 on page 27.

2. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.285*OVDD or 0.615*O VDD of the signal in

question for 3.3V PCI signaling levels. See Figure 14 on page 27.

3. All output timings assume a purely resistive 50Ω load (See Figure 16 on page 28). Outp ut timings are measured at the pin;

time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

4. PCI Bussed signals are comp osed of the following signals: LOCK, IRDY, C/BE[0–3], PAR, TR DY, FRAME, STOP, DEVSEL,

PERR, SERR, AD[0–31], REQ[4–0], GNT[4–0], IDSEL, INTA.

5. PCI hold times can be varied, see “PCI Signal Output Hold Timing” on page 29 for information on programmable PCI output

hold times. The values shown for item 13a are for PCI compliance.

6. These specifications are for the default driver strengths indicated in Table 8 on page 22.

Figure 16. AC Test Load for the PC107A

Table 12. Output AC Timing Specifications

Num Characteristics(3)(6) Min Max Unit Notes

12a

PCI_SYNC_IN to Output Va lid, 66 MHz PCI, with SDMA4 pulled-

down to logic 0 state. See Figure 17. –6.0ns

(2)(4)

PCI_SYNC_IN to Output Valid, 33 MHz PCI, with SDMA4 in the

default logic 1 state. See Figure 17. – 11.0 ns (2)(4)

12b Memory Interface Signals, SDRAM_SYNC_IN to Output Valid – 5.5 ns (1)

12b1 Memory Interface Signal: CKE (100 MHz Device),

SDRAM_SYNC_IN to Output Valid –5.5ns

(1)

12b2 Memory Interface Signal: CKE (66 MHz Device),

SDRAM_SYNC_IN to Output Valid –6.0ns

(1)

12c Epic, Misc. Debug Signals, SDRAM_SYNC_IN to Output Valid – 9.0 ns (1)

12d Two-wire interface, SDRAM_SYNC_IN to Output Valid – 5.0 ns (1)

12e 60x Processor Interface Signals, SDRAM_SYNC_IN to Output Valid – 5.5 ns (1)

13a

Output Hold, 66 MHz PCI, with SDMA4 and SDMA3 pulled-down to

logic 0 states. See Table 13. 1.0 – ns (2)(4)(5)

Output Hold, 33 MHz PCI, with SDMA4 in the default logic 1 state

and SDMA3 pulled-down to logic 0 state. See Table 13. 2.0 – ns (2)(4)(5)

13b Output Hold (For All Others) 1 ns (1)

14a PCI_SYNC_IN to Output High Impedance (Toff for PCI) – 14.0 ns (2)(4)

14b SDRAM_SYNC_IN to Output High Impedance (For All Others) – 4.0 ns (1)

OUTPUT Z0 = 50ΩOVdd/2

RL = 50Ω

Output measurements are made at the device pin.

PC107A [Preliminary]

2137C–HIREL–03/04

PCI Signal Output Hold

Timing In order to m eet minimum output hold specifications relative to PCI_SYNC_IN for both

33 MHz and 66 MHz PCI systems, the PC107A has a programmable output hold delay

for PCI signals. The initial value of the output hold delay is determined by the values on

the SDMA4 and SDMA3 reset configuration signals. Furthe r output hold delay values

are available by programming the PCI_HOLD_DEL value of the PMCR2 configuration

Table 13 describes the bit values for the PCI_HOLD_DEL values in PMCR2.

Table 13. Power Management Configuration Register 2-0x72

Bit Name Reset value Description

6 – 4 PCI_HOLD_DEL xx0 PCI output hold delay v alues relative to PCI_SYNC_IN. The initial values of bits 6 and 5

are determined by the reset configuration pins SDMA4 and SDMA3, respectively. As

these two pins have internal pull-up resistors, the def ault value after reset is 0b110.

While the minimum hold times are guaranteed at shown values, changes in the actual

hold time can be made by incrementing or decrementing the value in these bit fields of

this register via software or hardware configuration. The increment is in approximately

400 picosecond steps. Lowering the value in the three bit field decreases the amount of

output hold available.

000 66 MHz PCI. Pull-down SDMA4 configuration pi n w ith a 2 kΩ or less

value resistor. This setting guarantees the minimum output hold,

item 13a, and the maximum output valid, item 12a, times as specified in

Figure 14 are met for a 66 MHz PCI system. See Figure 17 on page 30.

001

010

011

100 33 MHz PCI. This setting guarantees the minimum output hold,

item 13a, and the maximum output valid, item 12a, times as specified in

Figure 14 are met for a 33 MHz PCI system. See Figure 17 on page 30.

101

110 (Default if reset configuration pins left unconnected)

111

30 PC107A [Preliminary] 2137C–HIREL–03/04

Figure 17. PCI_HOLD_DEL Effect on Output Valid and Hold Time

PCI_SYNC_IN

PCI INPUTS/OUTPUTS

33 MHz PCI

OVdd/2 OVdd/2

12a, 8 ns for 33 MHz PCI

PCI_HOLD_DEL = 100

12a, 6 ns for 66 MHz PCI

PCI_HOLD_DEL = 000

13a, 2 ns for 33 MHz PCI

PCI_HOLD_DEL = 100

13a, 1 ns for 66 MHz PCI

PCI_HOLD_DEL = 000

OUTPUT VALID OUTPUT HOLD Diagram Not to Scale

As PCI_HOLD_DEL

values decrease

As PCI_HOLD_DEL

values increase

PCI INPUTS

and OUTPUTS

PCI INPUTS/OUTPUTS

66 MHz PCI

PC107A [Preliminary]

2137C–HIREL–03/04

Two-wire Interface AC Timing

Specifications Table 14 provides the two-wire interface input AC timing specifications for the PC107A.

At recommended oper ating condition s (see Table 3 on page 12) with LVDD = 3.3 ±0.3V

Notes: 1. Units for these specifications are in SDRAM_CLK/CPU_CLK units.

2. The actual values depend on the setting of the Digital Filter Frequency Sampling Rate (DFFSR) bits in the Frequency

Divider Register two-wire interface FDR. Therefore, the noted timings in the above table are all relative to qualified signals.

The qualified SCL and SDA are delayed signals from what is seen in real time on the two-wire inte rface bus. The qualified

SCL, SDA signals are delayed by the SDRAM_CLK/CPU_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK/C PU_CLK

clock. The resulting delay value is added to the value in the table (where this note is referenced). See Figure 19 on page 34.

3. Timing is relative to the Sampling Clock (not SCL).

4. FDR[x] refers to the Frequency Divider Register I2CFDR bit x.

5. Input clock low and high periods in combination with the FDR value in the Frequency Divider Register (I2CFDR) deter mine

the maximum two-wire interface input frequency. See Figure 19 on page 34.

Table 14. Two-wire Interface Input AC Timing Specifications

Num Characteristics Min Max Unit Notes

1 Start condition hold time 4.0 – CLKs (1)(2)

Clock low period

(The time before the PC107A will driv e SC L l ow as a

transmitting slave after detecting SCL low as driven b y an

e xternal master)

8.0 + (16 × 2FDR[4:2]) × (5 -

4({FDR[5],FDR[1]} == b’10) -

3({FDR[5],FDR[1]} == b’11) -

2({FDR[5],FDR[1]} == b’00) -

1({FDR[5],FDR[1]} == b’01))

–CLKs

(1)(2)(4)(5)

3 SCL/SDA rise time (from 0.5V to 2.4V) – 1 ms

4 Data hold time 0 – ns (2)

5 SCL/SDA fall time (from 2.4V to 0.5V) – 1 mS

6 Clock high period

(Time needed to either receive a data bit or generate a

START or STOP) 5.0 – CLKs (1)(2)(5)

7 Data setup time 3.0 – ns (3)

8 Start conditio n setup time (for repeated start condition

only) 4.0 – CLKs (1)(2)

9 Stop conditi o n setup time 4.0 – CLKs (1)(2)

32 PC107A [Preliminary] 2137C–HIREL–03/04

Table 15 provides the two-wire interface Frequency Divider Register (I2CFDR) informa-

tion for the PC107A.

At recommended oper ating condition s (see Table 3 on page 12) with LVDD = 3.3V ± 5%

Notes: 1. Values are in kHz unless otherwise specified.

2. FDR Hex and Divider (Dec) values are listed in corresponding order.

3. Multiple Divider (Dec) values will generate the same input frequency but each Divider (Dec) value will generate a unique out-

put frequency as shown in Table 16 on page 33.

Table 15. PC8240 Ma xim u m Two-wire Interf ac e Input Frequency

FDR Hex(2) Divider (Dec)(2)

Max Two-wire Interface Input Frequency(1)

SDRAM_CLK/

CPU_CLK

at 25 MHz

SDRAM_CLK/

CPU_CLK

at 33 MHz

SDRAM_CLK/

CPU_CLK

at 50 MHz

SDRAM_CLK/

CPU_CLK

at 100 MHz

20, 21 160, 192 862 1.13 MHz 1.72 MHz 3.4 4 MH z

22, 23, 24, 25 224, 256, 320, 384 555 733 1.11 MHz 2.22 MHz

0, 1 288, 320 409 540 819 1.63 MHz

2, 3, 26, 27, 28, 29 384, 448, 480, 512, 640,

768 324 428 649 1.29 MHz

4, 5 576, 640 229 302 458 917

6, 7, 2A, 2B, 2C, 2D 768, 896, 960, 1024, 1280,

1536 177 234 354 709

8, 9 1152, 1280 121 160 243 487

A, B, 2E, 2F, 30, 31 1536, 1792, 1920, 2048,

2560, 3072 92 122 185 371

C, D 2304, 2560 62 83 125 251

E, F, 32, 33, 34, 35 3072, 3584, 3840, 4096,

5120, 6144 47 62 95 190

10, 11 4608, 5120 32 42 64 128

12, 13, 36, 37, 38, 39 6144, 7168, 7680, 8192,

10240, 12288 24 31 48 96

14, 15 9216, 10240 16 21 32 64

16, 17, 3A, 3B, 3C, 3D 12288, 14336, 15360,

16384, 20480, 24576 12 16 24 48

18, 19 18432, 20480 8 10 16 32

1A, 1B, 3E, 3F 24576, 28672, 307 20,

32768 681224

1C, 1D 36864, 40960 4 5 8 16

1E, 1F 49152, 61440 3 4 6 12

PC107A [Preliminary]

2137C–HIREL–03/04

Table 16 provides th e two-wire interface output AC timing specifications for the PC107A.

At recommended operating conditions (see Table 3 on page 12) with GVDD = 3.3V ± 5%

and LVDD = 3.3 ±0.3V

Notes: 1. Units for these specifications are in SDRAM_CLK/CPU_CLK units.

2. The actual values depend on the setting of the Digital Filter Frequency Sampling Rate (DFFSR) bits in the Frequency

Divider Register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The qualified

SCL and SDA are delayed signals from what is see n in real time on the two-wire in terface bus. The qualified SCL, SDA sig-

nals are delayed by the SDRAM_CLK/CPU_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK/CPU_CLK clock. The

resulting delay value is added to the value in the table (where this note is referenced). See Figure 19 on page 34.

3. Since SCL and SDA are open-dr ain type outputs, which the PC107A can only drive low, the time required for SCL or SDA to

reach a high level depends on external signal capacitance and pull-up resistor values.

4. Specified at a nominal 50 pF load.

5. DFDR is the decimal divider number indexed by FDR[5:0] value . Ref er to the two-wire Interf ace chapter’s Serial Bit Clock F re-

quency Divider Selections table. FDR[x] refers to the Frequency Divider Register I2CFDR bit x. N is equal to a variable

number that would mak e the result of the divide (Data Hold Time value) equal to a number less than 16. M is equal to a vari-

able number that would make the result of the divide (Data Hold Time value) equal to a number less than 9.

Figure 18. Two-wire Interface Timing Diagram II

Table 16. Two-wire Interface Output AC Timing Spe cif ications

Num Characteristics Min Max Unit Notes

1 Start condition hold time (FDR[5] == 0) × (DFDR/16) / 2N +

(FDR[5] == 1) × (DFDR/16) / 2M –CLKs

(1)(2)(5)

2 Clock low period DFDR / 2 – CLKs (1)(2)(5)

3 SCL/SDA rise time (from 0.5V to 2.4V) – – mS (3)

4 Data hold time

8.0 + (16 × 2FDR[4:2]) × (5 -

4({FDR[5],FDR[1 ]} == b’10) -

3({FDR[5],FDR[1 ]} == b’11) -

2({FDR[5],FDR[1 ]} == b’00) -

1({FDR[5],FDR[1]} == b’01))

–CLKs

(1)(2)(5)

5 SCL/SDA fall time (from 2.4V to 0.5V) – < 5 n s (4)

6 Clock high time DFDR / 2 – CLKs (1)(2)(5)

7 Data setup time (PC107A as a master only) ( DFDR / 2) - (Output data hold time) – CLKs (1)(5)

8Start condition setup time (for repeated start

condition only) DFDR + (Output start condition hold

time) –CLKs

(1)(2)(5)

9 Stop condition setup time 4.0 – CLKs (1)(2)

SCL

SDA

VM VM

1 4

34 PC107A [Preliminary] 2137C–HIREL–03/04

Figure 19. Two-wire Interface Timing Diagram II

Figure 20. Two-wire Interface Timing Diagram III

Note: DFFSR Filter Clock is the SDRAM_CLK clock times DFFSR value.

Figure 21. Two-wire Interface Timing Diagram IV (Qualified Signal)

Note: The delay is the Local Memory clock times DFFSR times 2 plus 1 Local Memory clock.

SCL

SDA

VM VL

INPUT DATA VALID

DFFSR FILTER CLK (1)

SDA

SCL/SDArealtime VM

SCL/SDAqualified VM

Delay (1)

PC107A [Preliminary]

2137C–HIREL–03/04

EPIC Serial Interrupt Mode AC

Timing Specifications Table 17 provides the EPIC serial interru pt mode AC timing specifications for the

PC107A.

At recommended oper ating condition s (see Table 3 on page 12) with LVDD = 3.3 ±0.3V

Notes: 1. See the PC107A User’s Man ual for a description of the EPIC Interrupt Control Register (EICR) describing S_CLK frequency

programming.

2. S_RST, S_FRAME, and S_INT shown in Figure 22 and Figure 23 depict timing relationships to sys_logic_clk and S_CLK

and do not descr ibe functional relationships b etween S_RST, S_FRAME, and S_INT. See the PC107 A User’s Manual for a

complete description of the functiona l relationships between these signals.

3. The sys_logic_clk wa veform is the clocking signal of the internal peripheral logic from the output of the peripheral logic PLL;

sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to SDRAM_SYNC_IN feedback loop is

implemented and the DLL is locked. See the PC107A User’s Manual for a complete clocking description.

Figure 22. EPIC Serial Inte rru p t Mo de Out put Tim i n g Dia gr am

Figure 23. EPIC Serial Interrupt Mode Input Timing Diagram

Table 17. EPIC Serial Interrupt Mode AC Timing Specifications

Num Characteristics Min Max Unit Notes

1 S_CLK Frequency 1/14 SDRAM_SYNC_IN 1/2 SDRAM_SYNC_IN MHz (1)

2 S_CLK Duty Cycle 40 60 %

3 S_CLK Output Valid Time – 6 nS

4 Output Hold Time 0 – nS

5S_FRAME

, S_RST Output Valid Time – 1 sys_logic_clk period + 6 nS (2)

6 S_INT Input Setup Time to S_CLK 1 sys_logic_clk period + 2 – nS (2)

7 S_INT Inputs Invalid (Hold Time) to S_CLK – 0 nS (2)

S_CLK

S_RST

S_FRAME

sys_logic_clk3

S_CLK

S_INT

36 PC107A [Preliminary] 2137C–HIREL–03/04

IEEE 1149.1 (JTAG) AC Timing

Specifications Table 18 provides the JTAG AC timing specifications for the PC107A while in the JTAG

operating mode.

At recommended oper ating condition s (see Table 3 on page 12) with LVDD = 3.3 ±0.3V

Notes: 1. TRST is an asynchronous signal. Th e setup time is for test purposes only.

2. Non-test (other than TDI and TMS) signal input timing with respect to TCK.

3. Non-test (other than TDO) signal output timing with respect to TCK.

4. Timings are independent of the system clock (PCI_SYNC_IN).

Figure 24. JTAG Clock Input Timing Diagram

Figure 25. JTAG TRST Timing Diagram

Table 18. JTAG AC Timing Specifications (Independent of PCI_SYNC_IN)

Num Characteristics(4) Min Max Unit Notes

TCK Fr equency of Operation 0 25 MHz

1 TCK Cycle Time 40 – ns

2 TCK Clock Pulse Width Measured at 1.5V 20 – ns

3 TCK Rise and Fall Times 0 3 ns

4 TRST_ Setup Time to TCK Falling Edge 10 – ns (1)

5 TRST_ Assert Time 10 – ns

6 Boundar y Scan Input Data Setup Time 5 – ns (2)

7 Boundary Scan Input Data Hold Time 15 – ns (2)

8 TCK to Output Data Valid 0 30 ns (3)

9 TCK to Output High Impedance 0 30 ns (3)

10 TMS, TDI Data Setup Time 5 – ns

11 TMS, TDI Data Hold Time 15 – ns

12 TCK to TDO Data Valid 0 15 ns

13 TCK to TDO High Impedance 0 15 ns

TCK

22 1

VMVMVM

33 VM = Midpoint Voltage

TRST

TCK

PC107A [Preliminary]

2137C–HIREL–03/04

Figure 26. JTAG Boundary Scan Timing Diagram

Figure 27. Test Access Port Timing Diagram

INPUT DATA VALID

OUTPUT DATA VALID

TCK

DATA INPUTS

DATA OUTPUTS

INPUT DATA VALID

OUTPUT DATA VALID

10 11

TCK

TDI, TMS

TDO

38 PC107A [Preliminary] 2137C–HIREL–03/04

Preparation for

Delivery

Packaging Microcircuits are prepared for delivery in accordance with internal standards.

Certificate of Compliance Atmel offers a certificate of compliance with each shipment of parts, affirming the prod-

ucts are in compliance either with internal specifications and guaranteeing the

parameters not tested at temper ature extremes for the entire temperature range.

Handling MOS devices must be handled with certain precautions to avoid damage due to accu-

mulation of static charge. Input protection devices have been designed in the chip to

minimize the effect of this static buildup. However, the following han dling practices are

recommended:

• Devices should be handled on benches with conductive and grounded surfaces.

• Ground test equipment, tools and operator.

• Do not handle devices by the leads.

• Store devices in conductive foam or carriers.

• Avoid use of plastic, rubber or silk in MOS areas.

• Maintain relative humidity above 50% if practical.

Package Mechanical

Data

Package Parameters The PC107A uses a 33 mm × 33 mm, 503 pin Plastic Ball Grid Array (PBGA) or HiTCE

package. The pl astic package parameters are as provided in the following list.

Package Outline 33 mm × 33 mm

Interconnects 503

Pitch 1.27 mm

Solder Attach 62 Sn/36 Pb/2 Ag

Solder Balls 62 Sn/36 Pb/2 Ag

Solder Balls Diameter 0.60 mm – 0.90 mm

Maximum Module Height 2.75 mm

Co-planarity Specification 0.20 mm

Maximum Force 6.0 lbs. total, uniformly distributed over package

(5.4 grams/ball)

PC107A [Preliminary]

2137C–HIREL–03/04

Mechanical Dimensions Figure 28 shows the top surface, side profile , and pinout of the PC107A, 50 3 PBGA

package.

Figure 28. PC107A Package Dimensions and Pinout Assignments

24Xe

Notes: 1. Dimensioning and tolerancing per A.

2. Dimensions in millimeters.

3. Dimension b is the maximum solder ball diameter measured parallel to datum A.

4. D2 and E2 define the area occupied on the die and underfill actual size of this area may be smaller than shown.

D3 and E3 are the minimum clearance from the package edge to the chip capacitors.

5. Capacitors may not be present on all devices.

6. Caution must be taken not to short expose metal capacitor pads on package top.

0.2 A

Millimeters

DIM Min Max

A 2.75

A1 0.50 0.70

A2 1.00 1.20

A3 0.80

A4 0.82 0.90

b 0.60 0.90

C 33 GSC

D1 30.48 BSC

D2 12.50

D3 3.43

D4 5.00

e 1.27 BSC

E 33 GSC

E1 30.48 BSC

E2 14.50

E3 3.43

E4 9.00

135791113151719212325

2 6 10 12 14 16

18 20

22 24

ADAC

ABAA

503 x ∅ b

24Xe

0.3

0.15 C

0.2

0.25 A

Side View

Bottom View

0.35 A

12.5 max

5 min

14.5 Max

Top View

9 min

INDEX

0.9

0.821.2

2.75 max

0.7

0.5

503X

SEATING

PLANE

40 PC107A [Preliminary] 2137C–HIREL–03/04

Figure 29. Mechanical Dimensions and Bottom Surface Nomenclature of the 503-b all HiTCE Package

CA B0.3

b (503x)

Bottom View

e (24x)

811

10 13

12 15

14 17

16 19

18 21

20 23 25

22 24

0.2

-A-

D5 (2X)

D3 (2X)

Chamfer: C (4x)

Top View

E3 (2x)

0.2

-B-

E5 (2X)

BALL

INDEX A1

1107

0.2

-C-

A2 A1

Side View

All dimension in mm

2.72

0.80

1.08

–

0.82

32.80

3.72

5.50

1.27 BASIC

32.80

3.72

8.90

3.20

1.00

1.32

–

0.90

0.93

33.20

11.0

3.92

5.70

33.20

14.4

3.92

9.10

Parameter Min Max

30.48 BASIC (1.27 x 24)

PC107A [Preliminary]

2137C–HIREL–03/04

Clock Relationships

Choice The PC107A’s internal PLL is configured by the PLL_CFG[0–3] signals. For a given

PCI_SYNC_IN (PCI bus) frequency, the PLL configuration sig nals set the Core/Mem-

ory/Processor PLL (VCO) frequency of operation for the PCI-to-

Core/Memory/Processor frequency multiplying, if any. All valid PLL configurations for

the PC107A are shown in Table 19.

Notes: 1. PLL_CFG[0–3] settings not listed (00000100, 0110, 0111, 1010, 1011, and 1110) are reserved.

2. In PLL Bypass mode, the PCI_SYNC_IN input signal clocks the internal core directly, the PLL is disabled, and the PCI: core

mode is set for 1:1 mode operation. The AC timing specifications given in this document do not apply in PLL Bypass mode.

3. In Clock Off mode, no clocking occurs inside the PC107A regardless of the PCI_SYNC_IN input.

4. Limited due to maximum memory VCO = 200 MHz.

5. Limited due to minimum VCO = 100 MHz.

6. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity.

7. Limited by maximum memory bus speed.

Table 19. PC107A Microprocessor PLL Configurat ion

Ref PLL_CFG

[0–3](2)

66 MHz Part 100 MHz Part

PCI: Core

Ratio VCO

Multiplier

PCI_SYNC_IN

Range (MHz) Core/Mem/CPU

Range (MHz) PCI_SYNC_IN

Range (MHz) Core/Mem/CPU

Range (MHz)

1 0001 25(5) – 33 25 – 33 25(5) – 50(4) 25 – 50 1 4

2 0010 13(5) – 16(4) 26 – 34 13(5) – 25(4) 26 – 50 2 4

3 0011 Bypass Bypass Bypass Bypass

5 0101 25(5) – 33 50 – 66 25(5) – 50 50 – 100 2 2

8 1000 17(5) – 22 51 – 66 17(5) – 33 50 – 100 3 2

9 1001 34(5) – 44 51 – 66 33(5) – 66 50 – 100 1.5 2

A1010 13(4)–16(7) 52–64 13(4)–25(7) 52–100 42

C 1100 20(5) – 26 50 – 65 20(5) – 40 50 – 100 2.5 2

D 1101 50(5) – 66 50 – 66 50(5) – 66 50 – 66 1 2

F 1111 Clock off(3) Not Usable Clock off (3) Not Usable Off Off

42 PC107A [Preliminary] 2137C–HIREL–03/04

System Design

Information

PLL Power Supply

Filtering The AVDD a nd LAVDD power signals are p rovided on the PC10 7A to pro vide power to the

peripheral logic/memory bus PLL and the SDRAM clock delay-locked loop (DLL),

respectively. To ensure stability of the internal clocks, the power supplied to the AVDD

and LAVDD input signals should be filtered of any noise in the 500 kHz to 10 MHz reso-

nant frequency range of the PLLs. A separate circuit similar to the one shown in Figure

30 using surface mou nt capacitors with minimum effective series induc tance (ESL) is

recommended for ea ch of the AVDD and LAVDD power signal pins. Consistent with the

recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of

Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recom-

mended over using multiple values.

The circuits should be placed as close as possible to the respective input signal pins to

minimize noise coupled from nearby circuits . Routing directly as possible from the

capacitors to the input signal p ins with minimal inductance of vias is important but pro-

portionately less critical for the LAVDD pin.

Figure 30. PLL Power Supply Filter Circuit

Power Supply Voltage

Sequencing The notes in Table 3 on page 12 contain cautions illustrated in Figure 3 on page 13

about the sequencing of the external bus voltages and internal voltages of the PC107A.

These cautions are necessary for the long term reliability of the part. If they are violated,

the electrostatic discharge (ESD) protection diodes will be forward biased and excessive

current can flow through these diodes. Figure 3 shows a typical ramping voltage

sequence where the DC power source s (voltage regulators and/or power supplies) are

connected as shown in Figure 31 . Th e voltage regulator delay shown in Figu re 3 can be

zero if the various DC vo ltage le vels ar e all applie d t o the targ et boa rd at th e same tim e.

The ramping voltage sequence shows a scenario in which the VDD/AVDD/LAVDD power

plane is not loaded as much as the OVDD/GVDD p ower plane and thus VDD/AVDD/LAVDD

ramps at a faster rate than OV DD/GVDD.

If the system power supp ly design does not control the voltage seque ncing, the circuit of

Figure 31 can be added to meet these requirements. The MUR420 diodes of Figure 31

control the maximum potential difference between the 3.3 bus and internal voltages on

power-up and the 1N5820 Schottky diodes regulate the maximum potential difference

on power-down .

Vdd AVdd or LAVdd

10Ω

2.2 µF 2.2 µF

GND

Low ESL surface mount capacitors

PC107A [Preliminary]

2137C–HIREL–03/04

Figure 31. Example Voltage Sequencing Circuits

Decoupling

Recommendations Due to the PC107A’s dynamic power management feature, large address and data

buses, and high operating frequencies, the PC107A can generate transient power

surges and high frequency noise in its power supply, especially while driving large

capacitive loads. This noise must be preve nted from reaching other components in the

PC107A system, and the PC107A itself requires a clean, tightly regulated source of

power. Therefore, it is recommended that the system designer place at least one decou-

pling capacitor at each VDD, OVDD, GVDD, and LVDD pin of the PC107A. It is also

recommended that these decoupling capacitors receive their power from separate VDD,

OVDD, GVDD, and GND power planes in the PCB, utilizing short traces to minimize induc-

tance. These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface

mount technology) capacitors should be used to minimize lead inductance, preferably

0508 or 0603, oriented such that connections are made along the length of the part.

In addition, it is recommended that there be several bulk storage capacitors distributed

around the PCB, feeding the VDD, OVDD, GVDD, BVDD, and LVDD planes, to enable quick

recharging of th e smaller chip capacito rs. These bulk capacitors should have a low ESR

(equivalent series resistance) r at ing to en su re th e q u i ck respons e time necessary. They

should also b e conn ec ted t o the p ower and g round planes through two vias to minimize

inductance. Suggested bulk capacitors-100 – 330 µF (AVX TPS tantalum or Sanyo

OSCON).

Connection

Recommendations To ensure r eliable operation, it is highly recomm ended to con nect unused inp uts to an

appropriate signal level. Unused active low inputs should be tie d to OVDD. Unused active

high inputs should be connected to GND. All NC (no-connect) signals must remain

unconnected.

Power and ground connections must be made to all external VDD, OVDD, GVDD, LVDD,

BVDD, and GND pins of the PC107A.

The PCI_SYNC_OUT signal is intended to be routed halfway out to the PCI devices and

then returned to the PCI_SYNC_IN input of the PC107A.

The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM

devices and then returned to the SDRAM_SYNC_IN input of the PC107A. The trac e

length may be used to ske w or adjust the timing window as n eeded. See Motorola ap pli-

cation note "AN1794/D" for more information on this topic.

The TRST signal must be asserted during reset to ensure proper initialization and oper-

ation of the PC107A. It is recomm ended that the TRST signal be connected to the

system HRESET signal or pulled down with a 100Ω - 1 kΩ resistor.

+ 5V

Source + 3.3V

Source

3.3V

3.3V MUR420 MUR420

IN5820

2.5V

+ 2.5V

Source

44 PC107A [Preliminary] 2137C–HIREL–03/04

Pull-up/Pull-down

Resistor Requirements The data bus input receivers are normally turned off when no read operation is in

progress; there fore , they do not req uir e pull-up resisto rs on the bu s. Th e proc esso r data

bus signals are: DH[0–31], DL[0–31], and PAR[0–7]. The memory data bus signals are:

MDH[0–31], MDL[0–31], an d PAR/A R[0 –7].

If the 32-bit d at a bus mo de is sele cted , th e input r eceiver s of th e u nused da ta an d pa rity

bits (DL[0–31], DP[4–7], MD L[0–31], and PAR[4–7]) will be disabled, and their outputs

will drive logic zeros when they would otherwise normally be driven. For this mode,

these pins do not req uire pull-up resistors, and should be left unconnected by the sys-

tem to minimize possible output switching.

It is recommended that ARTRY, TA, and TS have weak pu ll-up r esistors (2 kΩ – 10 kΩ)

connected to BVDD.

It is recommended that MTP[1–2] and TEST2 have weak pull-up resistor (2 kΩ – 10 kΩ)

connected to GVDD.

It is recommended that the following signals be pulled up to OVDD with weak pull-up

resistors (2 kΩ – 10 kΩ): SDA, SCL, TEST1, and FTP[3–3].

It is recommended that the following PCI control signals be pulled up to LVDD with weak

pull-up resistors (2 kΩ – 10 kΩ): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP,

TRDY and INTA. The resistor values may need to be adjusted stronger to reduce

induced noise on specific board desig ns .

The following pins have internal pull-up resistors enabled at all times: REQ[06–4], TCK,

TDI, TMS, and TRST, BR1, HRESET_CPU, MCP, QACK, SRESET, TEST and

TRIG_OUT. See Table 1, “PC107A Pinout Listing,” on page 5 for more information.

The following pins have internal pull-up resistors enabled only while device is in the

reset state: MDL0, FOE, RCS0, SDRAS, SDCAS, CKE, SDBAO, and SDMA[10–1]. See

Table 1, “PC107A Pinout Listing,” on page 5 for more information.

The following pins are re se t config ur ation pins: MDL 0, FOE, RCS0, SDBAO, SDMA[10–

1], and PLL_CF G[ 0–3]. These pins are sampled during reset to configure the device.

Any other unused active low input pins should be tied to a logic one level via weak pull-

up resistors (2 kΩ – 10 kΩ) to t he appropria te power supp ly listed in Table 3 on page 12.

Unused active high input pins should be tied to GND via weak pull-down resistors

(2 kΩ– 10 kΩ).

PC107A [Preliminary]

2137C–HIREL–03/04

Definitions

Datasheet Status

Description

Life Support

Applications These products are not designed for use in life support appliances, devices or systems

where malfunction of these products can reasonably be expected to result in personal

injury. Atmel customers using or selling these products for use in such applications do

so at their own risk and agree to fully indemnify Atmel for any damages resulting from

such improper use or sale.

Differences with

Commercial Part

Table 20. Datashee t Status

Datasheet Status Validity

Objective specification This datasheet contains target and goal

specifications for discussion with customer and

application validation.

Before design phase

Target specification This datasheet contains target or goal

specifications for product development. Valid during the design phase

Preliminary specification

α-site This datasheet contains preliminary data.

Additional data may be published later; could

include simulation results.

Valid before characterization phase

Preliminary specification β-site This datasheet contains also characterization

results. Valid before the industrialization phase

Product specification This datasheet contains final product

specification. Valid for production purposes

Limiting Values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the

limiting values may cause permanent damage to the device. These are stress ratings only and ope ration of the device at these or at

any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values

for e xtended periods may affect device reliability.

Application Information

Where application information is given, it is advisory and does not form part of the specification.

Table 21. Differences with Commercial Part

Commercial Part Industrial Part Military Part

Temperature range Tj = 0 to 105°C Tj = -40 to 110°C Tj = -55 to 125°C

46 PC107A [Preliminary] 2137C–HIREL–03/04

Ordering Information

Notes: 1. For availability of the different versions, contact your ATMEL sale office.

2. FC-PBGA = PBGA with Flip Chip Assembly process.

Document Revision

History Table 22 provides a revision history for this hardware specification.

PC107A M ZF U L

Type

(PCX107A if prototype)

Package

ZF: FC-PBGA(2)

GH: HiTCE (TBC)

Screening Level(1)

U: Upscreening Test

Bus divider (to be confirmed)

L: 2.5 ± 125 mV

Temperature Range: Tj

M: -55˚C, +125˚C

V: -40˚C, +110˚C Operating Frequency

100: 100 MHz

100 (C)

Revision Level(1)

C = 1.3

D = 1.4

Table 22. Document Revision History

Revision

Number Substantive Ch a ng e(s)

CAdd HiTCE Package with Thermal characteristics (see Table 5 on page 16)

Ordering Information (See “Ordering In formation” on page 46.)

PC107A [Preliminary]

2137C–HIREL–03/04

Table of Contents Features ................................................................................................1

Description ...........................................................................................1

Screening .............................................................................................1

General Description .............................................................................2

Simplified Block Diagram.......................................................................................2

General Parameters .....................................................................................................3

Features ......................................................................................................................3

Pin Assignments ...................................................................................................5

Pinout Listings ............................................................................................................5

Signal Description.....................................................................................................10

Detailed Specification ........................................................................11

Scope...................................................................................................11

Applicable Documents.......................................................................11

Requirements......................................................................................11

General ............................................................................................................... 11

Design and Cons tru ct ion ............. ... ................ ... .... ... ... ... ................ .... ... ... ... ........11

Terminal Connections ..............................................................................................11

Absolute Maximum Ratings ....................................................................................11

Recommende d Op e ra tin g Con d itio ns ... ... ... ................................ ... .... ... ... ... ........12

Thermal Information.............................................................................................15

Package Characteristics ...........................................................................................15

Thermal Management Information ...........................................................................17

Internal Package Conduction Resistance .................................................................19

Power Characteristics .........................................................................................20

Electrical Characteristics...................................................................21

Static Characteristics...........................................................................................21

DC Electrical Specification ......................................................................................21

Output Driver Characteristics ..................................................................................22

Dynamic Electrical Characteristics .....................................................................23

Clock AC Specifications ..........................................................................................23

Operating Frequency ................................................................................................25

Input AC Timing Specifications ...............................................................................26

Output AC Timing Specification .............................................................................28

PCI Signal Output Hold Timing ..............................................................................29

Two-wire Interface AC Timing Specifications ........................................................31

EPIC Serial Interrupt Mode AC Timing Specifications ..........................................35

IEEE 1149.1 (JTAG) AC Timing Specifications ....................................................36

Preparation for Delivery ....................................................................38

Packaging ........................................................................................................... 38

Certificate of Compliance ....................................................................................38

ii PC107A [Preliminary] 2137C–HIREL–03/04

Handling .............................................................................................38

Package Mechanical Data..................................................................38

Package Parame te rs...... ... ... .... ... ................................ ... .... ... ... ... ........................38

Mechanical Dim en sio n s.. ... ... .... ................ ... ... ... .... ... ................................ ... .... ... .39

Clock Relationships Choice ..............................................................41

System Design Information ..............................................................42

PLL Power Supply Filt er ing .................. ... ... ... ... ................................. ... ... ... .... ... .42

Power Supply Voltage Sequencing ....................................................................42

Decoupling Rec om m e ndat i on s................................. ... ... .... ... ... ...........................43

Connection Recommendations............................................................................43

Pull-up/Pull-down Resistor Requirements...........................................................44

Definitions ...........................................................................................45

Datasheet Statu s Desc rip tio n ........... .... ................ ... ... ... .... ... ..............................4 5

Life Support Applications.....................................................................................45

Differences with Commercial Part ......................................................................46

Ordering Information .........................................................................46

Document Revision History...............................................................46

iii

PC107A [Preliminary]

2137C–HIREL–03/04

Printed on recycled paper.

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granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not a uthorized for use

as critical components in life suppor t devices or systems.

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2137C–HIREL–03/04

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