1
Features
•Sensitive Layer Over a 0.8 µm CMOS Array
•Image Zone: 0.4 x 14 mm = 0.02" x 0.55"
•Image Array: 8 x 280 = 2240 pixels
•Pixel Pitch: 50 µm x 50 µm = 500 dpi
•Pixel Clock: up to 2 MHz Enabling up to 1780 Frames per Second
•Die Size: 1.7 x 17.3 mm
•Operating Voltage: 3V to 5.5V
•Naturally Protected Against ESD: > 16 kV Air Discharge
•Power Consumption: 20 mW at 3.3V, 1 MHz, 25°C
•Operating Temperature Range: 0°C to +70°C: C suffix
•Resistant to Abrasion: >1 Million Finger Sweeps
•Chip-On-Board (COB), Chip-On-Board (COB) with Connector, or 20-lead Ceramic DIP
Available for Development, with Specific Protective Layer
Applications
•PDA (Access Control, Data Protection)
•Cellular Phones, SmartPhone (Access e-business)
•Notebook, PC-add on (Access Control, e-business)
•PIN Code Replacement
•Automated Teller Machine, POS
•Building Access
•Electronic Keys (Cars, Home,...)
•Portable Fingerprint Imaging for Law Enforcement
•TV Access
Figure 1. FingerChip™ Packages
Note: AT77C101B part number replaces FCD4B14 and refers to same sensor.
Chip-on-Board Package
(COB)
Chip-on-Board Package
with connector
Real size
Thermal
Fingerprint
Sensor with
0.4 mm x 14 mm
(0.02" x 0.55")
Sensing Area
and
Digital Output
(On-chip ADC)
AT77C101B
FingerChip™
Sweep your finger
to make life easier
Rev. 2150A–BIOM–02/02
2AT77C101B
2150A–BIOM–02/02
Die Attach is connected to pins 1, 7 and 21, and must be grounded. FPL pin must be
grounded.
Table 1. Pin Description for Chip-On-Board Package: AT77C101B-CB01C
Pin Number Name Type
1GNDGND
2 AVE Analog output
3 AVO Analog output
4TPPPower
5 TPE Digital input
6 VCC Power
7GNDGND
8 RST Digital input
9 PCLK Digital input
10 OE Digital input
11 ACKN Digital output
12 De0 Digital output
13 Do0 Digital output
14 De1 Digital output
15 Do1 Digital output
16 De2 Digital output
17 Do2 Digital output
18 De3 Digital output
19 Do3 Digital output
20 FPL GND
21 GND GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
GND
AVE
AVO
TPP
TPE
VCC
GND
RST
PCLK
OE
ACKN
De0
Do0
De1
Do1
De2
Do2
De3
Do3
FPL
GND
3
AT77C101B
2150A–BIOM–02/02
Note: 1. “Ref Connector: FH18-21S-0.3SHW (HiROSE)” on page 4
Table 2. Pin Description for COB with Connector Package: AT77C101B-CB02C(1)
Pin Number Name Type
1FPLGND
2 Not connected
3 Not connected
4 DE3 Digital output
5 DO3 Digital output
6 DE2 Digital output
7 DO2 Digital output
8 DE1 Digital output
9 DO1 Digital output
10 DE0 Digital output
11 DO0 Digital output
12 AVE Analog output
13 AVO Analog output
14 TPP Power
15 TPE Digital input
16 VCC Power
17 GND GND
18 RST Digital input
19 PCLK Digital input
20 OE Digital input
21 ACKN Digital output
5
AT77C101B
2150A–BIOM–02/02
Die Attach is connected to pins 1 and 16, and must be grounded. FPL pin must be
grounded.
Table 3. Pin Description For DIP Ceramic Package: FCD4B14CC
Pin Number Name Type
1GNDGND
2 AVE Analog output
3TPPPower
4VCCPower
5 RST Digital input
6 OE Digital input
7 De0 Digital output
8 De1 Digital output
9 De2 Digital output
10 De3 Digital output
11 FPL GND
12 Do3 Digital output
13 Do2 Digital output
14 Do1 Digital output
15 Do0 Digital output
16 GND GND
17 ACKN Digital output
18 PCLK Digital input
19 TPE Digital input
20 AVO Analog output
GND
2
3
4
5
6
7
8
9
AVO
TPE
PCLK
ACKN
Do0
Do1
Do2
Do3
FPL
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AVE
TPP
VCC
RST
OE
De0
De1
De2
De3
GND
6AT77C101B
2150A–BIOM–02/02
Description AT77C101B is part of the Atmel FingerChip monolithic fingerprint sensor family for
which, no optics, no prism and no light source are required.
AT77C101B is a single chip, high performance, low cost sensor based on temperature
physical effects for fingerprint sensing.
AT77C101B has a linear shape, which captures a fingerprint image by sweeping the fin-
ger across the sensing area. After capturing several images, Atmel proprietary software
can reconstruct a full 8-bit fingerprint image, if needed.
AT77C101B has a small surface combined with CMOS technology, and a Chip-On-
Board or ceramic dual-in-line package assembly. These facts contribute to a low-cost
device.
AT77C101B delivers a programmable number of images per second, while an inte-
grated Analog to Digital Converter delivers a digital signal adapted to interfaces such as
an EPP parallel port, USB microcontroller or directly to microprocessors. Thus, no frame
grabber or glue interface is necessary to send the frames. These facts make
AT77C101B an easy device to include in any system for identification or verification
applications.
Note: 1. Absolute maximum ratings are limiting values, to be applied individually, while other parameters are within specified operat-
ing conditions. Long exposure to maximum ratings may affect device reliability.
Table 1. Absolute Maximum Ratings(1)
Parameter Symbol Comments Value Unit
Positive supply voltage VCC GND to 6.5 V
Temperature stabilization power TPP GND to 6.5 V
Front plane FPL GND to VCC V
Digital input voltage RST PCLK GND to VCC V
Storage temperature Tstg -50 to +85 °C
Lead temperature (soldering, 10 seconds) Tleads
Do not solder
DIP: socket mandatory Forbidden °C
Table 2. Recommended Conditions Of Use
Parameter Symbol Comments Min Typ Max Unit
Positive supply voltage VCC 3V 5V 5.5V V
Front plane FPL Must be grounded GND V
Digital input voltage CMOS levels V
Digital output voltage CMOS levels V
Digital load CL50 pF
Analog load CA
RA
Not connected pF
kΩ
Operating temperature range Tamb Civil: “C” grade 0 to +70 °C
Maximum current on TPP ITPP 0 100 mA
7
AT77C101B
2150A–BIOM–02/02
Table 3. Resistance
Parameter Min Value Standard Method
ESD
On pins. HBM (Human Body Model) CMOS I/O 2 kV MIL-STD-883- method 3015.7
On die surface (Zapgun)
Air discharge ±16 kV NF EN 6100-4-2
MECHANICAL ABRASION
Number of cycles without lubricant multiply by a factor of 20 for
correlation with a real finger
200 000 MIL E 12397B
CHEMICAL RESISTANCE
Cleaning agent, acid, grease, alcohol, diluted acetone 4 hours Internal method
Table 4. Specifications
Explanation Of Test Levels
I 100% production tested at +25°C
II 100% production tested at +25°C, and sample tested at specified temperatures (AC testing done on sample)
III Sample tested only
IV Parameter is guaranteed by design and/or characterization testing
V Parameter is a typical value only
VI 100% production tested at temperature extremes
D 100% probe tested on wafer at Tamb = +25°C
Parameter Test Level Min Typ Max Unit
Resolution IV 50 µm
Size IV 8x280 pixel
Yield: number of bad pixels I 15 bad pixels
Equivalent resistance on TPP pin I 23 30 47 Ω
8AT77C101B
2150A–BIOM–02/02
Note: 1. With IOL = 1 mA and IOH = -1 mA
Table 5. 5V Power Supply = +5V; Tamb = 25°C; FPCLK = 1 MHz; Duty cycle = 50%;
Cload 120 pF on digital outputs, analog outputs disconnected unless otherwise specified.
Parameter Symbol Test level Min Typ Max Unit
Power Requirements
Positive supply voltage VCC 4.5 5 5.5 V
Digital positive supply current on VCC pin
Cload = 0 ICC
I
IV
7
5
10
6
mA
mA
Power dissipation on VCC
Cload = 0 PCC
I
IV
35
25
50
30
mW
mW
Current on VCC in NAP mode ICCNAP I10µA
Analog Output
Voltage range VAVx I0 2.9V
Digital Inputs
Logic compatibility CMOS
Logic “0” voltage VIL I0 1.2V
Logic “1” voltage VIH I3.6 V
CC V
Logic “0” current IIL I-10 0µA
Logic “1”current IIH I 0 10 µA
Digital Outputs
Logic compatibility CMOS
Logic “0” voltage(1) VOL I1.5V
Logic “1” voltage(1) VOH I3.5 V
9
AT77C101B
2150A–BIOM–02/02
.
Note: 1. With IOL = 1 mA and IOH = -1 mA
Table 6. 3.3V Power supply = +3.3V; Tamb = 25°C; FPCLK = 1 MHz; Duty cycle = 50%;
Cload 120 pF on digital outputs, analog outputs disconnected unless otherwise specified
Parameter Symbol Test Level Min Typ Max Unit
Power Requirements
Positive supply voltage VCC 3.0 3.3 3.6 V
Digital positive supply current on VCC pin
Cload= 0 ICC
I
IV
6
5
10
6
mA
mA
Power dissipation on VCC
Cload = 0 PCC
I
IV
20
17
33
20
mW
mW
Current on VCC in NAP mode ICCNAP I10µA
Analog Output
Voltage range VAVx I0 2.9V
Digital Inputs
Logic compatibility CMOS
Logic “0” voltage VIL I0 0.8V
Logic “1” voltage VIH I2.3 VCCV
Logic “0” current IIL I-10 0µA
Logic “1”current IIH I0 10µA
Digital Outputs
Logic compatibility CMOS
Logic “0” voltage(1) VOL I0.6V
Logic “1” voltage(1) VOH I2.4 V
10 AT77C101B
2150A–BIOM–02/02
.
Table 7. Switching Performances. Tamb = 25°C; FPCLK = 1 MHz; Duty cycle = 50%
Cload 120 pF on digital and analog outputs unless otherwise specified
Parameter Symbol Test Level Min Typ Max Unit
Clock frequency fPCLK I0.512MHz
Clock pulse width (high) tHCLK I250 ns
Clock pulse width (low) tLCLK I250 ns
Clock setup time (high)/reset falling edge tSetup I0ns
No data change tNOOE IV 100 ns
Reset pulse width high tHRST IV 50 ns
Table 8. 5.0V All Power Supplies = +5V
Parameter Symbol Test Level Min Typ Max Unit
Output delay from PCLK to ACKN rising edge tPLHACKN I90ns
Output delay from PCLK to ACKN falling edge tPHLACKN I85ns
Output delay from PCLK to Data output Dxi tPDATA I75ns
Output delay from PCLK to Analog output Avx tPA V I D E O I 260 ns
Output delay from OE to data high-Z tDATAZ IV 25 ns
Output delay from OE to data output tZDATA IV 29 ns
Table 9. 3.3V All Power Supplies = +3.3V
Parameter Symbol Test Level Min Typ Max Unit
Output delay from PCLK to ACKN rising edge tPLHACKN I 110 ns
Output delay from PCLK to ACKN falling edge tPHLACKN I 100 ns
Output delay from PCLK to Data output Dxi tPDATA I90ns
Output delay from PCLK to Analog output AVx tPAV I D E O I 250 ns
Output delay from OE to data high-Z tDATAZ IV 34 ns
Output delay from OE to data output tZDATA IV 47 ns
11
AT77C101B
2150A–BIOM–02/02
Figure 4. Reset
Figure 5. Read One Byte/Two Pixels
tHRST
tSETUP
Reset RST
Clock PCLK
tPDATA
Clock
PCLK
fPCLK
tHCLK tLCLK
tPLHACKN tPHLACKN
tPAVIDEO
Acknowledge
ACKN
Data output
Do0-3, De0-3
Video analog output
AVO, AVE
Data #N+1
Data #N
Data #N-1
Data #N+2
Data #N+1
Data #N
12 AT77C101B
2150A–BIOM–02/02
Figure 6. Output Enable
Figure 7. No Data Change
Note: OE must not change during TNOOE after the PCLK falls. This is to ensure that the output drivers of the data are not driving cur-
rent, to reduce the noise level on the power supply.
Hi-Z Hi-Z
Output Enable
OE
Data output
Do0-3, De0 -3
Data output
tZDATA tDATAZ
PCLK tNOOE
OE
13
AT77C101B
2150A–BIOM–02/02
Figure 8. AT77C101B Block Diagram
Functional Description The circuit is divided into two main sections: sensor and data conversion. One particular
column among 280+1 is selected in the sensor array (1), then each pixel of the selected
column sends its electrical information to amplifiers (2) (one per line), then two lines at a
time are selected (odd and even) so that two particular pixels send their information to
the input of two 4-bit Analog-to-Digital Converters (3), so 2 pixels can be read for each
clock pulse (4).
Figure 9. Functional Description
Sensor Each pixel is a sensor in itself. The sensor detects a temperature differential between
the beginning of acquisition and the reading of information: this is the integration time.
The integration time begins with a reset of the pixel to a predefined initial state. Note that
the integration time reset has nothing to do with the reset of the digital section.
Then, at a rate depending on the sensitivity of the pyroelectric layer, on the temperature
variation between the reset and the end of the integration time, and on the duration of
the integration time, electrical charges are generated at the pixel level.
2240
8
latches
chip
temperature
sensor
line sel
odd
even
8 lines of 280 columns of pixels
4-bit
ADC
ADC
8
1 dummy column
4
4
amp
chip temperature
stabilization
ACKN
De0-3
Do0-3
output
enable
analog
output
OEAVE AVOTPE
TPP
1
8
PCLK
RST
clock
reset
column selection
4-bit
8
latches
chip
temperature
sensor
column selection line sel
odd
even
8 lines of 280 columns of pixels
4-bit
ADC
ADC
8
1 dummy column
4
4
amp
De0-3
Do0-3
1 2 3 4
4-bit
14 AT77C101B
2150A–BIOM–02/02
Analog-to-Digital
Converter/
Reconstructing an 8-bit
Fingerprint Image
An Analog-to-Digital Converter (ADC) is used to convert the analog signal coming from
the pixel into digital data that can be used by a processor.
As the data rate for parallel port and USB is in the range of 1 MB per second, and at
least a rate of 500 frames per second is needed to reconstruct the image with a fair
sweeping speed for the finger, two 4-bit ADCs have been used to output 2 pixels at a
time on 1 byte.
Start Sequence A reset is not necessary between each frame acquisition.
Start sequence must consist of:
1. Set the RST pin to high
2. Set the RST pin to low
3. Send 4 clock pulses (due to pipe-line)
4. Send clock pulses to skip the first frame
Note that the first frame never contains relevant information because the integration
time is not correct.
Figure 10. Start Sequence
Reading the Frames A frame consists of 280 true columns + 1 dummy column of 8 pixels. As two pixels are
output at a time, a system must send 281x4 = 1124 clock pulses to read one frame.
Reset must be low when reading the frames.
Read One Byte/Output
Enable
Clock is taken into account on the falling edge and data are output on the rising edge.
For each clock pulse, after the start sequence, a new byte is output on the Do0-3, De0-
3 pins. This byte contains 2 pixels: 4-bit on Do0-3 (odd pixels), 4-bit on De0-3 (even
pixels).
To output the data, the output enable (OE) pin must be low. When OE is high, the Do0-
3 and De0-3 pins are in high-impedance state. This facilitates an easy connection to a
microprocessor bus without additional circuitry since data output can be enabled using a
chip select signal. Note that the AT77C101B is always sending data: there is no data
exchange to perform using read/write mode.
Power Supply Noise IMPORTANT: When a falling edge is applied on OE (i.e when the Output Enable
becomes active), then some current is drained from the power supply to drive the 8 out-
puts, producing some noise. It is important to avoid such noise just after the falling edge
of the clock PCLK, when the pixels information is evaluated: the timing diagram figure 5
and time TNOOE defines the interval time where the power supply must be as quiet as
possible.
1431 2 11124
Clock PCLK
Reset RST 4+1124 clock pulses to skip the first frame
15
AT77C101B
2150A–BIOM–02/02
Video Output An analog signal is also available on pins AVE and AVO. Note that video output is avail-
able one clock pulse before the corresponding digital output (one clock pipe-line delay
for the analog to digital conversion).
Pixel Order After a reset, pixel number one is located on the upper left corner, looking at the chip
with bond pads to the right. For each column of 8 pixels, pixels 1-3-5-7 are output on
odd data Do0-3 pins, pixels 2-4-6-8 are output on even data De0-3 pins. Most significant
bit is bit #3, least significant is bit #0.
Figure 11. Pixel Order
Synchronization: The
Dummy Column
A dummy column has been added to the sensor to act as a specific pattern to detect the
first pixel. So, 280 true columns + 1 dummy column are read for each frame.
The 4 bytes of the dummy column contain a fixed pattern on the two first bytes, and tem-
perature information on the last two bytes.
Note: x represents 0 or 1
The sequence 111X0000 111X0000 appears on every frame (exactly every 1124 clock
pulses), so it is an easy pattern to recognize for synchronization purposes.
B ond pads
Pixel #1 (1,1) Pixel #2233 (280,1)
Pixel #8 (1,8) Pixel #2240 (280,8)
Dummy Byte Odd Even
Dummy Byte 1 DB1: 111X 0000
Dummy Byte 2 DB2: 111X 0000
Dummy Byte 3 DB3: rrrr nnnn
Dummy Byte 4 DB4: tttt pppp
16 AT77C101B
2150A–BIOM–02/02
Thermometer The dummy bytes DB3 and DB4 contain some internal and temperature information.
The even nibble nnnn in DB3 can be used to measure an increase (or decrease) of the
chip temperature, using the difference between two measures of the same physical
device. The following table gives values in Kelvin.
For code 0 and 15, the absolute value is a minimum (saturation).
When the image contrast becomes low because of a low temperature difference
between the finger and the sensor, it is recommended to use the temperature stabiliza-
tion circuitry to increase the temperature of two codes (i.e. from 8 to 10), to get at least
an increase >1.4 Kelvin of the sensor. This enables to recover enough contrast to get a
proper fingerprint for recognition purpose.
nnnn
Decimal
nnnn
Binary
Temperature differential with code 8
in Kelvin
15 1111 11.2
14 1110 8.4
13 1101 7
12 1100 5.6
11 1011 4.2
10 1010 2.8
9 1001 1.4
8 1000 0
7 0111 -1.4
6 0110 -2.8
5 0101 -4.2
4 0100 -5.6
3 0011 -7
2 0010 -8.4
1 0001 -11.2
0 0000 < -16.8
17
AT77C101B
2150A–BIOM–02/02
Integration Time and
Clock Jitter
The AT77C101B is not very sensitive to clock jitter (clock variation). The most important
requirement is a regular integration time that ensures the frame reading rate is also as
regular as possible, in order to get consistent fingerprint slices.
If the integration time is not regular, contrast will vary from one frame to another.
Note that it is possible to introduce some waiting time between each set of 1124 clock
pulses, but the overall time of one frame read must be regular. This waiting time is gen-
erally the time needed by the processor to perform some calculation over the frame (to
detect the finger, for instance).
Figure 12. Read One Frame
Figure 13. Regular Integration Time
Clock PCLK
Reset RST is low
123456 112411231122112111201119
Column 1 Column 2 Column 280 Dummy Column 281
Pixels 1 & 2 3 & 4 5 & 6 7 & 8 1 & 2 3 & 4 7 & 8 DB1 DB2 DB3 DB4
Clock PCLK
REGULAR INTEGRATION TIME
Frame n
1124 pulses
Frame n+1
1124 pulses
Frame n+2
1124 pulses
Frame n+3
1124 pulses
18 AT77C101B
2150A–BIOM–02/02
Power Management
Nap Mode Several strategies are possible to reduce power consumption when not in use.
The simplest and most efficient is to cut the power supply, using external means.
A nap mode is also implemented in the AT77C101B. To activate this nap mode, the user
must:
1. Set the reset RST pin to high. Doing this, all analog sections of the device are
internally powered down.
2. Set the clock PCLK pin to high (or low), thus stopping the entire digital section.
3. Set the TPE pin to low or disconnect TPP to stop the temperature stabilization
feature.
4. Set Output Enable OE pin to high, so that output are forced in HiZ.
Figure 14. Nap Mode
In Nap Mode, all internal transistors are in shut mode. Only leakage current is drained in
power supply, generally less than the tested value.
Static Current
Consumption
When the clock is stopped (set to 1) and the reset is low (set to 0), the analog sections
of the device drain some current and the digital section does not consume current if the
outputs are connected to a standard CMOS input (= no current is drained in the I/O). In
this case the typical current value is 5 mA. This current does not depend on the voltage
(i.e. it is almost the same from 3V to 5.5V).
Dynamic Current
Consumption
When the clock is running, the digital sections are consuming current, and particularly
the outputs if they are heavily loaded. In any case, it should be less than the testing
machine (120 pF load on each I/O), 50 pF maximum is recommended.
Connected to a USB interface chip (see application note 26 related to the FCDEMO4
kit) at 5V, and running at about 1 MHz, the AT77C101B consumes less than 7 mA on
VCC pin.
Temperature
Stabilization Power
Consumption (TPP pin)
When the TPE pin is set to 1, current is drained via the TPP pin. The current is limited by
the internal equivalent resistance given in table 4 and a possible external resistor.
Most of the time, TPE is set to 0 and no current is drained in TPP. When the image con-
trast becomes low because of a low temperature differential (less than one Kelvin), then
it is recommended to set TPE to 1 during a short time so that the dissipated power in the
chip elevates the temperature, enabling to recover contrast. The necessary time to
increase the chip temperature of one Kelvin depends on the dissipated power, the ther-
mal capacity of the silicon sensor and the thermal resistance between the sensor and
the surroundings.
As a rule of thumb, dissipating 300 mW in the chip elevates the temperature of 1 Kelvin
in one second. With the 30Ω typical value, 300 mW is 3V applied on TPP.
Nap
Clock PCLK
Reset RST
Nap mode
19
AT77C101B
2150A–BIOM–02/02
Packaging: Mechanical Data
Figure 15. Product Reference: AT77C101B-CB01C
Figure 16. Product Reference: AT77C101B-CB01C
Top view (all dimensions in mm)
at 0.4 height from B ref.
0.89 ± 0.3
2.32 ± 0.5 0.35
14
1.66 +0.07
-0.01
0.3 A
at 0.4 height from B ref.
26.6 ± 0.5
0.2 min
5.20 max
5.90 max
0.83 ± 0.50
9 ± 0.5
2.95 ± 0.50
1.5 max
0.83 ± 0.11
Dam & Fill
B
5.45 ±0.30
17.51 +0.07
-0.01
0.8
max
A
0.2 max
Bottom view (all dimensions in mm)
1.15 ± 0.15
2.15 ± 0.15
6.30 ± 0.1
0.75+0.33
-0.25
1 ± 0.08
0.5 ±0.08
R0.75 +0.08
-0.12 (x3)
1.5 +0.15
-0.23 (x3)
23.85 ± 0.1
2 ± 0.15
2 ± 0.08
1.5 ± 0.08
1 ± 0.15
3.5 ± 0.08
20 AT77C101B
2150A–BIOM–02/02
Figure 17. Product reference: AT77C101B-CB02C
5.9 max
9.85 ± 0.3
4.1 ± 0.2
FLEX OUTPUT
5.2 max
8.9 ± 0.5
8.8 ± 0.2
1.25 ± 0.5
26.6 ± 0.3
0.75 +0.33
-0.25
2.39 ± 0.5
0.8 MAX
4.1 ± 0.5
6.3 ± 0.1
1.78 ± 0.5 (x 2)
FLEX OUTPUT
R0.75+0.08
-0.12 (x 3)
All dimensions in mm
2.9 ± 0.5
0.2 min
1.9 ± 0.4
0.83 ± 0.11
COUPE AA
1.5 MAX
14.35 +0.04
-0.01
1.5 +0.15
-0.23 (x 3)
1.66 +0.07
-0.01
21
AT77C101B
2150A–BIOM–02/02
Figure 18. Product Reference: FCD4B14CC (For Development Only)
0.08
0.75 max
3.15 ± 0.32
0.81 ± 0.05
0.46 ± 0.05
0.25 max
1.1 ± 0.1
2.54 ± 0.13
22.86 ± 0.13
4.75 ± 0.1
60°
0.08
25.4 ± 0.25
9.36 ± 0.15 6.34 ± 0.15
0.1 min
(2.45)
(0.90)
NO.1 NO.10
NO.20 NO.11
(0.20) 5.4 max
7.5 ± 0.25
7.87 ± 0.25
0.25 ± 0.05
(7.62)
6.5 max
DIL (all dimensions in mm)
22 AT77C101B
2150A–BIOM–02/02
Ordering Information
Package Device
Note: AT77C101B part number replaces FCD4B14 and refers to same sensor.
AT77C 101B- C —
Atmel prefix
Temperature range
Com: 0° to +70°C
Quality level:
— : standard
Package
CB01: Chip On Board (COB)
CB02: COB with connector
CBXX
FingerChip family
Device type
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
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Atmel SarL
Route des Arsenaux 41
Casa Postale 80
CH-1705 Fribourg
Switzerland
TEL (41) 26-426-5555
FAX (41) 26-426-5500
Asia
Atmel Asia, Ltd.
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
Japan
Atmel Japan K.K.
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Memory
Atmel Corporate
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 436-4270
FAX 1(408) 436-4314
Microcontrollers
Atmel Corporate
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 436-4270
FAX 1(408) 436-4314
Atmel Nantes
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
TEL (33) 2-40-18-18-18
FAX (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
Atmel Rousset
Zone Industrielle
13106 Rousset Cedex, France
TEL (33) 4-42-53-60-00
FAX (33) 4-42-53-60-01
Atmel Colorado Springs
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Atmel Smart Card ICs
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
TEL (44) 1355-803-000
FAX (44) 1355-242-743
RF/Automotive
Atmel Heilbronn
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
TEL (49) 71-31-67-0
FAX (49) 71-31-67-2340
Atmel Colorado Springs
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Atmel Grenoble
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
TEL (33) 4-76-58-30-00
FAX (33) 4-76-58-34-80
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
2150A–BIOM–02/02 0M
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