FLEX 6000 Programmable Logic Device Family May 1999, ver. 4 Data Sheet Features... Provides an ideal low-cost, programmable alternative to high- volume gate array applications and allows fast design changes during prototyping or design testing Product features - Register-rich, look-up table (LUT)-based architecture OptiFLEX architecture that increases device area efficiency - Usable gates ranging from 5,000 to 24,000 gates (see Table 1) - Built-in low-skew clock distribution tree - 100% functional testing of all devices; test vectors or scan chains are not required - Advanced 2.96-mil (75-ym) bond pad pitch on 3.3-V devices for reduced die size System-level features - In-circuit reconfigurability (ICR) via external configuration device or intelligent controiler - 5.0-V devices are fully compliant with peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic - MultiVolt I/O interface operation, allowing a device to bridge between systems operating at different voltages - Low power consumption (typical specification less than 0.5 mA in standby mode) 3.3-V devices support hot-socketing Table 1. FLEX 6000 Device Features Feature EPF6010A EPF6016 EPF6016A EPF6024A Typical gates (1) 10,000 16,000 16,000 24,000 Pa Logic elements (LEs) 880 1,320 1,320 1,960 Maximum I/O pins 102 204 171 218 = Supply voltage (Vocint) 3.3 V 5.0V 3.3V 3.3V is Note: alt (1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 14,000 gates in addition to the listed typical gates. =] Altera Corporation A-DS-F6000-04 413FLEX 6000 Programmable Logic Device Family Data Sheet ...and More Features 414 Powerful I/O pins Individual tri-state output enable control for each pin - Programmable output slew-rate control to reduce switching noise - Fast path from register to I/O pin for fast clock-to-output time Flexible interconnect - FastTrack Interconnect continuous routing structure for fast, predictable interconnect delays - Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) - Dedicated cascade chain that implements high-speed, high-fan- in logic functions (automatically used by software tools and megafunctions) - Tri-state emulation that implements internal tri-state networks - Four low-skew global paths for clock, clear, preset, or logic signals Software design support and automatic place-and-route provided by Alteras MAX+PLUS II development system for Windows-based PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System /6000 workstations, and the Quartus development system for Windows-based PCs and Sun SPARCstation and HP 9000 Series 700 workstations Flexible package options ~ Available ina variety of packages with 100 to 256 pins, including the innovative FineLine BGA packages (see Table 2) SameFrame pin-compatibility (with other FLEX 6000 devices) across device densities and pin counts - Thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and ball-grid array (BGA) packages (see Table 2) - Footprint- and pin-compatibility with other FLEX 6000 devices in the same package Additional design entry and simulation support provided by EDIF 2 00 and 300 netlist files, the library of parameterized modules (LPM), Verilog HDL, VHDL, DesignWare components, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic Extensive package options Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Table 2. FLEX 6000 Package Options & 1/0 Pin Count Device | 100-Pin 100-pin 144-Pin | 208-Pin | 240-Pin | 256-Pin 256-pin TOFP FineLine BGA TOFP PQFP PQFP BGA FineLine BGA EPF6010A 71 (1) 102 - - - (1) EPF6016 - - 117 171 199 204 - EPF6016A 81 (1) 117 171 - - (1) EPF6024A - - 117 171 199 218 (1) Note: (1) Contact Altera for up-to-date information on this package. General Description Altera Corporation The Altera FLEX 6000 programmable logic device (PLD) family provides a low-cost alternative to high-volume gate arrays designs. FLEX 6000 devices are based on the OptiFLEX architecture, which minimizes die size while maintaining high performance and routability. The devices have reconfigurable SRAM elements, which give designers the flexibility to quickly change their designs during prototyping and design testing. Designers can also change functionality during operation via in-circuit reconfiguration. FLEX 6000 devices are reprogrammable, and they are 100% tested prior to shipment. As a result, designers are not required to generate test vectors for fault coverage purposes, allowing them to focus on simulation and design verification. In addition, the designer does not need to manage inventories of different gate array designs. FLEX 6000 devices are configured on the board for the specific functionality required. Table 3 shows FLEX 6000 performance for some common designs. All performance values shown were obtained using Synopsys DesignWare or LPM functions. Special design techniques are not required to implement the applications; the designer simply infers or instantiates a function ina Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or schematic design file. 415 mal i m > 4 mo oa fom] oFLEX 6000 Programmable Logic Device Family Data Sheet Table 3. FLEX 6000 Device Performance for Common Designs Application LEs Used Performance Units Speed Grade -1 -2 3 16-bit loadable counter 16 172 153 133 MHz 16-bit accumulator 16 172 153 133 MHz 24-bit accumulator 24 136 123 108 MHz 16-to-1 multiplexer (pin-to-pin) (1) 10 12.1 13.4 16.6 ns 16 x 16 multiplier with a 4-stage pipeline 592 84 67 58 MHz Note: (1) This performance value is measured as a pin-to-pin delay. Table 4 shows FLEX 6000 performance for more complex designs. Table 4, FLEX 6000 Device Performance for Complex Designs _Note (1) Application LEs Used Performance Units Speed Grade 1 2 3 8-bit, 16-tap parallel finite impulse response 599 94 80 72 MSPS (FIR) filter 8-bit, 512-point fast Fourier transform (FFT) 1,182 75 89 109 us function 63 53 43 MHz a16450 universal asynchronous 487 36 30 25 MHz receiver/transmitter (UART) PCI bus target with zero wait states 609 56 49 42 MHz Nate: (1) The applications in this table were created using Altera MegaCore functions. FLEX 6000 devices are supported by Quartus and MAX+PLUS II development systems; a single, integrated package that offers schematic, text (including AHDL), and waveform design entry, compilation and logic synthesis, full simulation and worst-case timing analysis, and device configuration. The Quartus and MAX+PLUS II software provides EDIF 200 and 300, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry- standard PC- and UNIX workstation-based EDA tools. 416 Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Functional Description Altera Corporation The Quartus and MAX+PLUS II software works easily with common gate array EDA tools for synthesis and simulation. For example, the MAX+PLUS II software can generate Verilog HDL files for simulation with tools such as Cadence Verilog-XL. Additionally, the Quartus and MAX+PLUS II software contains EDA libraries that use device-specific features such as carry chains which are used for fast counter and arithmetic functions. For instance, the Synopsys Design Compiler library supplied with the Quartus and MAX+PLUS II development systems include DesignWare functions that are optimized for the FLEX 6000 architecture. The MAX+PLUS II development system runs on Windows-based PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations, and the Quartus development system runs on Windows- based PCs and Sun SPARCstation and HP 9000 Series 700 workstations. See the MAX+PLUS II Programmable Logic Development System & Software Data Sheet for more information. The FLEX 6000 OptiFLEX architecture consists of logic elements (LEs). Each LE includes a 4~input look-up table (LUT), which can implement any 4-input function, a register, and dedicated paths for carry and cascade chain functions. Because each LE contains a register, a design can be easily pipelined without consuming more LEs. The specified gate count for FLEX 6000 devices includes all LUTs and registers. LEs are combined into groups called logic array blocks (LABs); each LAB contains 10 LEs. The MAX+PLUS II software automatically places related LEs into the same LAB, minimizing the number of required interconnects. Each LAB can implement a medium-sized block of logic, such as a counter or multiplexer. Signal interconnections within FLEX 6000 devicesand to and from device pinsare provided via the routing structure of the FastTrack Interconnect. The routing structure is a series of fast, continuous row and column channels that run the entire length and width of the device. Any LE or pin can feed or be fed by any other LE or pin via the FastTrack Interconnect. See FastTrack Interconnect on page 430 of this data sheet for more information. 417 rc laa! a lop) o o fon]FLEX 6000 Programmable Logic Device Family Data Sheet 418 Each I/O pin is fed by an 1/O element (IOE) located at the end of each row and column of the FastTrack Interconnect. Each IOE contains a bidirectional I/O buffer. Each IOE is placed next to an LAB, where it can be driven by the local interconnect of that LAB. This feature allows fast clock-to-output times of less than 8 ns when a pin is driven by any of the 10 LEs in the adjacent LAB. Also, any LE can drive any pin via the row and column interconnect. I/O pins can drive the LE registers via the row and column interconnect, providing setup times as low as 2 ns and hold times of 0 ns. IOEs provide a variety of features, such as JTAG BST support, slew-rate control, and tri-state buffers. Figure 1 shows a block diagram of the FLEX 6000 OptiFLEX architecture. Each group of ten LEs is combined into an LAB, and the LABs are arranged into rows and columns. The LABs are interconnected by the FastTrack Interconnect. IOEs are located at the end of each FastTrack Interconnect row and column. Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Figure 1. OptiFLEX Architecture Block Diagram Oo0nnoganananonAdnDaaoaAAnnAaoaAD PIF TPIT Ieee) (Os Jo . Row FastTrack "Interconnect Row FastTrack oN Interconnect onoggonnooo0ogMoao00noooO00 a / / IOEs Column FastTrack interconnect Column FastTrack Interconnect Local Interconnect (Each LAB accesses two focal interconnect areas.) Logic Elements FLEX 6000 devices provide four dedicated, global inputs that drive the control inputs of the flipflops to ensure efficient distribution of high- speed, low-skew control signals. These inputs use dedicated routing channels that provide shorter delays and lower skews than the FastTrack Interconnect. These inputs can also be driven by internal logic, providing an ideal solution for a clock divider or an internally generated asynchronous clear signal that clears many registers in the device. The dedicated global routing structure is built into the device, eliminating the need to create a clock tree. mal rc m > a =) =] o Altera Corporation 419FLEX 6000 Programmable Logic Device Family Data Sheet Logic Array Block An LAB consists of ten LEs, their associated carry and cascade chains, the LAB control signals, and the LAB local interconnect. The LAB provides the coarse-grained structure of the FLEX 6000 architecture, and facilitates efficient routing with optimum device utilization and high performance. The interleaved LAB structure an innovative feature of the FLEX 6000 architecture allows each LAB to drive two local interconnects. This feature minimizes the use of the FastTrack Interconnect, providing higher performance. An LAB can drive 20 LEs in adjacent LABs via the local interconnect, which maximizes fitting flexibility while minimizing die size. See Figure 2. Figure 2. Logic Array Block The row interconnect is bidirectionally connected _LEs can directly drive the row Row Interconnect to the local interconnect. and column interconnect. \ \ \ \ \ \ To/From To/From Adjacent Adjacent LAB or IOEs LAB or IOEs / / / \ Local Interconnect The 10 LEs in the LAB are driven by two Column Interconnect local interconnect areas. The LAB can drive two local interconnect areas. 420 In most designs, the registers only use global clock and clear signals. However, in some cases, other clock or asynchronous clear signals are needed. In addition, counters may also have synchronous clear or load signals. In a design that uses non-global clock and clear signals, inputs from the first LE in an LAB are re-routed to drive the control signals for that LAB. See Figure 3. Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Figure 3. LAB Contral Signals The dedicated input signals can drive the clock and asynchronous Clear signals. s, N \ Dedicated Inputs Input signals to the first LE in an LAB (i.., LE 1) can be rerouted to. drive fo control signals within al ca LABCTAL the LAB. CLK1/SYNLOAD CLK2 ~ LAB-wide control signals (SYNCLR and SYNLOAD signals are used in counter mode). Logic Element An LE, the smallest unit of logic in the FLEX 6000 architecture, has a compact size that provides efficient logic usage. Each LE contains a four- input LUT, which is a function generator that can quickly implement any function of four variables. An LE contains a programmable flipflop, carry and cascade chains. Additionally, each LE drives both the local and the FastTrack Interconnect. See Figure 4. ma! rc fag Pat fr o o o Altera Corporation 421FLEX 6000 Programmable Logic Device Family Data Sheet Figure 4. Logic Element Carry-In | | Cascade-In Register Bypass Programmable a Register - data . data2 data3 data4 Look-Up Table (LUT) Carry LE-Out Chain labetrl1 labetrl2 Creat! Preset Chip-Wide Reset ogic Clock Select labctrl3 labctri4 Carry-Out Cascade-Out The programmable flipflop in the LE can be configured for D, T, JK, or SR operation. The clock and clear control signals on the flipflop can be driven by global signals, general-purpose I/O pins, or any internal logic. For combinatorial functions, the flipflop is bypassed and the output of the LUT drives the outputs of the LE. The LE output can drive both the local interconnect and the FastTrack Interconnect. The FLEX 6000 architecture provides two types of dedicated high-speed data paths that connect adjacent LEs without using local interconnect paths: carry chains and cascade chains. A carry chain supports high-speed arithmetic functions such as counters and adders, while a cascade chain implements wide-input functions such as equivalent comparators with minimum delay. Carry and cascade chains connect LEs 2 through 10 in an LAB and all LABs in the same half of the row. Because extensive use of carry and cascade chains can reduce routing flexibility, these chains should be limited to speed-critical portions of a design. 422 Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Altera Corporation Carry Chain The carry chain provides a very fast (0.1 ns) carry-forward function between LEs. The carry-in signal from a lower-order bit drives forward into the higher-order bit via the carry chain, and feeds into both the LUT and the next portion of the carry chain. This feature allows the FLEX 6000 architecture to implement high-speed counters, adders, and comparators of arbitrary width. Carry chain logic can be created automatically by the MAX+PLUS I Compiler during design processing, or manually by the designer during design entry. Parameterized functions such as LPM and DesignWare functions automatically take advantage of carry chains for the appropriate functions. Because the first LE of each LAB can generate control signals for that LAB, the first LE in each LAB is not included in carry chains. In addition, the inputs of the first LE in each LAB may be used to generate synchronous clear and load enable signals for counters implemented with carry chains. Carry chains longer than nine LEs are implemented automatically by linking LABs together. For enhanced fitting, a long carry chain skips alternate LABs in a row. A carry chain longer than one LAB skips either from an even-numbered LAB to another even-numbered LAB, or from an odd-numbered LAB to another odd-numbered LAB. For example, the last LE of the first LAB in a row carries to the second LE of the third LAB in the row. In addition, the carry chain does not cross the middle of the row. For instance, in the EPF6016 device, the carry chain stops at the 11th LAB in a row and a new carry chain begins at the 12th LAB. Figure 5 shows how an n-bit full adder can be implemented in n + 1 LEs with the carry chain. One portion of the LUT generates the sum of two bits using the input signals and the carry-in signal; the sum is routed to the output of the LE. Although the register can be bypassed for simple adders, it can be used for an accumulator function. Another portion of the LUT and the carry chain logic generates the carry-out signal, which is routed directly to the carry-in signal of the next-higher-order bit. The final carry-out signal is routed to an LE, where it is driven onto the FastTrack Interconnect. 423 on a m =< a ao o Lowe]FLEX 6000 Programmable Logic Device Family Data Sheet Figure 5. Carry Chain Operation Carry-In al Register st b1 Carry Chain a2 Register $2 b2 Carry Chain e e e an Register sn bn Carry Chain Register Carry-Out Carry Chain 424 Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Cascade Chain The cascade chain enables the FLEX 6000 architecture to implement very wide fan-in functions. Adjacent LUTs can be used to implement portions of the function in parallel; the cascade chain serially connects the intermediate values. The cascade chain can use a logical AND or logical OR gate (via De Morgans inversion) to connect the outputs of adjacent LEs. Each additional LE provides four more inputs to the effective width of a function, with a delay as low as 0.5 ns per LE. Cascade chain logic can be created automatically by the MAX+PLUS II Compiler during design processing, or manually by the designer during design entry. Parameterized functions such as LPM and DesignWare functions automatically take advantage of cascade chains for the appropriate functions. A cascade chain implementing an AND gate can use the register in the last LE; a cascade chain implementing an OR gate cannot use this register because of the inversion required to implement the OR gate. Because the first LE of an LAB can generate control signals for that LAB, the first LE in each LAB is not included in cascade chains. Moreover, cascade chains longer than nine bits are automatically implemented by linking several LABs together. For easier routing, a long cascade chain skips every other LAB in a row. A cascade chain longer than one LAB skips either from an even-numbered LAB to another even-numbered LAB, or from an odd-numbered LAB to another odd-numbered LAB. For example, the last LE of the first LAB in a row cascades to the second LE of the third LAB. The cascade chain does not cross the center of the row. For example, in an EPF6016 device, the cascade chain stops at the 11th LAB in a row and a new cascade chain begins at the 12th LAB. Figure 6 shows how the cascade function can connect adjacent LEs to form functions with a wide fan-in. In this example, functions of 4n variables are implemented with n LEs. With the cascade chain, 3.4 ns are needed to decode a 16-bit address. mal aa mM a loz) o eo [ome] Altera Corporation 425FLEX 6000 Programmable Logic Device Family Data Sheet Figure 6. Cascade Chain Operation AND Cascade Chain OR Cascade Chain [3..0} inp) LUT LE 2 LE2 C[7..4] inp LES LE3 d[7..4] | LUT \- d[3..0] =f! LUT ] _ ~T ) |) > e e e e e ______} ___] ee LEn+t | LEn+4 d[(40-1)..4(-1)] be| LUT d[(4-1)..4(2-1)] LUT |) >> LE Operating Modes 426 The FLEX 6000 LE can operate in one of the following three modes: m@ = Normal mode @ = Arithmetic mode mg Counter mode Each of these modes uses LE resources differently. In each mode, seven available inputs to the LEthe four data inputs from the LAB local interconnect, the feedback from the programmable register, and the carry-in and cascade-in from the previous LEare directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, synchronous clear, and synchronous load control for the register. The MAX+PLUS II software, in conjunction with parameterized functions such as LPM and DesignWare functions, automatically chooses the appropriate mode for common functions such as counters, adders, and multipliers. If required, the designer can also create special-purpose functions to use an LE operating mode for optimal performance. Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Figure 7 shows the LE operating modes. Figure 7. LE Operating Modes Normal Mode Carry-In Cascade-In LE-Out data1 4 data2 PRN 4-Input BU a data3 LUT om data4 __ CLRN y Cascade-Out Arithmetic Mode Carry-In Cascade-In LE-Out 4 data1 PRN data2 S-Input ae LUT Ss 3-Input CLAN LUT v ? Cascade-Out Carry-Out Counter Mode LAB-Wide Synchronous LAB-Wide Synchronous Cascade-In Load (3) Clear (3) () data1 (2) data2 (2) LE-Out data3 (data) Carry-Out Cascade-Out Notes: (1) Register feedback multiplexer is available on LE 2 of each LAB. (2) The datal and data2 input signals can supply a clock enable, up or down control, or register feedback signals for all LEs other than the second LE in an LAB. (3) The LAB-wide synchronous clear and LAB-wide synchronous load affect all registers in an LAB. mal m 4 i=2) o o o Altera Corporation 427FLEX 6000 Programmable Logic Device Family Data Sheet 428 Normal Mode The normal mode is suitable for general logic applications, combinatorial functions, or wide decoding functions that can take advantage of a cascade chain. In normal mode, four data inputs from the LAB local interconnect and the carry-in are inputs to a 4-input LUT. The MAX+PLUS II Compiler automatically selects the carry-in or the DATA3 signal as one of the inputs to the LUT. The LUT output can be combined with the cascade-in signal to form a cascade chain through the cascade-out signal. Arithmetic Mode The arithmetic mode is ideal for implementing adders, accumulators, and comparators. An LE in arithmetic mode uses two 3-input LUTs. One LUT computes a 3-input function; the other generates a carry output. As shown in Figure 7, the first LUT uses the carry-in signal and two data inputs from the LAB local interconnect to generate a combinatorial or registered output. For example, when implementing an adder, this output is the sum of three signals: DATA1, DATA2, and carry-in. The second LUT uses the same three signals to generate a carry-out signal, thereby creating a carry chain. The arithmetic mode also supports simultaneous use of the cascade chain. The MAX+PLUS II software implements logic functions to use the arithmetic mode automatically where appropriate; the designer does not have to decide how the carry chain will be used. Counter Mode The counter mode offers counter enable, synchronous up/down control, synchronous clear, and synchronous load options. The counter enable and synchronous up/down control signals are generated from the data inputs of the LAB local interconnect. The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. Consequently; if any of the LEs in a LAB use counter mode, other LEs in that LAB must be used as part of the same counter or be used for a combinatorial function. In addition, the MAX+PLUS II Compiler automatically places registers that are not in the counter into other LABs. The counter mode uses two 3-input LUTs: one generates the counter data and the other generates the fast carry bit. A 2-to-1 multiplexer provides synchronous loading, and another AND gate provides synchronous clearing. If the cascade function is used by an LE in counter mode, the synchronous clear or load will override any signal carried on the cascade chain. The synchronous clear overrides the synchronous load. Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Either the counter enable or up/down control may be used for a given counter. Moreover, the synchronous load can be used as a count enable by routing the register output into the data input automatically when requested by the designer. The second LE of each LAB has a special function for counter mode; the carry-in of the LE can be driven by a fast feedback path from the register. This function gives a faster counter speed for counter carry chains starting in the second LE of an LAB. The MAX+PLUS II software implements functions to use the counter mode automatically where appropriate. The designer does not have to decide how the carry chain will be used. Internal Tri-State Emulation Internal tri-state emulation provides internal tri-states without the limitations of a physical tri-state bus. In a physical tri-state bus, the tri-state buffers output enable (OE) signals select which signal drives the bus. However, if multiple OE signals are active, contending signals can be driven onto the bus. Conversely, if no OE signals are active, the bus will float. Internal tri-state emulation resolves contending tri-state buffers to a low value and floating buses to a high value, thereby eliminating these problems. The MAX+PLUS II software automatically implements tri-state bus functionality with a multiplexer. Clear & Preset Logic Control Logic for the programmable registers clear and preset functions is controlled by the LAB-wide signals LABCTRL1 and LABCTRL2. The LE register has an asynchronous clear that can implement an asynchronous preset. Either LABCTRL1 or LABCTRL2 can control the asynchronous clear or preset. Because the clear and preset functions are active-low, the MAX+PLUS II Compiler automatically assigns a logic high to an unused clear or preset signal. The clear and preset logic is implemented in either the asynchronous clear or asynchronous preset mode, which is chosen during design entry (see Figure 8). nl ool m > a f=r) o o o Altera Corporation 429FLEX 6000 Programmable Logic Device Family Data Sheet 430 Figure 8. LE Clear & Preset Modes Asynchronous Clear Asynchronous Preset labctri1 or tabetrl2 4D ar Chip-Wide Reset p PRN CLRN ao ay- labctri1 or p labctri2 Chip-Wide Reset Asynchronous Clear The flipflop can be cleared by either LABCTRL1 or LABCTRL2. Asynchronous Preset An asynchronous preset is implemented with an asynchronous clear. The MAX+PLUS II software provides preset control by using the clear and inverting the input and output of the register. Inversion control is available for the inputs to both LEs and IOEs. Therefore, this technique can be used when a register drives logic or drives a pin. In addition to the two clear and preset modes, FLEX 6000 devices provide a chip-wide reset pin (DEV_CLRn) that can reset all registers in the device. The option to use this pin is set in the MAX+PLUS II software before compilation. The chip-wide reset overrides all other control signals. Any register with an asynchronous preset will be preset when the chip-wide reset is asserted because of the inversion technique used to implement the asynchronous preset. The MAX+PLUS II software can use a programmable NOT-gate push-back technique to emulate simultaneous preset and clear or asynchronous load. However, this technique uses an additional three LEs per register. FastTrack Interconnect In the FLEX 6000 OptiFLEX architecture, connections between LEs and device I/O pins are provided by the FastTrack Interconnect, a series of continuous horizontal and vertical routing channels that traverse the device. This global routing structure provides predictable performance, even for complex designs. In contrast, the segmented routing in FPGAs requires switch matrices to connect a variable number of routing paths, increasing the delays between logic resources and reducing performance. Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet The FastTrack Interconnect consists of column and row interconnect channels that span the entire device. Each row of LABs is served by a dedicated row interconnect, which routes signals between LABs in the same row, and also routes signals from I/O pins to LABs. Additionally, the local interconnect routes signals between LEs in the same LAB and in adjacent LABs. The column interconnect routes signals between rows and routes signals from I/O pins to rows. LEs 1 through 5 of an LAB drive the local interconnect to the right, while LEs 6 through 10 drive the local interconnect to the left. The DATA1 and DATA3 inputs of each LE are driven by the local interconnect to the left; DATA2 and DATA4 are driven by the local interconnect to the right. The local interconnect also routes signals from LEs to I/O pins. Figure 9 shows an overview of the FLEX 6000 interconnect architecture. LEs in the first and last columns have drivers on both sides so that all LEs in the LAB can drive I/O pins via the local interconnect. Figure 9. FastTrack Interconnect Architecture Row Interconnect (n Channels) (1) \ \ Lei LE 1 through through To/From LE5 LE5 To/From Adjacent Adjacent LAB LE6 LE6 LAB through through LE 10 LE 10 ~~ a a _ mS Ls _ _ a ae _ _ ~~ - Local Interconnect (32 Channels) Column Interconnect (m Channels) (1) Note: (1) For EPF6010A, EPF6016, and EPF6016A devices, n = 144 channels and m = 20 channels; for EPF6024A devices, n = 186 channels and m = 30 channels. mal rc a > f=2] Oo o o Altera Corporation 431FLEX 6000 Programmable Logic Device Family Data Sheet 432 A row channel can be driven by an LE or by one of two column channels. These three signals feed a 3-to-1 multiplexer that connects to six specific row channels. Row channels drive into the local interconnect via multiplexers. Each column of LABs is served by a dedicated column interconnect. The LEs in an LAB can drive the column interconnect. The LEs in an LAB, a column IOE, or a row interconnect can drive the column interconnect. The column interconnect can then drive another rows interconnect to route the signals to other LABs in the device. A signal from the column interconnect must be routed to the row interconnect before it can enter an LAB. Each LE has a FastTrack Interconnect output and a local output. The FastTrack interconnect output can drive six row and two column lines directly; the local output drives the local interconnect. Each local interconnect channel driven by an LE can drive four row and two column channels. This feature provides additional flexibility, because each LE can drive any of ten row lines and four column lines. In addition, LEs can drive global control signals. This feature is useful for distributing internally generated clock, asynchronous clear, and asynchronous preset signals. A pin-driven global signal can also drive data signals, which is useful for high-fan-out data signals. Each LAB drives two groups of local interconnects, which allows an LE to drive two LABs, or 20 LEs, via the local interconnect. The row-to-local multiplexers are used more efficiently, because the multiplexers can now drive two LABs. Figure 10 shows how an LAB connects to row and column interconnects. Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Figure 10. LAB Connections to Row & Column Interconnects Each LE FastTrack Interconnect output can drive six row channels. | Each local channel driven byanLEcan ~~ Each LE output signal driving drive two column the FastTrack Interconnect can channels. Crive two column channels. At each intersection, four row channels can drive column channels. Row Interconnect Each local channel driven by an LE can drive four row channels. Row interconnect drives the local interconnect. From Adjacent Local Interconnect _._-_"" Local Interconnect Column Interconnect Any column channel can drive six row channels. An LE can be driven by any signal from two local interconnect areas. For improved routability, the row interconnect consists of full-length and half-length channels. The full-length channels connect to all LABs in a row; the half-length channels connect to the LABs in half of the row. In addition to providing a predictable, row-wide interconnect, this architecture provides increased routing resources. Two neighboring LABs can be connected using a half-length channel, which saves the other half of the channel for the other half of the row. One-third of the row channels are half-length channels. Altera Corporation 433 um rc m Pd a oa o oFLEX 6000 Programmable Logic Device Family Data Sheet Table 5 summarizes the FastTrack Interconnect resources available in each FLEX 6000 device. Table 5. FLEX 6000 FastTrack Interconnect Resources Device Rows | Channels per Columns Channels per Row Column EPF6010A 4 144 22 20 EPF6016 6 144 22 20 EPF6016A EPF6024A 7 186 28 30 In addition to general-purpose I/O pins, FLEX 6000 devices have four dedicated input pins that provide low-skew signal distribution across the device. These four inputs can be used for global clock and asynchronous clear control signals. These signals are available as control signals for all LEs in the device. The dedicated inputs can also be used as general- purpose data inputs because they can feed the local interconnect of each LAB in the device. Using dedicated inputs to route data signals provides a fast path for high fan-out signals. The local interconnect from LABs located at either end of two rows can drive a global control signal. For instance, in an EPF6016 device, LABs C1, D1, C22, and D22 can all drive global control signals. When an LE drives a global control signal, the dedicated input pin that drives that signal cannot be used. Any LE in the device can drive a global control signal by driving the FastTrack Interconnect into the appropriate LAB. To minimize delay, however, the MAX+PLUS II software places the driving LE in the appropriate LAB. The LE-driving-global signal feature is optimized for speed for control signals; regular data signals are better routed on the FastTrack Interconnect and do not receive any advantage from being routed on global signals. This LE-driving-global control signal feature is controlled by the designer and is not used automatically by the MAX+PLUS II software. See Figure 11. 434 Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Figure 11. Global Clock & Clear Distribution _ Note (1) Ky LL > J e tw e +> | QI ; <j-o i > e> <q <f+-e (2) 4 3) (4) cc . 1 [ <q | re ' | Dedicated <} Dedicated Inputs Inputs Q @ 4 | | : | . <j ; <f+o oe oo Notes: (1) The global clock and clear distribution signals are shown for EPF6016 and EPF6016A devices. In EPF6010A devices, LABs in rows B and C drive global signals. In EPF6024A devices, LABs in rows C and E drive global signals. (2) The local interconnect from LABs C1 and D1 can drive two global control signals on the left side. (3) Global signals drive into every LAB as clock, asynchronous clear, preset, and data signals. (4) The local interconnect from LABs C22 and D22 can drive two global control signals on the right side. mal rc m > aon o o oe Altera Corporation 435FLEX 6000 Programmable Logic Device Family Data Sheet 436 1/0 Elements An JOE contains a bidirectional 1/O buffer and a tri-state buffer. IOEs can be used as input, output, or bidirectional pins. An IOE receives its data signals from the adjacent local interconnect, which can be driven by a row or column interconnect (allowing any LE in the device to drive the IOE) or by an adjacent LE (allowing fast clock-to-output delays). A FastFLEX I/O pin is a row or column output pin that receives its data signals from the adjacent local interconnect driven by an adjacent LE. The IOE receives its output enable signal through the same path, allowing individual output enables for every pin and permitting emulation of open-drain buffers. The MAX+PLUS II Compiler uses programmable inversion to invert the data or output enable signals automatically where appropriate. Open-drain emulation is provided by driving the data input low and toggling the OE of each IOE. This emulation is possible because there is one OE per pin. A chip-wide output enable feature allows the designer to disable all pins of the device by asserting one pin (DEV_OE). This feature is useful during board debugging or testing. Figure 12 shows the IOE block diagram. Figure 12. IO0E Block Diagram _, lo Row or Column interconnect pee Chip-Wide Output Enable From LAB Local Interconnect im From LAB Local Interconnect th + y an ql Slew-Rate Control Altera CorporationAltera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Each IOE drives a row or column interconnect when used as an input or bidirectional pin. A row IOE can drive up to six row lines; a column IOE can drive up to two column lines. The input path from the I/O pad to the FastTrack Interconnect has a programmable delay element that can be used to guarantee a zero hold time. Depending on the placement of the IOE relative to what it is driving, the designer may choose to turn on the programmable delay to ensure a zero hold time. Figure 13 shows how an TOE connects to a row interconnect, and Figure 14 shows how an IOE connects to a column interconnect. Figure 13. [OE Connection to Row Interconnect Y Row Interconnect / Any LE can drive in through th vow and foal | Up to 10 10Es are on either interconnect. ~._ side of a row. Each IOE can drive up to six row channels, and each IOE data and OF signal is driven by the local interconnect. LAB \ FastFLEX 1/0: An LE can drive a pin through the local interconnect for faster clock-to-output times. a rc m = [2] ] i ) 437FLEX 6000 Programmable Logic Device Family Data Sheet SameFrame Pin-Outs 438 Figure 14. JOE Connection to Column Interconnect Each IOE can drive two column interconnect channels. Each !0E data and OE signal is driven to a local interconnect. IOE OE AA Ab FastFLEX 1/0: An LE can drive a pin through a local interconnect for faster = [~* clock-to-output times. < LAB > Any LE can drive a pin through the row and local interconnect. \ Column Interconnect Row Interconnect FLEX 6000A devices support the SameFrame pin-out feature for FineLine BGA packages. The SameFrame pin-out feature is the arrangement of balls on FineLine BGA packages such that the lower-ball-count packages form a subset of the higher-ball-count packages. SameFrame pin-outs provide the flexibility to migrate not only from device to device within the same package, but also from one package to another. A given printed circuit board (PCB) layout can support multiple device density /package combinations. For example, a single board layout can support an EPF6010A device in a 100-pin FineLine BGA package or an EPF6024A device in a 256-pin FineLine BGA package. The MAX+PLUS II software version 9.1 and higher provides support to design PCBs with SameFrame pin-out devices. Devices can be defined for present and future use. The MAX+PLUS II software generates pin-outs describing how to lay out a board to take advantage of this migration (see Figure 15). Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Figure 15. SameFrame Pin-Out Example Printed Circuit Board Designed for 256-PinFineLine BGA Package 100-Pin 256-Pin FineLine FineLine isiery 100-Pin FineLine BGA Package (Reduced I/O Count or Logic Requirements) 256-Pin FineLine BGA Package (Increased I/O Count or Logic Requirements) Table 6 lists the FLEX 6000A devices with the SameFrame pin-out feature. Table 6. FLEX 6000A Devices with SameFrame Pin-Outs Device 100-Pin FineLine BGA | 256-Pin FineLine BGA EPF6010A vw Y EPF6016A v EPF6024A wv This section discusses slew-rate control, the MultiVolt I/O interface, power sequencing, and hot-socketing for FLEX 6000 devices. Output Configuration Slew-Rate Control The output buffer in each IOE has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A slower slew rate reduces system noise and adds a maximum delay of 6.8 ns. The fast slew rate should be used for speed-critical outputs in systems that are adequately protected against noise. Designers can specify the slew rate on a pin-by-pin basis during design entry or assign a default slew rate to all pins on a device-wide basis. The slew rate setting affects only the falling edge of the output. mm rc asl =< [2] fo] o Altera Corporation 439FLEX 6000 Programmable Logic Device Family Data Sheet MultiVolt 1/0 Interface The FLEX 6000 device architecture supports the MultiVolt I/O interface feature, which allows FLEX 6000 devices to interface with systems of differing supply voltages. The EPF6016 device can be set for 3.3-V or 5.0-V I/O pin operation. This device has one set of Vcc pins for internal operation and input buffers (VCCINT), and another set for output drivers (VCCIO). The VCCINT pins on 5.0-V FLEX 6000 devices must always be connected to a 5.0-V power supply. With a 5.0-V Vecyny level, input voltages are at TTL levels and are therefore compatible with 3.3-V and 5.0-V inputs. The VCCIO pins on 5.0-V FLEX 6000 devices can be connected to either a 3.3-V or 5.0-V power supply, depending on the output requirements. When the VCCIO pins are connected to a 5.0-V power supply, the output levels are compatible with 5.0-V systems. When the VCCIO pins are connected to a 3.3-V power supply, the output high is 3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with Vecio levels lower than 4.75 V incur a nominally greater timing delay of top2 instead of top1r On 3.3-V FLEX 6000 devices, the VCCINT pins must be connected to a 3.3-V power supply. Additionally, 3.3-V FLEX 6000A devices can interface with 2.5-V, 3.3-V, or 5.0-V systems when the VCCIO pins are tied to 2.5 V. The output can drive 2.5-V systems, and the inputs can be driven by 2.5-V, 3.3-V, or 5.0-V systems. When the VCCIO pins are tied to 3.3 V, the output can drive 3.3-V or 5.0-V systems. MultiVolt I/Os are not supported on 100-pin TQFPs. Table 7 describes FLEX 6000 MultiVolt I/O support. Table 7. FLEX 6000 MultiVolt /0 Support Veciwr | Vecio Input Signal (V) Output Signal (V) ) ) 2.5 3.3 5.0 2.5 3.3 5.0 3.3 2.5 Y Y Y ~ 3.3 3.3 Y Y Y |v) vo Y 5.0 3.3 Y 4 vv Y 5.0 5.0 Y Y Note: (1) When Vecjo = 3.3 V, a FLEX 6000 device can drive a 2.5-V device that has 3.3-V tolerant inputs. 440 Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Open-drain output pins on FLEX 6000 devices (with a pull-up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that require a Vj;; of 3.5 V. When the open-drain pin is active, it will drive low. When the pin is inactive, the trace will be pulled up to 5.0 V by the resistor. The open- drain pin will only drive low or tri-state; it will never drive high. The rise time is dependent on the value of the pull-up resistor and load impedance. The Ig, current specification should be considered when selecting a pull-up resistor. Output pins on 5.0-V FLEX 6000 devices with Vecjo = 3.3 V or 5.0 V (with a pull-up resistor to the 5.0-V supply) can also drive 5.0-V CMOS input pins. In this case, the pull-up transistor will turn off when the pin voltage exceeds 3.3 V. Therefore, the pin does not have to be open-drain. Power Sequencing & Hot-Socketing Because FLEX 6000 family devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. The Vecyjg and Veciyr power planes can be powered in any order. Signals can be driven into FLEX 6000 devices before and during power up without damaging the device. Additionally, FLEX 6000 devices do not drive out during power up. Once operating conditions are reached, FLEX 6000 devices operate as specified by the user. IEEE Std. All FLEX 6000 devices provide JTAG BST circuitry that comply with the IEEE Std. 1149.1-1990 specification. Table 8 shows JTAG instructions for 1 149.1 (JTAG) FLEX 6000 devices. JTAG BST can be performed before or after Bounda ry- Scan configuration, but not during configuration. Support Table 8. FLEX 6000 JTAG Instructions JTAG Instruction Description SAMPLE/PRELOAD | Allows a snapshot of the signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. EXTEST Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test result at the input pins. BYPASS Places the 1-bit bypass register between the TDI and TDo pins, which allows the BST data to pass synchronously through the selected device to adjacent devices during normal device operation. mal aa m = a i=] [aon] o Altera Corporation 441FLEX 6000 Programmable Logic Device Family Data Sheet The instruction register length for FLEX 6000 devices is three bits. Table 9 shows the boundary-scan register length for FLEX 6000 devices. Table 9. FLEX 6000 Device Boundary-Scan Register Length Device Boundary-Scan Register Length EPF6010A 522 EPF6016 621 EPF6016A 522 EPF6024A 681 FLEX 6000 devices include a weak pull-up on JTAG pins. . = aw =e Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) for more information. Figure 16 shows the timing requirements for the JTAG signals. Figure 16. JTAG Waveforms TMS x XK X xX ror X x x x TCK TDO Signal to Be Captured Signal to Be Driven 442 Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Generic Testing Altera Corporation Table 10 shows the JTAG timing parameters and values for FLEX 6000 devices. Table 10. JTAG Timing Parameters & Values Symbol Parameter Min | Max | Unit tycp TCK clock period 100 ns lich TCK clock high time 50 ns tye. TCK clock low time 50 ns typsu JTAG port setup time 20 ns typn JTAG port hold time 45 ns typco JTAG port clock-to-output 25 ns typzx JTAG port high impedance to valid output 25 ns typxz JTAG port valid output to high impedance 25 ns tussu Capture register setup time 20 ns su Capture register hold time 45 ns tysco Update register clock-to-output 35 ns tyszx Update register high impedance to valid output 35 ns tysxz Update register valid output to high impedance 35 ns Each FLEX 6000 device is functionally tested. Complete testing of each configurable SRAM bit and all logic functionality ensures 100% configuration yield. AC test measurements for FLEX 6000.devices are made under conditions equivalent to those shown in Figure 17. Multiple test patterns can be used to configure devices during all stages of the production flow. Figure 17. AC Test Conditions Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for accurate 4642 voc measurement. Threshold tests must (703 Q) not be performed under AC conditions. (521 Q] Large-amplitude, fast-ground-current transients normally occur as the Device To Test device outputs discharge the load Output System capacitances. When these transients flow through the parasitic inductance between the device 250 Q ground pin and the test system ground, (8.06 kQ) C1 (includes significant reductions in observable [481 Q] JIG ital noise immunity can result. Numbers capacitance) without parentheses are for 5.0-V Device input devices or outputs. Numbers in rise and fall parentheses are for 3.3-V devices or times < 3ns outputs. Numbers in brackets are for 2.5-V devices or outputs. baa! aa m =< a a a fam] 443FLEX 6000 Programmable Logic Device Family Data Sheet Operating Tables 11 through 18 provide information on absolute maximum ratings, was recommended operating conditions, operating conditions, and Conditions capacitance for 5.0-V and 3.3-V FLEX 6000 devices. Table 11. FLEX 6000 5.0-V Device Absolute Maximum Ratings _ Note (1) Symbol Parameter Conditions Min Max Unit Vec Supply voltage With respect to ground (2) -2.0 7.0 Vv V; DC input voltage ~2.0 7.0 Vv lout DC output current, per pin -25 25 mA Tst Storage temperature No bias -65 150 C Tame Ambient temperature Under bias 65 135 C Ty Junction temperature PQFP, TQFP, and BGA packages 135 S Table 12. FLEX 6000 5.0-V Device Recommended Operating Conditions Symbol Parameter Conditions Min Max Unit Vecint | Supply voltage for internal togic | (3), (4) 4.75 (4.50) 5.25 (5.50) Vv and input buffers Vecio Supply voltage for output buffers, | (3), (4) 4.75 (4.50) 5.25 (5.50) Vv .0-V operation Supply voltage for output buffers, | (3), (4) 3.00 (3.00) 3.60 (3.60) v 3.3-V operation Vi Input voltage -0.5 Vecint + 0.5 Vv Vo Output voltage 0 Vecio v Ty Operating temperature For commercial use 0 85 C For industrial use 40 100 C ta Input rise time 40 ns te Input fall time 40 ns 444 Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Table 13. FLEX 6000 5.0-V Device DC Operating Conditions _ Notes (5), (6) Symbol Parameter Conditions Min Tya Max Unit Vin High-level input voltage 2.0 Vocint + 0.5] V Vit Low-level input voltage -0.5 0.8 Vv Vou 5.0-V high-level TTL output lon = -8 mA DC, Vecig = 4.75 V (7) 2.4 Vv voltage 3.3-V high-level TTL output low = -8 MA DC, Vecig = 3.00 V (7) 2.4 v voltage 3.3-V high-level CMOS output lox = -0.1 mA DC, Vecig = 3.00 V (7) | Vocin- 0.2 Vv voltage Vou 5.0-V low-level TTL output lol = 8 mA DC, Vecio = 4.75 V (8) 0.45 Vv voltage 3.3-V low-level TTL output lo. = 8 MA DC, Vecio = 3.00 V (8) 0.45 Vv voltage 3.3-V low-level CMOS output lo, = 0.1 mA DC, Vecio = 3.00 V (8) 0.2 Vv voltage I Input pin leakage current Vi = Vee or ground -10 10 pA loz Tri-stated I/O pin leakage current | Vg = Vcc or ground 40 40 HA loco Vcc supply current (standby) V| = ground, no load 0.5 5 mA Table 14. FLEX 6000 5.0-V Device Capacitance __ Note (9) Symbol Parameter Conditions Min Max Unit Cin Input capacitance for I/O pin Vin = OV, f= 1.0 MHz 8 pF Cinctk | Input capacitance for dedicated input | Vix = 0 V, f = 1.0 MHz 12 pF Court Output capacitance Vout =0V, f= 1.0 MHz 8 pF Notes to tables: (1) (2) (3) (4) 6) (6) (7) (8) (9) See the Operating Requirements for Altera Devices Data Sheet in this data book. Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 7.0 V for input currents less than 100 mA and periods shorter than 20 ns. Numbers in parentheses are for industrial-temperature-range devices. Maximum Vcc rise time to 100 ms. Vcc must rise monotonically. Typical values are for T 4 = 25 C and Vcc = 5.0 V. These values are specified under Table 12 on page 444. The lop parameter refers to high-level TTL or CMOS output current. The Io, parameter refers to low-level TTL or CMOS output current. This parameter applies to open-drain pins as well as output pins. Capacitance is sample-tested only. Altera Corporation 445 an - m ad mz) o i] =FLEX 6000 Programmable Logic Device Family Data Sheet Table 15. FLEX 6000 3.3-V Device Absolute Maximum Ratings _ Note (1) Symbol Parameter Conditions Min Max Unit Vcc Supply voltage With respect to ground (2) 0.5 46 Vv vi DC input voltage -2.0 5.75 Vv lout DC output current, per pin 25 25 mA Tste Storage temperature No bias 65 150 C TamB Ambient temperature Under bias -65 135 C Ty Junction temperature PQFP, PLCC, and BGA packages 135 C Table 16. FLEX 6000 3.3-V Device Recommended Operating Conditions Symbol Parameter Conditions Min Max Unit Vecinr | Supply voltage for internal logic and | (3), (4) 3.00 (3.00) 3.60 (3.60) Vv input buffers Vecio Supply voltage for output buffers, (3), (4) 3.00 (3.00) 3.60 (3.60) v 3.3-V operation Supply voltage for output buffers, (3), (4) 2.30 (2.30) 2.70 (2.70) Vv 2.5-V operation vi Input voltage -0.5 5.75 Vv Vo Output voltage 0 Vocio Vv Ty Operating temperature For commercial use 0 85 C For industrial use 40 100 C tr Input rise time 40 ns te Input fall time 40 ns 446 Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Table 17. FLEX 6000 3.3-V Device DC Operating Conditions Notes (5), (6) Symbol Parameter Conditions Min |Typ Max = | Unit Vin High-level input voltage 1.7 5.75 v Vit Low-level input voltage 0.5 0.8 v Vou 3.3-V high-level TTL output lou =-8 mA DC, Vecio = 3.00 V (7) 2.4 V voltage 3.3-V high-level CMOS output fon = 0.1 MA DC, Vecig = 3.00 V (7) | Vecig 0.2 Vv voltage 2.5-V high-level output voltage low = -100 PA DC, Vecio = 2.30 V (7) 2.1 Vv lon =1 mA DC, Vecig = 2.30 V (7) 2.0 Vv lon =-2 MA DC, Vecig = 2.30 V (7) 17 Vv Vor 3.3-V low-level TTL output lo, = 8 MA DC, Vecio = 3.00 V (8) 0.45 v voltage 3.3-V low-level CMOS output lo. = 0.1 mA DC, Vecig = 3.00 V (8) 0.2 Vv voltage 2.5-V low-level output voltage lo = 100 pA DC, Vecig = 2.30 V (8) 0.2 Vv lo, = 1 MA DC, Vegin = 2.30 V (8) 0.4 v lo, = 2 MA DC, Vecig = 2.30 V (8) 0.7 Vv \ Input pin leakage current V, = 5.3 V to ground -10 10 pA loz Tri-stated I/O pin leakage current | Vo = 5.3 V to ground 10 10 pA leco Vec supply current (standby) V| = ground, no load 0.5 5 mA Table 18. FLEX 6000 3.3-V Device Capacitance __Note (9) Symbol Parameter Conditions Min Max Unit Cw Input capacitance for I/O pin Vin = 0 V, f= 1.0 MHz 8 pF Ciweik | Input capacitance for dedicated input | Vjy = 0 V, f = 1.0 MHz 12 pF Cour Output capacitance Vout =0V, f= 1.0 MHz 8 pF Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet in this data book. (2) The minimum DC input voltage is -0.5 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 5.75 V for input currents less than 100 mA and periods shorter than 20 ns. (3) Numbers in parentheses are for industrial-temperature-range devices. (4) Maximum Vcc rise time is 100 ms. Vcc must rise monotonically. (5) Typical values are for T, = 25 C and Vcc = 3.3 V. (6) These values are specified under Table 16 on page 446. (7) The Igy parameter refers to high-level TTL or CMOS output current. (8) The Io, parameter refers to low-level TTL or CMOS output current. This parameter applies to open-drain pins as well as output pins. (9) Capacitance is sample-tested only. Altera Corporation 447 mal rc m Pt [=>] oO ao oFLEX 6000 Programmable Logic Device Family Data Sheet Figure 18 shows the typical output drive characteristics of 5.0-V and 3.3-V FLEX 6000 devices with 5.0-V, 3.3-V, and 2.5-V Vecio. When Vecio = 5.0 V on EPF6016 devices, the output driver is compliant with the PCI Local Bus Specification, Revision 2.2 for 5.0-V operation. When Vecio = 3.3 V on the EPF6010A and EPF6016A devices, the output driver meets the drive requirements of the PCI Local Bus Specification, Revision 2.2 for 3.3-V operation. Figure 18. Output Drive Characteristics EPF6010A EPF6016A Voor = 3.3 V 100 Veco = 3.3 V Room Temperature Typical Ip 75 Output Current (mA) 50 lon 26 1 2 3 4 5 Vo Output Voltage (V) EPF6016 150- lot 120 Typical Io 90 Output Voeint = 5.0 V Current (mA) Voecio = 5.0 V 60;- Room Temperature 30f- 1 2 3 4 5 Vo Output Voitage (V) EPF6024A wor Veoint = 3.3 V peso +33 oom Temperature Typicallg = 75 P Output Current (mA) sok lon 25k lon 1 2 3 4 5 Vo Output Voltage (V) 448 EPF6010A EPF6016A Voor = 3.3 V 100 Vecio = 2.5 V Roam Temperature Typicallg 75 Output lou Current (mA) 50 25 1 2 3 4 5 Vo Output Voltage (V) EPF6016 lo. 120 Voowr ray ; gob ccio = 3. Typical lo Room Temperature Output Current (mA) 60 lox 30 1 2 333 4 5 Vo Output Voltage (V) EPF6024A oor Voor = 3.3 V Vecio= 2.5 V . Room Temperature Typicalig = 75- Output Current (mA) lov sok ask lon 1 2 3 4 5 Vo Output Voltage (V) Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Timing Model Altera Corporation The continuous, high-performance FastTrack Interconnect routing resources ensure predictable performance and accurate simulation and timing analysis. This predictable performance contrasts with that of FPGAs, which use a segmented connection scheme and therefore have unpredictable performance. Device performance can be estimated by following the signal path from a source, through the interconnect, to the destination. For example, the registered performance between two LEs on the same row can be calculated by adding the following parameters: LE register clock-to-output delay (fco +trEG TO _oUuT) Routing delay (frow + tLocat) LE LUT delay (!p4Ta_to_REG) LE register setup time (ts,)) The routing delay depends on the placement of the source and destination LEs. A more complex registered path may involve multiple combinatorial LEs between the source and destination LEs. Timing simulation and delay prediction are available with the MAX+PLUS II Simulator and Timing Analyzer, or with industry- standard EDA tools. The MAX+PLUS II Simulator offers both pre-synthesis functional simulation to evaluate logic design accuracy and post-synthesis timing simulation with 0.1-ns resolution. The MAX+PLUS II Timing Analyzer provides point-to-point timing delay information, setup and hold time analysis, and device-wide performance analysis. Figure 19 shows the overall timing model, which maps the possible routing paths to and from the various elements of the FLEX 6000 device. ma aa as Po an oa o o 449FLEX 6000 Programmable Logic Device Family Data Sheet Figure 19. FLEX 6000 Timing Model | tRow it. a] Carry-in from Cascade-In from Previous LE Previous LE . 'casc_TO_OUT 'pATA_TO_OUT 'REG_TO_OUT 'CARRY_TO_OUT Vv tLocaL tomo | Cc ~ * low. c 450 1LEGLOBAL Ie 'REG_TO_REG | tcasc_TO_REG >| ICARRY_TO_REG of tpaTa_TO_REG > 7 A >) t "| 4p cir vv a Y {CARRY_TO_CARRY ICARRY_TO_CASC 'REG_TO_CARRY | tease_to_casc tpaTA_TO_CARRY tREG TO_CASC foATA_TO_CASC 1. too, ~- LE : Y tapcanny Carry-out to Carry-outto Cascade-out Cascade-out NextLE in NextLEin toNextLEin to Next LE in Same LAB Next LAB Same LAB Next LAB Li} tin q__ tIN_DELAY 1OE PF) ton, PS] 1/0 Pin Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Tables 19 through 21 describe the FLEX 6000 internal timing microparameters, which are expressed as worst-case values. Using hand calculations, these parameters can be used to estimate design performance. However, before committing designs to silicon, actual worst-case performance should be modeled using timing simulation and timing analysis. Tables 22 and 23 describe FLEX 6000 external timing parameters. Table 19. LE Timing Microparameters _Note (1) Symbol Parameter Conditions 'REG_TO_REG LUT delay for LE register feedback in carry chain tcasc_TO_REG Cascade-in to register delay fcapRy_To_ReG | Carry-in to register delay 'DATA_TO_REG LE input to register delay {CASC_TO_OUT Cascade-in to LE output delay fcanRy_to_our | Carry-in to LE output delay tpaTA_TO_OUT LE input to LE output delay tREG_TO_OUT Register output to LE output delay toy LE register setup time before clock; LE register recovery time after asynchronous clear ty LE register hold time after clock tco LE register clock-to-output delay tcLR LE register clear delay tc LE register control signal delay tp cLR Synchronous load or clear delay in counter mode icanRY_TO_caRRY | Carry-in to carry-out delay treG_To_carry | Register output to carry-out delay topata_To_caRnAy |LE input to carry-out delay tcanry_To_casc | Carry-in to cascade-out delay tcasc_To_casc | Cascade-in to cascade-out delay tREG_TO_CASC Register-out to cascade-out delay tpata_To_casc | LE input to cascade-out delay toy LE register clock high time to LE register clock low time Altera Corporation 451 mal rc inal Pa a ao io] Lo)FLEX 6000 Programmable Logic Device Family Data Sheet Table 20. IOE Timing Microparameters _Note (1) Symbol Parameter Conditions top1 Output buffer and pad delay, slow slew rate = off, Vecio = Vecint C1 = 35 pF (2) lope Output buffer and pad delay, slow slew rate = off, Vecio = low voltage C1 = 35 pF (3) tops Output buffer and pad delay, slow slew rate = on Ci = 35 pF (4) tyz Output buffer disable delay C1=5pF toy Output buffer enable delay, slow slew rate = off, Vocio = Vocint C1 = 35 pF (2) toxo Output buffer enable delay, slow slew rate = off, Vocio = low voltage Ci = 35 pF (3) tox3 IOE output buffer enable delay, slow slew rate = on C1 = 35 pF (4) toe Output enable control delay tin Input pad and buffer to FastTrack interconnect delay UN_DELAY Input pad and buffer to FastTrack Interconnect delay with additional delay turned on Table 21. Interconnect Timing Micreparameters _ Note (1) Symbol Parameter Conditions tLOCAL LAB local interconnect delay trow Row interconnect routing delay (5) toot Column interconnect routing delay (5) tpIN_D Dedicated input to LE data delay (5) toin_c Dedicated input to LE control delay ti EGLOBAL LE output to LE control via internally-generated global signal delay (5) tLABCARRY Routing delay for the carry-out of an LE driving the carry-in signal of a different LE in a different LAB / tLABCASC Routing delay for the cascade-out signal of an LE driving the cascade-in signal of a different LE in a different LAB Table 22. External Reference Timing Parameters Symbol Parameter Conditions ty Register-to-register test pattern (6) torr Register-to-register delay via 4 LEs, 3 row interconnects, and 4 local (7) interconnects 452 Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Table 23. External Timing Parameters Symbol Parameter Conditions twsu Setup time with global clock at LE register (8) tiny Hold time with global clock at LE register (8) toutco Clock-to-output delay with global clock with LE register using FastFLEX '/O | (8) pin Notes to tables: (1) Microparameters are timing delays contributed by individual architectural elements and cannot be measured explicitly. (2) Operating conditions: Vecto = 5.0 V + 5% for commercial use in 5.0-V FLEX 6000 devices. Vecio = 5.0 V + 10% for industrial use in 5.0-V FLEX 6000 devices. Vecio = 3.3 V + 10% for commercial or industrial use in 3.3-V FLEX 6000 devices. (3) Operating conditions: Vecio = 3.3 V + 10% for commercial or industrial use in 5.0-V FLEX 6000 devices. Vecio = 2.5 V 0.2 V for commercial or industrial use in 3.3-V FLEX 6000 devices. (4) Operating conditions: Vcjo = 2.5 V, 3.3 V, or 5.0 V. (5) These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing analysis are required to determine actual worst-case performance. (6) This timing parameter shows the delay of a register-to-register test pattern and is used to determine speed grades. There are 12 LEs, including source and destination registers. The row and column interconnects between the registers vary in length. (7) This timing parameter is shown for reference and is specified by characterization. (8) This timing parameter is specified by characterization. a) aad as Pad a a So o Altera Corporation 453FLEX 6000 Programmable Logic Device Family Data Sheet Tables 24 through 28 show the timing information for EPF6010A and EPF6016A devices. Table 24. LE Timing Microparameters for EPF6010A & EPF6016A Devices Parameter Speed Grade Unit 4 2 3 Min Max Min Max Min Max 'REG_TO_REG 1.2 1.3 17 ns 'CASC_TO_REG 0.9 1.0 1.2 ns 'CARRY_TO_REG 0.9 1.0 1.2 ns 'DATA_TO_REG 11 1.2 1.5 ns 'casc_TO_OUT 1.3 1.4 1.8 ns 'CARRY_TO_OUT 1.6 1.8 2.3 ns 'paTA_TO_OUT 1.7 2.0 25 ns 'REG_TO_OUT 0.4 0.4 0.5 ns fsu 0.9 1.0 1.3 ns fy 1.4 1.7 2.1 ns lco 0.3 0.4 0.4 ns four 0.4 0.4 0.5 ns lo 1.8 2.1 2.6 ns lo cLA 1.8 2.1 2.6 ns CARRY_TO_CARRY 0.1 0.1 0.1 ns 'REG TO_CARRY 1.6 1.9 2.3 ns 'DATA_TO_CARAY 24 2.5 3.0 ns ICARRY_TO_CASC 1.0 11 1.4 ns 'caSC_TO_CASC 0.5 0.6 0.7 ns 'REG_TO_CASC 1.4 1.7 2.1 ns 'DATA_TO_CASC 14 1.2 1.5 ns low 2.5 3.0 3.5 ns lor 2.5 3.0 3.5 ns 454 Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Table 25. IOE Timing Microparameters for EPF6010A & EPF6016A Devices Parameter Speed Grade Unit -1 -2 3 Min Max Min Max Min Max loo1 1.9 2.2 2.7 ns lop2 4.1 4.8 5.8 ns long 5.8 6.8 8.3 ns tyz 1.4 1.7 2.1 ns tyzy 1.4 1.7 2.1 ns tyze 3.6 4.3 5.2 ns tyz9 5.3 6.3 77 ns hoe 0.5 0.6 0.7 ns tin 3.6 4.1 5.1 ns lIN_DELAY 4.8 5.4 6.7 ns Table 26. Interconnect Timing Microparameters for EPF6010A & EPF6016A Devices Parameter Speed Grade Unit -1 -2 3 Min Max Min Max Min Max {LOCAL 0.7 0.7 1.0 ns trow 2.9 3.2 3.2 ns tco 1.2 1.3 1.4 ns ton D 5.4 5.7 6.4 ns lpIN_C 4.3 5.0 6.1 ns {LEGLOBAL 2.6 3.0 3.7 ns {LABCARRY 0.7 0.8 0.9 ns {LABCASC 1.3 1.4 1.8 ns Table 27. External Reference Timing Parameters for EPF6010A & EPF6016A Devices Parameter Device Speed Grade Unit -1 -2 -3 Min Max Min Max Min Max ty EPF6010A 37.6 43.6 53.7 ns EPF6016A 38.0 44.0 54.1 ns Altera Corporation 455 7m rc m =< a o So oFLEX 6000 Programmable Logic Device Family Data Sheet Table 28. External Timing Parameters for EPF6010A & EPF6016A Devices Parameter Speed Grade Unit -1 2 -3 Min Max Min Max Min Max tinsu 2.1 (1) 2.4 (1) 3.3 (1) ns tind 0.2 (2) 0.3 (2) 0.1 (2) ns toutco 2.0 7.1 2.0 8.2 2.0 10.1 ns Notes: (1) Setup times are longer when the Increase Input Delay option is turned on. The setup time values are shown with the Increase Input Delay option turned off. (2) Hold time is zero when the Increase Input Delay option is turned on. Tables 29 through 33 show the timing information for EPF6016 devices. Table 29. LE Timing Microparameters for EPF6016 Devices (Part 1 of 2) Parameter Speed Grade Unit 2 3 Min Max Min Max 'REG_TO_REG 2.2 2.8 ns 'cASC_TO_REG 0.9 1.2 ns 'CARRY_TO_REG 1.6 2.1 ns tDATA_TO_REG 2.4 3.0 ns caSC_TO_OUT 1.3 17 ns 'CARRY_TO_OUT 2.4 3.0 ns tpATA_TO_OUT 2.7 3.4 ns 'REG_TO_OUT 0.3 0.5 ns toy 1.1 1.6 ns ty 1.8 2.3 ns co 0.3 0.4 ns toua 0.5 0.6 ns te 1.2 1.5 ns Lp CLR 1.2 1.5 ns 'CARRY_TO_CARRY 0.2 0.4 ns 'REG_TO_CARRY 0.8 1.4 ns tDATA_TO_CARAY 1.7 2.2 ns tCARRY_TO_CASC 1.7 2.2 ns 'caSC_TO_CASC 0.9 1.2 ns 456 Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Table 29. LE Timing Microparameters for EPF6016 Devices (Part 2 of 2) Parameter Speed Grade Unit 2 3 Min Max Min Max tREG_TO_CASC 1.6 2.0 ns 'DATA_TO_CASC 1.7 2.1 tns tou 4.0 4.0 ns tor 4.0 4.0 ns Table 30. 1OE Timing Microparameters for EPF6016 Devices Parameter Speed Grade Unit -2 -3 Min Max Min Max top1 2.3 2.8 ns top2 4.6 5.1 ns top3 4.7 5.2 ns tyz 2.3 2.8 ns boxy 2.3 2.8 ns texo 4.6 5.1 ns tzx3 4.7 5.2 ns toe 0.5 0.6 ns tin 3.3 4.0 ns tin_ DELAY 4.6 5.6 ns mn a a > a i] oa ) Altera Corporation 457FLEX 6000 Programmable Logic Device Family Data Sheet Table 31. Interconnect Timing Microparameters for EPF6016 Devices Parameter Speed Grade Unit -2 3 Min Max Min Max tLOCAL 0.8 1.0 ns tpow 29 3.3 ns toot 2.3 2.5 ns tpin_D 49 6.0 ns tpin_C 4.8 6.0 ns tL EGLOBAL 3.1 3.9 ns tL ABCARRY 0.4 0.5 ns tL aABCASC 0.8 1.0 ns Table 32. External Reference Timing Parameters for EPF6016 Devices Parameter Speed Grade Unit -2 3 Min Max Min Max ty 53.0 65.0 ns torr 16.0 20.0 ns Table 33. External Timing Parameters for EPF6016 Devices Parameter Speed Grade Unit -2 3 Min Max Min Max tinsu 3.2 4.1 ns {INH 0.0 0.0 ns toutco 2.0 7.9 2.0 9.9 ns 458 Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Tables 34 through 38 show the timing information for EPF6024A devices. Table 34. LE Timing Microparameters for EPF6024A Devices Parameter Speed Grade Unit 1 2 3 Min Max Min Max Min Max 'REG_TO_REG 1.2 1.3 1.6 ns iCASC_TO_REG 0.7 0.8 1.0 ns tcARRY_TO_REG 1.6 1.8 2.2 ns tpATA_TO_REG 1.3 1.4 1.7 ns icaSC_TO_OUT 1.2 1.3 1.6 ns ICARRY_TO_OUT 2.0 2.2 2.6 ns toaTA_TO_QUT 1.8 2.1 2.6 ns {REG _TO_OUT 0.3 0.3 0.4 ns toy 0.9 1.0 1.2 ns ty 1.3 1.4 1.7 ns tco 0.2 0.3 0.3 ns tcLA 0.3 0.3 0.4 ns tc 1.9 24 2.5 ns tip CLR 1.9 2.1 2.5 ns {CARRY_TO_CARRY 0.2 0.2 0.3 ns 'REG_TO_CARRY 1.4 1.6 1.9 ns 'DATA_TO_CARRY 1.3 1.4 1.7 ns tcARRAY_TO_CASC 14 1.2 1.4 ns icASC_TO_CASC 0.7 0.8 1.0 ns tREG_TO_CASC 1.4 1.6 1.9 ns tDATA_TO_CASC 1.0 1.1 1.3 ns toy 2.5 3.0 3.5 ns to. 2.5 3.0 3.5 ns ms) faa m = an oe o oa Altera Corporation 459FLEX 6000 Programmable Logic Device Family Data Sheet Table 35. 1OE Timing Microparameters for EPF6024A Devices Parameter Speed Grade Unit -1 2 3 Min Max Min Max Min Max toni 1.9 2.1 2.5 ns top2 4.0 44 5.3 ns tona 7.0 7.8 9.3 ns tyz 43 4.8 5.8 ns tyzy 4.3 4.8 5.8 ns tyzo 6.4 74 8.6 ns tyz3 9.4 10.5 12.6 ns toe 0.5 0.6 0.7 ns tin 3.3 3.7 4.4 ns liN_ DELAY 5.3 5.9 7.0 ns Table 36. Interconnect Timing Microparameters for EPF6024A Devices Parameter Speed Grade Unit 1 2 3 Min Max Min Max Min Max tLocaL 0.8 0.8 11 ns trow 3.0 3.1 3.3 ns toot 3.0 3.2 3.4 ns toIn_D 5.4 5.6 6.2 ns toin_c 4.6 5.1 6.1 ns tL EGLOBAL 3.1 3.5 4.3 ns tLABCARRY 0.6 0.7 0.8 ns tL ABCASC 0.3 0.3 0.4 ns Table 37. External Reference Timing Parameters for EPF6024A Devices Parameter Speed Grade Unit -1 2 3 Min Max Min Max Min Max t 45.0 50.0 60.0 ns 460 Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Table 38. External Timing Parameters for EPF6024A Devices Parameter Speed Grade Unit -1 2 3 Min Max Min Max Min Max tinsu 2.0 (1) 2.2 (1) 2.6 (1) ns tin 0.2 (2) 0.2 (2) 0.3 (2) ns toutco 2.0 7.4 2.0 8.2 2.0 9.9 ns Notes: (1) Setup times are longer when the Increase Input Delay option is turned on. The setup time values are shown with the Increase Input Delay option turned off. (2) Hold time is zero when the Increase Input Delay option is turned on. Power The supply power (P) for FLEX 6000 devices can be calculated with the . following equations: Consumption P= Pinr + Pio P = (ecstanpsy + Iecactive) x Vcc + Pio Typical Iccspanppy Values are shown as Icco in the FLEX 6000 Device DC Operating Conditions table on pages 444 and 445 of this data sheet. The Iccactive Value depends on the switching frequency and the application logic. This value is based on the amount of current that each LE typically consumes. The Pjg value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera Devices) in this data book. The Iccactive Value can be calculated with the following equation: _ pA Iccactive = Kx fax x N x togie x aE Where: fyax = Maximum operating frequency in MHz N = Total number of LEs used in a FLEX 6000 device togrc = Average percentage of LEs toggling at each clock (typically 12.5%) K = Constant, shown in Table 39 mn rc fa = a =] = ) Altera Corporation 461FLEX 6000 Programmable Logic Device Family Data Sheet 462 Table 39. K Constant Values Device K Value EPF6010A 14 EPF6016 88 EPF6016A 14 EPF6024A 14 This calculation provides an Icc estimate based on typical conditions with no output load. The actual Icc should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. To better reflect actual designs, the power model (and the constant K in the power calculation equations shown above) for continuous interconnect FLEX devices assumes that LEs drive FastTrack Interconnect channels. In contrast, the power model of segmented FPGAs assumes that all LEs drive only one short interconnect segment. This assumption may lead to inaccurate results, compared to measured power consumption for an actual design in a segmented interconnect FPGA. Figure 20 shows the relationship between the current and operating frequency for EPF6010A, EPF6016, EPF6016A, and EPF6024A devices. Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Figure 20. Iceacrive VS. Operating Frequency EPF6010A EPF6016 1000 200 800 150 loc Supply lec Supply 600 Current Current (may (mA) 400 50 200 0 T T 0 F T 50 100 30 60 Frequency (MHz) Frequency (MHz) EPF6016A EPF6024A 250 400 200 300 lec Supply 15 loc Supply Current Current 200 (mA) 100 (mA) 50 100 0 50 100 9 50 100 Frequency (MHz) Frequency (MHz) Device The FLEX 6000 architecture supports several configuration schemes to . load a design into the device(s) on the circuit board. This section Configuration & summarizes the device operating modes and available device 0 pe ration configuration schemes. . = @ =-&e Application Note 87 (Configuring FLEX 6000 Devices) for detailed Altera Corporation information on configuring FLEX 6000 devices, including sample schematics, timing diagrams, configuration options, pins names, and timing parameters. mn - m 4 i=2) i] i=] jo 463FLEX 6000 Programmable Logic Device Family Data Sheet Operating Modes The FLEX 6000 architecture uses SRAM configuration elements that require configuration data to be loaded every time the circuit powers up. This process of physically loading the SRAM data into a FLEX 6000 device is known as configuration. During initializationa process that occurs immediately after configurationthe device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri- stated during power-up, and before and during configuration. The configuration and initialization processes of a device are referred to as command mode; normal device operation is called user mode. SRAM configuration elements allow FLEX 6000 devices to be reconfigured in-circuit by loading new configuration data into the device. Real-time reconfiguration is performed by forcing the device into command mode with a device pin, loading different configuration data, reinitializing the device, and resuming user-mode operation. The entire reconfiguration process requires less than 100 ms and is used to dynamically reconfigure an entire system. Also, in-field system upgrades can be performed by distributing new configuration files. Configuration Schemes The configuration data for a FLEX 6000 device can be loaded with one of three configuration schemes, which is chosen on the basis of the target application. An EPC2, EPC1, or EPC1441 configuration device or intelligent controller can be used to control the configuration of a FLEX 6000 device, allowing automatic configuration on system power- up. Multiple FLEX 6000 devices can be configured in any of the three configuration schemes by connecting the configuration enable input (nCE) and configuration enable output (nCEO) pins on each device. Table 40 shows the data sources for each configuration scheme. Table 40. Configuration Schemes Configuration Scheme Data Source Configuration device EPC2, EPC1, or EPC 1441 configuration device Passive serial (PS) BitBlaster, ByteBlaster, or ByteBlasterMvV download cables, or serial data source (1) Passive serial asynchronous | BitBlaster, ByteBlaster, or ByteBlasterMV (PSA) download cables, or serial data source (1) Note: (1) The ByteBlaster cable is obsolete and is replaced by the ByteBlasterMV cable, which can program or configure 2.5-V, 3.3-V, and 5.0-V devices. 464 Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Device Pin- Tables 41 and 42 show the pin names and numbers for FLEX 6000 device 0 uts packages. Table 41. FLEX 6000 Device Pin-Outs _ Note (1) Pin Name 100-Pin TOFP 100-Pin TOFP 144-Pin TOFP 144-Pin TQFP EPF6010A EPF6016A EPF6010A EPF6016 EPF6016A EPF6024A MSEL (2) 22 22 33 33 nSTATUS (2) 39 39 56 56 nCONFIG (2) 36 36 53 53 DCLK (2) 89 89 128 128 CONF_DONE (2) 72 72 105 105 INIT_DONE (3) 64 64 94 94 ncE (2) 4 4 4 4 nCEO (4) 49 49 70 70 nws (4) 81 81 117 117 nRS (4) 83 83 120 120 ncs (4) 77 77 111 111 cs (4) 78 78 114 114 RDYnBUSY (4) 67 67 97 97 CLKUSR 69 (2) 69 (4) 100 (2) 100 (4) DATA (2), (5) 86 86 125 125 TDI (6) 10 10 13 13 TDo (6) 51 51 73 73 TCK 23 (2) 23 (6), (7) 34 (2) 34 (6), (7) TMS 18 (2) 18 (6) 27 (2) 27 (6) Dedicated Inputs 12, 13, 62, 63 12, 13, 62, 63 17, 20, 89, 92 17, 20, 89, 92 DEV_CLRn (3) 91 91 130 130 DEV_OE (3) 85 85 123 123 VCCINT 6, 21, 38, 54, 71, 88 | 6, 21, 38, 54, 71, 88 | 6, 31, 77, 103 6, 31, 77, 103 vccio - - 7, 19, 32, 55, 78, 91, | 7, 19, 32, 55, 78, 91, 104, 127 104, 127 GND 5, 20, 37, 53, 70, 87 | 5, 20, 37, 53, 70, 87 | 5, 18, 30, 54, 76, 90, | 5, 18, 30, 54, 76, 90, 102, 126 102, 126 No connect (N.C.) 3, 7, 19, 52, 55, 56, |- 3, 8, 9,28, 29,74, |- 68 (10) 75, 79, 80, 98, 99, 101 (17) Total user I/O pins (8) | 71 81 102 117 Altera Corporation 465 mal aa m =< on oS oa oFLEX 6000 Programmable Logic Device Family Data Sheet 110, 129, 147, 165, 182, 199 90, 109, 120, 129, 149, 169, 181, 191, 210, 229, 240 D17, H4, H17, N4, N17, U4, U8, U13, U17 Table 42. FLEX 6000 Device Pin-Outs Notes (1) Pin Name 208-Pin POFP 240-Pin POFP 256-Pin BGA 256-Pin BGA EPF6016 EPF6016 EPF6016 EPF6024A EPF6016A EPF6024A EPF6024A MSEL (2) 46 52 T3 T3 nSTATUS (2) 80 92 wit wit nCONFIG (2) 77 89 Y11 Yt1 DCLK (2) 184 212 C10 C10 CONF_DONE (2) 150 172 E18 E18 INIT_DONE (3) 135 155 J19 J19 nCE (2) 6 9 E1 E1 nCEO (4) 102 117 V18 V18 nws (4) 169 195 B15 B15 nRS (4) 174 200 C13 C13 ncs (4) 159 184 B17 B17 cs (4) 162 188 A17 A17 RDYnBsy (4) 140 161 G20 G20 CLKUSR (4} 144 166 G17 G17 DATA (2), (5) 181 209 B10 B10 TDI (6) 19 22 J3 J3 TDO (6) 107 124 T17 T17 TCK (6), (7) 47 54 v4 v1 TMs (6) 38 44 P3 P3 Dedicated Inputs 24, 28, 128, 132 28, 32, 148, 152 K19, L1, L3, L20 K19, L1, L3, L20 DEV_CLRn (3) 187 216 cg cg DEV_OE (3) 178 205 A12 A12 VCCINT 8, 26, 44, 111, 130, | 11,30, 50, 130, 150, | D20, F3, K20, L2, D20, F3, K20, L2, 148 .170 T20, U1 T20, U1 VCCIO 9, 27, 45, 63, 79, 96, | 12, 31, 51, 72,91, |D6,D11,D15,F4, |D6, D11, D15, F4, 112, 131, 149, 166, | 110, 131, 151, 171, | F17, K4, L17, R4, F17, K4, L17, R4, 183, 200 192, 211, 230 R17, U6, U10, U15 | R17, U6, U10, U15 GND 7, 25, 43, 62, 78, 95, | 10, 29, 49, 61, 71, | A1, D4, D8, D13, A1, D4, D8, D13, D17, H4, H17, N4, Nt7, U4, U8, U13, U17 No connect (N.C.) (9) A11, A16, B4, C7, D12, E20, J20, T2, U12, V8, V14, W5, Y17, Y19 Total user I/O pins (8) 171 199 204 218 466 Altera CorporationFLEX 6000 Programmable Logic Device Family Data Sheet Notes to tables: (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) All pins not listed are user I/O pins. This pin is a dedicated configuration or JTAG pin; therefore, it is not available for use as a user I/O pin. This pin can be used as a user I/O pin if it is not used for its chip-wide or configuration function. This pin can be used as a user I/O pin after configuration. This pin is tri-stated in user mode. If the device is not configured to use the JTAG BST circuitry, this pin is available as a user I/O pin. If the JTAG BST circuitry device option is not used, JTAG testing may still be performed before configuration. If this pin is used as an input in user mode, ensure that it does not toggle before or during configuration. The user I/O count includes dedicated input and I/O pins. To maintain pin compatibility when migrating from an EPF6024AB256 device to an EPF6016B256 device, do not use these pins as user I/O pins. To maintain pin compatibility when migrating from an EPF6016AT100 device to an EPF6010AT100 device, do not use these pin as user I/O pins. To maintain pin compatibility when migrating to an EPF6010AT144 from a larger device, do not use these pins as user I/O pins. Altera Corporation 467 ma rc m = an ao a o