98820 (04/01)
© 2001 IXYS All rights reserved
DSP 8
ADVANCE TECHNICAL INFORMATION
VRSM VRRM Type
V V
900 800 DSP 8-08AC
1300 1200 DSP 8-12AC
Symbol Test Conditions Maximum Ratings
IFRMS TVJ = TVJM 30 A
IF(AV)M Tcase = 100°C; 180° sine 2 x 11 A
IFSM TVJ = 45°C; t = 10 ms (50 Hz), sine 100 A
t = 8.3 ms (60 Hz), sine 105 A
TVJ = 150°C; t = 10 ms (50 Hz), sine 85 A
t = 8.3 ms (60 Hz), sine 90 A
I2tTVJ = 45°C t = 10 ms (50 Hz), sine 50 A2s
t = 8.3 ms (60 Hz), sine 45 A2s
TVJ = 150°C; t = 10 ms (50 Hz), sine 35 A2s
t = 8.3 ms (60 Hz), sine 30 A2s
TVJ -40...+150 °C
TVJM 150 °C
Tstg -55...+150 °C
TL1.6 mm (0.063 in) from case for 10 s 260 °C
VISOL 50/60 Hz RMS; IISOL ≤ 1 mA 2500 V~
FCMounting Force 11...65 / 2.5..15 N/lb
Weight 2g
Symbol Test Conditions Characteristic Values
IR
QVR= VRRM; TVJ = 25°C≤10 µA
TVJ = 150°C≤0.7 mA
VF
RIF = 10 A; TVJ = 25°C≤1.22 V
TVJ = 125°C≤1.26 V
VT0 For power-loss calculations only 0.8 V
rTTVJ = TVJM 41 mΩ
RthJC DC current 1.8 K/W
RthCK DC current (with heatsink compound) typ. 0.6 K/W
aMaximum allowable acceleration 100 m/s2
VRRM = 800/1200 V
IF(AV)M =2 x 11 A
Phase-leg Rectifier Diode
ISOPLUS220TM
Electrically Isolated Back Surface
ISOPLUS220 Outline
1 2 3
Features
lSilicon chip on Direct-Copper-Bond
substrate
- High power dissipation
- Isolated mounting surface
- 2500V electrical isolation
lFor single and three phase bridge
configuration
lLow cathode to tab capacitance (<15pF)
lPlanar passivated chips
lEpoxy meets UL 94V-0
Notes: Data given for TVJ = 25OC and per diode unless otherwise specified
Q Pulse test: pulse Width = 5 ms, Duty Cycle < 2.0 %
RPulse test: pulse Width = 300 µs, Duty Cycle < 2.0 %
IXYS reserves the right to change limits, test conditions and dimensions.
* Patent pending
ISOPLUS220TM
3
2
Isolated back surface *
1
