19-0873; Fev 3; 695 General Description The MAX280/MXL1062 are Sth-order all-pole instrumen- tation lowpass filters with no DC error, The filter uses an external resistor and capacitor to isolate the integrated circuit from the DC signal path, thus providing excellent DC accuracy. The resistor and capacitor, along with the on-chip 4th- arder switched capacitor filter, form a Sth-order low- pass filter. Two MAX280/MXL1062s can be cascaded to form a 10th-order lowpass filter. Tha filter cutoff frequency is set by an internal ciock which can be externally driven. The clock to cutoff- frequency ratio is 100:1, allowing clock ripple ta be easily removed. The MAX280 is an enhanced version of the MXL1062. MA AKXIMM 5th Order, Zero DC Error, Lowpass Filter Features @ Lowpess Fitter with No DC Error @ Low Passband Noles @ DC to 20kHz Cutoff Frequency @ 5th Order All Pole Fitter @ Internal or External Clock @ Cascadable for Higher Order Rolloff @ Buffered Output Avaliable @ 8-Pin DIP or 16-Pin SOIC Ordering Information Enchancements include tighter specifications on the PART TEMP. RANGE ___PIN-PACKAGE internal clock oscillator frequency and the buffer ampl- MAX280CPA OPC to + 70C 8 Lead Plastic DIP fier offset voltage. MAX280CWE 0C to +70G 16 Lead-Wide SO ______(estCAppiications MAX280EPA 40C to 485C 8 Lead Plastic DIP Anti-Aliasing Filter MAX280EWE -40C to +85C 16 Lead Wide SO Data Loggers MAX280MJA 55C to4125C GS Lead CERDIP Digital Voltmeters MXL1062CN8 -40C to +85C 4 Lead Plastic DIP MXL1062CJ8 -40C ta 485C 8 Lead CERDIP Weigh Scales MXL1062CS -AOPC to 485C 16 Lead Wide SO Strain Gauges MXL1062MJB BEPC to + 125C 8 Lead CERDIP Typical Operating Circult Pin Configurations Top View DC ACCURATE INPUT wT Cd OUTPUT Use out BUFFERED Bout ourpuT MAX280 vt +SV Coscr ND vv Al og 7 = Ht Lowpass Filter aGND (2) FIA KI mre DIVIDER RATIO [4] ma CE) MAX280 &Pin 0.300 DIP Vv we we (F 16-Pin 0.300" SO MAAXLM Maxim Integrated Products 1 For free samples & the latest literature: hitp:/;jvww.maxim-ic.com, or phone 1-800-998-8800 290} IXW/08eXVMAX280/MXL 1062 Sth Order, Zero DC Error, Lowpass Filter ABSOLUTE MAXIMUM RATINGS Total Supply Voltage (V+ to V-).. tne LOM Storage Temperature Range ............0.00..0... 85C ta +160C Input Voltage at Any Pin... ences LGV S VIN Ss V+ +0.3V Lead Temperature Range (Soldering, 10sec).................4300C Operating Temperature Pawer Dissipation MAX280CXXIMAL10G2C occ ceceeeeee ee PE to 470C Plastic DIP (derate 6.26mWPC above 70C)... 500mwW MAX280EXX oe ~40C to +86C CERDIP (derate 8.00 mWPC above 70C}... ..640mW MAX280MXX/MXL1062M....0 i BPC to $1259C SO (derate 9.52mW/C above 70C)... eee FOZ Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the davice. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in fhe operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extanded perlods may affact device rallabillty. ELECTRICAL CHARACTERISTICS (vt = +5, Vo = -5, Ta = 25C, unless otherwise specified, AC output measured at pin 7, Figure 1.} PARAMETER ; CONDITIONS MIN TYP MAX UNITS Operating Supply Voltage Dual Supply +2.375 +8.0 Vv Single Supply 4.75 16.0 Coase (Pin 5 to V) = 100pF Power Supply Current Ta = 25C 5.0 70 mA Ta = Twin to Taax 5.0 10.0 Input Frequency Range 0-20 kHz Fitter Gain at fork = 100kHz, Pin 4 at V* G = O.01pF, R = 25.78kQ fin =0 0 fin = 0.5fe (Note 1) 0.02 0.3 fin = tc Ta = Tain to Tax 2 -3 dB fin = 2fc Ta = Twin to Trax -2B -30 tin = 4fe Ta = Twin to Tyax -54 -60 Clock to Cutoff Frequency Ratio fotk = 100kHz, Pin 4 at * 100 1 Terk /fe C = O0.01pF, A = 25.78k0 Filter Gain at fin = 16kKHz ferk = 400kHz, Pin 4 at Vt C = 0.01uF, R= 6.5kN 46 -52 dB Ta = Tw to Twax ferxfc Tempoo Same a8 above 10 ppm/?C . : Pin 7 buffered with an ext op Filter Output (Pin 7) DG Swing amp Ta = Twin to Twax +35 +3.8 Vv Clock Feedthrough 10 TMVpp INTERNAL BUFFER Bias Currant Ta = 26C 2 50 pA Ta = Twin to Tax 170 1000 Offset Voltage mV MXL1062 2 20 Voltage Swing Ri = 20K9; Ta = Taw to Tax +3.5 +3.8 v Short Gircuit Gurrent Source/Sink 30/2 mA CLOCK (NOTE 2) Cosc (Pin 5 to V) = 100pF Internal Oscillator Frequency Ta = Twin to Taax wre (eOpr to MXL1062 Max Clock Frequency 4 MHz Cose Input Sink/Source Current Ta = Taw to Twax 25 80 HA Note 1: fc is the frequency where the gain is -3d5 with respect to the input signal. Note 2; The external or driven clock frequency is divided by either 1, 2, or 4 depending upon the voltage at pin 4, When pin 4 = Vi. fouxfe = 100; when pin 4 = GND, foik/fc = 200; pin 4 = V, foix/fe = 400. 2 MAXISth Order, Zero DC Error, Lowpass Filter Pin Deecription PIN # NAME FUNCTION PIN # NAME FUNCTION 1 FB External capacitor couples to the 5 Cose Clock Input pin for extemal clock chip through this pin. applications. For internal clock tion connect an extemal 2 AGND Ground. Connect to system operat ws ground for dual supply operation capacitor between this pin and or mid-supply for single operation. - This pin should be well bypassed 6 vt Positive supply valtage opel oneveti tor for single 7 | ouT Input to on-chip buffer amplifier 3 v Negative supply voltage Bour Output of buffer amplifier 4 DIVIDER | The oscillator frequency is divided RATIO by either 1, 2, or 4 depending upon the voltage on this pin. This in turn gives a clock to cutott frequency ratlo when tied to V* of 100:1; when tied to GND of 200:1; and when tied to V" of 400:1. Typical Operating Characteristics GAIN NORMALIZED GAIN NORMALIZED TO CUTOFF FREQUENCY TO CUTOFF FREQUENCY PASSBAND GAIN (, = +5) {Vg = +2.5V) vs. INPUT FREQUENCY Tverasy erase Te -10 | Ta =2C N -10 + | Th. =3C +0 ta 1 te HN 1 fe ITY = -20 | -= -= -2 + = 2AAc 2nRC 1.62 2nAC 1.62 B00] g a = a WW Zz +20 S40 = 0 SH 3 Zz z per] o a 4 0 Many a og 0 z 60 x Pasay im -20 foik = 1MHE, fo = tok PtH fouk = IMH2, fe = 10kHz oF I teu = SOOKE, Ie ~ skHz TNT IT 70 T ter = SOOKHZ, fo = SkHz 7 0 60 FicLk = 100kHz, ip = 1kHz4 bo | fork = 100kHz, fo = tkHz =! Hy -6.0 9g Lit = 1kHe, fe = 100Hz, i 0 fer = kHz, fc = 100Hz 11 an a 0 10.0 o1 10 0 x) o3 05 D7agts {intic bic fivfic GAIN vs. PASSBAND PHASE SHIFT CUTOFF FREQUENCY INPUT FREQUENCY ve. INPUT FREQUENCY vs. Cose 10 1000 a 1 lfey vow 1 anRC 8 g mo - = w = ~ 2rnc 5 a PIN TO Vt 3S 207 1 | te a 2 Z _go L2rRC 1.62 E aa 3 - _1_. fe = Z ark y 5 0.1 | PIN TO AGND V5 = t8v : 3 go [Ta = 25C a o oo fein = 1kHz DIVIDER F nm ooo LPIN TOV DA 10 10.0 oA 02 O83 o4050808 1 oof of 1 #19 #100 1K 1K finite finfle fe (Hz} MAXIM 3 290} IXW/O8CXVNMAX280/MXL 1062 Sth Order, Zero DC Error, Lowpeass Filter Typical Operating Characteristics (continued) NORMALIZED OSCILLATOR FREQUENCY, POWER SUPPLY OSCILLATOR FREQUENCY osc S- CURRENT vs. POWER foge 8. SUPPLY VOLTAGE AMBIENT TEMPERATURE SUPPLY VOLTAGE 8 13 __ 180 ITI a = = A= 3 12 z Cose = OpF =? Onc eh S14. & wo | E 6 1 Fi vF = SV Ee E BAL ives E a1 a0 Pot & 4 3 iL Pa, o Bos E a zi 4 5 0 vay) 52 Noa =- Z 5 | | 1 z o 5 07 100 a > 5 F 8 H 8 6 -50 -25 0 25 S50 75 100 125 4 6 8 0 @ 4 6 Veuppoy {} AMBIENT TEMPERATURE ("C) POWER SUPPLY () VARIATION OF PASSBAND GAIN WITH TEMPERATURE Ta = 126C tite introduction Figure 1 illustrates the architecture of the circuit. The output voltage is sensed through an internal buffer, then applied to an internal switched capacitar network which drives the bottom plate of an external capacitor to form a 5th order lowpass filter. The input and output appear across an external resistor and the IC part of the overall filter handles only the AC path of the signal, The DC offsets of the buffer and the switched capacitor network are blocked by the capa- citor and do not appear at the zero offset output pin. Use of this external resistor and capacitor also auto- matically provides the required anti-aliasing filtering for the sampled filter. Further, low frequency noise in the filter IC is attenuated by the external capacitor since any noise at the FB pin goes through a highpass path to the filter output. The filter output pin is unbuffered. This signal can be buffered by the on-chip buffer or by a high accuracy op amp (such as a 4 PASSBAND GAIN vs. INPUT FREQUENCY Vg = +5 1 te] fl tog bTA= C 4 rR 51.614- feux = 1OOKHE |" Y 1.62 +02 TT te TN A eh is it q 0 LL - Fa 1 NS mr 02 SS fe -03 165 7 na |_| te6 0.100 O32 O05 O7 0944 tiwtc chopper stabilized op amp) to obtain a buffered DC accurate system. The on-chip buffer has an offset voltage of 2mV for the MAX280 and 20mV for the MXL1062. The offset voltage for both devices have a typical tempce of 1n/C. Detailed Description Clock Requirements Using Divider Raifo DIVIDER RATIO sets the ratio between the internal fork (supplied to the MAX280/MXL1062) and fogc (the output at the DIVIDER RATIO pin). Connect DEA RATIO to V* for a 1/1, to GND for a 1/2, and to V" for a 1/4 ferxose ratio. Using Internal Oscillator The internal 140kHz (nominal) oscillator frequency can be modified by connecting an external capacitor MAAS5th Order, Zero DC Error, Lowpass Filter in parallel with tha on-chip 33pF capacitor; from the Cosc pin to GND (or ta V" if the capacitor is polarized). The clock frequency can be calculated by: fosc = 140kKHz (33pF/(33pF+Cog)} (1) Due to process tolerances, f, can vary by +62.5% in the MXL1062. In the MASESO, on-chip trimming reduces the fog, tolerance to +19.5%, The oscillator frequency can Be adjusted by adding a series poten- tiometer between the capacitor and the Cogc pin as shown in Figure 2 The new frequency can be computed as: fase = fase/(1-4ACogcfosc) (2) where fosc is the value of the oscillator frequency when R = 6. When an external potentiometer is used, the new value of the oscillator frequency is always higher than the one calculated in (equation 1). To achieve a wide tuning range, calculate (aquation 1} the ideal fosc, Cosc pair, then double the value of Cosc and use a 50k potentiometer to adjust foge. For example: to obtain a 1kHz oscillator frequency. G 5 ig 3000pF. By using 8800pF for Coge and a 50k potentiometer, the clock frequency can be adjusted from 500Hz to 1.56kHz. The internal oscillation fre- quency can be measured directly at the Cogc pin using a low capacitance probe. MAX280 DC ACCURATE LOWPASS R IN ZERO OFFSET OUTPUT BUFFERED Wao OUTPUT + pz) Cosc|5 (2mV MAK Vos} = : ve I OSC Cose -[oee 7 } 33pF fasc Figure 1, Block Diagram 50k Cosc PIN ET | 6a00pF = Figure 2. External Oscillator Trim SV AAL/VI Using an External Clock The internal switched capacitor filter requires a clock 100 times higher than the desired cutoff frequency. If an external clock is used the input on the C pin must swing close to the power rails (V*,V"). ARnough standard 74HCOO0 series CMOS gates do not guarantee CMOS levels with the source and sink currents of the C pin, they will in reality drive the Cogc pin. CMGs gates conforming to standard B series output drive have the appropriate voltage levels and current to simultaneously drive several chips. The typical trip levels of the internal Schmitt trigger sensing Gog pin are: POWER SUPPLY TRIP LEVEL Woa+25V0 Vo = -2.5V Vin = 0.9V Vit = -1.18V += 4+6h.0 V-=-5.0V Win = 1.4V Vit = -2.1 * = +6.0V Vo = -6.0V Vin = 17V Vit = -2.5V Ve o= +5.0 -= ov Vin = 3.4V Vic = 1.5V += +40 V-= ov Vin = 6.4V Vit = 2.9V VWr= +15V v- = OV Vin = 9.5V Vit = 44 Choosing External Resistor and Capacitor Values The external resistor and capacitor is used as part of @ feedback loop for the filter and also forms one pole. The internal 4 pole switched capacitor filter is driven by a clock which also determines the filter cutoff frequency. For a maximally flat amplitude rasponse, the clock should be 100 times the desired cutoff frequency and the resistor and capacitor should be chosen such that: fe 1 1620 2aRC where f. = filter cutoff frequency, (-3dB point) For example to implement a 10Hz cutoff filter, a 1kHz clock is required with 1/27RC = 10Hz/1.62 = 617Hz. Typically R is chosen to be around 20kQ. The mini- mum value of R depends upon the maximum input signal, and the current sinking capability of the FB pin (typically 1mA}. So for a 1V peak-to-peak signal, the minimum value of the resistor is 1kQ. The passband response for values of 1/(27RC) around (f,/1.62) can be seen on the Passband Gain vs. Input Frequency plot (see Typical Operating Characteris- tics). If maximum flatness is required (as in Butter- worth filters), the RC product should be well con- trolled. When the input resistor and capacitor cutoff frequency approaches the cutoff frequency of the on-chip 4th order filter, response peaking becomes severe as can be seen in the response piots. However the attenuation slope is virtually unaffected by the resistor and capacitor since. it is set by internal cir- cuitry. This can be seen in the Gain vs. Input Frequency plot. For wide temperature range applications NPO ceramic capacitors are recommended. Their tempcos are around +20ppm and values are available to 0.1yF. 5 290} IXW/082XVWNMAX280/MXL 1062 Sth Order, Zero DC Error, Lowpass Filter Other ceramic capacitors are not recommended due to their large tempcos. Mylar, polystyrene and paly- Propylene capacitors all provide acceptable perfor- mance. Solid tantalum capacitors connected back-to- back and disc ceramic capacitors introduce additional passband arrors (0.06-0.1dB). Applications information Fliter input Voltage Range Every node of the filter typically swings within 1V of both supplies. With the appropriate external resistor and capacitor values, tha amplitude response of all the internal and external nodes should not exceed a gain of CdB with the exception of the FB pin. The amplitude response of the FB pin, where some peaking may occur, is shown in Figure 3. For an input frequency around 0.8f,, the gain is 1.7W/V and, with +5V sup- plies, the peak-to-peak input voltage should not exceed 4,7. If the input voltage goes beyond this value, clipping and distortion of the output waveform may occur; however, the filter will not be damaged. The absolute maximum input voltage to any pin should not exceed the power supplies. internal Buffer The internal output buffer of the FB pin and the OUT pin is part of the AC signal path. Hence capacitive jcading greater than 30pF may cause gain errors in the passband around the cutoff frequency. The internal buffer can also be used as the filter output, however, there will be a few millivolts of output offset. Filter Atienuation The rolloff is 30dB/actave. When the clock rate is increased and hence the cutoff frequency is increased, the filter's maximum attenuation decreases as shown in the Typical Operating Characteristics. This decrease is caused by rolloff at higher frequencies of the loop gains of the various internal feedback paths and is not due to any increase in noise floor. Vep/Vin (8) O01 0203 05 1 10 finlc Figure 3. Amplitude Response of FB Pin Filter Noise The filter wideband noise is typically 90uVpyc with =-5V-supplies and typically 804Vpys for +2.5V supplies or a +5V single supply. This value is nearly indepandent of the cutoff frequency. The noise spectral density, unlike conventional active filters, is nearly zero for frequencies below 0.1 f.. Roughly 2/3 of the entire wideband noise is in the band DC to fe. Transient Response Figure 44 shows the step response of the filter, This response approximates that of an ideal 5th order maximally flat (Butterworth) filter. The ringing in the transient response can be reduced by using a Bessel filter. The Bessel filtar response can be approximated by setting 1/27 RC to f,/2 instead of f,/1.62. Figure 4B shows the step response of the Bessel approximation. Figure 4A. Step Response of Butterworth Approximation 1 fc 2nAC 1.62 . (ImSidiv, 0.5Widiv) Figure 4B. Step Response of Bessel Approximation 1 fe 2nRG 2 (imS/div, 0.5v/div.} FVIA XI VlSth Order, Zero DC Error, Lowpass Filter Anti-Allasing The internal 4th order switched capacitor filter is a sampled device and as such will alias unless preceded a band limited signal, or a continuous non-sam fitter. The external resistor and capacitor used to fo the 5th filter. pole also automatically provides this function. Attenuation Is greater than 43dB at the Nyquist frequency. Single Supply Operation Figure 5 shows a schematic for single supply opera- tion. The AGND pin and the OUT pin should be biased at 1/2 supply. The value of the resistors Al and R2 should be chosen to conduct 100uA or more. PR DCG biases the buffer and C isolates the buffer from the DC value of the output. Under these conditions the external resistor and capacitor should be adjusted such that (1/27RC) = f,/1.84. This accounts for the extra loading of the A,C combination. A and C' are not requi if the input voltage has a DC value around 1/2 supply. If an external capacitor is used to activate the internal oscillator, its bottom plate should be tied to system ground. The AGND pin should also be bypassed by a decoupling capacitor. Clock Feedthrough Clock feedthrough can be reduced by using a resistor and capacitor at the buffered output pin provided that this pin is used as an output. If an external op amp is used to buffer the OC accurate output. an input resistor and capacitor can be used to eliminate clock feedthrough (see Figure 6) and further reduce the attenuation floor of the filter. FOR A MHz FILTER A = 29.4k0, C = Iw. fork = TkHz THE FILTER IS MAXIMALLY FLAT FOR 1 c c_ Figura 5. Singls 5V Supply 5th Order LP Filter Vin pie Vou THE MAK#30 ec CONNECTEO AS A 2nd ORDER SALLEN AND KEY LOWPASS FILTER. ae a CUTOFF FREQUENCY EQUAL 10 THE MAX220, THE ADDITIONAL FILTERING ELIMINATES ANY 10kHz CLOCK FEED THROUGH PLUS DECREASES THE WIDEBAND NOSE OF THE FILTER. OC OUTPUT OFFSET (REFERRED TO A DC GAIN OF UNITY) = Be Mex. OC GAIN Rs Ra Ri RZ c1 OUTPUT FILTER COMPONENT VALUES o 0 14.3k 3.6k OF 2.57k 324k 48k 274k O1pF am 224k ontk Bok OAT C2 0.033 uF O.2uF VF WIDEBAND NOISE (REFERRED TO A DC GAIN OF UNIT) = is Figure 6. 7th Order 100Hz Lowpass Filter with Continuous Output Filtering, Output Buffering and Gain Adjustment MAAIL/VI 2901 IXIW/O08CXVNMAX280/MXL 1062 Sth Order, Zero DC Error, Lowpass Filter Cascading for Higher Order Filters Two chips can be cascaded with or without inter- mediate buffers. Figure 7A shows a DC accurate 10th order iowpass filter. The unbuffered output of the first chip directly drives the next stage input. To minimize loading the first resistor and capacitor, the next stage RF should be much jarger. The recommended ratio of AAR is 11771. The values chosen were 1/(27RC) = ffs? and 1/(27R'C'} = f,/1.6. For example, for f- = 18kKHz, fer, = 416kKHz, A = 909, R = 107kN, 0.066uF, = 574pF. For this example the maximum assband error occurs around 0.5f and is -0.6dB. igure 6B corrects for loading the buffered output when the first stage is used to drive the input of the next stage. This introduces a maximum DC error of 2mvV over temperature using the MAX280. Now R and R can be similar in value and the passband gain error is reduced typically -0.15d8. The RC values used were V(27RC) = fo/1.59 and 1/(27R'C) = f,/1.64. Creating Notch Filters The MAX280/MXL1062 can be used to craate a notch because the frequency, where it exhibits -180 phase shift, is inside its passband as shown in Figure 8A. It i$ repeatable and predictable from part-to-part. An input signal can be summed with the output of the filter to form a notch.as shown in Fiqure 8B. The 180 phase shift of the MAX2S0/MXL1062 occurs at folK/ 118.3 or 0.85 times the lowpass cutoff frequency. For instance, to obtain a 60Hz notch, the clock frequency should be 7086kHz and the input (1/27AC) should be approximately 70.96Hz/1.63. The optional (R2C2) at the output filters the clock feedthrough. The 1/27R2C2 should be 12-15 times the notch frequency. The major advantage of this notch is its wide bandwidth. The input frequency range is not limited by the clock frequency because the MAX280/MXL1002 by itself does not alias. The circuit of Figure &C is an extension of the pre- vious notch filter. The input signal is summed with the lowpass filter output through A1, as previously described; then, the output of Al is again summed with the input voltage through A2. R6 = R2 = R3 = A? and R4 = Ro = 0.5R7, the output of A2, at least theoretically, should look like the output of MAX280/MXL1062, the Bayt pin. If the ratio of - DC ACCURATE OUTPUT SOdB/OCTAVE ROLLOFF 10Hz, 10th ORDER DC ACCURATE LOW PASS FILTER 0.506 PASSBAND ERROR, 0dB DC GAIN MAXIMUM ATTENUATION 110dB ffcix = 10kHz) 40008 (Icik = 1kKHz) 35dB (fcix = 1MHz) Figure 7A. Simple Cascading Technique tee- VOUT p> BUFFERED OUTPUT Figure 7B. Cascading Two MAX280/MXL 1062s. The 2nd Stage is Driven by the Buffered Output of the First Stage. SAAXLAYISth Order, Zero DC Error, Lowpass Filter (R6/R5) is slightly jess than 2, a notch is introduced in the stopband of the filter as shown in Figure 8D. pass. The frequency of the notch is at f the value of the resistor ratio (R6/R5) should /47.3 and be equal The overall filter response looks pseudoelliptic low- to: 1.935. . 2 TT -20 1 tr ww aun 1.62 o -60 a -3 T M iE 100 t } 4 = fe = 5 -20 | 4 t 2nRC 17a = y 10 Paane "198 B gmy 1 $ O -180 ForRC (1.78 5 -200 4 ig o +: -220 ZAG 82 -240 1 02 03 04 OS 06 OF O8 08 10 1 10 60100 1k Tin/fe fin (Hz) Figure 8A, Phase Response af the MAX280/MAL 1062 for Various fnput (A, C)s Figure 8D. Amplitude Response of the Filter aA W ~ 100 * 1.62 Ri A4 Vin Apafe wee R R2 RS c -te cz te Vout Te i 1 + Ri = 4 = (R2 + RS) rp MAXI OPTIONAL = 4 7 ti = vr] MAX280 [6 pat vt 2rAC 100 * 1.63 t we CLK IN tworen = fou Figure 88, Using the MAX2G0/MNXL 1062 to Create 4 Noich cr Re JL. 19.35k a We A ? Ra Aa AT 20k 10k 20k WY me Vout Figure 8C. A Lowpass Filter with a 60Hz Notch SVIAAI SI 290} IXW/O8eXVNMAX280/MXL1062 5th Order, Zero DC Error, Lowpass Filter Application Circults 25,8 Vin Your 0.2uF 30 CLK IN 100k 45 CONTROL TO PIN 5 OF CD46 (HIGH, 100k GROUND, > BY CONNECTING PIN 4 OF THE MAX280 HIGH/ Low) GROUNDYLOW THE FILTER CUTOFF FREQUENCY -sv IS 100Hz/S0Hz/25Hz. +5v 100k TO PIN 13 OF CD4016 100k -5V 100Hz, 50Hz, 25Hz Sth Order DC Accurate LP Filter Yin Vouri BUFFERED Amplitude Response for the Octave Tuning Circuit Vout @00kHz cmos CLOCK IN Vin o Vourz BUFFERED Your vn VYoura BUFFERED Voura AMPLITUDE RESPONSE (dB) & oa MAX280 +5 a 12 4 #10 20.40 100 fin(kHz) Octave Tuning with @ Single Input Clock 10 MAXIM5th Order, Zero DC Error, Lowpass Filter Chip Topography - palais res jem OUT 4 rie errs me ; DIVIDER cose RATIO O11" (2,.82mm) Package information Tite MAX oreo ams # | bei =p RAD, nes = 1015 _| n070 eae Suen 5 _ ce tae {= a 25 an - 10 oom = pais a wT (L018 + 1003 al Lacs ass Aah [0457 + O07G) 25M + 0.264) tot Jazss Sih 8 Lead Plastic DIP (PA) Oy, = 160C/AW Byjc = 75C/W MAXIM 1 Z90L TXW/082XVINMAX280/MXL 1062 Sth Order, Zero DC Error, Lowpass Filter Package information (continued) cree MAX LEAD #1 mel al sg eee 1790 - 0320 at - aie 0.20 - caliiill ieee Max wn pan MAX tr A 1 0s -noiz ALDHO. aay (EOS - 1 (1.524) anh sno sera be el 3 8 Lead CERDIP (JA) Oya = 125C/W 8yc = 55C AW HARA A EAE D.2O1- 0.709 0.344-0.354 _0.304-9.419_ (7-390 7.959) (8.738-9.246) (70.008 - 10.643) TT ! (1.270) east) {0.381} a\ 9 6 ; i eee _ | ala lease TT ae 9.005 - 0.011 = 0-076 0.279) 20 ~ 2.480) EELS 16 Lead Small Outline, Wide (WE) 8), = 105C/W djc = 60 C/V Maxim cannot assume resconsibitily for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent scensas are implied, Maxim reserves the right fo change the circuitry and speciticabans without notice al any time, 12 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 ol fe 2.014 -0.018 =e 1995 Maxim Integrated Products Printed USA AAAXLA js a registered trademark of Maxim Integrated Products.